2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 /include/ "skeleton_hs_idu.dtsi"
13 compatible = "snps,nsim_hs";
14 interrupt-parent = <&core_intc>;
17 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
25 compatible = "simple-bus";
29 /* child and parent address space 1:1 mapped */
34 compatible = "fixed-clock";
35 clock-frequency = <80000000>;
38 core_intc: core-interrupt-controller {
39 compatible = "snps,archs-intc";
41 #interrupt-cells = <1>;
44 idu_intc: idu-interrupt-controller {
45 compatible = "snps,archs-idu-intc";
47 interrupt-parent = <&core_intc>;
50 * <hwirq distribution>
51 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
53 #interrupt-cells = <2>;
56 * upstream irqs to core intc - downstream these are
59 interrupts = <24 25 26 27 28 29 30 31>;
62 arcuart0: serial@c0fc1000 {
63 compatible = "snps,arc-uart";
64 reg = <0xc0fc1000 0x100>;
65 interrupt-parent = <&idu_intc>;
67 clock-frequency = <80000000>;
68 current-speed = <115200>;
73 compatible = "snps,archs-pct";
74 #interrupt-cells = <1>;