arch/arc/kernel/entry-compact.S

   1 /*
   2  * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
   3  *
   4  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   5  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * vineetg: May 2011
  12  *  -Userspace unaligned access emulation
  13  *
  14  * vineetg: Feb 2011 (ptrace low level code fixes)
  15  *  -traced syscall return code (r0) was not saved into pt_regs for restoring
  16  *   into user reg-file when traded task rets to user space.
  17  *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
  18  *   were not invoking post-syscall trace hook (jumping directly into
  19  *   ret_from_system_call)
  20  *
  21  * vineetg: Nov 2010:
  22  *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
  23  *  -To maintain the slot size of 8 bytes/vector, added nop, which is
  24  *   not executed at runtime.
  25  *
  26  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  27  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
  28  *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
  29  *   need ptregs anymore
  30  *
  31  * Vineetg: Oct 2009
  32  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
  33  *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
  34  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  35  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  36  *   Instr Error could also cause similar scenario, so same there as well.
  37  *
  38  * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
  39  *
  40  * Vineetg: Aug 28th 2008: Bug #94984
  41  *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
  42  *   Normally CPU does this automatically, however when doing FAKE rtie,
  43  *   we need to explicitly do this. The problem in macros
  44  *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
  45  *   was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
  46  *   setting it and not clearing it clears ZOL context
  47  *
  48  * Vineetg: May 16th, 2008
  49  *  - r25 now contains the Current Task when in kernel
  50  *
  51  * Vineetg: Dec 22, 2007
  52  *    Minor Surgery of Low Level ISR to make it SMP safe
  53  *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
  54  *    - _current_task is made an array of NR_CPUS
  55  *    - Access of _current_task wrapped inside a macro so that if hardware
  56  *       team agrees for a dedicated reg, no other code is touched
  57  *
  58  * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
  59  */
  60
  61 #include <linux/errno.h>
  62 #include <linux/linkage.h>      /* {EXTRY,EXIT} */
  63 #include <asm/entry.h>
  64 #include <asm/irqflags.h>
  65
  66         .cpu A7
  67
  68 ;############################ Vector Table #################################
  69
  70 .macro VECTOR  lbl
  71 #if 1   /* Just in case, build breaks */
  72         j   \lbl
  73 #else
  74         b   \lbl
  75         nop
  76 #endif
  77 .endm
  78
  79         .section .vector, "ax",@progbits
  80         .align 4
  81
  82 /* Each entry in the vector table must occupy 2 words. Since it is a jump
  83  * across sections (.vector to .text) we are gauranteed that 'j somewhere'
  84  * will use the 'j limm' form of the intrsuction as long as somewhere is in
  85  * a section other than .vector.
  86  */
  87
  88 ; ********* Critical System Events **********************
  89 VECTOR   res_service             ; 0x0, Restart Vector  (0x0)
  90 VECTOR   mem_service             ; 0x8, Mem exception   (0x1)
  91 VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)
  92
  93 ; ******************** Device ISRs **********************
  94 #ifdef CONFIG_ARC_IRQ3_LV2
  95 VECTOR   handle_interrupt_level2
  96 #else
  97 VECTOR   handle_interrupt_level1
  98 #endif
  99
 100 VECTOR   handle_interrupt_level1
 101
 102 #ifdef CONFIG_ARC_IRQ5_LV2
 103 VECTOR   handle_interrupt_level2
 104 #else
 105 VECTOR   handle_interrupt_level1
 106 #endif
 107
 108 #ifdef CONFIG_ARC_IRQ6_LV2
 109 VECTOR   handle_interrupt_level2
 110 #else
 111 VECTOR   handle_interrupt_level1
 112 #endif
 113
 114 .rept   25
 115 VECTOR   handle_interrupt_level1 ; Other devices
 116 .endr
 117
 118 /* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
 119
 120 ; ******************** Exceptions **********************
 121 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
 122 VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
 123 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
 124 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
 125                                  ;         or Misaligned Access
 126 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
 127 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
 128 VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
 129
 130 .rept   24
 131 VECTOR   reserved                ; Reserved Exceptions
 132 .endr
 133
 134
 135 ;##################### Scratch Mem for IRQ stack switching #############
 136
 137 ARCFP_DATA int1_saved_reg
 138         .align 32
 139         .type   int1_saved_reg, @object
 140         .size   int1_saved_reg, 4
 141 int1_saved_reg:
 142         .zero 4
 143
 144 /* Each Interrupt level needs its own scratch */
 145 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
 146
 147 ARCFP_DATA int2_saved_reg
 148         .type   int2_saved_reg, @object
 149         .size   int2_saved_reg, 4
 150 int2_saved_reg:
 151         .zero 4
 152
 153 #endif
 154
 155 ; ---------------------------------------------
 156         .section .text, "ax",@progbits
 157
 158 res_service:            ; processor restart
 159         flag    0x1     ; not implemented
 160         nop
 161         nop
 162
 163 reserved:               ; processor restart
 164         rtie            ; jump to processor initializations
 165
 166 ;##################### Interrupt Handling ##############################
 167
 168 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
 169 ; ---------------------------------------------
 170 ;  Level 2 ISR: Can interrupt a Level 1 ISR
 171 ; ---------------------------------------------
 172 ENTRY(handle_interrupt_level2)
 173
 174         INTERRUPT_PROLOGUE 2
 175
 176         ;------------------------------------------------------
 177         ; if L2 IRQ interrupted a L1 ISR, disable preemption
 178         ;
 179         ; This is to avoid a potential L1-L2-L1 scenario
 180         ;  -L1 IRQ taken
 181         ;  -L2 interrupts L1 (before L1 ISR could run)
 182         ;  -preemption off IRQ, user task in syscall picked to run
 183         ;  -RTIE to userspace
 184         ;       Returns from L2 context fine
 185         ;       But both L1 and L2 re-enabled, so another L1 can be taken
 186         ;       while prev L1 is still unserviced
 187         ;
 188         ;------------------------------------------------------
 189
 190         ; L2 interrupting L1 implies both L2 and L1 active
 191         ; However both A2 and A1 are NOT set in STATUS32, thus
 192         ; need to check STATUS32_L2 to determine if L1 was active
 193
 194         ld r9, [sp, PT_status32]        ; get statu32_l2 (saved in pt_regs)
 195         bbit0 r9, STATUS_A1_BIT, 1f     ; L1 not active when L2 IRQ, so normal
 196
 197         ; bump thread_info->preempt_count (Disable preemption)
 198         GET_CURR_THR_INFO_FROM_SP   r10
 199         ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
 200         add     r9, r9, 1
 201         st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
 202
 203 1:
 204         ;------------------------------------------------------
 205         ; setup params for Linux common ISR and invoke it
 206         ;------------------------------------------------------
 207         lr  r0, [icause2]
 208         and r0, r0, 0x1f
 209
 210         bl.d  @arch_do_IRQ
 211         mov r1, sp
 212
 213         mov r8,0x2
 214         sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
 215
 216         b   ret_from_exception
 217
 218 END(handle_interrupt_level2)
 219
 220 #endif
 221
 222 ; ---------------------------------------------
 223 ;  Level 1 ISR
 224 ; ---------------------------------------------
 225 ENTRY(handle_interrupt_level1)
 226
 227         INTERRUPT_PROLOGUE 1
 228
 229         lr  r0, [icause1]
 230         and r0, r0, 0x1f
 231
 232 #ifdef CONFIG_TRACE_IRQFLAGS
 233         ; icause1 needs to be read early, before calling tracing, which
 234         ; can clobber scratch regs, hence use of stack to stash it
 235         push r0
 236         TRACE_ASM_IRQ_DISABLE
 237         pop  r0
 238 #endif
 239
 240         bl.d  @arch_do_IRQ
 241         mov r1, sp
 242
 243         mov r8,0x1
 244         sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
 245
 246         b   ret_from_exception
 247 END(handle_interrupt_level1)
 248
 249 ;################### Non TLB Exception Handling #############################
 250
 251 ; ---------------------------------------------
 252 ; Protection Violation Exception Handler
 253 ; ---------------------------------------------
 254
 255 ENTRY(EV_TLBProtV)
 256
 257         EXCEPTION_PROLOGUE
 258
 259         lr  r2, [ecr]
 260         lr  r0, [efa]   ; Faulting Data address (not part of pt_regs saved above)
 261
 262         ; Exception auto-disables further Intr/exceptions.
 263         ; Re-enable them by pretending to return from exception
 264         ; (so rest of handler executes in pure K mode)
 265
 266         FAKE_RET_FROM_EXCPN
 267
 268         mov   r1, sp    ; Handle to pt_regs
 269
 270         ;------ (5) Type of Protection Violation? ----------
 271         ;
 272         ; ProtV Hardware Exception is triggered for Access Faults of 2 types
 273         ;   -Access Violaton    : 00_23_(00|01|02|03)_00
 274         ;                                x  r  w  r+w
 275         ;   -Unaligned Access   : 00_23_04_00
 276         ;
 277         bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
 278
 279         ;========= (6a) Access Violation Processing ========
 280         bl  do_page_fault
 281         b   ret_from_exception
 282
 283         ;========== (6b) Non aligned access ============
 284 4:
 285
 286         SAVE_CALLEE_SAVED_USER
 287         mov r2, sp              ; callee_regs
 288
 289         bl  do_misaligned_access
 290
 291         ; TBD: optimize - do this only if a callee reg was involved
 292         ; either a dst of emulated LD/ST or src with address-writeback
 293         RESTORE_CALLEE_SAVED_USER
 294
 295         b   ret_from_exception
 296
 297 END(EV_TLBProtV)
 298
 299 ; Wrapper for Linux page fault handler called from EV_TLBMiss*
 300 ; Very similar to ProtV handler case (6a) above, but avoids the extra checks
 301 ; for Misaligned access
 302 ;
 303 ENTRY(call_do_page_fault)
 304
 305         EXCEPTION_PROLOGUE
 306         lr  r0, [efa]   ; Faulting Data address
 307         mov   r1, sp
 308         FAKE_RET_FROM_EXCPN
 309
 310         mov blink, ret_from_exception
 311         b  do_page_fault
 312
 313 END(call_do_page_fault)
 314
 315 ;############# Common Handlers for ARCompact and ARCv2 ##############
 316
 317 #include "entry.S"
 318
 319 ;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
 320 ;
 321 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
 322 ; IRQ shd definitely not happen between now and rtie
 323 ; All 2 entry points to here already disable interrupts
 324
 325 .Lrestore_regs:
 326
 327         TRACE_ASM_IRQ_ENABLE
 328
 329         lr      r10, [status32]
 330
 331         ; Restore REG File. In case multiple Events outstanding,
 332         ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
 333         ; Note that we use realtime STATUS32 (not pt_regs->status32) to
 334         ; decide that.
 335
 336         ; if Returning from Exception
 337         btst   r10, STATUS_AE_BIT
 338         bnz    .Lexcep_ret
 339
 340         ; Not Exception so maybe Interrupts (Level 1 or 2)
 341
 342 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
 343
 344         ; Level 2 interrupt return Path - from hardware standpoint
 345         bbit0  r10, STATUS_A2_BIT, not_level2_interrupt
 346
 347         ;------------------------------------------------------------------
 348         ; However the context returning might not have taken L2 intr itself
 349         ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
 350         ; Special considerations needed for the context which took L2 intr
 351
 352         ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
 353         brne r9, event_IRQ2, 149f
 354
 355         ;------------------------------------------------------------------
 356         ; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
 357         ; so that sched doesn't move to new task, causing L1 to be delayed
 358         ; undeterministically. Now that we've achieved that, let's reset
 359         ; things to what they were, before returning from L2 context
 360         ;----------------------------------------------------------------
 361
 362         ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
 363         bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal
 364
 365         ; decrement thread_info->preempt_count (re-enable preemption)
 366         GET_CURR_THR_INFO_FROM_SP   r10
 367         ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
 368
 369         ; paranoid check, given A1 was active when A2 happened, preempt count
 370         ; must not be 0 because we would have incremented it.
 371         ; If this does happen we simply HALT as it means a BUG !!!
 372         cmp     r9, 0
 373         bnz     2f
 374         flag 1
 375
 376 2:
 377         sub     r9, r9, 1
 378         st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
 379
 380 149:
 381         ;return from level 2
 382         INTERRUPT_EPILOGUE 2
 383 debug_marker_l2:
 384         rtie
 385
 386 not_level2_interrupt:
 387
 388 #endif
 389
 390         bbit0  r10, STATUS_A1_BIT, .Lpure_k_mode_ret
 391
 392         ;return from level 1
 393         INTERRUPT_EPILOGUE 1
 394 debug_marker_l1:
 395         rtie
 396
 397 .Lexcep_ret:
 398 .Lpure_k_mode_ret:
 399
 400         ;this case is for syscalls or Exceptions or pure kernel mode
 401
 402         EXCEPTION_EPILOGUE
 403 debug_marker_syscall:
 404         rtie
 405
 406 END(ret_from_exception)