2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/smp.h>
12 #include <linux/irq.h>
13 #include <linux/spinlock.h>
16 static char smp_cpuinfo_buf
[128];
17 static int idu_detected
;
19 static DEFINE_RAW_SPINLOCK(mcip_lock
);
22 * Any SMP specific init any CPU does when it comes up.
23 * Here we setup the CPU to enable Inter-Processor-Interrupts
25 * -Master : init_IRQ()
26 * -Other(s) : start_kernel_secondary()
28 void mcip_init_smp(unsigned int cpu
)
30 smp_ipi_irq_setup(cpu
, IPI_IRQ
);
33 static void mcip_ipi_send(int cpu
)
39 * NOTE: We must spin here if the other cpu hasn't yet
40 * serviced a previous message. This can burn lots
41 * of time, but we MUST follows this protocol or
42 * ipi messages can be lost!!!
43 * Also, we must release the lock in this loop because
44 * the other side may get to this same loop and not
45 * be able to ack -- thus causing deadlock.
49 raw_spin_lock_irqsave(&mcip_lock
, flags
);
50 __mcip_cmd(CMD_INTRPT_READ_STATUS
, cpu
);
51 ipi_was_pending
= read_aux_reg(ARC_REG_MCIP_READBACK
);
52 if (ipi_was_pending
== 0)
53 break; /* break out but keep lock */
54 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
57 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ
, cpu
);
58 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
60 #ifdef CONFIG_ARC_IPI_DBG
62 pr_info("IPI ACK delayed from cpu %d\n", cpu
);
66 static void mcip_ipi_clear(int irq
)
70 unsigned int __maybe_unused copy
;
72 raw_spin_lock_irqsave(&mcip_lock
, flags
);
74 /* Who sent the IPI */
75 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE
, 0);
77 copy
= cpu
= read_aux_reg(ARC_REG_MCIP_READBACK
); /* 1,2,4,8... */
80 * In rare case, multiple concurrent IPIs sent to same target can
81 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
82 * "vectored" (multiple bits sets) as opposed to typical single bit
85 c
= __ffs(cpu
); /* 0,1,2,3 */
86 __mcip_cmd(CMD_INTRPT_GENERATE_ACK
, c
);
90 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
92 #ifdef CONFIG_ARC_IPI_DBG
94 pr_info("IPIs from %x coalesced to %x\n",
95 copy
, raw_smp_processor_id());
99 volatile int wake_flag
;
101 static void mcip_wakeup_cpu(int cpu
, unsigned long pc
)
107 void arc_platform_smp_wait_to_boot(int cpu
)
109 while (wake_flag
!= cpu
)
113 __asm__
__volatile__("j @first_lines_of_secondary \n");
116 struct plat_smp_ops plat_smp_ops
= {
117 .info
= smp_cpuinfo_buf
,
118 .cpu_kick
= mcip_wakeup_cpu
,
119 .ipi_send
= mcip_ipi_send
,
120 .ipi_clear
= mcip_ipi_clear
,
123 void mcip_init_early_smp(void)
125 #define IS_AVAIL1(var, str) ((var) ? str : "")
128 #ifdef CONFIG_CPU_BIG_ENDIAN
130 idu
:1, llm
:1, num_cores
:6,
131 iocoh
:1, grtc
:1, dbg
:1, pad2
:1,
132 msg
:1, sem
:1, ipi
:1, pad
:1,
136 pad
:1, ipi
:1, sem
:1, msg
:1,
137 pad2
:1, dbg
:1, grtc
:1, iocoh
:1,
138 num_cores
:6, llm
:1, idu
:1,
143 READ_BCR(ARC_REG_MCIP_BCR
, mp
);
145 sprintf(smp_cpuinfo_buf
,
146 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
147 mp
.ver
, mp
.num_cores
,
148 IS_AVAIL1(mp
.ipi
, "IPI "),
149 IS_AVAIL1(mp
.idu
, "IDU "),
150 IS_AVAIL1(mp
.dbg
, "DEBUG "),
151 IS_AVAIL1(mp
.grtc
, "GRTC"));
153 idu_detected
= mp
.idu
;
156 __mcip_cmd_data(CMD_DEBUG_SET_SELECT
, 0, 0xf);
157 __mcip_cmd_data(CMD_DEBUG_SET_MASK
, 0xf, 0xf);
160 if (IS_ENABLED(CONFIG_ARC_HAS_GRTC
) && !mp
.grtc
)
161 panic("kernel trying to use non-existent GRTC\n");
164 /***************************************************************************
165 * ARCv2 Interrupt Distribution Unit (IDU)
167 * Connects external "COMMON" IRQs to core intc, providing:
168 * -dynamic routing (IRQ affinity)
169 * -load balancing (Round Robin interrupt distribution)
172 * It physically resides in the MCIP hw block
175 #include <linux/irqchip.h>
176 #include <linux/of.h>
177 #include <linux/of_irq.h>
180 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
182 static void idu_set_dest(unsigned int cmn_irq
, unsigned int cpu_mask
)
184 __mcip_cmd_data(CMD_IDU_SET_DEST
, cmn_irq
, cpu_mask
);
187 static void idu_set_mode(unsigned int cmn_irq
, unsigned int lvl
,
193 unsigned int distr
:2, pad
:2, lvl
:1, pad2
:27;
199 __mcip_cmd_data(CMD_IDU_SET_MODE
, cmn_irq
, data
.word
);
202 static void idu_irq_mask(struct irq_data
*data
)
206 raw_spin_lock_irqsave(&mcip_lock
, flags
);
207 __mcip_cmd_data(CMD_IDU_SET_MASK
, data
->hwirq
, 1);
208 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
211 static void idu_irq_unmask(struct irq_data
*data
)
215 raw_spin_lock_irqsave(&mcip_lock
, flags
);
216 __mcip_cmd_data(CMD_IDU_SET_MASK
, data
->hwirq
, 0);
217 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
222 idu_irq_set_affinity(struct irq_data
*data
, const struct cpumask
*cpumask
,
228 /* errout if no online cpu per @cpumask */
229 if (!cpumask_and(&online
, cpumask
, cpu_online_mask
))
232 raw_spin_lock_irqsave(&mcip_lock
, flags
);
234 idu_set_dest(data
->hwirq
, cpumask_bits(&online
)[0]);
235 idu_set_mode(data
->hwirq
, IDU_M_TRIG_LEVEL
, IDU_M_DISTRI_RR
);
237 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
239 return IRQ_SET_MASK_OK
;
243 static struct irq_chip idu_irq_chip
= {
244 .name
= "MCIP IDU Intc",
245 .irq_mask
= idu_irq_mask
,
246 .irq_unmask
= idu_irq_unmask
,
248 .irq_set_affinity
= idu_irq_set_affinity
,
253 static int idu_first_irq
;
255 static void idu_cascade_isr(unsigned int __core_irq
, struct irq_desc
*desc
)
257 struct irq_domain
*domain
= irq_desc_get_handler_data(desc
);
258 unsigned int core_irq
= irq_desc_get_irq(desc
);
259 unsigned int idu_irq
;
261 idu_irq
= core_irq
- idu_first_irq
;
262 generic_handle_irq(irq_find_mapping(domain
, idu_irq
));
265 static int idu_irq_map(struct irq_domain
*d
, unsigned int virq
, irq_hw_number_t hwirq
)
267 irq_set_chip_and_handler(virq
, &idu_irq_chip
, handle_level_irq
);
268 irq_set_status_flags(virq
, IRQ_MOVE_PCNTXT
);
273 static int idu_irq_xlate(struct irq_domain
*d
, struct device_node
*n
,
274 const u32
*intspec
, unsigned int intsize
,
275 irq_hw_number_t
*out_hwirq
, unsigned int *out_type
)
277 irq_hw_number_t hwirq
= *out_hwirq
= intspec
[0];
278 int distri
= intspec
[1];
281 *out_type
= IRQ_TYPE_NONE
;
283 /* XXX: validate distribution scheme again online cpu mask */
285 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */
286 raw_spin_lock_irqsave(&mcip_lock
, flags
);
287 idu_set_dest(hwirq
, BIT(num_online_cpus()) - 1);
288 idu_set_mode(hwirq
, IDU_M_TRIG_LEVEL
, IDU_M_DISTRI_RR
);
289 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
292 * DEST based distribution for Level Triggered intr can only
293 * have 1 CPU, so generalize it to always contain 1 cpu
295 int cpu
= ffs(distri
);
297 if (cpu
!= fls(distri
))
298 pr_warn("IDU irq %lx distri mode set to cpu %x\n",
301 raw_spin_lock_irqsave(&mcip_lock
, flags
);
302 idu_set_dest(hwirq
, cpu
);
303 idu_set_mode(hwirq
, IDU_M_TRIG_LEVEL
, IDU_M_DISTRI_DEST
);
304 raw_spin_unlock_irqrestore(&mcip_lock
, flags
);
310 static const struct irq_domain_ops idu_irq_ops
= {
311 .xlate
= idu_irq_xlate
,
316 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
317 * [24, 23+C]: If C > 0 then "C" common IRQs
318 * [24+C, N]: Not statically assigned, private-per-core
323 idu_of_init(struct device_node
*intc
, struct device_node
*parent
)
325 struct irq_domain
*domain
;
326 /* Read IDU BCR to confirm nr_irqs */
327 int nr_irqs
= of_irq_count(intc
);
331 panic("IDU not detected, but DeviceTree using it");
333 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs
);
335 domain
= irq_domain_add_linear(intc
, nr_irqs
, &idu_irq_ops
, NULL
);
337 /* Parent interrupts (core-intc) are already mapped */
339 for (i
= 0; i
< nr_irqs
; i
++) {
341 * Return parent uplink IRQs (towards core intc) 24,25,.....
342 * this step has been done before already
343 * however we need it to get the parent virq and set IDU handler
346 irq
= irq_of_parse_and_map(intc
, i
);
350 irq_set_chained_handler_and_data(irq
, idu_cascade_isr
, domain
);
353 __mcip_cmd(CMD_IDU_ENABLE
, 0);
357 IRQCHIP_DECLARE(arcv2_idu_intc
, "snps,archs-idu-intc", idu_of_init
);