2 * ARC700 VIPT Cache Management
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg
20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases)
24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now)
32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub
36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers.
45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug
52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k.
64 #include <linux/module.h>
66 #include <linux/sched.h>
67 #include <linux/cache.h>
68 #include <linux/mmu_context.h>
69 #include <linux/syscalls.h>
70 #include <linux/uaccess.h>
71 #include <linux/pagemap.h>
72 #include <asm/cacheflush.h>
73 #include <asm/cachectl.h>
74 #include <asm/setup.h>
76 char *arc_cache_mumbojumbo(int c
, char *buf
, int len
)
80 #define PR_CACHE(p, cfg, str) \
82 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
84 n += scnprintf(buf + n, len - n, \
85 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
86 (p)->sz_k, (p)->assoc, (p)->line_len, \
87 (p)->vipt ? "VIPT" : "PIPT", \
88 (p)->alias ? " aliasing" : "", \
89 IS_ENABLED(cfg) ? "" : " (not used)");
91 PR_CACHE(&cpuinfo_arc700
[c
].icache
, CONFIG_ARC_HAS_ICACHE
, "I-Cache");
92 PR_CACHE(&cpuinfo_arc700
[c
].dcache
, CONFIG_ARC_HAS_DCACHE
, "D-Cache");
98 * Read the Cache Build Confuration Registers, Decode them and save into
99 * the cpuinfo structure for later use.
100 * No Validation done here, simply read/convert the BCRs
102 void read_decode_cache_bcr(void)
104 struct cpuinfo_arc_cache
*p_ic
, *p_dc
;
105 unsigned int cpu
= smp_processor_id();
107 #ifdef CONFIG_CPU_BIG_ENDIAN
108 unsigned int pad
:12, line_len
:4, sz
:4, config
:4, ver
:8;
110 unsigned int ver
:8, config
:4, sz
:4, line_len
:4, pad
:12;
114 p_ic
= &cpuinfo_arc700
[cpu
].icache
;
115 READ_BCR(ARC_REG_IC_BCR
, ibcr
);
120 BUG_ON(ibcr
.config
!= 3);
121 p_ic
->assoc
= 2; /* Fixed to 2w set assoc */
122 p_ic
->line_len
= 8 << ibcr
.line_len
;
123 p_ic
->sz_k
= 1 << (ibcr
.sz
- 1);
124 p_ic
->ver
= ibcr
.ver
;
126 p_ic
->alias
= p_ic
->sz_k
/p_ic
->assoc
/TO_KB(PAGE_SIZE
) > 1;
129 p_dc
= &cpuinfo_arc700
[cpu
].dcache
;
130 READ_BCR(ARC_REG_DC_BCR
, dbcr
);
135 BUG_ON(dbcr
.config
!= 2);
136 p_dc
->assoc
= 4; /* Fixed to 4w set assoc */
137 p_dc
->line_len
= 16 << dbcr
.line_len
;
138 p_dc
->sz_k
= 1 << (dbcr
.sz
- 1);
139 p_dc
->ver
= dbcr
.ver
;
141 p_dc
->alias
= p_dc
->sz_k
/p_dc
->assoc
/TO_KB(PAGE_SIZE
) > 1;
145 * 1. Validate the Cache Geomtery (compile time config matches hardware)
146 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
147 * (aliasing D-cache configurations are not supported YET)
148 * 3. Enable the Caches, setup default flush mode for D-Cache
149 * 3. Calculate the SHMLBA used by user space
151 void arc_cache_init(void)
153 unsigned int __maybe_unused cpu
= smp_processor_id();
156 printk(arc_cache_mumbojumbo(0, str
, sizeof(str
)));
158 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE
)) {
159 struct cpuinfo_arc_cache
*ic
= &cpuinfo_arc700
[cpu
].icache
;
162 panic("cache support enabled but non-existent cache\n");
164 if (ic
->line_len
!= L1_CACHE_BYTES
)
165 panic("ICache line [%d] != kernel Config [%d]",
166 ic
->line_len
, L1_CACHE_BYTES
);
168 if (ic
->ver
!= CONFIG_ARC_MMU_VER
)
169 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
170 ic
->ver
, CONFIG_ARC_MMU_VER
);
173 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE
)) {
174 struct cpuinfo_arc_cache
*dc
= &cpuinfo_arc700
[cpu
].dcache
;
178 panic("cache support enabled but non-existent cache\n");
180 if (dc
->line_len
!= L1_CACHE_BYTES
)
181 panic("DCache line [%d] != kernel Config [%d]",
182 dc
->line_len
, L1_CACHE_BYTES
);
184 /* check for D-Cache aliasing */
185 handled
= IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING
);
187 if (dc
->alias
&& !handled
)
188 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
189 else if (!dc
->alias
&& handled
)
190 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
196 #define OP_FLUSH_N_INV 0x3
197 #define OP_INV_IC 0x4
200 * Common Helper for Line Operations on {I,D}-Cache
202 static inline void __cache_line_loop(unsigned long paddr
, unsigned long vaddr
,
203 unsigned long sz
, const int cacheop
)
205 unsigned int aux_cmd
, aux_tag
;
207 const int full_page_op
= __builtin_constant_p(sz
) && sz
== PAGE_SIZE
;
209 if (cacheop
== OP_INV_IC
) {
210 aux_cmd
= ARC_REG_IC_IVIL
;
211 #if (CONFIG_ARC_MMU_VER > 2)
212 aux_tag
= ARC_REG_IC_PTAG
;
216 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
217 aux_cmd
= cacheop
& OP_INV
? ARC_REG_DC_IVDL
: ARC_REG_DC_FLDL
;
218 #if (CONFIG_ARC_MMU_VER > 2)
219 aux_tag
= ARC_REG_DC_PTAG
;
223 /* Ensure we properly floor/ceil the non-line aligned/sized requests
224 * and have @paddr - aligned to cache line and integral @num_lines.
225 * This however can be avoided for page sized since:
226 * -@paddr will be cache-line aligned already (being page aligned)
227 * -@sz will be integral multiple of line size (being page sized).
230 sz
+= paddr
& ~CACHE_LINE_MASK
;
231 paddr
&= CACHE_LINE_MASK
;
232 vaddr
&= CACHE_LINE_MASK
;
235 num_lines
= DIV_ROUND_UP(sz
, L1_CACHE_BYTES
);
237 #if (CONFIG_ARC_MMU_VER <= 2)
238 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
239 paddr
|= (vaddr
>> PAGE_SHIFT
) & 0x1F;
241 /* if V-P const for loop, PTAG can be written once outside loop */
243 write_aux_reg(aux_tag
, paddr
);
246 while (num_lines
-- > 0) {
247 #if (CONFIG_ARC_MMU_VER > 2)
248 /* MMUv3, cache ops require paddr seperately */
250 write_aux_reg(aux_tag
, paddr
);
251 paddr
+= L1_CACHE_BYTES
;
254 write_aux_reg(aux_cmd
, vaddr
);
255 vaddr
+= L1_CACHE_BYTES
;
257 write_aux_reg(aux_cmd
, paddr
);
258 paddr
+= L1_CACHE_BYTES
;
263 #ifdef CONFIG_ARC_HAS_DCACHE
265 /***************************************************************
266 * Machine specific helpers for Entire D-Cache or Per Line ops
269 static inline void wait_for_flush(void)
271 while (read_aux_reg(ARC_REG_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
276 * Operation on Entire D-Cache
277 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
278 * Note that constant propagation ensures all the checks are gone
281 static inline void __dc_entire_op(const int cacheop
)
283 unsigned int tmp
= tmp
;
286 if (cacheop
== OP_FLUSH_N_INV
) {
287 /* Dcache provides 2 cmd: FLUSH or INV
288 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
289 * flush-n-inv is achieved by INV cmd but with IM=1
290 * Default INV sub-mode is DISCARD, which needs to be toggled
292 tmp
= read_aux_reg(ARC_REG_DC_CTRL
);
293 write_aux_reg(ARC_REG_DC_CTRL
, tmp
| DC_CTRL_INV_MODE_FLUSH
);
296 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
297 aux
= ARC_REG_DC_IVDC
;
299 aux
= ARC_REG_DC_FLSH
;
301 write_aux_reg(aux
, 0x1);
303 if (cacheop
& OP_FLUSH
) /* flush / flush-n-inv both wait */
306 /* Switch back the DISCARD ONLY Invalidate mode */
307 if (cacheop
== OP_FLUSH_N_INV
)
308 write_aux_reg(ARC_REG_DC_CTRL
, tmp
& ~DC_CTRL_INV_MODE_FLUSH
);
311 /* For kernel mappings cache operation: index is same as paddr */
312 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
315 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
317 static inline void __dc_line_op(unsigned long paddr
, unsigned long vaddr
,
318 unsigned long sz
, const int cacheop
)
320 unsigned long flags
, tmp
= tmp
;
322 local_irq_save(flags
);
324 if (cacheop
== OP_FLUSH_N_INV
) {
326 * Dcache provides 2 cmd: FLUSH or INV
327 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
328 * flush-n-inv is achieved by INV cmd but with IM=1
329 * Default INV sub-mode is DISCARD, which needs to be toggled
331 tmp
= read_aux_reg(ARC_REG_DC_CTRL
);
332 write_aux_reg(ARC_REG_DC_CTRL
, tmp
| DC_CTRL_INV_MODE_FLUSH
);
335 __cache_line_loop(paddr
, vaddr
, sz
, cacheop
);
337 if (cacheop
& OP_FLUSH
) /* flush / flush-n-inv both wait */
340 /* Switch back the DISCARD ONLY Invalidate mode */
341 if (cacheop
== OP_FLUSH_N_INV
)
342 write_aux_reg(ARC_REG_DC_CTRL
, tmp
& ~DC_CTRL_INV_MODE_FLUSH
);
344 local_irq_restore(flags
);
349 #define __dc_entire_op(cacheop)
350 #define __dc_line_op(paddr, vaddr, sz, cacheop)
351 #define __dc_line_op_k(paddr, sz, cacheop)
353 #endif /* CONFIG_ARC_HAS_DCACHE */
356 #ifdef CONFIG_ARC_HAS_ICACHE
359 * I-Cache Aliasing in ARC700 VIPT caches
361 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
362 * The orig Cache Management Module "CDU" only required paddr to invalidate a
363 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
364 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
365 * the exact same line.
367 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
368 * paddr alone could not be used to correctly index the cache.
371 * MMU v1/v2 (Fixed Page Size 8k)
373 * The solution was to provide CDU with these additonal vaddr bits. These
374 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
375 * standard page size of 8k.
376 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
377 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
378 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
379 * represent the offset within cache-line. The adv of using this "clumsy"
380 * interface for additional info was no new reg was needed in CDU programming
383 * 17:13 represented the max num of bits passable, actual bits needed were
384 * fewer, based on the num-of-aliases possible.
385 * -for 2 alias possibility, only bit 13 needed (32K cache)
386 * -for 4 alias possibility, bits 14:13 needed (64K cache)
391 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
392 * only support 8k (default), 16k and 4k.
393 * However from hardware perspective, smaller page sizes aggrevate aliasing
394 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
395 * the existing scheme of piggybacking won't work for certain configurations.
396 * Two new registers IC_PTAG and DC_PTAG inttoduced.
397 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
400 /***********************************************************
401 * Machine specific helper for per line I-Cache invalidate.
403 static void __ic_line_inv_vaddr_local(unsigned long paddr
, unsigned long vaddr
,
408 local_irq_save(flags
);
409 __cache_line_loop(paddr
, vaddr
, sz
, OP_INV_IC
);
410 local_irq_restore(flags
);
413 static inline void __ic_entire_inv(void)
415 write_aux_reg(ARC_REG_IC_IVIC
, 1);
416 read_aux_reg(ARC_REG_IC_CTRL
); /* blocks */
419 struct ic_line_inv_vaddr_ipi
{
420 unsigned long paddr
, vaddr
;
424 static void __ic_line_inv_vaddr_helper(void *info
)
426 struct ic_line_inv_vaddr_ipi
*ic_inv
= (struct ic_line_inv_vaddr_ipi
*) info
;
427 __ic_line_inv_vaddr_local(ic_inv
->paddr
, ic_inv
->vaddr
, ic_inv
->sz
);
430 static void __ic_line_inv_vaddr(unsigned long paddr
, unsigned long vaddr
,
433 struct ic_line_inv_vaddr_ipi ic_inv
= { paddr
, vaddr
, sz
};
434 on_each_cpu(__ic_line_inv_vaddr_helper
, &ic_inv
, 1);
438 #define __ic_entire_inv()
439 #define __ic_line_inv_vaddr(pstart, vstart, sz)
441 #endif /* CONFIG_ARC_HAS_ICACHE */
444 /***********************************************************
449 * Handle cache congruency of kernel and userspace mappings of page when kernel
450 * writes-to/reads-from
452 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
453 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
454 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
455 * -In SMP, if hardware caches are coherent
457 * There's a corollary case, where kernel READs from a userspace mapped page.
458 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
460 void flush_dcache_page(struct page
*page
)
462 struct address_space
*mapping
;
464 if (!cache_is_vipt_aliasing()) {
465 clear_bit(PG_dc_clean
, &page
->flags
);
469 /* don't handle anon pages here */
470 mapping
= page_mapping(page
);
475 * pagecache page, file not yet mapped to userspace
476 * Make a note that K-mapping is dirty
478 if (!mapping_mapped(mapping
)) {
479 clear_bit(PG_dc_clean
, &page
->flags
);
480 } else if (page_mapped(page
)) {
482 /* kernel reading from page with U-mapping */
483 void *paddr
= page_address(page
);
484 unsigned long vaddr
= page
->index
<< PAGE_CACHE_SHIFT
;
486 if (addr_not_cache_congruent(paddr
, vaddr
))
487 __flush_dcache_page(paddr
, vaddr
);
490 EXPORT_SYMBOL(flush_dcache_page
);
493 void dma_cache_wback_inv(unsigned long start
, unsigned long sz
)
495 __dc_line_op_k(start
, sz
, OP_FLUSH_N_INV
);
497 EXPORT_SYMBOL(dma_cache_wback_inv
);
499 void dma_cache_inv(unsigned long start
, unsigned long sz
)
501 __dc_line_op_k(start
, sz
, OP_INV
);
503 EXPORT_SYMBOL(dma_cache_inv
);
505 void dma_cache_wback(unsigned long start
, unsigned long sz
)
507 __dc_line_op_k(start
, sz
, OP_FLUSH
);
509 EXPORT_SYMBOL(dma_cache_wback
);
512 * This is API for making I/D Caches consistent when modifying
513 * kernel code (loadable modules, kprobes, kgdb...)
514 * This is called on insmod, with kernel virtual address for CODE of
515 * the module. ARC cache maintenance ops require PHY address thus we
516 * need to convert vmalloc addr to PHY addr
518 void flush_icache_range(unsigned long kstart
, unsigned long kend
)
520 unsigned int tot_sz
, off
, sz
;
521 unsigned long phy
, pfn
;
523 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
525 /* This is not the right API for user virtual address */
526 if (kstart
< TASK_SIZE
) {
527 BUG_ON("Flush icache range for user virtual addr space");
531 /* Shortcut for bigger flush ranges.
532 * Here we don't care if this was kernel virtual or phy addr
534 tot_sz
= kend
- kstart
;
535 if (tot_sz
> PAGE_SIZE
) {
540 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
541 if (likely(kstart
> PAGE_OFFSET
)) {
543 * The 2nd arg despite being paddr will be used to index icache
544 * This is OK since no alternate virtual mappings will exist
545 * given the callers for this case: kprobe/kgdb in built-in
548 __sync_icache_dcache(kstart
, kstart
, kend
- kstart
);
553 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
554 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
555 * handling of kernel vaddr.
557 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
558 * it still needs to handle a 2 page scenario, where the range
559 * straddles across 2 virtual pages and hence need for loop
562 off
= kstart
% PAGE_SIZE
;
563 pfn
= vmalloc_to_pfn((void *)kstart
);
564 phy
= (pfn
<< PAGE_SHIFT
) + off
;
565 sz
= min_t(unsigned int, tot_sz
, PAGE_SIZE
- off
);
566 __sync_icache_dcache(phy
, kstart
, sz
);
573 * General purpose helper to make I and D cache lines consistent.
574 * @paddr is phy addr of region
575 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
576 * However in one instance, when called by kprobe (for a breakpt in
577 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
578 * use a paddr to index the cache (despite VIPT). This is fine since since a
579 * builtin kernel page will not have any virtual mappings.
580 * kprobe on loadable module will be kernel vaddr.
582 void __sync_icache_dcache(unsigned long paddr
, unsigned long vaddr
, int len
)
584 __dc_line_op(paddr
, vaddr
, len
, OP_FLUSH_N_INV
);
585 __ic_line_inv_vaddr(paddr
, vaddr
, len
);
588 /* wrapper to compile time eliminate alignment checks in flush loop */
589 void __inv_icache_page(unsigned long paddr
, unsigned long vaddr
)
591 __ic_line_inv_vaddr(paddr
, vaddr
, PAGE_SIZE
);
595 * wrapper to clearout kernel or userspace mappings of a page
596 * For kernel mappings @vaddr == @paddr
598 void ___flush_dcache_page(unsigned long paddr
, unsigned long vaddr
)
600 __dc_line_op(paddr
, vaddr
& PAGE_MASK
, PAGE_SIZE
, OP_FLUSH_N_INV
);
603 noinline
void flush_cache_all(void)
607 local_irq_save(flags
);
610 __dc_entire_op(OP_FLUSH_N_INV
);
612 local_irq_restore(flags
);
616 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
618 void flush_cache_mm(struct mm_struct
*mm
)
623 void flush_cache_page(struct vm_area_struct
*vma
, unsigned long u_vaddr
,
626 unsigned int paddr
= pfn
<< PAGE_SHIFT
;
628 u_vaddr
&= PAGE_MASK
;
630 ___flush_dcache_page(paddr
, u_vaddr
);
632 if (vma
->vm_flags
& VM_EXEC
)
633 __inv_icache_page(paddr
, u_vaddr
);
636 void flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
,
642 void flush_anon_page(struct vm_area_struct
*vma
, struct page
*page
,
643 unsigned long u_vaddr
)
645 /* TBD: do we really need to clear the kernel mapping */
646 __flush_dcache_page(page_address(page
), u_vaddr
);
647 __flush_dcache_page(page_address(page
), page_address(page
));
653 void copy_user_highpage(struct page
*to
, struct page
*from
,
654 unsigned long u_vaddr
, struct vm_area_struct
*vma
)
656 void *kfrom
= page_address(from
);
657 void *kto
= page_address(to
);
658 int clean_src_k_mappings
= 0;
661 * If SRC page was already mapped in userspace AND it's U-mapping is
662 * not congruent with K-mapping, sync former to physical page so that
663 * K-mapping in memcpy below, sees the right data
665 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
666 * equally valid for SRC page as well
668 if (page_mapped(from
) && addr_not_cache_congruent(kfrom
, u_vaddr
)) {
669 __flush_dcache_page(kfrom
, u_vaddr
);
670 clean_src_k_mappings
= 1;
673 copy_page(kto
, kfrom
);
676 * Mark DST page K-mapping as dirty for a later finalization by
677 * update_mmu_cache(). Although the finalization could have been done
678 * here as well (given that both vaddr/paddr are available).
679 * But update_mmu_cache() already has code to do that for other
680 * non copied user pages (e.g. read faults which wire in pagecache page
683 clear_bit(PG_dc_clean
, &to
->flags
);
686 * if SRC was already usermapped and non-congruent to kernel mapping
687 * sync the kernel mapping back to physical page
689 if (clean_src_k_mappings
) {
690 __flush_dcache_page(kfrom
, kfrom
);
691 set_bit(PG_dc_clean
, &from
->flags
);
693 clear_bit(PG_dc_clean
, &from
->flags
);
697 void clear_user_page(void *to
, unsigned long u_vaddr
, struct page
*page
)
700 clear_bit(PG_dc_clean
, &page
->flags
);
704 /**********************************************************************
705 * Explicit Cache flush request from user space via syscall
706 * Needed for JITs which generate code on the fly
708 SYSCALL_DEFINE3(cacheflush
, uint32_t, start
, uint32_t, sz
, uint32_t, flags
)
710 /* TBD: optimize this */