2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DMA Coherent API Notes
12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
13 * implemented by accessintg it using a kernel virtual address, with
14 * Cache bit off in the TLB entry.
16 * The default DMA address == Phy address which is 0x8000_0000 based.
19 #include <linux/dma-mapping.h>
20 #include <asm/cache.h>
21 #include <asm/cacheflush.h>
24 static void *arc_dma_alloc(struct device
*dev
, size_t size
,
25 dma_addr_t
*dma_handle
, gfp_t gfp
, struct dma_attrs
*attrs
)
27 unsigned long order
= get_order(size
);
31 int need_coh
= 1, need_kvaddr
= 0;
33 page
= alloc_pages(gfp
, order
);
38 * IOC relies on all data (even coherent DMA data) being in cache
39 * Thus allocate normal cached memory
41 * The gains with IOC are two pronged:
42 * -For streaming data, elides need for cache maintenance, saving
43 * cycles in flush code, and bus bandwidth as all the lines of a
44 * buffer need to be flushed out to memory
45 * -For coherent data, Read/Write to buffers terminate early in cache
46 * (vs. always going to memory - thus are faster)
48 if ((is_isa_arcv2() && ioc_exists
) ||
49 dma_get_attr(DMA_ATTR_NON_CONSISTENT
, attrs
))
53 * - A coherent buffer needs MMU mapping to enforce non-cachability
54 * - A highmem page needs a virtual handle (hence MMU mapping)
55 * independent of cachability
57 if (PageHighMem(page
) || need_coh
)
60 /* This is linear addr (0x8000_0000 based) */
61 paddr
= page_to_phys(page
);
63 /* For now bus address is exactly same as paddr */
66 /* This is kernel Virtual address (0x7000_0000 based) */
68 kvaddr
= ioremap_nocache((unsigned long)paddr
, size
);
70 __free_pages(page
, order
);
74 kvaddr
= (void *)paddr
;
78 * Evict any existing L1 and/or L2 lines for the backing page
79 * in case it was used earlier as a normal "cached" page.
80 * Yeah this bit us - STAR 9000898266
82 * Although core does call flush_cache_vmap(), it gets kvaddr hence
83 * can't be used to efficiently flush L1 and/or L2 which need paddr
84 * Currently flush_cache_vmap nukes the L1 cache completely which
85 * will be optimized as a separate commit
88 dma_cache_wback_inv((unsigned long)paddr
, size
);
93 static void arc_dma_free(struct device
*dev
, size_t size
, void *vaddr
,
94 dma_addr_t dma_handle
, struct dma_attrs
*attrs
)
96 struct page
*page
= virt_to_page(dma_handle
);
99 is_non_coh
= dma_get_attr(DMA_ATTR_NON_CONSISTENT
, attrs
) ||
100 (is_isa_arcv2() && ioc_exists
);
102 if (PageHighMem(page
) || !is_non_coh
)
103 iounmap((void __force __iomem
*)vaddr
);
105 __free_pages(page
, get_order(size
));
109 * streaming DMA Mapping API...
110 * CPU accesses page via normal paddr, thus needs to explicitly made
111 * consistent before each use
113 static void _dma_cache_sync(unsigned long paddr
, size_t size
,
114 enum dma_data_direction dir
)
117 case DMA_FROM_DEVICE
:
118 dma_cache_inv(paddr
, size
);
121 dma_cache_wback(paddr
, size
);
123 case DMA_BIDIRECTIONAL
:
124 dma_cache_wback_inv(paddr
, size
);
127 pr_err("Invalid DMA dir [%d] for OP @ %lx\n", dir
, paddr
);
131 static dma_addr_t
arc_dma_map_page(struct device
*dev
, struct page
*page
,
132 unsigned long offset
, size_t size
, enum dma_data_direction dir
,
133 struct dma_attrs
*attrs
)
135 unsigned long paddr
= page_to_phys(page
) + offset
;
136 _dma_cache_sync(paddr
, size
, dir
);
137 return (dma_addr_t
)paddr
;
140 static int arc_dma_map_sg(struct device
*dev
, struct scatterlist
*sg
,
141 int nents
, enum dma_data_direction dir
, struct dma_attrs
*attrs
)
143 struct scatterlist
*s
;
146 for_each_sg(sg
, s
, nents
, i
)
147 s
->dma_address
= dma_map_page(dev
, sg_page(s
), s
->offset
,
153 static void arc_dma_sync_single_for_cpu(struct device
*dev
,
154 dma_addr_t dma_handle
, size_t size
, enum dma_data_direction dir
)
156 _dma_cache_sync(dma_handle
, size
, DMA_FROM_DEVICE
);
159 static void arc_dma_sync_single_for_device(struct device
*dev
,
160 dma_addr_t dma_handle
, size_t size
, enum dma_data_direction dir
)
162 _dma_cache_sync(dma_handle
, size
, DMA_TO_DEVICE
);
165 static void arc_dma_sync_sg_for_cpu(struct device
*dev
,
166 struct scatterlist
*sglist
, int nelems
,
167 enum dma_data_direction dir
)
170 struct scatterlist
*sg
;
172 for_each_sg(sglist
, sg
, nelems
, i
)
173 _dma_cache_sync((unsigned int)sg_virt(sg
), sg
->length
, dir
);
176 static void arc_dma_sync_sg_for_device(struct device
*dev
,
177 struct scatterlist
*sglist
, int nelems
,
178 enum dma_data_direction dir
)
181 struct scatterlist
*sg
;
183 for_each_sg(sglist
, sg
, nelems
, i
)
184 _dma_cache_sync((unsigned int)sg_virt(sg
), sg
->length
, dir
);
187 static int arc_dma_supported(struct device
*dev
, u64 dma_mask
)
189 /* Support 32 bit DMA mask exclusively */
190 return dma_mask
== DMA_BIT_MASK(32);
193 struct dma_map_ops arc_dma_ops
= {
194 .alloc
= arc_dma_alloc
,
195 .free
= arc_dma_free
,
196 .map_page
= arc_dma_map_page
,
197 .map_sg
= arc_dma_map_sg
,
198 .sync_single_for_device
= arc_dma_sync_single_for_device
,
199 .sync_single_for_cpu
= arc_dma_sync_single_for_cpu
,
200 .sync_sg_for_cpu
= arc_dma_sync_sg_for_cpu
,
201 .sync_sg_for_device
= arc_dma_sync_sg_for_device
,
202 .dma_supported
= arc_dma_supported
,
204 EXPORT_SYMBOL(arc_dma_ops
);