arch/arc/plat-arcfpga/platform.c

   1 /*
   2  * ARC FPGA Platform support code
   3  *
   4  * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/io.h>
  16 #include <linux/console.h>
  17 #include <linux/of_platform.h>
  18 #include <asm/setup.h>
  19 #include <asm/clk.h>
  20 #include <asm/mach_desc.h>
  21 #include <plat/memmap.h>
  22 #include <plat/smp.h>
  23 #include <plat/irq.h>
  24
  25 /*-----------------------BVCI Latency Unit -----------------------------*/
  26
  27 #ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
  28
  29 int lat_cycles = CONFIG_BVCI_LAT_CYCLES;
  30
  31 /* BVCI Bus Profiler: Latency Unit */
  32 static void __init setup_bvci_lat_unit(void)
  33 {
  34 #define MAX_BVCI_UNITS 12
  35
  36         unsigned int i;
  37         unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE;
  38         const unsigned long units_req = CONFIG_BVCI_LAT_UNITS;
  39         const unsigned int REG_UNIT = 21;
  40         const unsigned int REG_VAL = 22;
  41
  42         /*
  43          * There are multiple Latency Units corresponding to the many
  44          * interfaces of the system bus arbiter (both CPU side as well as
  45          * the peripheral side).
  46          *
  47          * Unit  0 - System Arb and Mem Controller - adds latency to all
  48          *          memory trasactions
  49          * Unit  1 - I$ and System Bus
  50          * Unit  2 - D$ and System Bus
  51          * ..
  52          * Unit 12 - IDE Disk controller and System Bus
  53          *
  54          * The programmers model requires writing to lat_unit reg first
  55          * and then the latency value (cycles) to lat_value reg
  56          */
  57
  58         if (CONFIG_BVCI_LAT_UNITS == 0) {
  59                 writel(0, base + REG_UNIT);
  60                 writel(lat_cycles, base + REG_VAL);
  61                 pr_info("BVCI Latency for all Memory Transactions %d cycles\n",
  62                         lat_cycles);
  63         } else {
  64                 for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) {
  65                         writel(i + 1, base + REG_UNIT); /* loop is 0 based */
  66                         writel(lat_cycles, base + REG_VAL);
  67                         pr_info("BVCI Latency for Unit[%d] = %d cycles\n",
  68                                 (i + 1), lat_cycles);
  69                 }
  70         }
  71 }
  72 #else
  73 static void __init setup_bvci_lat_unit(void)
  74 {
  75 }
  76 #endif
  77
  78 /*----------------------- Platform Devices -----------------------------*/
  79
  80 static unsigned long arc_uart_info[] = {
  81         0,      /* uart->is_emulated (runtime @running_on_hw) */
  82         0,      /* uart->port.uartclk */
  83         0,      /* uart->baud */
  84         0
  85 };
  86
  87 #if defined(CONFIG_SERIAL_ARC_CONSOLE)
  88 /*
  89  * static platform data - but only for early serial
  90  * TBD: derive this from a special DT node
  91  */
  92 static struct resource arc_uart0_res[] = {
  93         {
  94                 .start = UART0_BASE,
  95                 .end   = UART0_BASE + 0xFF,
  96                 .flags = IORESOURCE_MEM,
  97         },
  98         {
  99                 .start = UART0_IRQ,
 100                 .end   = UART0_IRQ,
 101                 .flags = IORESOURCE_IRQ,
 102         },
 103 };
 104
 105 static struct platform_device arc_uart0_dev = {
 106         .name = "arc-uart",
 107         .id = 0,
 108         .num_resources = ARRAY_SIZE(arc_uart0_res),
 109         .resource = arc_uart0_res,
 110         .dev = {
 111                 .platform_data = &arc_uart_info,
 112         },
 113 };
 114
 115 static struct platform_device *fpga_early_devs[] __initdata = {
 116         &arc_uart0_dev,
 117 };
 118 #endif
 119
 120 static void arc_fpga_serial_init(void)
 121 {
 122         /* To let driver workaround ISS bug: baudh Reg can't be set to 0 */
 123         arc_uart_info[0] = !running_on_hw;
 124
 125         arc_uart_info[1] = arc_get_core_freq();
 126
 127         arc_uart_info[2] = CONFIG_ARC_SERIAL_BAUD;
 128
 129 #if defined(CONFIG_SERIAL_ARC_CONSOLE)
 130         early_platform_add_devices(fpga_early_devs,
 131                                    ARRAY_SIZE(fpga_early_devs));
 132
 133         /*
 134          * ARC console driver registers itself as an early platform driver
 135          * of class "earlyprintk".
 136          * Install it here, followed by probe of devices.
 137          * The installation here doesn't require earlyprintk in command line
 138          * To do so however, replace the lines below with
 139          *      parse_early_param();
 140          *      early_platform_driver_probe("earlyprintk", 1, 1);
 141          *                                                    ^^
 142          */
 143         early_platform_driver_register_all("earlyprintk");
 144         early_platform_driver_probe("earlyprintk", 1, 0);
 145
 146         /*
 147          * This is to make sure that arc uart would be preferred console
 148          * despite one/more of following:
 149          *   -command line lacked "console=ttyARC0" or
 150          *   -CONFIG_VT_CONSOLE was enabled (for no reason whatsoever)
 151          * Note that this needs to be done after above early console is reg,
 152          * otherwise the early console never gets a chance to run.
 153          */
 154         add_preferred_console("ttyARC", 0, "115200");
 155 #endif
 156 }
 157
 158 static void __init plat_fpga_early_init(void)
 159 {
 160         pr_info("[plat-arcfpga]: registering early dev resources\n");
 161
 162         setup_bvci_lat_unit();
 163
 164         arc_fpga_serial_init();
 165 }
 166
 167 static struct of_dev_auxdata plat_auxdata_lookup[] __initdata = {
 168 #if defined(CONFIG_SERIAL_ARC) || defined(CONFIG_SERIAL_ARC_MODULE)
 169         OF_DEV_AUXDATA("snps,arc-uart", UART0_BASE, "arc-uart", arc_uart_info),
 170 #endif
 171         {}
 172 };
 173
 174 static void __init plat_fpga_populate_dev(void)
 175 {
 176         pr_info("[plat-arcfpga]: registering device resources\n");
 177
 178         /*
 179          * Traverses flattened DeviceTree - registering platform devices
 180          * complete with their resources
 181          */
 182         of_platform_populate(NULL, of_default_bus_match_table,
 183                              plat_auxdata_lookup, NULL);
 184 }
 185
 186 /*----------------------- Machine Descriptions ------------------------------
 187  *
 188  * Machine description is simply a set of platform/board specific callbacks
 189  * This is not directly related to DeviceTree based dynamic device creation,
 190  * however as part of early device tree scan, we also select the right
 191  * callback set, by matching the DT compatible name.
 192  */
 193
 194 static const char *aa4_compat[] __initdata = {
 195         "snps,arc-angel4",
 196         NULL,
 197 };
 198
 199 MACHINE_START(ANGEL4, "angel4")
 200         .dt_compat      = aa4_compat,
 201         .init_early     = plat_fpga_early_init,
 202         .init_machine   = plat_fpga_populate_dev,
 203         .init_irq       = plat_fpga_init_IRQ,
 204 #ifdef CONFIG_SMP
 205         .init_smp       = iss_model_init_smp,
 206 #endif
 207 MACHINE_END
 208
 209 static const char *ml509_compat[] __initdata = {
 210         "snps,arc-ml509",
 211         NULL,
 212 };
 213
 214 MACHINE_START(ML509, "ml509")
 215         .dt_compat      = ml509_compat,
 216         .init_early     = plat_fpga_early_init,
 217         .init_machine   = plat_fpga_populate_dev,
 218         .init_irq       = plat_fpga_init_IRQ,
 219 #ifdef CONFIG_SMP
 220         .init_smp       = iss_model_init_smp,
 221 #endif
 222 MACHINE_END