arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_IRQ_SHOW_LEVEL
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARM_SINGLE_ARMV7M
 333         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 334         depends on !MMU
 335         select ARCH_WANT_OPTIONAL_GPIOLIB
 336         select ARM_NVIC
 337         select AUTO_ZRELADDR
 338         select CLKSRC_OF
 339         select COMMON_CLK
 340         select CPU_V7M
 341         select GENERIC_CLOCKEVENTS
 342         select NO_IOPORT_MAP
 343         select SPARSE_IRQ
 344         select USE_OF
 345
 346 config ARCH_REALVIEW
 347         bool "ARM Ltd. RealView family"
 348         select ARCH_WANT_OPTIONAL_GPIOLIB
 349         select ARM_AMBA
 350         select ARM_TIMER_SP804
 351         select COMMON_CLK
 352         select COMMON_CLK_VERSATILE
 353         select GENERIC_CLOCKEVENTS
 354         select GPIO_PL061 if GPIOLIB
 355         select ICST
 356         select NEED_MACH_MEMORY_H
 357         select PLAT_VERSATILE
 358         select PLAT_VERSATILE_SCHED_CLOCK
 359         help
 360           This enables support for ARM Ltd RealView boards.
 361
 362 config ARCH_VERSATILE
 363         bool "ARM Ltd. Versatile family"
 364         select ARCH_WANT_OPTIONAL_GPIOLIB
 365         select ARM_AMBA
 366         select ARM_TIMER_SP804
 367         select ARM_VIC
 368         select CLKDEV_LOOKUP
 369         select GENERIC_CLOCKEVENTS
 370         select HAVE_MACH_CLKDEV
 371         select ICST
 372         select PLAT_VERSATILE
 373         select PLAT_VERSATILE_CLOCK
 374         select PLAT_VERSATILE_SCHED_CLOCK
 375         select VERSATILE_FPGA_IRQ
 376         help
 377           This enables support for ARM Ltd Versatile board.
 378
 379 config ARCH_CLPS711X
 380         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 381         select ARCH_REQUIRE_GPIOLIB
 382         select AUTO_ZRELADDR
 383         select CLKSRC_MMIO
 384         select COMMON_CLK
 385         select CPU_ARM720T
 386         select GENERIC_CLOCKEVENTS
 387         select MFD_SYSCON
 388         select SOC_BUS
 389         help
 390           Support for Cirrus Logic 711x/721x/731x based boards.
 391
 392 config ARCH_GEMINI
 393         bool "Cortina Systems Gemini"
 394         select ARCH_REQUIRE_GPIOLIB
 395         select CLKSRC_MMIO
 396         select CPU_FA526
 397         select GENERIC_CLOCKEVENTS
 398         help
 399           Support for the Cortina Systems Gemini family SoCs
 400
 401 config ARCH_EBSA110
 402         bool "EBSA-110"
 403         select ARCH_USES_GETTIMEOFFSET
 404         select CPU_SA110
 405         select ISA
 406         select NEED_MACH_IO_H
 407         select NEED_MACH_MEMORY_H
 408         select NO_IOPORT_MAP
 409         help
 410           This is an evaluation board for the StrongARM processor available
 411           from Digital. It has limited hardware on-board, including an
 412           Ethernet interface, two PCMCIA sockets, two serial ports and a
 413           parallel port.
 414
 415 config ARCH_EP93XX
 416         bool "EP93xx-based"
 417         select ARCH_HAS_HOLES_MEMORYMODEL
 418         select ARCH_REQUIRE_GPIOLIB
 419         select ARCH_USES_GETTIMEOFFSET
 420         select ARM_AMBA
 421         select ARM_VIC
 422         select CLKDEV_LOOKUP
 423         select CPU_ARM920T
 424         help
 425           This enables support for the Cirrus EP93xx series of CPUs.
 426
 427 config ARCH_FOOTBRIDGE
 428         bool "FootBridge"
 429         select CPU_SA110
 430         select FOOTBRIDGE
 431         select GENERIC_CLOCKEVENTS
 432         select HAVE_IDE
 433         select NEED_MACH_IO_H if !MMU
 434         select NEED_MACH_MEMORY_H
 435         help
 436           Support for systems based on the DC21285 companion chip
 437           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 438
 439 config ARCH_NETX
 440         bool "Hilscher NetX based"
 441         select ARM_VIC
 442         select CLKSRC_MMIO
 443         select CPU_ARM926T
 444         select GENERIC_CLOCKEVENTS
 445         help
 446           This enables support for systems based on the Hilscher NetX Soc
 447
 448 config ARCH_IOP13XX
 449         bool "IOP13xx-based"
 450         depends on MMU
 451         select CPU_XSC3
 452         select NEED_MACH_MEMORY_H
 453         select NEED_RET_TO_USER
 454         select PCI
 455         select PLAT_IOP
 456         select VMSPLIT_1G
 457         select SPARSE_IRQ
 458         help
 459           Support for Intel's IOP13XX (XScale) family of processors.
 460
 461 config ARCH_IOP32X
 462         bool "IOP32x-based"
 463         depends on MMU
 464         select ARCH_REQUIRE_GPIOLIB
 465         select CPU_XSCALE
 466         select GPIO_IOP
 467         select NEED_RET_TO_USER
 468         select PCI
 469         select PLAT_IOP
 470         help
 471           Support for Intel's 80219 and IOP32X (XScale) family of
 472           processors.
 473
 474 config ARCH_IOP33X
 475         bool "IOP33x-based"
 476         depends on MMU
 477         select ARCH_REQUIRE_GPIOLIB
 478         select CPU_XSCALE
 479         select GPIO_IOP
 480         select NEED_RET_TO_USER
 481         select PCI
 482         select PLAT_IOP
 483         help
 484           Support for Intel's IOP33X (XScale) family of processors.
 485
 486 config ARCH_IXP4XX
 487         bool "IXP4xx-based"
 488         depends on MMU
 489         select ARCH_HAS_DMA_SET_COHERENT_MASK
 490         select ARCH_REQUIRE_GPIOLIB
 491         select ARCH_SUPPORTS_BIG_ENDIAN
 492         select CLKSRC_MMIO
 493         select CPU_XSCALE
 494         select DMABOUNCE if PCI
 495         select GENERIC_CLOCKEVENTS
 496         select MIGHT_HAVE_PCI
 497         select NEED_MACH_IO_H
 498         select USB_EHCI_BIG_ENDIAN_DESC
 499         select USB_EHCI_BIG_ENDIAN_MMIO
 500         help
 501           Support for Intel's IXP4XX (XScale) family of processors.
 502
 503 config ARCH_DOVE
 504         bool "Marvell Dove"
 505         select ARCH_REQUIRE_GPIOLIB
 506         select CPU_PJ4
 507         select GENERIC_CLOCKEVENTS
 508         select MIGHT_HAVE_PCI
 509         select MVEBU_MBUS
 510         select PINCTRL
 511         select PINCTRL_DOVE
 512         select PLAT_ORION_LEGACY
 513         help
 514           Support for the Marvell Dove SoC 88AP510
 515
 516 config ARCH_MV78XX0
 517         bool "Marvell MV78xx0"
 518         select ARCH_REQUIRE_GPIOLIB
 519         select CPU_FEROCEON
 520         select GENERIC_CLOCKEVENTS
 521         select MVEBU_MBUS
 522         select PCI
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the following Marvell MV78xx0 series SoCs:
 526           MV781x0, MV782x0.
 527
 528 config ARCH_ORION5X
 529         bool "Marvell Orion"
 530         depends on MMU
 531         select ARCH_REQUIRE_GPIOLIB
 532         select CPU_FEROCEON
 533         select GENERIC_CLOCKEVENTS
 534         select MVEBU_MBUS
 535         select PCI
 536         select PLAT_ORION_LEGACY
 537         help
 538           Support for the following Marvell Orion 5x series SoCs:
 539           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 540           Orion-2 (5281), Orion-1-90 (6183).
 541
 542 config ARCH_MMP
 543         bool "Marvell PXA168/910/MMP2"
 544         depends on MMU
 545         select ARCH_REQUIRE_GPIOLIB
 546         select CLKDEV_LOOKUP
 547         select GENERIC_ALLOCATOR
 548         select GENERIC_CLOCKEVENTS
 549         select GPIO_PXA
 550         select IRQ_DOMAIN
 551         select MULTI_IRQ_HANDLER
 552         select PINCTRL
 553         select PLAT_PXA
 554         select SPARSE_IRQ
 555         help
 556           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 557
 558 config ARCH_KS8695
 559         bool "Micrel/Kendin KS8695"
 560         select ARCH_REQUIRE_GPIOLIB
 561         select CLKSRC_MMIO
 562         select CPU_ARM922T
 563         select GENERIC_CLOCKEVENTS
 564         select NEED_MACH_MEMORY_H
 565         help
 566           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 567           System-on-Chip devices.
 568
 569 config ARCH_W90X900
 570         bool "Nuvoton W90X900 CPU"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKDEV_LOOKUP
 573         select CLKSRC_MMIO
 574         select CPU_ARM926T
 575         select GENERIC_CLOCKEVENTS
 576         help
 577           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 578           At present, the w90x900 has been renamed nuc900, regarding
 579           the ARM series product line, you can login the following
 580           link address to know more.
 581
 582           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 583                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 584
 585 config ARCH_LPC32XX
 586         bool "NXP LPC32XX"
 587         select ARCH_REQUIRE_GPIOLIB
 588         select ARM_AMBA
 589         select CLKDEV_LOOKUP
 590         select CLKSRC_MMIO
 591         select CPU_ARM926T
 592         select GENERIC_CLOCKEVENTS
 593         select HAVE_IDE
 594         select USE_OF
 595         help
 596           Support for the NXP LPC32XX family of processors
 597
 598 config ARCH_PXA
 599         bool "PXA2xx/PXA3xx-based"
 600         depends on MMU
 601         select ARCH_MTD_XIP
 602         select ARCH_REQUIRE_GPIOLIB
 603         select ARM_CPU_SUSPEND if PM
 604         select AUTO_ZRELADDR
 605         select COMMON_CLK
 606         select CLKDEV_LOOKUP
 607         select CLKSRC_MMIO
 608         select CLKSRC_OF
 609         select GENERIC_CLOCKEVENTS
 610         select GPIO_PXA
 611         select HAVE_IDE
 612         select IRQ_DOMAIN
 613         select MULTI_IRQ_HANDLER
 614         select PLAT_PXA
 615         select SPARSE_IRQ
 616         help
 617           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 618
 619 config ARCH_SHMOBILE_LEGACY
 620         bool "Renesas ARM SoCs (non-multiplatform)"
 621         select ARCH_SHMOBILE
 622         select ARM_PATCH_PHYS_VIRT if MMU
 623         select CLKDEV_LOOKUP
 624         select CPU_V7
 625         select GENERIC_CLOCKEVENTS
 626         select HAVE_ARM_SCU if SMP
 627         select HAVE_ARM_TWD if SMP
 628         select HAVE_SMP
 629         select MIGHT_HAVE_CACHE_L2X0
 630         select MULTI_IRQ_HANDLER
 631         select NO_IOPORT_MAP
 632         select PINCTRL
 633         select PM_GENERIC_DOMAINS if PM
 634         select SH_CLK_CPG
 635         select SPARSE_IRQ
 636         help
 637           Support for Renesas ARM SoC platforms using a non-multiplatform
 638           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 639           and RZ families.
 640
 641 config ARCH_RPC
 642         bool "RiscPC"
 643         select ARCH_ACORN
 644         select ARCH_MAY_HAVE_PC_FDC
 645         select ARCH_SPARSEMEM_ENABLE
 646         select ARCH_USES_GETTIMEOFFSET
 647         select CPU_SA110
 648         select FIQ
 649         select HAVE_IDE
 650         select HAVE_PATA_PLATFORM
 651         select ISA_DMA_API
 652         select NEED_MACH_IO_H
 653         select NEED_MACH_MEMORY_H
 654         select NO_IOPORT_MAP
 655         select VIRT_TO_BUS
 656         help
 657           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 658           CD-ROM interface, serial and parallel port, and the floppy drive.
 659
 660 config ARCH_SA1100
 661         bool "SA1100-based"
 662         select ARCH_MTD_XIP
 663         select ARCH_REQUIRE_GPIOLIB
 664         select ARCH_SPARSEMEM_ENABLE
 665         select CLKDEV_LOOKUP
 666         select CLKSRC_MMIO
 667         select CPU_FREQ
 668         select CPU_SA1100
 669         select GENERIC_CLOCKEVENTS
 670         select HAVE_IDE
 671         select IRQ_DOMAIN
 672         select ISA
 673         select MULTI_IRQ_HANDLER
 674         select NEED_MACH_MEMORY_H
 675         select SPARSE_IRQ
 676         help
 677           Support for StrongARM 11x0 based boards.
 678
 679 config ARCH_S3C24XX
 680         bool "Samsung S3C24XX SoCs"
 681         select ARCH_REQUIRE_GPIOLIB
 682         select ATAGS
 683         select CLKDEV_LOOKUP
 684         select CLKSRC_SAMSUNG_PWM
 685         select GENERIC_CLOCKEVENTS
 686         select GPIO_SAMSUNG
 687         select HAVE_S3C2410_I2C if I2C
 688         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 689         select HAVE_S3C_RTC if RTC_CLASS
 690         select MULTI_IRQ_HANDLER
 691         select NEED_MACH_IO_H
 692         select SAMSUNG_ATAGS
 693         help
 694           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 695           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 696           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 697           Samsung SMDK2410 development board (and derivatives).
 698
 699 config ARCH_S3C64XX
 700         bool "Samsung S3C64XX"
 701         select ARCH_REQUIRE_GPIOLIB
 702         select ARM_AMBA
 703         select ARM_VIC
 704         select ATAGS
 705         select CLKDEV_LOOKUP
 706         select CLKSRC_SAMSUNG_PWM
 707         select COMMON_CLK_SAMSUNG
 708         select CPU_V6K
 709         select GENERIC_CLOCKEVENTS
 710         select GPIO_SAMSUNG
 711         select HAVE_S3C2410_I2C if I2C
 712         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 713         select HAVE_TCM
 714         select NO_IOPORT_MAP
 715         select PLAT_SAMSUNG
 716         select PM_GENERIC_DOMAINS if PM
 717         select S3C_DEV_NAND
 718         select S3C_GPIO_TRACK
 719         select SAMSUNG_ATAGS
 720         select SAMSUNG_WAKEMASK
 721         select SAMSUNG_WDT_RESET
 722         help
 723           Samsung S3C64XX series based systems
 724
 725 config ARCH_DAVINCI
 726         bool "TI DaVinci"
 727         select ARCH_HAS_HOLES_MEMORYMODEL
 728         select ARCH_REQUIRE_GPIOLIB
 729         select CLKDEV_LOOKUP
 730         select GENERIC_ALLOCATOR
 731         select GENERIC_CLOCKEVENTS
 732         select GENERIC_IRQ_CHIP
 733         select HAVE_IDE
 734         select TI_PRIV_EDMA
 735         select USE_OF
 736         select ZONE_DMA
 737         help
 738           Support for TI's DaVinci platform.
 739
 740 config ARCH_OMAP1
 741         bool "TI OMAP1"
 742         depends on MMU
 743         select ARCH_HAS_HOLES_MEMORYMODEL
 744         select ARCH_OMAP
 745         select ARCH_REQUIRE_GPIOLIB
 746         select CLKDEV_LOOKUP
 747         select CLKSRC_MMIO
 748         select GENERIC_CLOCKEVENTS
 749         select GENERIC_IRQ_CHIP
 750         select HAVE_IDE
 751         select IRQ_DOMAIN
 752         select MULTI_IRQ_HANDLER
 753         select NEED_MACH_IO_H if PCCARD
 754         select NEED_MACH_MEMORY_H
 755         select SPARSE_IRQ
 756         help
 757           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 758
 759 endchoice
 760
 761 menu "Multiple platform selection"
 762         depends on ARCH_MULTIPLATFORM
 763
 764 comment "CPU Core family selection"
 765
 766 config ARCH_MULTI_V4
 767         bool "ARMv4 based platforms (FA526)"
 768         depends on !ARCH_MULTI_V6_V7
 769         select ARCH_MULTI_V4_V5
 770         select CPU_FA526
 771
 772 config ARCH_MULTI_V4T
 773         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 774         depends on !ARCH_MULTI_V6_V7
 775         select ARCH_MULTI_V4_V5
 776         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 777                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 778                 CPU_ARM925T || CPU_ARM940T)
 779
 780 config ARCH_MULTI_V5
 781         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 782         depends on !ARCH_MULTI_V6_V7
 783         select ARCH_MULTI_V4_V5
 784         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 785                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 786                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 787
 788 config ARCH_MULTI_V4_V5
 789         bool
 790
 791 config ARCH_MULTI_V6
 792         bool "ARMv6 based platforms (ARM11)"
 793         select ARCH_MULTI_V6_V7
 794         select CPU_V6K
 795
 796 config ARCH_MULTI_V7
 797         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 798         default y
 799         select ARCH_MULTI_V6_V7
 800         select CPU_V7
 801         select HAVE_SMP
 802
 803 config ARCH_MULTI_V6_V7
 804         bool
 805         select MIGHT_HAVE_CACHE_L2X0
 806
 807 config ARCH_MULTI_CPU_AUTO
 808         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 809         select ARCH_MULTI_V5
 810
 811 endmenu
 812
 813 config ARCH_VIRT
 814         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 815         select ARM_AMBA
 816         select ARM_GIC
 817         select ARM_PSCI
 818         select HAVE_ARM_ARCH_TIMER
 819
 820 #
 821 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 822 # Kconfigs may be included either alphabetically (according to the
 823 # plat- suffix) or along side the corresponding mach-* source.
 824 #
 825 source "arch/arm/mach-mvebu/Kconfig"
 826
 827 source "arch/arm/mach-alpine/Kconfig"
 828
 829 source "arch/arm/mach-asm9260/Kconfig"
 830
 831 source "arch/arm/mach-at91/Kconfig"
 832
 833 source "arch/arm/mach-axxia/Kconfig"
 834
 835 source "arch/arm/mach-bcm/Kconfig"
 836
 837 source "arch/arm/mach-berlin/Kconfig"
 838
 839 source "arch/arm/mach-clps711x/Kconfig"
 840
 841 source "arch/arm/mach-cns3xxx/Kconfig"
 842
 843 source "arch/arm/mach-davinci/Kconfig"
 844
 845 source "arch/arm/mach-digicolor/Kconfig"
 846
 847 source "arch/arm/mach-dove/Kconfig"
 848
 849 source "arch/arm/mach-ep93xx/Kconfig"
 850
 851 source "arch/arm/mach-footbridge/Kconfig"
 852
 853 source "arch/arm/mach-gemini/Kconfig"
 854
 855 source "arch/arm/mach-highbank/Kconfig"
 856
 857 source "arch/arm/mach-hisi/Kconfig"
 858
 859 source "arch/arm/mach-integrator/Kconfig"
 860
 861 source "arch/arm/mach-iop32x/Kconfig"
 862
 863 source "arch/arm/mach-iop33x/Kconfig"
 864
 865 source "arch/arm/mach-iop13xx/Kconfig"
 866
 867 source "arch/arm/mach-ixp4xx/Kconfig"
 868
 869 source "arch/arm/mach-keystone/Kconfig"
 870
 871 source "arch/arm/mach-ks8695/Kconfig"
 872
 873 source "arch/arm/mach-meson/Kconfig"
 874
 875 source "arch/arm/mach-moxart/Kconfig"
 876
 877 source "arch/arm/mach-mv78xx0/Kconfig"
 878
 879 source "arch/arm/mach-imx/Kconfig"
 880
 881 source "arch/arm/mach-mediatek/Kconfig"
 882
 883 source "arch/arm/mach-mxs/Kconfig"
 884
 885 source "arch/arm/mach-netx/Kconfig"
 886
 887 source "arch/arm/mach-nomadik/Kconfig"
 888
 889 source "arch/arm/mach-nspire/Kconfig"
 890
 891 source "arch/arm/plat-omap/Kconfig"
 892
 893 source "arch/arm/mach-omap1/Kconfig"
 894
 895 source "arch/arm/mach-omap2/Kconfig"
 896
 897 source "arch/arm/mach-orion5x/Kconfig"
 898
 899 source "arch/arm/mach-picoxcell/Kconfig"
 900
 901 source "arch/arm/mach-pxa/Kconfig"
 902 source "arch/arm/plat-pxa/Kconfig"
 903
 904 source "arch/arm/mach-mmp/Kconfig"
 905
 906 source "arch/arm/mach-qcom/Kconfig"
 907
 908 source "arch/arm/mach-realview/Kconfig"
 909
 910 source "arch/arm/mach-rockchip/Kconfig"
 911
 912 source "arch/arm/mach-sa1100/Kconfig"
 913
 914 source "arch/arm/mach-socfpga/Kconfig"
 915
 916 source "arch/arm/mach-spear/Kconfig"
 917
 918 source "arch/arm/mach-sti/Kconfig"
 919
 920 source "arch/arm/mach-s3c24xx/Kconfig"
 921
 922 source "arch/arm/mach-s3c64xx/Kconfig"
 923
 924 source "arch/arm/mach-s5pv210/Kconfig"
 925
 926 source "arch/arm/mach-exynos/Kconfig"
 927 source "arch/arm/plat-samsung/Kconfig"
 928
 929 source "arch/arm/mach-shmobile/Kconfig"
 930
 931 source "arch/arm/mach-sunxi/Kconfig"
 932
 933 source "arch/arm/mach-prima2/Kconfig"
 934
 935 source "arch/arm/mach-tegra/Kconfig"
 936
 937 source "arch/arm/mach-u300/Kconfig"
 938
 939 source "arch/arm/mach-uniphier/Kconfig"
 940
 941 source "arch/arm/mach-ux500/Kconfig"
 942
 943 source "arch/arm/mach-versatile/Kconfig"
 944
 945 source "arch/arm/mach-vexpress/Kconfig"
 946 source "arch/arm/plat-versatile/Kconfig"
 947
 948 source "arch/arm/mach-vt8500/Kconfig"
 949
 950 source "arch/arm/mach-w90x900/Kconfig"
 951
 952 source "arch/arm/mach-zx/Kconfig"
 953
 954 source "arch/arm/mach-zynq/Kconfig"
 955
 956 # ARMv7-M architecture
 957 config ARCH_EFM32
 958         bool "Energy Micro efm32"
 959         depends on ARM_SINGLE_ARMV7M
 960         select ARCH_REQUIRE_GPIOLIB
 961         help
 962           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 963           processors.
 964
 965 config ARCH_LPC18XX
 966         bool "NXP LPC18xx/LPC43xx"
 967         depends on ARM_SINGLE_ARMV7M
 968         select ARCH_HAS_RESET_CONTROLLER
 969         select ARM_AMBA
 970         select CLKSRC_LPC32XX
 971         select PINCTRL
 972         help
 973           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 974           high performance microcontrollers.
 975
 976 config ARCH_STM32
 977         bool "STMicrolectronics STM32"
 978         depends on ARM_SINGLE_ARMV7M
 979         select ARCH_HAS_RESET_CONTROLLER
 980         select ARMV7M_SYSTICK
 981         select RESET_CONTROLLER
 982         help
 983           Support for STMicroelectronics STM32 processors.
 984
 985 # Definitions to make life easier
 986 config ARCH_ACORN
 987         bool
 988
 989 config PLAT_IOP
 990         bool
 991         select GENERIC_CLOCKEVENTS
 992
 993 config PLAT_ORION
 994         bool
 995         select CLKSRC_MMIO
 996         select COMMON_CLK
 997         select GENERIC_IRQ_CHIP
 998         select IRQ_DOMAIN
 999
1000 config PLAT_ORION_LEGACY
1001         bool
1002         select PLAT_ORION
1003
1004 config PLAT_PXA
1005         bool
1006
1007 config PLAT_VERSATILE
1008         bool
1009
1010 config ARM_TIMER_SP804
1011         bool
1012         select CLKSRC_MMIO
1013         select CLKSRC_OF if OF
1014
1015 source "arch/arm/firmware/Kconfig"
1016
1017 source arch/arm/mm/Kconfig
1018
1019 config IWMMXT
1020         bool "Enable iWMMXt support"
1021         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1022         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1023         help
1024           Enable support for iWMMXt context switching at run time if
1025           running on a CPU that supports it.
1026
1027 config MULTI_IRQ_HANDLER
1028         bool
1029         help
1030           Allow each machine to specify it's own IRQ handler at run time.
1031
1032 if !MMU
1033 source "arch/arm/Kconfig-nommu"
1034 endif
1035
1036 config PJ4B_ERRATA_4742
1037         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1038         depends on CPU_PJ4B && MACH_ARMADA_370
1039         default y
1040         help
1041           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1042           Event (WFE) IDLE states, a specific timing sensitivity exists between
1043           the retiring WFI/WFE instructions and the newly issued subsequent
1044           instructions.  This sensitivity can result in a CPU hang scenario.
1045           Workaround:
1046           The software must insert either a Data Synchronization Barrier (DSB)
1047           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1048           instruction
1049
1050 config ARM_ERRATA_326103
1051         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1052         depends on CPU_V6
1053         help
1054           Executing a SWP instruction to read-only memory does not set bit 11
1055           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1056           treat the access as a read, preventing a COW from occurring and
1057           causing the faulting task to livelock.
1058
1059 config ARM_ERRATA_411920
1060         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1061         depends on CPU_V6 || CPU_V6K
1062         help
1063           Invalidation of the Instruction Cache operation can
1064           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1065           It does not affect the MPCore. This option enables the ARM Ltd.
1066           recommended workaround.
1067
1068 config ARM_ERRATA_430973
1069         bool "ARM errata: Stale prediction on replaced interworking branch"
1070         depends on CPU_V7
1071         help
1072           This option enables the workaround for the 430973 Cortex-A8
1073           r1p* erratum. If a code sequence containing an ARM/Thumb
1074           interworking branch is replaced with another code sequence at the
1075           same virtual address, whether due to self-modifying code or virtual
1076           to physical address re-mapping, Cortex-A8 does not recover from the
1077           stale interworking branch prediction. This results in Cortex-A8
1078           executing the new code sequence in the incorrect ARM or Thumb state.
1079           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1080           and also flushes the branch target cache at every context switch.
1081           Note that setting specific bits in the ACTLR register may not be
1082           available in non-secure mode.
1083
1084 config ARM_ERRATA_458693
1085         bool "ARM errata: Processor deadlock when a false hazard is created"
1086         depends on CPU_V7
1087         depends on !ARCH_MULTIPLATFORM
1088         help
1089           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1090           erratum. For very specific sequences of memory operations, it is
1091           possible for a hazard condition intended for a cache line to instead
1092           be incorrectly associated with a different cache line. This false
1093           hazard might then cause a processor deadlock. The workaround enables
1094           the L1 caching of the NEON accesses and disables the PLD instruction
1095           in the ACTLR register. Note that setting specific bits in the ACTLR
1096           register may not be available in non-secure mode.
1097
1098 config ARM_ERRATA_460075
1099         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1100         depends on CPU_V7
1101         depends on !ARCH_MULTIPLATFORM
1102         help
1103           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1104           erratum. Any asynchronous access to the L2 cache may encounter a
1105           situation in which recent store transactions to the L2 cache are lost
1106           and overwritten with stale memory contents from external memory. The
1107           workaround disables the write-allocate mode for the L2 cache via the
1108           ACTLR register. Note that setting specific bits in the ACTLR register
1109           may not be available in non-secure mode.
1110
1111 config ARM_ERRATA_742230
1112         bool "ARM errata: DMB operation may be faulty"
1113         depends on CPU_V7 && SMP
1114         depends on !ARCH_MULTIPLATFORM
1115         help
1116           This option enables the workaround for the 742230 Cortex-A9
1117           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1118           between two write operations may not ensure the correct visibility
1119           ordering of the two writes. This workaround sets a specific bit in
1120           the diagnostic register of the Cortex-A9 which causes the DMB
1121           instruction to behave as a DSB, ensuring the correct behaviour of
1122           the two writes.
1123
1124 config ARM_ERRATA_742231
1125         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1126         depends on CPU_V7 && SMP
1127         depends on !ARCH_MULTIPLATFORM
1128         help
1129           This option enables the workaround for the 742231 Cortex-A9
1130           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1131           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1132           accessing some data located in the same cache line, may get corrupted
1133           data due to bad handling of the address hazard when the line gets
1134           replaced from one of the CPUs at the same time as another CPU is
1135           accessing it. This workaround sets specific bits in the diagnostic
1136           register of the Cortex-A9 which reduces the linefill issuing
1137           capabilities of the processor.
1138
1139 config ARM_ERRATA_643719
1140         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1141         depends on CPU_V7 && SMP
1142         default y
1143         help
1144           This option enables the workaround for the 643719 Cortex-A9 (prior to
1145           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1146           register returns zero when it should return one. The workaround
1147           corrects this value, ensuring cache maintenance operations which use
1148           it behave as intended and avoiding data corruption.
1149
1150 config ARM_ERRATA_720789
1151         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1152         depends on CPU_V7
1153         help
1154           This option enables the workaround for the 720789 Cortex-A9 (prior to
1155           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1156           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1157           As a consequence of this erratum, some TLB entries which should be
1158           invalidated are not, resulting in an incoherency in the system page
1159           tables. The workaround changes the TLB flushing routines to invalidate
1160           entries regardless of the ASID.
1161
1162 config ARM_ERRATA_743622
1163         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1164         depends on CPU_V7
1165         depends on !ARCH_MULTIPLATFORM
1166         help
1167           This option enables the workaround for the 743622 Cortex-A9
1168           (r2p*) erratum. Under very rare conditions, a faulty
1169           optimisation in the Cortex-A9 Store Buffer may lead to data
1170           corruption. This workaround sets a specific bit in the diagnostic
1171           register of the Cortex-A9 which disables the Store Buffer
1172           optimisation, preventing the defect from occurring. This has no
1173           visible impact on the overall performance or power consumption of the
1174           processor.
1175
1176 config ARM_ERRATA_751472
1177         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1178         depends on CPU_V7
1179         depends on !ARCH_MULTIPLATFORM
1180         help
1181           This option enables the workaround for the 751472 Cortex-A9 (prior
1182           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1183           completion of a following broadcasted operation if the second
1184           operation is received by a CPU before the ICIALLUIS has completed,
1185           potentially leading to corrupted entries in the cache or TLB.
1186
1187 config ARM_ERRATA_754322
1188         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1189         depends on CPU_V7
1190         help
1191           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1192           r3p*) erratum. A speculative memory access may cause a page table walk
1193           which starts prior to an ASID switch but completes afterwards. This
1194           can populate the micro-TLB with a stale entry which may be hit with
1195           the new ASID. This workaround places two dsb instructions in the mm
1196           switching code so that no page table walks can cross the ASID switch.
1197
1198 config ARM_ERRATA_754327
1199         bool "ARM errata: no automatic Store Buffer drain"
1200         depends on CPU_V7 && SMP
1201         help
1202           This option enables the workaround for the 754327 Cortex-A9 (prior to
1203           r2p0) erratum. The Store Buffer does not have any automatic draining
1204           mechanism and therefore a livelock may occur if an external agent
1205           continuously polls a memory location waiting to observe an update.
1206           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1207           written polling loops from denying visibility of updates to memory.
1208
1209 config ARM_ERRATA_364296
1210         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1211         depends on CPU_V6
1212         help
1213           This options enables the workaround for the 364296 ARM1136
1214           r0p2 erratum (possible cache data corruption with
1215           hit-under-miss enabled). It sets the undocumented bit 31 in
1216           the auxiliary control register and the FI bit in the control
1217           register, thus disabling hit-under-miss without putting the
1218           processor into full low interrupt latency mode. ARM11MPCore
1219           is not affected.
1220
1221 config ARM_ERRATA_764369
1222         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1223         depends on CPU_V7 && SMP
1224         help
1225           This option enables the workaround for erratum 764369
1226           affecting Cortex-A9 MPCore with two or more processors (all
1227           current revisions). Under certain timing circumstances, a data
1228           cache line maintenance operation by MVA targeting an Inner
1229           Shareable memory region may fail to proceed up to either the
1230           Point of Coherency or to the Point of Unification of the
1231           system. This workaround adds a DSB instruction before the
1232           relevant cache maintenance functions and sets a specific bit
1233           in the diagnostic control register of the SCU.
1234
1235 config ARM_ERRATA_775420
1236        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1237        depends on CPU_V7
1238        help
1239          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1240          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1241          operation aborts with MMU exception, it might cause the processor
1242          to deadlock. This workaround puts DSB before executing ISB if
1243          an abort may occur on cache maintenance.
1244
1245 config ARM_ERRATA_798181
1246         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1247         depends on CPU_V7 && SMP
1248         help
1249           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1250           adequately shooting down all use of the old entries. This
1251           option enables the Linux kernel workaround for this erratum
1252           which sends an IPI to the CPUs that are running the same ASID
1253           as the one being invalidated.
1254
1255 config ARM_ERRATA_773022
1256         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1257         depends on CPU_V7
1258         help
1259           This option enables the workaround for the 773022 Cortex-A15
1260           (up to r0p4) erratum. In certain rare sequences of code, the
1261           loop buffer may deliver incorrect instructions. This
1262           workaround disables the loop buffer to avoid the erratum.
1263
1264 endmenu
1265
1266 source "arch/arm/common/Kconfig"
1267
1268 menu "Bus support"
1269
1270 config ISA
1271         bool
1272         help
1273           Find out whether you have ISA slots on your motherboard.  ISA is the
1274           name of a bus system, i.e. the way the CPU talks to the other stuff
1275           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1276           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1277           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1278
1279 # Select ISA DMA controller support
1280 config ISA_DMA
1281         bool
1282         select ISA_DMA_API
1283
1284 # Select ISA DMA interface
1285 config ISA_DMA_API
1286         bool
1287
1288 config PCI
1289         bool "PCI support" if MIGHT_HAVE_PCI
1290         help
1291           Find out whether you have a PCI motherboard. PCI is the name of a
1292           bus system, i.e. the way the CPU talks to the other stuff inside
1293           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1294           VESA. If you have PCI, say Y, otherwise N.
1295
1296 config PCI_DOMAINS
1297         bool
1298         depends on PCI
1299
1300 config PCI_DOMAINS_GENERIC
1301         def_bool PCI_DOMAINS
1302
1303 config PCI_NANOENGINE
1304         bool "BSE nanoEngine PCI support"
1305         depends on SA1100_NANOENGINE
1306         help
1307           Enable PCI on the BSE nanoEngine board.
1308
1309 config PCI_SYSCALL
1310         def_bool PCI
1311
1312 config PCI_HOST_ITE8152
1313         bool
1314         depends on PCI && MACH_ARMCORE
1315         default y
1316         select DMABOUNCE
1317
1318 source "drivers/pci/Kconfig"
1319 source "drivers/pci/pcie/Kconfig"
1320
1321 source "drivers/pcmcia/Kconfig"
1322
1323 endmenu
1324
1325 menu "Kernel Features"
1326
1327 config HAVE_SMP
1328         bool
1329         help
1330           This option should be selected by machines which have an SMP-
1331           capable CPU.
1332
1333           The only effect of this option is to make the SMP-related
1334           options available to the user for configuration.
1335
1336 config SMP
1337         bool "Symmetric Multi-Processing"
1338         depends on CPU_V6K || CPU_V7
1339         depends on GENERIC_CLOCKEVENTS
1340         depends on HAVE_SMP
1341         depends on MMU || ARM_MPU
1342         help
1343           This enables support for systems with more than one CPU. If you have
1344           a system with only one CPU, say N. If you have a system with more
1345           than one CPU, say Y.
1346
1347           If you say N here, the kernel will run on uni- and multiprocessor
1348           machines, but will use only one CPU of a multiprocessor machine. If
1349           you say Y here, the kernel will run on many, but not all,
1350           uniprocessor machines. On a uniprocessor machine, the kernel
1351           will run faster if you say N here.
1352
1353           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1354           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1355           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1356
1357           If you don't know what to do here, say N.
1358
1359 config SMP_ON_UP
1360         bool "Allow booting SMP kernel on uniprocessor systems"
1361         depends on SMP && !XIP_KERNEL && MMU
1362         default y
1363         help
1364           SMP kernels contain instructions which fail on non-SMP processors.
1365           Enabling this option allows the kernel to modify itself to make
1366           these instructions safe.  Disabling it allows about 1K of space
1367           savings.
1368
1369           If you don't know what to do here, say Y.
1370
1371 config ARM_CPU_TOPOLOGY
1372         bool "Support cpu topology definition"
1373         depends on SMP && CPU_V7
1374         default y
1375         help
1376           Support ARM cpu topology definition. The MPIDR register defines
1377           affinity between processors which is then used to describe the cpu
1378           topology of an ARM System.
1379
1380 config SCHED_MC
1381         bool "Multi-core scheduler support"
1382         depends on ARM_CPU_TOPOLOGY
1383         help
1384           Multi-core scheduler support improves the CPU scheduler's decision
1385           making when dealing with multi-core CPU chips at a cost of slightly
1386           increased overhead in some places. If unsure say N here.
1387
1388 config SCHED_SMT
1389         bool "SMT scheduler support"
1390         depends on ARM_CPU_TOPOLOGY
1391         help
1392           Improves the CPU scheduler's decision making when dealing with
1393           MultiThreading at a cost of slightly increased overhead in some
1394           places. If unsure say N here.
1395
1396 config HAVE_ARM_SCU
1397         bool
1398         help
1399           This option enables support for the ARM system coherency unit
1400
1401 config HAVE_ARM_ARCH_TIMER
1402         bool "Architected timer support"
1403         depends on CPU_V7
1404         select ARM_ARCH_TIMER
1405         select GENERIC_CLOCKEVENTS
1406         help
1407           This option enables support for the ARM architected timer
1408
1409 config HAVE_ARM_TWD
1410         bool
1411         depends on SMP
1412         select CLKSRC_OF if OF
1413         help
1414           This options enables support for the ARM timer and watchdog unit
1415
1416 config MCPM
1417         bool "Multi-Cluster Power Management"
1418         depends on CPU_V7 && SMP
1419         help
1420           This option provides the common power management infrastructure
1421           for (multi-)cluster based systems, such as big.LITTLE based
1422           systems.
1423
1424 config MCPM_QUAD_CLUSTER
1425         bool
1426         depends on MCPM
1427         help
1428           To avoid wasting resources unnecessarily, MCPM only supports up
1429           to 2 clusters by default.
1430           Platforms with 3 or 4 clusters that use MCPM must select this
1431           option to allow the additional clusters to be managed.
1432
1433 config BIG_LITTLE
1434         bool "big.LITTLE support (Experimental)"
1435         depends on CPU_V7 && SMP
1436         select MCPM
1437         help
1438           This option enables support selections for the big.LITTLE
1439           system architecture.
1440
1441 config BL_SWITCHER
1442         bool "big.LITTLE switcher support"
1443         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1444         select ARM_CPU_SUSPEND
1445         select CPU_PM
1446         help
1447           The big.LITTLE "switcher" provides the core functionality to
1448           transparently handle transition between a cluster of A15's
1449           and a cluster of A7's in a big.LITTLE system.
1450
1451 config BL_SWITCHER_DUMMY_IF
1452         tristate "Simple big.LITTLE switcher user interface"
1453         depends on BL_SWITCHER && DEBUG_KERNEL
1454         help
1455           This is a simple and dummy char dev interface to control
1456           the big.LITTLE switcher core code.  It is meant for
1457           debugging purposes only.
1458
1459 choice
1460         prompt "Memory split"
1461         depends on MMU
1462         default VMSPLIT_3G
1463         help
1464           Select the desired split between kernel and user memory.
1465
1466           If you are not absolutely sure what you are doing, leave this
1467           option alone!
1468
1469         config VMSPLIT_3G
1470                 bool "3G/1G user/kernel split"
1471         config VMSPLIT_2G
1472                 bool "2G/2G user/kernel split"
1473         config VMSPLIT_1G
1474                 bool "1G/3G user/kernel split"
1475 endchoice
1476
1477 config PAGE_OFFSET
1478         hex
1479         default PHYS_OFFSET if !MMU
1480         default 0x40000000 if VMSPLIT_1G
1481         default 0x80000000 if VMSPLIT_2G
1482         default 0xC0000000
1483
1484 config NR_CPUS
1485         int "Maximum number of CPUs (2-32)"
1486         range 2 32
1487         depends on SMP
1488         default "4"
1489
1490 config HOTPLUG_CPU
1491         bool "Support for hot-pluggable CPUs"
1492         depends on SMP
1493         help
1494           Say Y here to experiment with turning CPUs off and on.  CPUs
1495           can be controlled through /sys/devices/system/cpu.
1496
1497 config ARM_PSCI
1498         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1499         depends on CPU_V7
1500         help
1501           Say Y here if you want Linux to communicate with system firmware
1502           implementing the PSCI specification for CPU-centric power
1503           management operations described in ARM document number ARM DEN
1504           0022A ("Power State Coordination Interface System Software on
1505           ARM processors").
1506
1507 # The GPIO number here must be sorted by descending number. In case of
1508 # a multiplatform kernel, we just want the highest value required by the
1509 # selected platforms.
1510 config ARCH_NR_GPIO
1511         int
1512         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1513                 ARCH_ZYNQ
1514         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1515                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1516         default 416 if ARCH_SUNXI
1517         default 392 if ARCH_U8500
1518         default 352 if ARCH_VT8500
1519         default 288 if ARCH_ROCKCHIP
1520         default 264 if MACH_H4700
1521         default 0
1522         help
1523           Maximum number of GPIOs in the system.
1524
1525           If unsure, leave the default value.
1526
1527 source kernel/Kconfig.preempt
1528
1529 config HZ_FIXED
1530         int
1531         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1532                 ARCH_S5PV210 || ARCH_EXYNOS4
1533         default 128 if SOC_AT91RM9200
1534         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1535         default 0
1536
1537 choice
1538         depends on HZ_FIXED = 0
1539         prompt "Timer frequency"
1540
1541 config HZ_100
1542         bool "100 Hz"
1543
1544 config HZ_200
1545         bool "200 Hz"
1546
1547 config HZ_250
1548         bool "250 Hz"
1549
1550 config HZ_300
1551         bool "300 Hz"
1552
1553 config HZ_500
1554         bool "500 Hz"
1555
1556 config HZ_1000
1557         bool "1000 Hz"
1558
1559 endchoice
1560
1561 config HZ
1562         int
1563         default HZ_FIXED if HZ_FIXED != 0
1564         default 100 if HZ_100
1565         default 200 if HZ_200
1566         default 250 if HZ_250
1567         default 300 if HZ_300
1568         default 500 if HZ_500
1569         default 1000
1570
1571 config SCHED_HRTICK
1572         def_bool HIGH_RES_TIMERS
1573
1574 config THUMB2_KERNEL
1575         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1576         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1577         default y if CPU_THUMBONLY
1578         select AEABI
1579         select ARM_ASM_UNIFIED
1580         select ARM_UNWIND
1581         help
1582           By enabling this option, the kernel will be compiled in
1583           Thumb-2 mode. A compiler/assembler that understand the unified
1584           ARM-Thumb syntax is needed.
1585
1586           If unsure, say N.
1587
1588 config THUMB2_AVOID_R_ARM_THM_JUMP11
1589         bool "Work around buggy Thumb-2 short branch relocations in gas"
1590         depends on THUMB2_KERNEL && MODULES
1591         default y
1592         help
1593           Various binutils versions can resolve Thumb-2 branches to
1594           locally-defined, preemptible global symbols as short-range "b.n"
1595           branch instructions.
1596
1597           This is a problem, because there's no guarantee the final
1598           destination of the symbol, or any candidate locations for a
1599           trampoline, are within range of the branch.  For this reason, the
1600           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1601           relocation in modules at all, and it makes little sense to add
1602           support.
1603
1604           The symptom is that the kernel fails with an "unsupported
1605           relocation" error when loading some modules.
1606
1607           Until fixed tools are available, passing
1608           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1609           code which hits this problem, at the cost of a bit of extra runtime
1610           stack usage in some cases.
1611
1612           The problem is described in more detail at:
1613               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1614
1615           Only Thumb-2 kernels are affected.
1616
1617           Unless you are sure your tools don't have this problem, say Y.
1618
1619 config ARM_ASM_UNIFIED
1620         bool
1621
1622 config AEABI
1623         bool "Use the ARM EABI to compile the kernel"
1624         help
1625           This option allows for the kernel to be compiled using the latest
1626           ARM ABI (aka EABI).  This is only useful if you are using a user
1627           space environment that is also compiled with EABI.
1628
1629           Since there are major incompatibilities between the legacy ABI and
1630           EABI, especially with regard to structure member alignment, this
1631           option also changes the kernel syscall calling convention to
1632           disambiguate both ABIs and allow for backward compatibility support
1633           (selected with CONFIG_OABI_COMPAT).
1634
1635           To use this you need GCC version 4.0.0 or later.
1636
1637 config OABI_COMPAT
1638         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1639         depends on AEABI && !THUMB2_KERNEL
1640         help
1641           This option preserves the old syscall interface along with the
1642           new (ARM EABI) one. It also provides a compatibility layer to
1643           intercept syscalls that have structure arguments which layout
1644           in memory differs between the legacy ABI and the new ARM EABI
1645           (only for non "thumb" binaries). This option adds a tiny
1646           overhead to all syscalls and produces a slightly larger kernel.
1647
1648           The seccomp filter system will not be available when this is
1649           selected, since there is no way yet to sensibly distinguish
1650           between calling conventions during filtering.
1651
1652           If you know you'll be using only pure EABI user space then you
1653           can say N here. If this option is not selected and you attempt
1654           to execute a legacy ABI binary then the result will be
1655           UNPREDICTABLE (in fact it can be predicted that it won't work
1656           at all). If in doubt say N.
1657
1658 config ARCH_HAS_HOLES_MEMORYMODEL
1659         bool
1660
1661 config ARCH_SPARSEMEM_ENABLE
1662         bool
1663
1664 config ARCH_SPARSEMEM_DEFAULT
1665         def_bool ARCH_SPARSEMEM_ENABLE
1666
1667 config ARCH_SELECT_MEMORY_MODEL
1668         def_bool ARCH_SPARSEMEM_ENABLE
1669
1670 config HAVE_ARCH_PFN_VALID
1671         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1672
1673 config HAVE_GENERIC_RCU_GUP
1674         def_bool y
1675         depends on ARM_LPAE
1676
1677 config HIGHMEM
1678         bool "High Memory Support"
1679         depends on MMU
1680         help
1681           The address space of ARM processors is only 4 Gigabytes large
1682           and it has to accommodate user address space, kernel address
1683           space as well as some memory mapped IO. That means that, if you
1684           have a large amount of physical memory and/or IO, not all of the
1685           memory can be "permanently mapped" by the kernel. The physical
1686           memory that is not permanently mapped is called "high memory".
1687
1688           Depending on the selected kernel/user memory split, minimum
1689           vmalloc space and actual amount of RAM, you may not need this
1690           option which should result in a slightly faster kernel.
1691
1692           If unsure, say n.
1693
1694 config HIGHPTE
1695         bool "Allocate 2nd-level pagetables from highmem"
1696         depends on HIGHMEM
1697
1698 config HW_PERF_EVENTS
1699         bool "Enable hardware performance counter support for perf events"
1700         depends on PERF_EVENTS
1701         default y
1702         help
1703           Enable hardware performance counter support for perf events. If
1704           disabled, perf events will use software events only.
1705
1706 config SYS_SUPPORTS_HUGETLBFS
1707        def_bool y
1708        depends on ARM_LPAE
1709
1710 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1711        def_bool y
1712        depends on ARM_LPAE
1713
1714 config ARCH_WANT_GENERAL_HUGETLB
1715         def_bool y
1716
1717 source "mm/Kconfig"
1718
1719 config FORCE_MAX_ZONEORDER
1720         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1721         range 11 64 if ARCH_SHMOBILE_LEGACY
1722         default "12" if SOC_AM33XX
1723         default "9" if SA1111 || ARCH_EFM32
1724         default "11"
1725         help
1726           The kernel memory allocator divides physically contiguous memory
1727           blocks into "zones", where each zone is a power of two number of
1728           pages.  This option selects the largest power of two that the kernel
1729           keeps in the memory allocator.  If you need to allocate very large
1730           blocks of physically contiguous memory, then you may need to
1731           increase this value.
1732
1733           This config option is actually maximum order plus one. For example,
1734           a value of 11 means that the largest free memory block is 2^10 pages.
1735
1736 config ALIGNMENT_TRAP
1737         bool
1738         depends on CPU_CP15_MMU
1739         default y if !ARCH_EBSA110
1740         select HAVE_PROC_CPU if PROC_FS
1741         help
1742           ARM processors cannot fetch/store information which is not
1743           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1744           address divisible by 4. On 32-bit ARM processors, these non-aligned
1745           fetch/store instructions will be emulated in software if you say
1746           here, which has a severe performance impact. This is necessary for
1747           correct operation of some network protocols. With an IP-only
1748           configuration it is safe to say N, otherwise say Y.
1749
1750 config UACCESS_WITH_MEMCPY
1751         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1752         depends on MMU
1753         default y if CPU_FEROCEON
1754         help
1755           Implement faster copy_to_user and clear_user methods for CPU
1756           cores where a 8-word STM instruction give significantly higher
1757           memory write throughput than a sequence of individual 32bit stores.
1758
1759           A possible side effect is a slight increase in scheduling latency
1760           between threads sharing the same address space if they invoke
1761           such copy operations with large buffers.
1762
1763           However, if the CPU data cache is using a write-allocate mode,
1764           this option is unlikely to provide any performance gain.
1765
1766 config SECCOMP
1767         bool
1768         prompt "Enable seccomp to safely compute untrusted bytecode"
1769         ---help---
1770           This kernel feature is useful for number crunching applications
1771           that may need to compute untrusted bytecode during their
1772           execution. By using pipes or other transports made available to
1773           the process as file descriptors supporting the read/write
1774           syscalls, it's possible to isolate those applications in
1775           their own address space using seccomp. Once seccomp is
1776           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1777           and the task is only allowed to execute a few safe syscalls
1778           defined by each seccomp mode.
1779
1780 config SWIOTLB
1781         def_bool y
1782
1783 config IOMMU_HELPER
1784         def_bool SWIOTLB
1785
1786 config XEN_DOM0
1787         def_bool y
1788         depends on XEN
1789
1790 config XEN
1791         bool "Xen guest support on ARM"
1792         depends on ARM && AEABI && OF
1793         depends on CPU_V7 && !CPU_V6
1794         depends on !GENERIC_ATOMIC64
1795         depends on MMU
1796         select ARCH_DMA_ADDR_T_64BIT
1797         select ARM_PSCI
1798         select SWIOTLB_XEN
1799         help
1800           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1801
1802 endmenu
1803
1804 menu "Boot options"
1805
1806 config USE_OF
1807         bool "Flattened Device Tree support"
1808         select IRQ_DOMAIN
1809         select OF
1810         select OF_EARLY_FLATTREE
1811         select OF_RESERVED_MEM
1812         help
1813           Include support for flattened device tree machine descriptions.
1814
1815 config ATAGS
1816         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1817         default y
1818         help
1819           This is the traditional way of passing data to the kernel at boot
1820           time. If you are solely relying on the flattened device tree (or
1821           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1822           to remove ATAGS support from your kernel binary.  If unsure,
1823           leave this to y.
1824
1825 config DEPRECATED_PARAM_STRUCT
1826         bool "Provide old way to pass kernel parameters"
1827         depends on ATAGS
1828         help
1829           This was deprecated in 2001 and announced to live on for 5 years.
1830           Some old boot loaders still use this way.
1831
1832 # Compressed boot loader in ROM.  Yes, we really want to ask about
1833 # TEXT and BSS so we preserve their values in the config files.
1834 config ZBOOT_ROM_TEXT
1835         hex "Compressed ROM boot loader base address"
1836         default "0"
1837         help
1838           The physical address at which the ROM-able zImage is to be
1839           placed in the target.  Platforms which normally make use of
1840           ROM-able zImage formats normally set this to a suitable
1841           value in their defconfig file.
1842
1843           If ZBOOT_ROM is not enabled, this has no effect.
1844
1845 config ZBOOT_ROM_BSS
1846         hex "Compressed ROM boot loader BSS address"
1847         default "0"
1848         help
1849           The base address of an area of read/write memory in the target
1850           for the ROM-able zImage which must be available while the
1851           decompressor is running. It must be large enough to hold the
1852           entire decompressed kernel plus an additional 128 KiB.
1853           Platforms which normally make use of ROM-able zImage formats
1854           normally set this to a suitable value in their defconfig file.
1855
1856           If ZBOOT_ROM is not enabled, this has no effect.
1857
1858 config ZBOOT_ROM
1859         bool "Compressed boot loader in ROM/flash"
1860         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1861         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1862         help
1863           Say Y here if you intend to execute your compressed kernel image
1864           (zImage) directly from ROM or flash.  If unsure, say N.
1865
1866 config ARM_APPENDED_DTB
1867         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1868         depends on OF
1869         help
1870           With this option, the boot code will look for a device tree binary
1871           (DTB) appended to zImage
1872           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1873
1874           This is meant as a backward compatibility convenience for those
1875           systems with a bootloader that can't be upgraded to accommodate
1876           the documented boot protocol using a device tree.
1877
1878           Beware that there is very little in terms of protection against
1879           this option being confused by leftover garbage in memory that might
1880           look like a DTB header after a reboot if no actual DTB is appended
1881           to zImage.  Do not leave this option active in a production kernel
1882           if you don't intend to always append a DTB.  Proper passing of the
1883           location into r2 of a bootloader provided DTB is always preferable
1884           to this option.
1885
1886 config ARM_ATAG_DTB_COMPAT
1887         bool "Supplement the appended DTB with traditional ATAG information"
1888         depends on ARM_APPENDED_DTB
1889         help
1890           Some old bootloaders can't be updated to a DTB capable one, yet
1891           they provide ATAGs with memory configuration, the ramdisk address,
1892           the kernel cmdline string, etc.  Such information is dynamically
1893           provided by the bootloader and can't always be stored in a static
1894           DTB.  To allow a device tree enabled kernel to be used with such
1895           bootloaders, this option allows zImage to extract the information
1896           from the ATAG list and store it at run time into the appended DTB.
1897
1898 choice
1899         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1900         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1901
1902 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1903         bool "Use bootloader kernel arguments if available"
1904         help
1905           Uses the command-line options passed by the boot loader instead of
1906           the device tree bootargs property. If the boot loader doesn't provide
1907           any, the device tree bootargs property will be used.
1908
1909 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1910         bool "Extend with bootloader kernel arguments"
1911         help
1912           The command-line arguments provided by the boot loader will be
1913           appended to the the device tree bootargs property.
1914
1915 endchoice
1916
1917 config CMDLINE
1918         string "Default kernel command string"
1919         default ""
1920         help
1921           On some architectures (EBSA110 and CATS), there is currently no way
1922           for the boot loader to pass arguments to the kernel. For these
1923           architectures, you should supply some command-line options at build
1924           time by entering them here. As a minimum, you should specify the
1925           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1926
1927 choice
1928         prompt "Kernel command line type" if CMDLINE != ""
1929         default CMDLINE_FROM_BOOTLOADER
1930         depends on ATAGS
1931
1932 config CMDLINE_FROM_BOOTLOADER
1933         bool "Use bootloader kernel arguments if available"
1934         help
1935           Uses the command-line options passed by the boot loader. If
1936           the boot loader doesn't provide any, the default kernel command
1937           string provided in CMDLINE will be used.
1938
1939 config CMDLINE_EXTEND
1940         bool "Extend bootloader kernel arguments"
1941         help
1942           The command-line arguments provided by the boot loader will be
1943           appended to the default kernel command string.
1944
1945 config CMDLINE_FORCE
1946         bool "Always use the default kernel command string"
1947         help
1948           Always use the default kernel command string, even if the boot
1949           loader passes other arguments to the kernel.
1950           This is useful if you cannot or don't want to change the
1951           command-line options your boot loader passes to the kernel.
1952 endchoice
1953
1954 config XIP_KERNEL
1955         bool "Kernel Execute-In-Place from ROM"
1956         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1957         help
1958           Execute-In-Place allows the kernel to run from non-volatile storage
1959           directly addressable by the CPU, such as NOR flash. This saves RAM
1960           space since the text section of the kernel is not loaded from flash
1961           to RAM.  Read-write sections, such as the data section and stack,
1962           are still copied to RAM.  The XIP kernel is not compressed since
1963           it has to run directly from flash, so it will take more space to
1964           store it.  The flash address used to link the kernel object files,
1965           and for storing it, is configuration dependent. Therefore, if you
1966           say Y here, you must know the proper physical address where to
1967           store the kernel image depending on your own flash memory usage.
1968
1969           Also note that the make target becomes "make xipImage" rather than
1970           "make zImage" or "make Image".  The final kernel binary to put in
1971           ROM memory will be arch/arm/boot/xipImage.
1972
1973           If unsure, say N.
1974
1975 config XIP_PHYS_ADDR
1976         hex "XIP Kernel Physical Location"
1977         depends on XIP_KERNEL
1978         default "0x00080000"
1979         help
1980           This is the physical address in your flash memory the kernel will
1981           be linked for and stored to.  This address is dependent on your
1982           own flash usage.
1983
1984 config KEXEC
1985         bool "Kexec system call (EXPERIMENTAL)"
1986         depends on (!SMP || PM_SLEEP_SMP)
1987         help
1988           kexec is a system call that implements the ability to shutdown your
1989           current kernel, and to start another kernel.  It is like a reboot
1990           but it is independent of the system firmware.   And like a reboot
1991           you can start any kernel with it, not just Linux.
1992
1993           It is an ongoing process to be certain the hardware in a machine
1994           is properly shutdown, so do not be surprised if this code does not
1995           initially work for you.
1996
1997 config ATAGS_PROC
1998         bool "Export atags in procfs"
1999         depends on ATAGS && KEXEC
2000         default y
2001         help
2002           Should the atags used to boot the kernel be exported in an "atags"
2003           file in procfs. Useful with kexec.
2004
2005 config CRASH_DUMP
2006         bool "Build kdump crash kernel (EXPERIMENTAL)"
2007         help
2008           Generate crash dump after being started by kexec. This should
2009           be normally only set in special crash dump kernels which are
2010           loaded in the main kernel with kexec-tools into a specially
2011           reserved region and then later executed after a crash by
2012           kdump/kexec. The crash dump kernel must be compiled to a
2013           memory address not used by the main kernel
2014
2015           For more details see Documentation/kdump/kdump.txt
2016
2017 config AUTO_ZRELADDR
2018         bool "Auto calculation of the decompressed kernel image address"
2019         help
2020           ZRELADDR is the physical address where the decompressed kernel
2021           image will be placed. If AUTO_ZRELADDR is selected, the address
2022           will be determined at run-time by masking the current IP with
2023           0xf8000000. This assumes the zImage being placed in the first 128MB
2024           from start of memory.
2025
2026 endmenu
2027
2028 menu "CPU Power Management"
2029
2030 source "drivers/cpufreq/Kconfig"
2031
2032 source "drivers/cpuidle/Kconfig"
2033
2034 endmenu
2035
2036 menu "Floating point emulation"
2037
2038 comment "At least one emulation must be selected"
2039
2040 config FPE_NWFPE
2041         bool "NWFPE math emulation"
2042         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2043         ---help---
2044           Say Y to include the NWFPE floating point emulator in the kernel.
2045           This is necessary to run most binaries. Linux does not currently
2046           support floating point hardware so you need to say Y here even if
2047           your machine has an FPA or floating point co-processor podule.
2048
2049           You may say N here if you are going to load the Acorn FPEmulator
2050           early in the bootup.
2051
2052 config FPE_NWFPE_XP
2053         bool "Support extended precision"
2054         depends on FPE_NWFPE
2055         help
2056           Say Y to include 80-bit support in the kernel floating-point
2057           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2058           Note that gcc does not generate 80-bit operations by default,
2059           so in most cases this option only enlarges the size of the
2060           floating point emulator without any good reason.
2061
2062           You almost surely want to say N here.
2063
2064 config FPE_FASTFPE
2065         bool "FastFPE math emulation (EXPERIMENTAL)"
2066         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2067         ---help---
2068           Say Y here to include the FAST floating point emulator in the kernel.
2069           This is an experimental much faster emulator which now also has full
2070           precision for the mantissa.  It does not support any exceptions.
2071           It is very simple, and approximately 3-6 times faster than NWFPE.
2072
2073           It should be sufficient for most programs.  It may be not suitable
2074           for scientific calculations, but you have to check this for yourself.
2075           If you do not feel you need a faster FP emulation you should better
2076           choose NWFPE.
2077
2078 config VFP
2079         bool "VFP-format floating point maths"
2080         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2081         help
2082           Say Y to include VFP support code in the kernel. This is needed
2083           if your hardware includes a VFP unit.
2084
2085           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2086           release notes and additional status information.
2087
2088           Say N if your target does not have VFP hardware.
2089
2090 config VFPv3
2091         bool
2092         depends on VFP
2093         default y if CPU_V7
2094
2095 config NEON
2096         bool "Advanced SIMD (NEON) Extension support"
2097         depends on VFPv3 && CPU_V7
2098         help
2099           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2100           Extension.
2101
2102 config KERNEL_MODE_NEON
2103         bool "Support for NEON in kernel mode"
2104         depends on NEON && AEABI
2105         help
2106           Say Y to include support for NEON in kernel mode.
2107
2108 endmenu
2109
2110 menu "Userspace binary formats"
2111
2112 source "fs/Kconfig.binfmt"
2113
2114 endmenu
2115
2116 menu "Power management options"
2117
2118 source "kernel/power/Kconfig"
2119
2120 config ARCH_SUSPEND_POSSIBLE
2121         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2122                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2123         def_bool y
2124
2125 config ARM_CPU_SUSPEND
2126         def_bool PM_SLEEP
2127
2128 config ARCH_HIBERNATION_POSSIBLE
2129         bool
2130         depends on MMU
2131         default y if ARCH_SUSPEND_POSSIBLE
2132
2133 endmenu
2134
2135 source "net/Kconfig"
2136
2137 source "drivers/Kconfig"
2138
2139 source "drivers/firmware/Kconfig"
2140
2141 source "fs/Kconfig"
2142
2143 source "arch/arm/Kconfig.debug"
2144
2145 source "security/Kconfig"
2146
2147 source "crypto/Kconfig"
2148 if CRYPTO
2149 source "arch/arm/crypto/Kconfig"
2150 endif
2151
2152 source "lib/Kconfig"
2153
2154 source "arch/arm/kvm/Kconfig"