4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_IO_H
283 select NEED_MACH_MEMORY_H
285 select MULTI_IRQ_HANDLER
287 Support for ARM's Integrator platform.
290 bool "ARM Ltd. RealView family"
293 select HAVE_MACH_CLKDEV
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLOCK
299 select PLAT_VERSATILE_CLCD
300 select ARM_TIMER_SP804
301 select GPIO_PL061 if GPIOLIB
302 select NEED_MACH_MEMORY_H
304 This enables support for ARM Ltd RealView boards.
306 config ARCH_VERSATILE
307 bool "ARM Ltd. Versatile family"
311 select HAVE_MACH_CLKDEV
313 select GENERIC_CLOCKEVENTS
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select NEED_MACH_IO_H if PCI
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLOCK
318 select PLAT_VERSATILE_CLCD
319 select PLAT_VERSATILE_FPGA_IRQ
320 select ARM_TIMER_SP804
322 This enables support for ARM Ltd Versatile board.
325 bool "ARM Ltd. Versatile Express family"
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 select ARM_TIMER_SP804
331 select GENERIC_CLOCKEVENTS
333 select HAVE_PATA_PLATFORM
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
338 select REGULATOR_FIXED_VOLTAGE if REGULATOR
340 This enables support for the ARM Ltd Versatile Express boards.
344 select ARCH_REQUIRE_GPIOLIB
348 select NEED_MACH_IO_H if PCCARD
350 This enables support for systems based on Atmel
351 AT91RM9200 and AT91SAM9* processors.
354 bool "Broadcom BCM2835 family"
355 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_ERRATA_411920
358 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select MULTI_IRQ_HANDLER
367 This enables support for the Broadcom BCM2835 SoC. This SoC is
368 use in the Raspberry Pi, and Roku 2 devices.
371 bool "Broadcom BCMRING"
375 select ARM_TIMER_SP804
377 select GENERIC_CLOCKEVENTS
378 select ARCH_WANT_OPTIONAL_GPIOLIB
380 Support for Broadcom's BCMRing platform.
383 bool "Calxeda Highbank-based"
384 select ARCH_WANT_OPTIONAL_GPIOLIB
387 select ARM_TIMER_SP804
392 select GENERIC_CLOCKEVENTS
398 Support for the Calxeda Highbank SoC based boards.
401 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
403 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_MEMORY_H
406 Support for Cirrus Logic 711x/721x/731x based boards.
409 bool "Cavium Networks CNS3XXX family"
411 select GENERIC_CLOCKEVENTS
413 select MIGHT_HAVE_CACHE_L2X0
414 select MIGHT_HAVE_PCI
415 select PCI_DOMAINS if PCI
417 Support for Cavium Networks CNS3XXX platform.
420 bool "Cortina Systems Gemini"
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_USES_GETTIMEOFFSET
425 Support for the Cortina Systems Gemini family SoCs
428 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
431 select ARCH_REQUIRE_GPIOLIB
432 select GENERIC_CLOCKEVENTS
434 select GENERIC_IRQ_CHIP
435 select MIGHT_HAVE_CACHE_L2X0
441 Support for CSR SiRFSoC ARM Cortex A9 Platform
448 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_IO_H
450 select NEED_MACH_MEMORY_H
452 This is an evaluation board for the StrongARM processor available
453 from Digital. It has limited hardware on-board, including an
454 Ethernet interface, two PCMCIA sockets, two serial ports and a
463 select ARCH_REQUIRE_GPIOLIB
464 select ARCH_HAS_HOLES_MEMORYMODEL
465 select ARCH_USES_GETTIMEOFFSET
466 select NEED_MACH_MEMORY_H
468 This enables support for the Cirrus EP93xx series of CPUs.
470 config ARCH_FOOTBRIDGE
474 select GENERIC_CLOCKEVENTS
476 select NEED_MACH_IO_H
477 select NEED_MACH_MEMORY_H
479 Support for systems based on the DC21285 companion chip
480 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
483 bool "Freescale MXC/iMX-based"
484 select GENERIC_CLOCKEVENTS
485 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_IRQ_CHIP
489 select MULTI_IRQ_HANDLER
493 Support for Freescale MXC/iMX-based family of processors
496 bool "Freescale MXS-based"
497 select GENERIC_CLOCKEVENTS
498 select ARCH_REQUIRE_GPIOLIB
502 select HAVE_CLK_PREPARE
506 Support for Freescale MXS-based family of processors
509 bool "Hilscher NetX based"
513 select GENERIC_CLOCKEVENTS
515 This enables support for systems based on the Hilscher NetX Soc
518 bool "Hynix HMS720x-based"
521 select ARCH_USES_GETTIMEOFFSET
523 This enables support for systems based on the Hynix HMS720x
531 select ARCH_SUPPORTS_MSI
533 select NEED_MACH_IO_H
534 select NEED_MACH_MEMORY_H
535 select NEED_RET_TO_USER
537 Support for Intel's IOP13XX (XScale) family of processors.
543 select NEED_MACH_IO_H
544 select NEED_RET_TO_USER
547 select ARCH_REQUIRE_GPIOLIB
549 Support for Intel's 80219 and IOP32X (XScale) family of
556 select NEED_MACH_IO_H
557 select NEED_RET_TO_USER
560 select ARCH_REQUIRE_GPIOLIB
562 Support for Intel's IOP33X (XScale) family of processors.
567 select ARCH_HAS_DMA_SET_COHERENT_MASK
570 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
572 select MIGHT_HAVE_PCI
573 select NEED_MACH_IO_H
574 select DMABOUNCE if PCI
576 Support for Intel's IXP4XX (XScale) family of processors.
579 bool "Marvell SOCs with Device Tree support"
580 select GENERIC_CLOCKEVENTS
581 select MULTI_IRQ_HANDLER
584 select GENERIC_IRQ_CHIP
588 Support for the Marvell SoC Family with device tree support
594 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select NEED_MACH_IO_H
599 Support for the Marvell Dove SoC 88AP510
602 bool "Marvell Kirkwood"
605 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_IO_H
610 Support for the following Marvell Kirkwood series SoCs:
611 88F6180, 88F6192 and 88F6281.
617 select ARCH_REQUIRE_GPIOLIB
620 select USB_ARCH_HAS_OHCI
622 select GENERIC_CLOCKEVENTS
626 Support for the NXP LPC32XX family of processors
629 bool "Marvell MV78xx0"
632 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
634 select NEED_MACH_IO_H
637 Support for the following Marvell MV78xx0 series SoCs:
645 select ARCH_REQUIRE_GPIOLIB
646 select GENERIC_CLOCKEVENTS
647 select NEED_MACH_IO_H
650 Support for the following Marvell Orion 5x series SoCs:
651 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
652 Orion-2 (5281), Orion-1-90 (6183).
655 bool "Marvell PXA168/910/MMP2"
657 select ARCH_REQUIRE_GPIOLIB
659 select GENERIC_CLOCKEVENTS
664 select GENERIC_ALLOCATOR
666 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
669 bool "Micrel/Kendin KS8695"
671 select ARCH_REQUIRE_GPIOLIB
672 select ARCH_USES_GETTIMEOFFSET
673 select NEED_MACH_MEMORY_H
675 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
676 System-on-Chip devices.
679 bool "Nuvoton W90X900 CPU"
681 select ARCH_REQUIRE_GPIOLIB
684 select GENERIC_CLOCKEVENTS
686 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
687 At present, the w90x900 has been renamed nuc900, regarding
688 the ARM series product line, you can login the following
689 link address to know more.
691 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
692 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
698 select GENERIC_CLOCKEVENTS
702 select MIGHT_HAVE_CACHE_L2X0
703 select NEED_MACH_IO_H if PCI
704 select ARCH_HAS_CPUFREQ
708 This enables support for NVIDIA Tegra based systems (Tegra APX,
709 Tegra 6xx and Tegra 2 series).
711 config ARCH_PICOXCELL
712 bool "Picochip picoXcell"
713 select ARCH_REQUIRE_GPIOLIB
714 select ARM_PATCH_PHYS_VIRT
718 select DW_APB_TIMER_OF
719 select GENERIC_CLOCKEVENTS
726 This enables support for systems based on the Picochip picoXcell
727 family of Femtocell devices. The picoxcell support requires device tree
731 bool "Philips Nexperia PNX4008 Mobile"
734 select ARCH_USES_GETTIMEOFFSET
736 This enables support for Philips PNX4008 mobile platform.
739 bool "PXA2xx/PXA3xx-based"
742 select ARCH_HAS_CPUFREQ
745 select ARCH_REQUIRE_GPIOLIB
746 select GENERIC_CLOCKEVENTS
751 select MULTI_IRQ_HANDLER
752 select ARM_CPU_SUSPEND if PM
755 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
760 select GENERIC_CLOCKEVENTS
761 select ARCH_REQUIRE_GPIOLIB
764 Support for Qualcomm MSM/QSD based systems. This runs on the
765 apps processor of the MSM/QSD and depends on a shared memory
766 interface to the modem processor which runs the baseband
767 stack and controls some vital subsystems
768 (clock and power control, etc).
771 bool "Renesas SH-Mobile / R-Mobile"
774 select HAVE_MACH_CLKDEV
776 select GENERIC_CLOCKEVENTS
777 select MIGHT_HAVE_CACHE_L2X0
780 select MULTI_IRQ_HANDLER
781 select PM_GENERIC_DOMAINS if PM
782 select NEED_MACH_MEMORY_H
784 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
790 select ARCH_MAY_HAVE_PC_FDC
791 select HAVE_PATA_PLATFORM
794 select ARCH_SPARSEMEM_ENABLE
795 select ARCH_USES_GETTIMEOFFSET
797 select NEED_MACH_IO_H
798 select NEED_MACH_MEMORY_H
800 On the Acorn Risc-PC, Linux can support the internal IDE disk and
801 CD-ROM interface, serial and parallel port, and the floppy drive.
808 select ARCH_SPARSEMEM_ENABLE
810 select ARCH_HAS_CPUFREQ
812 select GENERIC_CLOCKEVENTS
814 select ARCH_REQUIRE_GPIOLIB
816 select NEED_MACH_MEMORY_H
819 Support for StrongARM 11x0 based boards.
822 bool "Samsung S3C24XX SoCs"
824 select ARCH_HAS_CPUFREQ
827 select ARCH_USES_GETTIMEOFFSET
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C_RTC if RTC_CLASS
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 select NEED_MACH_IO_H
833 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
834 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
835 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
836 Samsung SMDK2410 development board (and derivatives).
839 bool "Samsung S3C64XX"
847 select ARCH_USES_GETTIMEOFFSET
848 select ARCH_HAS_CPUFREQ
849 select ARCH_REQUIRE_GPIOLIB
850 select SAMSUNG_CLKSRC
851 select SAMSUNG_IRQ_VIC_TIMER
852 select S3C_GPIO_TRACK
854 select USB_ARCH_HAS_OHCI
855 select SAMSUNG_GPIOLIB_4BIT
856 select HAVE_S3C2410_I2C if I2C
857 select HAVE_S3C2410_WATCHDOG if WATCHDOG
859 Samsung S3C64XX series based systems
862 bool "Samsung S5P6440 S5P6450"
868 select HAVE_S3C2410_WATCHDOG if WATCHDOG
869 select GENERIC_CLOCKEVENTS
870 select HAVE_S3C2410_I2C if I2C
871 select HAVE_S3C_RTC if RTC_CLASS
873 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
877 bool "Samsung S5PC100"
882 select ARCH_USES_GETTIMEOFFSET
883 select HAVE_S3C2410_I2C if I2C
884 select HAVE_S3C_RTC if RTC_CLASS
885 select HAVE_S3C2410_WATCHDOG if WATCHDOG
887 Samsung S5PC100 series based systems
890 bool "Samsung S5PV210/S5PC110"
892 select ARCH_SPARSEMEM_ENABLE
893 select ARCH_HAS_HOLES_MEMORYMODEL
898 select ARCH_HAS_CPUFREQ
899 select GENERIC_CLOCKEVENTS
900 select HAVE_S3C2410_I2C if I2C
901 select HAVE_S3C_RTC if RTC_CLASS
902 select HAVE_S3C2410_WATCHDOG if WATCHDOG
903 select NEED_MACH_MEMORY_H
905 Samsung S5PV210/S5PC110 series based systems
908 bool "SAMSUNG EXYNOS"
910 select ARCH_SPARSEMEM_ENABLE
911 select ARCH_HAS_HOLES_MEMORYMODEL
915 select ARCH_HAS_CPUFREQ
916 select GENERIC_CLOCKEVENTS
917 select HAVE_S3C_RTC if RTC_CLASS
918 select HAVE_S3C2410_I2C if I2C
919 select HAVE_S3C2410_WATCHDOG if WATCHDOG
920 select NEED_MACH_MEMORY_H
922 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
931 select ARCH_USES_GETTIMEOFFSET
932 select NEED_MACH_MEMORY_H
933 select NEED_MACH_IO_H
935 Support for the StrongARM based Digital DNARD machine, also known
936 as "Shark" (<http://www.shark-linux.de/shark.html>).
939 bool "ST-Ericsson U300 Series"
945 select ARM_PATCH_PHYS_VIRT
947 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
953 Support for ST-Ericsson U300 series mobile platforms.
956 bool "ST-Ericsson U8500 Series"
960 select GENERIC_CLOCKEVENTS
962 select ARCH_REQUIRE_GPIOLIB
963 select ARCH_HAS_CPUFREQ
965 select MIGHT_HAVE_CACHE_L2X0
967 Support for ST-Ericsson's Ux500 architecture
970 bool "STMicroelectronics Nomadik"
975 select GENERIC_CLOCKEVENTS
977 select MIGHT_HAVE_CACHE_L2X0
978 select ARCH_REQUIRE_GPIOLIB
980 Support for the Nomadik platform by ST-Ericsson
984 select GENERIC_CLOCKEVENTS
985 select ARCH_REQUIRE_GPIOLIB
989 select GENERIC_ALLOCATOR
990 select GENERIC_IRQ_CHIP
991 select ARCH_HAS_HOLES_MEMORYMODEL
993 Support for TI's DaVinci platform.
999 select ARCH_REQUIRE_GPIOLIB
1000 select ARCH_HAS_CPUFREQ
1002 select GENERIC_CLOCKEVENTS
1003 select ARCH_HAS_HOLES_MEMORYMODEL
1005 Support for TI's OMAP platform (OMAP1/2/3/4).
1010 select ARCH_REQUIRE_GPIOLIB
1011 select CLKDEV_LOOKUP
1014 select GENERIC_CLOCKEVENTS
1017 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1020 bool "VIA/WonderMedia 85xx"
1023 select ARCH_HAS_CPUFREQ
1024 select GENERIC_CLOCKEVENTS
1025 select ARCH_REQUIRE_GPIOLIB
1027 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1030 bool "Xilinx Zynq ARM Cortex A9 Platform"
1032 select GENERIC_CLOCKEVENTS
1033 select CLKDEV_LOOKUP
1037 select MIGHT_HAVE_CACHE_L2X0
1040 Support for Xilinx Zynq ARM Cortex A9 Platform
1044 # This is sorted alphabetically by mach-* pathname. However, plat-*
1045 # Kconfigs may be included either alphabetically (according to the
1046 # plat- suffix) or along side the corresponding mach-* source.
1048 source "arch/arm/mach-mvebu/Kconfig"
1050 source "arch/arm/mach-at91/Kconfig"
1052 source "arch/arm/mach-bcmring/Kconfig"
1054 source "arch/arm/mach-clps711x/Kconfig"
1056 source "arch/arm/mach-cns3xxx/Kconfig"
1058 source "arch/arm/mach-davinci/Kconfig"
1060 source "arch/arm/mach-dove/Kconfig"
1062 source "arch/arm/mach-ep93xx/Kconfig"
1064 source "arch/arm/mach-footbridge/Kconfig"
1066 source "arch/arm/mach-gemini/Kconfig"
1068 source "arch/arm/mach-h720x/Kconfig"
1070 source "arch/arm/mach-integrator/Kconfig"
1072 source "arch/arm/mach-iop32x/Kconfig"
1074 source "arch/arm/mach-iop33x/Kconfig"
1076 source "arch/arm/mach-iop13xx/Kconfig"
1078 source "arch/arm/mach-ixp4xx/Kconfig"
1080 source "arch/arm/mach-kirkwood/Kconfig"
1082 source "arch/arm/mach-ks8695/Kconfig"
1084 source "arch/arm/mach-msm/Kconfig"
1086 source "arch/arm/mach-mv78xx0/Kconfig"
1088 source "arch/arm/plat-mxc/Kconfig"
1090 source "arch/arm/mach-mxs/Kconfig"
1092 source "arch/arm/mach-netx/Kconfig"
1094 source "arch/arm/mach-nomadik/Kconfig"
1095 source "arch/arm/plat-nomadik/Kconfig"
1097 source "arch/arm/plat-omap/Kconfig"
1099 source "arch/arm/mach-omap1/Kconfig"
1101 source "arch/arm/mach-omap2/Kconfig"
1103 source "arch/arm/mach-orion5x/Kconfig"
1105 source "arch/arm/mach-pxa/Kconfig"
1106 source "arch/arm/plat-pxa/Kconfig"
1108 source "arch/arm/mach-mmp/Kconfig"
1110 source "arch/arm/mach-realview/Kconfig"
1112 source "arch/arm/mach-sa1100/Kconfig"
1114 source "arch/arm/plat-samsung/Kconfig"
1115 source "arch/arm/plat-s3c24xx/Kconfig"
1117 source "arch/arm/plat-spear/Kconfig"
1119 source "arch/arm/mach-s3c24xx/Kconfig"
1121 source "arch/arm/mach-s3c2412/Kconfig"
1122 source "arch/arm/mach-s3c2440/Kconfig"
1126 source "arch/arm/mach-s3c64xx/Kconfig"
1129 source "arch/arm/mach-s5p64x0/Kconfig"
1131 source "arch/arm/mach-s5pc100/Kconfig"
1133 source "arch/arm/mach-s5pv210/Kconfig"
1135 source "arch/arm/mach-exynos/Kconfig"
1137 source "arch/arm/mach-shmobile/Kconfig"
1139 source "arch/arm/mach-tegra/Kconfig"
1141 source "arch/arm/mach-u300/Kconfig"
1143 source "arch/arm/mach-ux500/Kconfig"
1145 source "arch/arm/mach-versatile/Kconfig"
1147 source "arch/arm/mach-vexpress/Kconfig"
1148 source "arch/arm/plat-versatile/Kconfig"
1150 source "arch/arm/mach-vt8500/Kconfig"
1152 source "arch/arm/mach-w90x900/Kconfig"
1154 # Definitions to make life easier
1160 select GENERIC_CLOCKEVENTS
1165 select GENERIC_IRQ_CHIP
1172 config PLAT_VERSATILE
1175 config ARM_TIMER_SP804
1178 select HAVE_SCHED_CLOCK
1180 source arch/arm/mm/Kconfig
1184 default 16 if ARCH_EP93XX
1188 bool "Enable iWMMXt support"
1189 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1190 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1192 Enable support for iWMMXt context switching at run time if
1193 running on a CPU that supports it.
1197 depends on CPU_XSCALE
1200 config MULTI_IRQ_HANDLER
1203 Allow each machine to specify it's own IRQ handler at run time.
1206 source "arch/arm/Kconfig-nommu"
1209 config ARM_ERRATA_326103
1210 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1213 Executing a SWP instruction to read-only memory does not set bit 11
1214 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1215 treat the access as a read, preventing a COW from occurring and
1216 causing the faulting task to livelock.
1218 config ARM_ERRATA_411920
1219 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1220 depends on CPU_V6 || CPU_V6K
1222 Invalidation of the Instruction Cache operation can
1223 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1224 It does not affect the MPCore. This option enables the ARM Ltd.
1225 recommended workaround.
1227 config ARM_ERRATA_430973
1228 bool "ARM errata: Stale prediction on replaced interworking branch"
1231 This option enables the workaround for the 430973 Cortex-A8
1232 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1233 interworking branch is replaced with another code sequence at the
1234 same virtual address, whether due to self-modifying code or virtual
1235 to physical address re-mapping, Cortex-A8 does not recover from the
1236 stale interworking branch prediction. This results in Cortex-A8
1237 executing the new code sequence in the incorrect ARM or Thumb state.
1238 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1239 and also flushes the branch target cache at every context switch.
1240 Note that setting specific bits in the ACTLR register may not be
1241 available in non-secure mode.
1243 config ARM_ERRATA_458693
1244 bool "ARM errata: Processor deadlock when a false hazard is created"
1247 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1248 erratum. For very specific sequences of memory operations, it is
1249 possible for a hazard condition intended for a cache line to instead
1250 be incorrectly associated with a different cache line. This false
1251 hazard might then cause a processor deadlock. The workaround enables
1252 the L1 caching of the NEON accesses and disables the PLD instruction
1253 in the ACTLR register. Note that setting specific bits in the ACTLR
1254 register may not be available in non-secure mode.
1256 config ARM_ERRATA_460075
1257 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1260 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1261 erratum. Any asynchronous access to the L2 cache may encounter a
1262 situation in which recent store transactions to the L2 cache are lost
1263 and overwritten with stale memory contents from external memory. The
1264 workaround disables the write-allocate mode for the L2 cache via the
1265 ACTLR register. Note that setting specific bits in the ACTLR register
1266 may not be available in non-secure mode.
1268 config ARM_ERRATA_742230
1269 bool "ARM errata: DMB operation may be faulty"
1270 depends on CPU_V7 && SMP
1272 This option enables the workaround for the 742230 Cortex-A9
1273 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1274 between two write operations may not ensure the correct visibility
1275 ordering of the two writes. This workaround sets a specific bit in
1276 the diagnostic register of the Cortex-A9 which causes the DMB
1277 instruction to behave as a DSB, ensuring the correct behaviour of
1280 config ARM_ERRATA_742231
1281 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1282 depends on CPU_V7 && SMP
1284 This option enables the workaround for the 742231 Cortex-A9
1285 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1286 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1287 accessing some data located in the same cache line, may get corrupted
1288 data due to bad handling of the address hazard when the line gets
1289 replaced from one of the CPUs at the same time as another CPU is
1290 accessing it. This workaround sets specific bits in the diagnostic
1291 register of the Cortex-A9 which reduces the linefill issuing
1292 capabilities of the processor.
1294 config PL310_ERRATA_588369
1295 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1296 depends on CACHE_L2X0
1298 The PL310 L2 cache controller implements three types of Clean &
1299 Invalidate maintenance operations: by Physical Address
1300 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1301 They are architecturally defined to behave as the execution of a
1302 clean operation followed immediately by an invalidate operation,
1303 both performing to the same memory location. This functionality
1304 is not correctly implemented in PL310 as clean lines are not
1305 invalidated as a result of these operations.
1307 config ARM_ERRATA_720789
1308 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1311 This option enables the workaround for the 720789 Cortex-A9 (prior to
1312 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1313 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1314 As a consequence of this erratum, some TLB entries which should be
1315 invalidated are not, resulting in an incoherency in the system page
1316 tables. The workaround changes the TLB flushing routines to invalidate
1317 entries regardless of the ASID.
1319 config PL310_ERRATA_727915
1320 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1321 depends on CACHE_L2X0
1323 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1324 operation (offset 0x7FC). This operation runs in background so that
1325 PL310 can handle normal accesses while it is in progress. Under very
1326 rare circumstances, due to this erratum, write data can be lost when
1327 PL310 treats a cacheable write transaction during a Clean &
1328 Invalidate by Way operation.
1330 config ARM_ERRATA_743622
1331 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1334 This option enables the workaround for the 743622 Cortex-A9
1335 (r2p*) erratum. Under very rare conditions, a faulty
1336 optimisation in the Cortex-A9 Store Buffer may lead to data
1337 corruption. This workaround sets a specific bit in the diagnostic
1338 register of the Cortex-A9 which disables the Store Buffer
1339 optimisation, preventing the defect from occurring. This has no
1340 visible impact on the overall performance or power consumption of the
1343 config ARM_ERRATA_751472
1344 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1347 This option enables the workaround for the 751472 Cortex-A9 (prior
1348 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1349 completion of a following broadcasted operation if the second
1350 operation is received by a CPU before the ICIALLUIS has completed,
1351 potentially leading to corrupted entries in the cache or TLB.
1353 config PL310_ERRATA_753970
1354 bool "PL310 errata: cache sync operation may be faulty"
1355 depends on CACHE_PL310
1357 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1359 Under some condition the effect of cache sync operation on
1360 the store buffer still remains when the operation completes.
1361 This means that the store buffer is always asked to drain and
1362 this prevents it from merging any further writes. The workaround
1363 is to replace the normal offset of cache sync operation (0x730)
1364 by another offset targeting an unmapped PL310 register 0x740.
1365 This has the same effect as the cache sync operation: store buffer
1366 drain and waiting for all buffers empty.
1368 config ARM_ERRATA_754322
1369 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1372 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1373 r3p*) erratum. A speculative memory access may cause a page table walk
1374 which starts prior to an ASID switch but completes afterwards. This
1375 can populate the micro-TLB with a stale entry which may be hit with
1376 the new ASID. This workaround places two dsb instructions in the mm
1377 switching code so that no page table walks can cross the ASID switch.
1379 config ARM_ERRATA_754327
1380 bool "ARM errata: no automatic Store Buffer drain"
1381 depends on CPU_V7 && SMP
1383 This option enables the workaround for the 754327 Cortex-A9 (prior to
1384 r2p0) erratum. The Store Buffer does not have any automatic draining
1385 mechanism and therefore a livelock may occur if an external agent
1386 continuously polls a memory location waiting to observe an update.
1387 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1388 written polling loops from denying visibility of updates to memory.
1390 config ARM_ERRATA_364296
1391 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1392 depends on CPU_V6 && !SMP
1394 This options enables the workaround for the 364296 ARM1136
1395 r0p2 erratum (possible cache data corruption with
1396 hit-under-miss enabled). It sets the undocumented bit 31 in
1397 the auxiliary control register and the FI bit in the control
1398 register, thus disabling hit-under-miss without putting the
1399 processor into full low interrupt latency mode. ARM11MPCore
1402 config ARM_ERRATA_764369
1403 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1404 depends on CPU_V7 && SMP
1406 This option enables the workaround for erratum 764369
1407 affecting Cortex-A9 MPCore with two or more processors (all
1408 current revisions). Under certain timing circumstances, a data
1409 cache line maintenance operation by MVA targeting an Inner
1410 Shareable memory region may fail to proceed up to either the
1411 Point of Coherency or to the Point of Unification of the
1412 system. This workaround adds a DSB instruction before the
1413 relevant cache maintenance functions and sets a specific bit
1414 in the diagnostic control register of the SCU.
1416 config PL310_ERRATA_769419
1417 bool "PL310 errata: no automatic Store Buffer drain"
1418 depends on CACHE_L2X0
1420 On revisions of the PL310 prior to r3p2, the Store Buffer does
1421 not automatically drain. This can cause normal, non-cacheable
1422 writes to be retained when the memory system is idle, leading
1423 to suboptimal I/O performance for drivers using coherent DMA.
1424 This option adds a write barrier to the cpu_idle loop so that,
1425 on systems with an outer cache, the store buffer is drained
1430 source "arch/arm/common/Kconfig"
1440 Find out whether you have ISA slots on your motherboard. ISA is the
1441 name of a bus system, i.e. the way the CPU talks to the other stuff
1442 inside your box. Other bus systems are PCI, EISA, MicroChannel
1443 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1444 newer boards don't support it. If you have ISA, say Y, otherwise N.
1446 # Select ISA DMA controller support
1451 # Select ISA DMA interface
1456 bool "PCI support" if MIGHT_HAVE_PCI
1458 Find out whether you have a PCI motherboard. PCI is the name of a
1459 bus system, i.e. the way the CPU talks to the other stuff inside
1460 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1461 VESA. If you have PCI, say Y, otherwise N.
1467 config PCI_NANOENGINE
1468 bool "BSE nanoEngine PCI support"
1469 depends on SA1100_NANOENGINE
1471 Enable PCI on the BSE nanoEngine board.
1476 # Select the host bridge type
1477 config PCI_HOST_VIA82C505
1479 depends on PCI && ARCH_SHARK
1482 config PCI_HOST_ITE8152
1484 depends on PCI && MACH_ARMCORE
1488 source "drivers/pci/Kconfig"
1490 source "drivers/pcmcia/Kconfig"
1494 menu "Kernel Features"
1499 This option should be selected by machines which have an SMP-
1502 The only effect of this option is to make the SMP-related
1503 options available to the user for configuration.
1506 bool "Symmetric Multi-Processing"
1507 depends on CPU_V6K || CPU_V7
1508 depends on GENERIC_CLOCKEVENTS
1511 select USE_GENERIC_SMP_HELPERS
1512 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1514 This enables support for systems with more than one CPU. If you have
1515 a system with only one CPU, like most personal computers, say N. If
1516 you have a system with more than one CPU, say Y.
1518 If you say N here, the kernel will run on single and multiprocessor
1519 machines, but will use only one CPU of a multiprocessor machine. If
1520 you say Y here, the kernel will run on many, but not all, single
1521 processor machines. On a single processor machine, the kernel will
1522 run faster if you say N here.
1524 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1525 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1526 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1528 If you don't know what to do here, say N.
1531 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1532 depends on EXPERIMENTAL
1533 depends on SMP && !XIP_KERNEL
1536 SMP kernels contain instructions which fail on non-SMP processors.
1537 Enabling this option allows the kernel to modify itself to make
1538 these instructions safe. Disabling it allows about 1K of space
1541 If you don't know what to do here, say Y.
1543 config ARM_CPU_TOPOLOGY
1544 bool "Support cpu topology definition"
1545 depends on SMP && CPU_V7
1548 Support ARM cpu topology definition. The MPIDR register defines
1549 affinity between processors which is then used to describe the cpu
1550 topology of an ARM System.
1553 bool "Multi-core scheduler support"
1554 depends on ARM_CPU_TOPOLOGY
1556 Multi-core scheduler support improves the CPU scheduler's decision
1557 making when dealing with multi-core CPU chips at a cost of slightly
1558 increased overhead in some places. If unsure say N here.
1561 bool "SMT scheduler support"
1562 depends on ARM_CPU_TOPOLOGY
1564 Improves the CPU scheduler's decision making when dealing with
1565 MultiThreading at a cost of slightly increased overhead in some
1566 places. If unsure say N here.
1571 This option enables support for the ARM system coherency unit
1573 config ARM_ARCH_TIMER
1574 bool "Architected timer support"
1577 This option enables support for the ARM architected timer
1583 This options enables support for the ARM timer and watchdog unit
1586 prompt "Memory split"
1589 Select the desired split between kernel and user memory.
1591 If you are not absolutely sure what you are doing, leave this
1595 bool "3G/1G user/kernel split"
1597 bool "2G/2G user/kernel split"
1599 bool "1G/3G user/kernel split"
1604 default 0x40000000 if VMSPLIT_1G
1605 default 0x80000000 if VMSPLIT_2G
1609 int "Maximum number of CPUs (2-32)"
1615 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1616 depends on SMP && HOTPLUG && EXPERIMENTAL
1618 Say Y here to experiment with turning CPUs off and on. CPUs
1619 can be controlled through /sys/devices/system/cpu.
1622 bool "Use local timer interrupts"
1625 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1627 Enable support for local timers on SMP platforms, rather then the
1628 legacy IPI broadcast method. Local timers allows the system
1629 accounting to be spread across the timer interval, preventing a
1630 "thundering herd" at every timer tick.
1634 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1635 default 355 if ARCH_U8500
1636 default 264 if MACH_H4700
1637 default 512 if SOC_OMAP5
1640 Maximum number of GPIOs in the system.
1642 If unsure, leave the default value.
1644 source kernel/Kconfig.preempt
1648 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1649 ARCH_S5PV210 || ARCH_EXYNOS4
1650 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1651 default AT91_TIMER_HZ if ARCH_AT91
1652 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1655 config THUMB2_KERNEL
1656 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1657 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1659 select ARM_ASM_UNIFIED
1662 By enabling this option, the kernel will be compiled in
1663 Thumb-2 mode. A compiler/assembler that understand the unified
1664 ARM-Thumb syntax is needed.
1668 config THUMB2_AVOID_R_ARM_THM_JUMP11
1669 bool "Work around buggy Thumb-2 short branch relocations in gas"
1670 depends on THUMB2_KERNEL && MODULES
1673 Various binutils versions can resolve Thumb-2 branches to
1674 locally-defined, preemptible global symbols as short-range "b.n"
1675 branch instructions.
1677 This is a problem, because there's no guarantee the final
1678 destination of the symbol, or any candidate locations for a
1679 trampoline, are within range of the branch. For this reason, the
1680 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1681 relocation in modules at all, and it makes little sense to add
1684 The symptom is that the kernel fails with an "unsupported
1685 relocation" error when loading some modules.
1687 Until fixed tools are available, passing
1688 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1689 code which hits this problem, at the cost of a bit of extra runtime
1690 stack usage in some cases.
1692 The problem is described in more detail at:
1693 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1695 Only Thumb-2 kernels are affected.
1697 Unless you are sure your tools don't have this problem, say Y.
1699 config ARM_ASM_UNIFIED
1703 bool "Use the ARM EABI to compile the kernel"
1705 This option allows for the kernel to be compiled using the latest
1706 ARM ABI (aka EABI). This is only useful if you are using a user
1707 space environment that is also compiled with EABI.
1709 Since there are major incompatibilities between the legacy ABI and
1710 EABI, especially with regard to structure member alignment, this
1711 option also changes the kernel syscall calling convention to
1712 disambiguate both ABIs and allow for backward compatibility support
1713 (selected with CONFIG_OABI_COMPAT).
1715 To use this you need GCC version 4.0.0 or later.
1718 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1719 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1722 This option preserves the old syscall interface along with the
1723 new (ARM EABI) one. It also provides a compatibility layer to
1724 intercept syscalls that have structure arguments which layout
1725 in memory differs between the legacy ABI and the new ARM EABI
1726 (only for non "thumb" binaries). This option adds a tiny
1727 overhead to all syscalls and produces a slightly larger kernel.
1728 If you know you'll be using only pure EABI user space then you
1729 can say N here. If this option is not selected and you attempt
1730 to execute a legacy ABI binary then the result will be
1731 UNPREDICTABLE (in fact it can be predicted that it won't work
1732 at all). If in doubt say Y.
1734 config ARCH_HAS_HOLES_MEMORYMODEL
1737 config ARCH_SPARSEMEM_ENABLE
1740 config ARCH_SPARSEMEM_DEFAULT
1741 def_bool ARCH_SPARSEMEM_ENABLE
1743 config ARCH_SELECT_MEMORY_MODEL
1744 def_bool ARCH_SPARSEMEM_ENABLE
1746 config HAVE_ARCH_PFN_VALID
1747 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1750 bool "High Memory Support"
1753 The address space of ARM processors is only 4 Gigabytes large
1754 and it has to accommodate user address space, kernel address
1755 space as well as some memory mapped IO. That means that, if you
1756 have a large amount of physical memory and/or IO, not all of the
1757 memory can be "permanently mapped" by the kernel. The physical
1758 memory that is not permanently mapped is called "high memory".
1760 Depending on the selected kernel/user memory split, minimum
1761 vmalloc space and actual amount of RAM, you may not need this
1762 option which should result in a slightly faster kernel.
1767 bool "Allocate 2nd-level pagetables from highmem"
1770 config HW_PERF_EVENTS
1771 bool "Enable hardware performance counter support for perf events"
1772 depends on PERF_EVENTS
1775 Enable hardware performance counter support for perf events. If
1776 disabled, perf events will use software events only.
1780 config FORCE_MAX_ZONEORDER
1781 int "Maximum zone order" if ARCH_SHMOBILE
1782 range 11 64 if ARCH_SHMOBILE
1783 default "9" if SA1111
1786 The kernel memory allocator divides physically contiguous memory
1787 blocks into "zones", where each zone is a power of two number of
1788 pages. This option selects the largest power of two that the kernel
1789 keeps in the memory allocator. If you need to allocate very large
1790 blocks of physically contiguous memory, then you may need to
1791 increase this value.
1793 This config option is actually maximum order plus one. For example,
1794 a value of 11 means that the largest free memory block is 2^10 pages.
1797 bool "Timer and CPU usage LEDs"
1798 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1799 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1800 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1801 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1802 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1803 ARCH_AT91 || ARCH_DAVINCI || \
1804 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1806 If you say Y here, the LEDs on your machine will be used
1807 to provide useful information about your current system status.
1809 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1810 be able to select which LEDs are active using the options below. If
1811 you are compiling a kernel for the EBSA-110 or the LART however, the
1812 red LED will simply flash regularly to indicate that the system is
1813 still functional. It is safe to say Y here if you have a CATS
1814 system, but the driver will do nothing.
1817 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1818 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1819 || MACH_OMAP_PERSEUS2
1821 depends on !GENERIC_CLOCKEVENTS
1822 default y if ARCH_EBSA110
1824 If you say Y here, one of the system LEDs (the green one on the
1825 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1826 will flash regularly to indicate that the system is still
1827 operational. This is mainly useful to kernel hackers who are
1828 debugging unstable kernels.
1830 The LART uses the same LED for both Timer LED and CPU usage LED
1831 functions. You may choose to use both, but the Timer LED function
1832 will overrule the CPU usage LED.
1835 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1837 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1838 || MACH_OMAP_PERSEUS2
1841 If you say Y here, the red LED will be used to give a good real
1842 time indication of CPU usage, by lighting whenever the idle task
1843 is not currently executing.
1845 The LART uses the same LED for both Timer LED and CPU usage LED
1846 functions. You may choose to use both, but the Timer LED function
1847 will overrule the CPU usage LED.
1849 config ALIGNMENT_TRAP
1851 depends on CPU_CP15_MMU
1852 default y if !ARCH_EBSA110
1853 select HAVE_PROC_CPU if PROC_FS
1855 ARM processors cannot fetch/store information which is not
1856 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1857 address divisible by 4. On 32-bit ARM processors, these non-aligned
1858 fetch/store instructions will be emulated in software if you say
1859 here, which has a severe performance impact. This is necessary for
1860 correct operation of some network protocols. With an IP-only
1861 configuration it is safe to say N, otherwise say Y.
1863 config UACCESS_WITH_MEMCPY
1864 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1865 depends on MMU && EXPERIMENTAL
1866 default y if CPU_FEROCEON
1868 Implement faster copy_to_user and clear_user methods for CPU
1869 cores where a 8-word STM instruction give significantly higher
1870 memory write throughput than a sequence of individual 32bit stores.
1872 A possible side effect is a slight increase in scheduling latency
1873 between threads sharing the same address space if they invoke
1874 such copy operations with large buffers.
1876 However, if the CPU data cache is using a write-allocate mode,
1877 this option is unlikely to provide any performance gain.
1881 prompt "Enable seccomp to safely compute untrusted bytecode"
1883 This kernel feature is useful for number crunching applications
1884 that may need to compute untrusted bytecode during their
1885 execution. By using pipes or other transports made available to
1886 the process as file descriptors supporting the read/write
1887 syscalls, it's possible to isolate those applications in
1888 their own address space using seccomp. Once seccomp is
1889 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1890 and the task is only allowed to execute a few safe syscalls
1891 defined by each seccomp mode.
1893 config CC_STACKPROTECTOR
1894 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1895 depends on EXPERIMENTAL
1897 This option turns on the -fstack-protector GCC feature. This
1898 feature puts, at the beginning of functions, a canary value on
1899 the stack just before the return address, and validates
1900 the value just before actually returning. Stack based buffer
1901 overflows (that need to overwrite this return address) now also
1902 overwrite the canary, which gets detected and the attack is then
1903 neutralized via a kernel panic.
1904 This feature requires gcc version 4.2 or above.
1906 config DEPRECATED_PARAM_STRUCT
1907 bool "Provide old way to pass kernel parameters"
1909 This was deprecated in 2001 and announced to live on for 5 years.
1910 Some old boot loaders still use this way.
1917 bool "Flattened Device Tree support"
1919 select OF_EARLY_FLATTREE
1922 Include support for flattened device tree machine descriptions.
1924 # Compressed boot loader in ROM. Yes, we really want to ask about
1925 # TEXT and BSS so we preserve their values in the config files.
1926 config ZBOOT_ROM_TEXT
1927 hex "Compressed ROM boot loader base address"
1930 The physical address at which the ROM-able zImage is to be
1931 placed in the target. Platforms which normally make use of
1932 ROM-able zImage formats normally set this to a suitable
1933 value in their defconfig file.
1935 If ZBOOT_ROM is not enabled, this has no effect.
1937 config ZBOOT_ROM_BSS
1938 hex "Compressed ROM boot loader BSS address"
1941 The base address of an area of read/write memory in the target
1942 for the ROM-able zImage which must be available while the
1943 decompressor is running. It must be large enough to hold the
1944 entire decompressed kernel plus an additional 128 KiB.
1945 Platforms which normally make use of ROM-able zImage formats
1946 normally set this to a suitable value in their defconfig file.
1948 If ZBOOT_ROM is not enabled, this has no effect.
1951 bool "Compressed boot loader in ROM/flash"
1952 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1954 Say Y here if you intend to execute your compressed kernel image
1955 (zImage) directly from ROM or flash. If unsure, say N.
1958 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1959 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1960 default ZBOOT_ROM_NONE
1962 Include experimental SD/MMC loading code in the ROM-able zImage.
1963 With this enabled it is possible to write the ROM-able zImage
1964 kernel image to an MMC or SD card and boot the kernel straight
1965 from the reset vector. At reset the processor Mask ROM will load
1966 the first part of the ROM-able zImage which in turn loads the
1967 rest the kernel image to RAM.
1969 config ZBOOT_ROM_NONE
1970 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1972 Do not load image from SD or MMC
1974 config ZBOOT_ROM_MMCIF
1975 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1977 Load image from MMCIF hardware block.
1979 config ZBOOT_ROM_SH_MOBILE_SDHI
1980 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1982 Load image from SDHI hardware block
1986 config ARM_APPENDED_DTB
1987 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1988 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1990 With this option, the boot code will look for a device tree binary
1991 (DTB) appended to zImage
1992 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1994 This is meant as a backward compatibility convenience for those
1995 systems with a bootloader that can't be upgraded to accommodate
1996 the documented boot protocol using a device tree.
1998 Beware that there is very little in terms of protection against
1999 this option being confused by leftover garbage in memory that might
2000 look like a DTB header after a reboot if no actual DTB is appended
2001 to zImage. Do not leave this option active in a production kernel
2002 if you don't intend to always append a DTB. Proper passing of the
2003 location into r2 of a bootloader provided DTB is always preferable
2006 config ARM_ATAG_DTB_COMPAT
2007 bool "Supplement the appended DTB with traditional ATAG information"
2008 depends on ARM_APPENDED_DTB
2010 Some old bootloaders can't be updated to a DTB capable one, yet
2011 they provide ATAGs with memory configuration, the ramdisk address,
2012 the kernel cmdline string, etc. Such information is dynamically
2013 provided by the bootloader and can't always be stored in a static
2014 DTB. To allow a device tree enabled kernel to be used with such
2015 bootloaders, this option allows zImage to extract the information
2016 from the ATAG list and store it at run time into the appended DTB.
2019 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2020 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2022 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2023 bool "Use bootloader kernel arguments if available"
2025 Uses the command-line options passed by the boot loader instead of
2026 the device tree bootargs property. If the boot loader doesn't provide
2027 any, the device tree bootargs property will be used.
2029 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2030 bool "Extend with bootloader kernel arguments"
2032 The command-line arguments provided by the boot loader will be
2033 appended to the the device tree bootargs property.
2038 string "Default kernel command string"
2041 On some architectures (EBSA110 and CATS), there is currently no way
2042 for the boot loader to pass arguments to the kernel. For these
2043 architectures, you should supply some command-line options at build
2044 time by entering them here. As a minimum, you should specify the
2045 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2048 prompt "Kernel command line type" if CMDLINE != ""
2049 default CMDLINE_FROM_BOOTLOADER
2051 config CMDLINE_FROM_BOOTLOADER
2052 bool "Use bootloader kernel arguments if available"
2054 Uses the command-line options passed by the boot loader. If
2055 the boot loader doesn't provide any, the default kernel command
2056 string provided in CMDLINE will be used.
2058 config CMDLINE_EXTEND
2059 bool "Extend bootloader kernel arguments"
2061 The command-line arguments provided by the boot loader will be
2062 appended to the default kernel command string.
2064 config CMDLINE_FORCE
2065 bool "Always use the default kernel command string"
2067 Always use the default kernel command string, even if the boot
2068 loader passes other arguments to the kernel.
2069 This is useful if you cannot or don't want to change the
2070 command-line options your boot loader passes to the kernel.
2074 bool "Kernel Execute-In-Place from ROM"
2075 depends on !ZBOOT_ROM && !ARM_LPAE
2077 Execute-In-Place allows the kernel to run from non-volatile storage
2078 directly addressable by the CPU, such as NOR flash. This saves RAM
2079 space since the text section of the kernel is not loaded from flash
2080 to RAM. Read-write sections, such as the data section and stack,
2081 are still copied to RAM. The XIP kernel is not compressed since
2082 it has to run directly from flash, so it will take more space to
2083 store it. The flash address used to link the kernel object files,
2084 and for storing it, is configuration dependent. Therefore, if you
2085 say Y here, you must know the proper physical address where to
2086 store the kernel image depending on your own flash memory usage.
2088 Also note that the make target becomes "make xipImage" rather than
2089 "make zImage" or "make Image". The final kernel binary to put in
2090 ROM memory will be arch/arm/boot/xipImage.
2094 config XIP_PHYS_ADDR
2095 hex "XIP Kernel Physical Location"
2096 depends on XIP_KERNEL
2097 default "0x00080000"
2099 This is the physical address in your flash memory the kernel will
2100 be linked for and stored to. This address is dependent on your
2104 bool "Kexec system call (EXPERIMENTAL)"
2105 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2107 kexec is a system call that implements the ability to shutdown your
2108 current kernel, and to start another kernel. It is like a reboot
2109 but it is independent of the system firmware. And like a reboot
2110 you can start any kernel with it, not just Linux.
2112 It is an ongoing process to be certain the hardware in a machine
2113 is properly shutdown, so do not be surprised if this code does not
2114 initially work for you. It may help to enable device hotplugging
2118 bool "Export atags in procfs"
2122 Should the atags used to boot the kernel be exported in an "atags"
2123 file in procfs. Useful with kexec.
2126 bool "Build kdump crash kernel (EXPERIMENTAL)"
2127 depends on EXPERIMENTAL
2129 Generate crash dump after being started by kexec. This should
2130 be normally only set in special crash dump kernels which are
2131 loaded in the main kernel with kexec-tools into a specially
2132 reserved region and then later executed after a crash by
2133 kdump/kexec. The crash dump kernel must be compiled to a
2134 memory address not used by the main kernel
2136 For more details see Documentation/kdump/kdump.txt
2138 config AUTO_ZRELADDR
2139 bool "Auto calculation of the decompressed kernel image address"
2140 depends on !ZBOOT_ROM && !ARCH_U300
2142 ZRELADDR is the physical address where the decompressed kernel
2143 image will be placed. If AUTO_ZRELADDR is selected, the address
2144 will be determined at run-time by masking the current IP with
2145 0xf8000000. This assumes the zImage being placed in the first 128MB
2146 from start of memory.
2150 menu "CPU Power Management"
2154 source "drivers/cpufreq/Kconfig"
2157 tristate "CPUfreq driver for i.MX CPUs"
2158 depends on ARCH_MXC && CPU_FREQ
2159 select CPU_FREQ_TABLE
2161 This enables the CPUfreq driver for i.MX CPUs.
2163 config CPU_FREQ_SA1100
2166 config CPU_FREQ_SA1110
2169 config CPU_FREQ_INTEGRATOR
2170 tristate "CPUfreq driver for ARM Integrator CPUs"
2171 depends on ARCH_INTEGRATOR && CPU_FREQ
2174 This enables the CPUfreq driver for ARM Integrator CPUs.
2176 For details, take a look at <file:Documentation/cpu-freq>.
2182 depends on CPU_FREQ && ARCH_PXA && PXA25x
2184 select CPU_FREQ_TABLE
2185 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2190 Internal configuration node for common cpufreq on Samsung SoC
2192 config CPU_FREQ_S3C24XX
2193 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2194 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2197 This enables the CPUfreq driver for the Samsung S3C24XX family
2200 For details, take a look at <file:Documentation/cpu-freq>.
2204 config CPU_FREQ_S3C24XX_PLL
2205 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2206 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2208 Compile in support for changing the PLL frequency from the
2209 S3C24XX series CPUfreq driver. The PLL takes time to settle
2210 after a frequency change, so by default it is not enabled.
2212 This also means that the PLL tables for the selected CPU(s) will
2213 be built which may increase the size of the kernel image.
2215 config CPU_FREQ_S3C24XX_DEBUG
2216 bool "Debug CPUfreq Samsung driver core"
2217 depends on CPU_FREQ_S3C24XX
2219 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2221 config CPU_FREQ_S3C24XX_IODEBUG
2222 bool "Debug CPUfreq Samsung driver IO timing"
2223 depends on CPU_FREQ_S3C24XX
2225 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2227 config CPU_FREQ_S3C24XX_DEBUGFS
2228 bool "Export debugfs for CPUFreq"
2229 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2231 Export status information via debugfs.
2235 source "drivers/cpuidle/Kconfig"
2239 menu "Floating point emulation"
2241 comment "At least one emulation must be selected"
2244 bool "NWFPE math emulation"
2245 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2247 Say Y to include the NWFPE floating point emulator in the kernel.
2248 This is necessary to run most binaries. Linux does not currently
2249 support floating point hardware so you need to say Y here even if
2250 your machine has an FPA or floating point co-processor podule.
2252 You may say N here if you are going to load the Acorn FPEmulator
2253 early in the bootup.
2256 bool "Support extended precision"
2257 depends on FPE_NWFPE
2259 Say Y to include 80-bit support in the kernel floating-point
2260 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2261 Note that gcc does not generate 80-bit operations by default,
2262 so in most cases this option only enlarges the size of the
2263 floating point emulator without any good reason.
2265 You almost surely want to say N here.
2268 bool "FastFPE math emulation (EXPERIMENTAL)"
2269 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2271 Say Y here to include the FAST floating point emulator in the kernel.
2272 This is an experimental much faster emulator which now also has full
2273 precision for the mantissa. It does not support any exceptions.
2274 It is very simple, and approximately 3-6 times faster than NWFPE.
2276 It should be sufficient for most programs. It may be not suitable
2277 for scientific calculations, but you have to check this for yourself.
2278 If you do not feel you need a faster FP emulation you should better
2282 bool "VFP-format floating point maths"
2283 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2285 Say Y to include VFP support code in the kernel. This is needed
2286 if your hardware includes a VFP unit.
2288 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2289 release notes and additional status information.
2291 Say N if your target does not have VFP hardware.
2299 bool "Advanced SIMD (NEON) Extension support"
2300 depends on VFPv3 && CPU_V7
2302 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2307 menu "Userspace binary formats"
2309 source "fs/Kconfig.binfmt"
2312 tristate "RISC OS personality"
2315 Say Y here to include the kernel code necessary if you want to run
2316 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2317 experimental; if this sounds frightening, say N and sleep in peace.
2318 You can also say M here to compile this support as a module (which
2319 will be called arthur).
2323 menu "Power management options"
2325 source "kernel/power/Kconfig"
2327 config ARCH_SUSPEND_POSSIBLE
2328 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2329 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2330 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2333 config ARM_CPU_SUSPEND
2338 source "net/Kconfig"
2340 source "drivers/Kconfig"
2344 source "arch/arm/Kconfig.debug"
2346 source "security/Kconfig"
2348 source "crypto/Kconfig"
2350 source "lib/Kconfig"