4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
276 select COMMON_CLK_VERSATILE
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_MEMORY_H
284 select MULTI_IRQ_HANDLER
286 Support for ARM's Integrator platform.
289 bool "ARM Ltd. RealView family"
292 select COMMON_CLK_VERSATILE
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLCD
298 select ARM_TIMER_SP804
299 select GPIO_PL061 if GPIOLIB
300 select NEED_MACH_MEMORY_H
302 This enables support for ARM Ltd RealView boards.
304 config ARCH_VERSATILE
305 bool "ARM Ltd. Versatile family"
309 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLOCK
315 select PLAT_VERSATILE_CLCD
316 select PLAT_VERSATILE_FPGA_IRQ
317 select ARM_TIMER_SP804
319 This enables support for ARM Ltd Versatile board.
322 bool "ARM Ltd. Versatile Express family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
325 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
330 select HAVE_PATA_PLATFORM
333 select PLAT_VERSATILE
334 select PLAT_VERSATILE_CLCD
335 select REGULATOR_FIXED_VOLTAGE if REGULATOR
337 This enables support for the ARM Ltd Versatile Express boards.
341 select ARCH_REQUIRE_GPIOLIB
345 select NEED_MACH_IO_H if PCCARD
347 This enables support for systems based on Atmel
348 AT91RM9200 and AT91SAM9* processors.
351 bool "Broadcom BCM2835 family"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select ARM_ERRATA_411920
355 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select MULTI_IRQ_HANDLER
364 This enables support for the Broadcom BCM2835 SoC. This SoC is
365 use in the Raspberry Pi, and Roku 2 devices.
368 bool "Calxeda Highbank-based"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
372 select ARM_TIMER_SP804
377 select GENERIC_CLOCKEVENTS
383 Support for the Calxeda Highbank SoC based boards.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
388 select ARCH_USES_GETTIMEOFFSET
391 select NEED_MACH_MEMORY_H
393 Support for Cirrus Logic 711x/721x/731x based boards.
396 bool "Cavium Networks CNS3XXX family"
398 select GENERIC_CLOCKEVENTS
400 select MIGHT_HAVE_CACHE_L2X0
401 select MIGHT_HAVE_PCI
402 select PCI_DOMAINS if PCI
404 Support for Cavium Networks CNS3XXX platform.
407 bool "Cortina Systems Gemini"
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_USES_GETTIMEOFFSET
412 Support for the Cortina Systems Gemini family SoCs
417 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_CLOCKEVENTS
420 select GENERIC_IRQ_CHIP
421 select MIGHT_HAVE_CACHE_L2X0
426 Support for CSR SiRFprimaII/Marco/Polo platforms
433 select ARCH_USES_GETTIMEOFFSET
434 select NEED_MACH_IO_H
435 select NEED_MACH_MEMORY_H
437 This is an evaluation board for the StrongARM processor available
438 from Digital. It has limited hardware on-board, including an
439 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_REQUIRE_GPIOLIB
449 select ARCH_HAS_HOLES_MEMORYMODEL
450 select ARCH_USES_GETTIMEOFFSET
451 select NEED_MACH_MEMORY_H
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Freescale MXC/iMX-based"
469 select GENERIC_CLOCKEVENTS
470 select ARCH_REQUIRE_GPIOLIB
473 select GENERIC_IRQ_CHIP
474 select MULTI_IRQ_HANDLER
478 Support for Freescale MXC/iMX-based family of processors
481 bool "Freescale MXS-based"
482 select GENERIC_CLOCKEVENTS
483 select ARCH_REQUIRE_GPIOLIB
487 select HAVE_CLK_PREPARE
488 select MULTI_IRQ_HANDLER
493 Support for Freescale MXS-based family of processors
496 bool "Hilscher NetX based"
500 select GENERIC_CLOCKEVENTS
502 This enables support for systems based on the Hilscher NetX Soc
505 bool "Hynix HMS720x-based"
508 select ARCH_USES_GETTIMEOFFSET
510 This enables support for systems based on the Hynix HMS720x
518 select ARCH_SUPPORTS_MSI
520 select NEED_MACH_MEMORY_H
521 select NEED_RET_TO_USER
523 Support for Intel's IOP13XX (XScale) family of processors.
529 select NEED_RET_TO_USER
532 select ARCH_REQUIRE_GPIOLIB
534 Support for Intel's 80219 and IOP32X (XScale) family of
541 select NEED_RET_TO_USER
544 select ARCH_REQUIRE_GPIOLIB
546 Support for Intel's IOP33X (XScale) family of processors.
551 select ARCH_HAS_DMA_SET_COHERENT_MASK
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
556 select MIGHT_HAVE_PCI
557 select NEED_MACH_IO_H
558 select DMABOUNCE if PCI
560 Support for Intel's IXP4XX (XScale) family of processors.
563 bool "Marvell SOCs with Device Tree support"
564 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
568 select GENERIC_IRQ_CHIP
572 Support for the Marvell SoC Family with device tree support
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
582 Support for the Marvell Dove SoC 88AP510
585 bool "Marvell Kirkwood"
588 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
592 Support for the following Marvell Kirkwood series SoCs:
593 88F6180, 88F6192 and 88F6281.
599 select ARCH_REQUIRE_GPIOLIB
602 select USB_ARCH_HAS_OHCI
604 select GENERIC_CLOCKEVENTS
608 Support for the NXP LPC32XX family of processors
611 bool "Marvell MV78xx0"
614 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
618 Support for the following Marvell MV78xx0 series SoCs:
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 Support for the following Marvell Orion 5x series SoCs:
631 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
632 Orion-2 (5281), Orion-1-90 (6183).
635 bool "Marvell PXA168/910/MMP2"
637 select ARCH_REQUIRE_GPIOLIB
639 select GENERIC_CLOCKEVENTS
644 select GENERIC_ALLOCATOR
646 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
649 bool "Micrel/Kendin KS8695"
651 select ARCH_REQUIRE_GPIOLIB
652 select NEED_MACH_MEMORY_H
654 select GENERIC_CLOCKEVENTS
656 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
657 System-on-Chip devices.
660 bool "Nuvoton W90X900 CPU"
662 select ARCH_REQUIRE_GPIOLIB
665 select GENERIC_CLOCKEVENTS
667 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
668 At present, the w90x900 has been renamed nuc900, regarding
669 the ARM series product line, you can login the following
670 link address to know more.
672 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
673 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
679 select GENERIC_CLOCKEVENTS
683 select MIGHT_HAVE_CACHE_L2X0
684 select ARCH_HAS_CPUFREQ
688 This enables support for NVIDIA Tegra based systems (Tegra APX,
689 Tegra 6xx and Tegra 2 series).
691 config ARCH_PICOXCELL
692 bool "Picochip picoXcell"
693 select ARCH_REQUIRE_GPIOLIB
694 select ARM_PATCH_PHYS_VIRT
698 select DW_APB_TIMER_OF
699 select GENERIC_CLOCKEVENTS
706 This enables support for systems based on the Picochip picoXcell
707 family of Femtocell devices. The picoxcell support requires device tree
711 bool "PXA2xx/PXA3xx-based"
714 select ARCH_HAS_CPUFREQ
717 select ARCH_REQUIRE_GPIOLIB
718 select GENERIC_CLOCKEVENTS
723 select MULTI_IRQ_HANDLER
724 select ARM_CPU_SUSPEND if PM
727 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
732 select GENERIC_CLOCKEVENTS
733 select ARCH_REQUIRE_GPIOLIB
736 Support for Qualcomm MSM/QSD based systems. This runs on the
737 apps processor of the MSM/QSD and depends on a shared memory
738 interface to the modem processor which runs the baseband
739 stack and controls some vital subsystems
740 (clock and power control, etc).
743 bool "Renesas SH-Mobile / R-Mobile"
746 select HAVE_MACH_CLKDEV
748 select GENERIC_CLOCKEVENTS
749 select MIGHT_HAVE_CACHE_L2X0
752 select MULTI_IRQ_HANDLER
753 select PM_GENERIC_DOMAINS if PM
754 select NEED_MACH_MEMORY_H
756 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
762 select ARCH_MAY_HAVE_PC_FDC
763 select HAVE_PATA_PLATFORM
766 select ARCH_SPARSEMEM_ENABLE
767 select ARCH_USES_GETTIMEOFFSET
769 select NEED_MACH_IO_H
770 select NEED_MACH_MEMORY_H
772 On the Acorn Risc-PC, Linux can support the internal IDE disk and
773 CD-ROM interface, serial and parallel port, and the floppy drive.
780 select ARCH_SPARSEMEM_ENABLE
782 select ARCH_HAS_CPUFREQ
784 select GENERIC_CLOCKEVENTS
786 select ARCH_REQUIRE_GPIOLIB
788 select NEED_MACH_MEMORY_H
791 Support for StrongARM 11x0 based boards.
794 bool "Samsung S3C24XX SoCs"
796 select ARCH_HAS_CPUFREQ
799 select ARCH_USES_GETTIMEOFFSET
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C_RTC if RTC_CLASS
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select NEED_MACH_IO_H
805 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
806 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
807 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
808 Samsung SMDK2410 development board (and derivatives).
811 bool "Samsung S3C64XX"
819 select ARCH_USES_GETTIMEOFFSET
820 select ARCH_HAS_CPUFREQ
821 select ARCH_REQUIRE_GPIOLIB
822 select SAMSUNG_CLKSRC
823 select SAMSUNG_IRQ_VIC_TIMER
824 select S3C_GPIO_TRACK
826 select USB_ARCH_HAS_OHCI
827 select SAMSUNG_GPIOLIB_4BIT
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 Samsung S3C64XX series based systems
834 bool "Samsung S5P6440 S5P6450"
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C_RTC if RTC_CLASS
845 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
849 bool "Samsung S5PC100"
854 select ARCH_USES_GETTIMEOFFSET
855 select HAVE_S3C2410_I2C if I2C
856 select HAVE_S3C_RTC if RTC_CLASS
857 select HAVE_S3C2410_WATCHDOG if WATCHDOG
859 Samsung S5PC100 series based systems
862 bool "Samsung S5PV210/S5PC110"
864 select ARCH_SPARSEMEM_ENABLE
865 select ARCH_HAS_HOLES_MEMORYMODEL
870 select ARCH_HAS_CPUFREQ
871 select GENERIC_CLOCKEVENTS
872 select HAVE_S3C2410_I2C if I2C
873 select HAVE_S3C_RTC if RTC_CLASS
874 select HAVE_S3C2410_WATCHDOG if WATCHDOG
875 select NEED_MACH_MEMORY_H
877 Samsung S5PV210/S5PC110 series based systems
880 bool "SAMSUNG EXYNOS"
882 select ARCH_SPARSEMEM_ENABLE
883 select ARCH_HAS_HOLES_MEMORYMODEL
887 select ARCH_HAS_CPUFREQ
888 select GENERIC_CLOCKEVENTS
889 select HAVE_S3C_RTC if RTC_CLASS
890 select HAVE_S3C2410_I2C if I2C
891 select HAVE_S3C2410_WATCHDOG if WATCHDOG
892 select NEED_MACH_MEMORY_H
894 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
903 select ARCH_USES_GETTIMEOFFSET
904 select NEED_MACH_MEMORY_H
906 Support for the StrongARM based Digital DNARD machine, also known
907 as "Shark" (<http://www.shark-linux.de/shark.html>).
910 bool "ST-Ericsson U300 Series"
916 select ARM_PATCH_PHYS_VIRT
918 select GENERIC_CLOCKEVENTS
922 select ARCH_REQUIRE_GPIOLIB
925 Support for ST-Ericsson U300 series mobile platforms.
928 bool "ST-Ericsson U8500 Series"
932 select GENERIC_CLOCKEVENTS
934 select ARCH_REQUIRE_GPIOLIB
935 select ARCH_HAS_CPUFREQ
937 select MIGHT_HAVE_CACHE_L2X0
939 Support for ST-Ericsson's Ux500 architecture
942 bool "STMicroelectronics Nomadik"
947 select GENERIC_CLOCKEVENTS
949 select MIGHT_HAVE_CACHE_L2X0
950 select ARCH_REQUIRE_GPIOLIB
952 Support for the Nomadik platform by ST-Ericsson
956 select GENERIC_CLOCKEVENTS
957 select ARCH_REQUIRE_GPIOLIB
961 select GENERIC_ALLOCATOR
962 select GENERIC_IRQ_CHIP
963 select ARCH_HAS_HOLES_MEMORYMODEL
965 Support for TI's DaVinci platform.
971 select ARCH_REQUIRE_GPIOLIB
972 select ARCH_HAS_CPUFREQ
974 select GENERIC_CLOCKEVENTS
975 select ARCH_HAS_HOLES_MEMORYMODEL
977 Support for TI's OMAP platform (OMAP1/2/3/4).
982 select ARCH_REQUIRE_GPIOLIB
986 select GENERIC_CLOCKEVENTS
989 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
992 bool "VIA/WonderMedia 85xx"
995 select ARCH_HAS_CPUFREQ
996 select GENERIC_CLOCKEVENTS
997 select ARCH_REQUIRE_GPIOLIB
1001 select CLKDEV_LOOKUP
1003 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1006 bool "Xilinx Zynq ARM Cortex A9 Platform"
1008 select GENERIC_CLOCKEVENTS
1009 select CLKDEV_LOOKUP
1013 select MIGHT_HAVE_CACHE_L2X0
1016 Support for Xilinx Zynq ARM Cortex A9 Platform
1020 # This is sorted alphabetically by mach-* pathname. However, plat-*
1021 # Kconfigs may be included either alphabetically (according to the
1022 # plat- suffix) or along side the corresponding mach-* source.
1024 source "arch/arm/mach-mvebu/Kconfig"
1026 source "arch/arm/mach-at91/Kconfig"
1028 source "arch/arm/mach-clps711x/Kconfig"
1030 source "arch/arm/mach-cns3xxx/Kconfig"
1032 source "arch/arm/mach-davinci/Kconfig"
1034 source "arch/arm/mach-dove/Kconfig"
1036 source "arch/arm/mach-ep93xx/Kconfig"
1038 source "arch/arm/mach-footbridge/Kconfig"
1040 source "arch/arm/mach-gemini/Kconfig"
1042 source "arch/arm/mach-h720x/Kconfig"
1044 source "arch/arm/mach-integrator/Kconfig"
1046 source "arch/arm/mach-iop32x/Kconfig"
1048 source "arch/arm/mach-iop33x/Kconfig"
1050 source "arch/arm/mach-iop13xx/Kconfig"
1052 source "arch/arm/mach-ixp4xx/Kconfig"
1054 source "arch/arm/mach-kirkwood/Kconfig"
1056 source "arch/arm/mach-ks8695/Kconfig"
1058 source "arch/arm/mach-msm/Kconfig"
1060 source "arch/arm/mach-mv78xx0/Kconfig"
1062 source "arch/arm/plat-mxc/Kconfig"
1064 source "arch/arm/mach-mxs/Kconfig"
1066 source "arch/arm/mach-netx/Kconfig"
1068 source "arch/arm/mach-nomadik/Kconfig"
1069 source "arch/arm/plat-nomadik/Kconfig"
1071 source "arch/arm/plat-omap/Kconfig"
1073 source "arch/arm/mach-omap1/Kconfig"
1075 source "arch/arm/mach-omap2/Kconfig"
1077 source "arch/arm/mach-orion5x/Kconfig"
1079 source "arch/arm/mach-pxa/Kconfig"
1080 source "arch/arm/plat-pxa/Kconfig"
1082 source "arch/arm/mach-mmp/Kconfig"
1084 source "arch/arm/mach-realview/Kconfig"
1086 source "arch/arm/mach-sa1100/Kconfig"
1088 source "arch/arm/plat-samsung/Kconfig"
1089 source "arch/arm/plat-s3c24xx/Kconfig"
1091 source "arch/arm/plat-spear/Kconfig"
1093 source "arch/arm/mach-s3c24xx/Kconfig"
1095 source "arch/arm/mach-s3c2412/Kconfig"
1096 source "arch/arm/mach-s3c2440/Kconfig"
1100 source "arch/arm/mach-s3c64xx/Kconfig"
1103 source "arch/arm/mach-s5p64x0/Kconfig"
1105 source "arch/arm/mach-s5pc100/Kconfig"
1107 source "arch/arm/mach-s5pv210/Kconfig"
1109 source "arch/arm/mach-exynos/Kconfig"
1111 source "arch/arm/mach-shmobile/Kconfig"
1113 source "arch/arm/mach-prima2/Kconfig"
1115 source "arch/arm/mach-tegra/Kconfig"
1117 source "arch/arm/mach-u300/Kconfig"
1119 source "arch/arm/mach-ux500/Kconfig"
1121 source "arch/arm/mach-versatile/Kconfig"
1123 source "arch/arm/mach-vexpress/Kconfig"
1124 source "arch/arm/plat-versatile/Kconfig"
1126 source "arch/arm/mach-w90x900/Kconfig"
1128 # Definitions to make life easier
1134 select GENERIC_CLOCKEVENTS
1139 select GENERIC_IRQ_CHIP
1146 config PLAT_VERSATILE
1149 config ARM_TIMER_SP804
1152 select HAVE_SCHED_CLOCK
1154 source arch/arm/mm/Kconfig
1158 default 16 if ARCH_EP93XX
1162 bool "Enable iWMMXt support"
1163 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1164 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1166 Enable support for iWMMXt context switching at run time if
1167 running on a CPU that supports it.
1171 depends on CPU_XSCALE
1174 config MULTI_IRQ_HANDLER
1177 Allow each machine to specify it's own IRQ handler at run time.
1180 source "arch/arm/Kconfig-nommu"
1183 config ARM_ERRATA_326103
1184 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1187 Executing a SWP instruction to read-only memory does not set bit 11
1188 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1189 treat the access as a read, preventing a COW from occurring and
1190 causing the faulting task to livelock.
1192 config ARM_ERRATA_411920
1193 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1194 depends on CPU_V6 || CPU_V6K
1196 Invalidation of the Instruction Cache operation can
1197 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1198 It does not affect the MPCore. This option enables the ARM Ltd.
1199 recommended workaround.
1201 config ARM_ERRATA_430973
1202 bool "ARM errata: Stale prediction on replaced interworking branch"
1205 This option enables the workaround for the 430973 Cortex-A8
1206 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1207 interworking branch is replaced with another code sequence at the
1208 same virtual address, whether due to self-modifying code or virtual
1209 to physical address re-mapping, Cortex-A8 does not recover from the
1210 stale interworking branch prediction. This results in Cortex-A8
1211 executing the new code sequence in the incorrect ARM or Thumb state.
1212 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1213 and also flushes the branch target cache at every context switch.
1214 Note that setting specific bits in the ACTLR register may not be
1215 available in non-secure mode.
1217 config ARM_ERRATA_458693
1218 bool "ARM errata: Processor deadlock when a false hazard is created"
1221 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1222 erratum. For very specific sequences of memory operations, it is
1223 possible for a hazard condition intended for a cache line to instead
1224 be incorrectly associated with a different cache line. This false
1225 hazard might then cause a processor deadlock. The workaround enables
1226 the L1 caching of the NEON accesses and disables the PLD instruction
1227 in the ACTLR register. Note that setting specific bits in the ACTLR
1228 register may not be available in non-secure mode.
1230 config ARM_ERRATA_460075
1231 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1234 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1235 erratum. Any asynchronous access to the L2 cache may encounter a
1236 situation in which recent store transactions to the L2 cache are lost
1237 and overwritten with stale memory contents from external memory. The
1238 workaround disables the write-allocate mode for the L2 cache via the
1239 ACTLR register. Note that setting specific bits in the ACTLR register
1240 may not be available in non-secure mode.
1242 config ARM_ERRATA_742230
1243 bool "ARM errata: DMB operation may be faulty"
1244 depends on CPU_V7 && SMP
1246 This option enables the workaround for the 742230 Cortex-A9
1247 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1248 between two write operations may not ensure the correct visibility
1249 ordering of the two writes. This workaround sets a specific bit in
1250 the diagnostic register of the Cortex-A9 which causes the DMB
1251 instruction to behave as a DSB, ensuring the correct behaviour of
1254 config ARM_ERRATA_742231
1255 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 742231 Cortex-A9
1259 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1260 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1261 accessing some data located in the same cache line, may get corrupted
1262 data due to bad handling of the address hazard when the line gets
1263 replaced from one of the CPUs at the same time as another CPU is
1264 accessing it. This workaround sets specific bits in the diagnostic
1265 register of the Cortex-A9 which reduces the linefill issuing
1266 capabilities of the processor.
1268 config PL310_ERRATA_588369
1269 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1270 depends on CACHE_L2X0
1272 The PL310 L2 cache controller implements three types of Clean &
1273 Invalidate maintenance operations: by Physical Address
1274 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1275 They are architecturally defined to behave as the execution of a
1276 clean operation followed immediately by an invalidate operation,
1277 both performing to the same memory location. This functionality
1278 is not correctly implemented in PL310 as clean lines are not
1279 invalidated as a result of these operations.
1281 config ARM_ERRATA_720789
1282 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1285 This option enables the workaround for the 720789 Cortex-A9 (prior to
1286 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1287 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1288 As a consequence of this erratum, some TLB entries which should be
1289 invalidated are not, resulting in an incoherency in the system page
1290 tables. The workaround changes the TLB flushing routines to invalidate
1291 entries regardless of the ASID.
1293 config PL310_ERRATA_727915
1294 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1295 depends on CACHE_L2X0
1297 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1298 operation (offset 0x7FC). This operation runs in background so that
1299 PL310 can handle normal accesses while it is in progress. Under very
1300 rare circumstances, due to this erratum, write data can be lost when
1301 PL310 treats a cacheable write transaction during a Clean &
1302 Invalidate by Way operation.
1304 config ARM_ERRATA_743622
1305 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1308 This option enables the workaround for the 743622 Cortex-A9
1309 (r2p*) erratum. Under very rare conditions, a faulty
1310 optimisation in the Cortex-A9 Store Buffer may lead to data
1311 corruption. This workaround sets a specific bit in the diagnostic
1312 register of the Cortex-A9 which disables the Store Buffer
1313 optimisation, preventing the defect from occurring. This has no
1314 visible impact on the overall performance or power consumption of the
1317 config ARM_ERRATA_751472
1318 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1321 This option enables the workaround for the 751472 Cortex-A9 (prior
1322 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1323 completion of a following broadcasted operation if the second
1324 operation is received by a CPU before the ICIALLUIS has completed,
1325 potentially leading to corrupted entries in the cache or TLB.
1327 config PL310_ERRATA_753970
1328 bool "PL310 errata: cache sync operation may be faulty"
1329 depends on CACHE_PL310
1331 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1333 Under some condition the effect of cache sync operation on
1334 the store buffer still remains when the operation completes.
1335 This means that the store buffer is always asked to drain and
1336 this prevents it from merging any further writes. The workaround
1337 is to replace the normal offset of cache sync operation (0x730)
1338 by another offset targeting an unmapped PL310 register 0x740.
1339 This has the same effect as the cache sync operation: store buffer
1340 drain and waiting for all buffers empty.
1342 config ARM_ERRATA_754322
1343 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1346 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1347 r3p*) erratum. A speculative memory access may cause a page table walk
1348 which starts prior to an ASID switch but completes afterwards. This
1349 can populate the micro-TLB with a stale entry which may be hit with
1350 the new ASID. This workaround places two dsb instructions in the mm
1351 switching code so that no page table walks can cross the ASID switch.
1353 config ARM_ERRATA_754327
1354 bool "ARM errata: no automatic Store Buffer drain"
1355 depends on CPU_V7 && SMP
1357 This option enables the workaround for the 754327 Cortex-A9 (prior to
1358 r2p0) erratum. The Store Buffer does not have any automatic draining
1359 mechanism and therefore a livelock may occur if an external agent
1360 continuously polls a memory location waiting to observe an update.
1361 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1362 written polling loops from denying visibility of updates to memory.
1364 config ARM_ERRATA_364296
1365 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1366 depends on CPU_V6 && !SMP
1368 This options enables the workaround for the 364296 ARM1136
1369 r0p2 erratum (possible cache data corruption with
1370 hit-under-miss enabled). It sets the undocumented bit 31 in
1371 the auxiliary control register and the FI bit in the control
1372 register, thus disabling hit-under-miss without putting the
1373 processor into full low interrupt latency mode. ARM11MPCore
1376 config ARM_ERRATA_764369
1377 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1378 depends on CPU_V7 && SMP
1380 This option enables the workaround for erratum 764369
1381 affecting Cortex-A9 MPCore with two or more processors (all
1382 current revisions). Under certain timing circumstances, a data
1383 cache line maintenance operation by MVA targeting an Inner
1384 Shareable memory region may fail to proceed up to either the
1385 Point of Coherency or to the Point of Unification of the
1386 system. This workaround adds a DSB instruction before the
1387 relevant cache maintenance functions and sets a specific bit
1388 in the diagnostic control register of the SCU.
1390 config PL310_ERRATA_769419
1391 bool "PL310 errata: no automatic Store Buffer drain"
1392 depends on CACHE_L2X0
1394 On revisions of the PL310 prior to r3p2, the Store Buffer does
1395 not automatically drain. This can cause normal, non-cacheable
1396 writes to be retained when the memory system is idle, leading
1397 to suboptimal I/O performance for drivers using coherent DMA.
1398 This option adds a write barrier to the cpu_idle loop so that,
1399 on systems with an outer cache, the store buffer is drained
1404 source "arch/arm/common/Kconfig"
1414 Find out whether you have ISA slots on your motherboard. ISA is the
1415 name of a bus system, i.e. the way the CPU talks to the other stuff
1416 inside your box. Other bus systems are PCI, EISA, MicroChannel
1417 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1418 newer boards don't support it. If you have ISA, say Y, otherwise N.
1420 # Select ISA DMA controller support
1425 # Select ISA DMA interface
1430 bool "PCI support" if MIGHT_HAVE_PCI
1432 Find out whether you have a PCI motherboard. PCI is the name of a
1433 bus system, i.e. the way the CPU talks to the other stuff inside
1434 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1435 VESA. If you have PCI, say Y, otherwise N.
1441 config PCI_NANOENGINE
1442 bool "BSE nanoEngine PCI support"
1443 depends on SA1100_NANOENGINE
1445 Enable PCI on the BSE nanoEngine board.
1450 # Select the host bridge type
1451 config PCI_HOST_VIA82C505
1453 depends on PCI && ARCH_SHARK
1456 config PCI_HOST_ITE8152
1458 depends on PCI && MACH_ARMCORE
1462 source "drivers/pci/Kconfig"
1464 source "drivers/pcmcia/Kconfig"
1468 menu "Kernel Features"
1473 This option should be selected by machines which have an SMP-
1476 The only effect of this option is to make the SMP-related
1477 options available to the user for configuration.
1480 bool "Symmetric Multi-Processing"
1481 depends on CPU_V6K || CPU_V7
1482 depends on GENERIC_CLOCKEVENTS
1485 select USE_GENERIC_SMP_HELPERS
1486 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1488 This enables support for systems with more than one CPU. If you have
1489 a system with only one CPU, like most personal computers, say N. If
1490 you have a system with more than one CPU, say Y.
1492 If you say N here, the kernel will run on single and multiprocessor
1493 machines, but will use only one CPU of a multiprocessor machine. If
1494 you say Y here, the kernel will run on many, but not all, single
1495 processor machines. On a single processor machine, the kernel will
1496 run faster if you say N here.
1498 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1499 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1500 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1502 If you don't know what to do here, say N.
1505 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1506 depends on EXPERIMENTAL
1507 depends on SMP && !XIP_KERNEL
1510 SMP kernels contain instructions which fail on non-SMP processors.
1511 Enabling this option allows the kernel to modify itself to make
1512 these instructions safe. Disabling it allows about 1K of space
1515 If you don't know what to do here, say Y.
1517 config ARM_CPU_TOPOLOGY
1518 bool "Support cpu topology definition"
1519 depends on SMP && CPU_V7
1522 Support ARM cpu topology definition. The MPIDR register defines
1523 affinity between processors which is then used to describe the cpu
1524 topology of an ARM System.
1527 bool "Multi-core scheduler support"
1528 depends on ARM_CPU_TOPOLOGY
1530 Multi-core scheduler support improves the CPU scheduler's decision
1531 making when dealing with multi-core CPU chips at a cost of slightly
1532 increased overhead in some places. If unsure say N here.
1535 bool "SMT scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Improves the CPU scheduler's decision making when dealing with
1539 MultiThreading at a cost of slightly increased overhead in some
1540 places. If unsure say N here.
1545 This option enables support for the ARM system coherency unit
1547 config ARM_ARCH_TIMER
1548 bool "Architected timer support"
1551 This option enables support for the ARM architected timer
1557 This options enables support for the ARM timer and watchdog unit
1560 prompt "Memory split"
1563 Select the desired split between kernel and user memory.
1565 If you are not absolutely sure what you are doing, leave this
1569 bool "3G/1G user/kernel split"
1571 bool "2G/2G user/kernel split"
1573 bool "1G/3G user/kernel split"
1578 default 0x40000000 if VMSPLIT_1G
1579 default 0x80000000 if VMSPLIT_2G
1583 int "Maximum number of CPUs (2-32)"
1589 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1590 depends on SMP && HOTPLUG && EXPERIMENTAL
1592 Say Y here to experiment with turning CPUs off and on. CPUs
1593 can be controlled through /sys/devices/system/cpu.
1596 bool "Use local timer interrupts"
1599 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1601 Enable support for local timers on SMP platforms, rather then the
1602 legacy IPI broadcast method. Local timers allows the system
1603 accounting to be spread across the timer interval, preventing a
1604 "thundering herd" at every timer tick.
1608 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1609 default 355 if ARCH_U8500
1610 default 264 if MACH_H4700
1611 default 512 if SOC_OMAP5
1612 default 288 if ARCH_VT8500
1615 Maximum number of GPIOs in the system.
1617 If unsure, leave the default value.
1619 source kernel/Kconfig.preempt
1623 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1624 ARCH_S5PV210 || ARCH_EXYNOS4
1625 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1626 default AT91_TIMER_HZ if ARCH_AT91
1627 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1630 config THUMB2_KERNEL
1631 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1632 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1634 select ARM_ASM_UNIFIED
1637 By enabling this option, the kernel will be compiled in
1638 Thumb-2 mode. A compiler/assembler that understand the unified
1639 ARM-Thumb syntax is needed.
1643 config THUMB2_AVOID_R_ARM_THM_JUMP11
1644 bool "Work around buggy Thumb-2 short branch relocations in gas"
1645 depends on THUMB2_KERNEL && MODULES
1648 Various binutils versions can resolve Thumb-2 branches to
1649 locally-defined, preemptible global symbols as short-range "b.n"
1650 branch instructions.
1652 This is a problem, because there's no guarantee the final
1653 destination of the symbol, or any candidate locations for a
1654 trampoline, are within range of the branch. For this reason, the
1655 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1656 relocation in modules at all, and it makes little sense to add
1659 The symptom is that the kernel fails with an "unsupported
1660 relocation" error when loading some modules.
1662 Until fixed tools are available, passing
1663 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1664 code which hits this problem, at the cost of a bit of extra runtime
1665 stack usage in some cases.
1667 The problem is described in more detail at:
1668 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1670 Only Thumb-2 kernels are affected.
1672 Unless you are sure your tools don't have this problem, say Y.
1674 config ARM_ASM_UNIFIED
1678 bool "Use the ARM EABI to compile the kernel"
1680 This option allows for the kernel to be compiled using the latest
1681 ARM ABI (aka EABI). This is only useful if you are using a user
1682 space environment that is also compiled with EABI.
1684 Since there are major incompatibilities between the legacy ABI and
1685 EABI, especially with regard to structure member alignment, this
1686 option also changes the kernel syscall calling convention to
1687 disambiguate both ABIs and allow for backward compatibility support
1688 (selected with CONFIG_OABI_COMPAT).
1690 To use this you need GCC version 4.0.0 or later.
1693 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1694 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1697 This option preserves the old syscall interface along with the
1698 new (ARM EABI) one. It also provides a compatibility layer to
1699 intercept syscalls that have structure arguments which layout
1700 in memory differs between the legacy ABI and the new ARM EABI
1701 (only for non "thumb" binaries). This option adds a tiny
1702 overhead to all syscalls and produces a slightly larger kernel.
1703 If you know you'll be using only pure EABI user space then you
1704 can say N here. If this option is not selected and you attempt
1705 to execute a legacy ABI binary then the result will be
1706 UNPREDICTABLE (in fact it can be predicted that it won't work
1707 at all). If in doubt say Y.
1709 config ARCH_HAS_HOLES_MEMORYMODEL
1712 config ARCH_SPARSEMEM_ENABLE
1715 config ARCH_SPARSEMEM_DEFAULT
1716 def_bool ARCH_SPARSEMEM_ENABLE
1718 config ARCH_SELECT_MEMORY_MODEL
1719 def_bool ARCH_SPARSEMEM_ENABLE
1721 config HAVE_ARCH_PFN_VALID
1722 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1725 bool "High Memory Support"
1728 The address space of ARM processors is only 4 Gigabytes large
1729 and it has to accommodate user address space, kernel address
1730 space as well as some memory mapped IO. That means that, if you
1731 have a large amount of physical memory and/or IO, not all of the
1732 memory can be "permanently mapped" by the kernel. The physical
1733 memory that is not permanently mapped is called "high memory".
1735 Depending on the selected kernel/user memory split, minimum
1736 vmalloc space and actual amount of RAM, you may not need this
1737 option which should result in a slightly faster kernel.
1742 bool "Allocate 2nd-level pagetables from highmem"
1745 config HW_PERF_EVENTS
1746 bool "Enable hardware performance counter support for perf events"
1747 depends on PERF_EVENTS
1750 Enable hardware performance counter support for perf events. If
1751 disabled, perf events will use software events only.
1755 config FORCE_MAX_ZONEORDER
1756 int "Maximum zone order" if ARCH_SHMOBILE
1757 range 11 64 if ARCH_SHMOBILE
1758 default "9" if SA1111
1761 The kernel memory allocator divides physically contiguous memory
1762 blocks into "zones", where each zone is a power of two number of
1763 pages. This option selects the largest power of two that the kernel
1764 keeps in the memory allocator. If you need to allocate very large
1765 blocks of physically contiguous memory, then you may need to
1766 increase this value.
1768 This config option is actually maximum order plus one. For example,
1769 a value of 11 means that the largest free memory block is 2^10 pages.
1771 config ALIGNMENT_TRAP
1773 depends on CPU_CP15_MMU
1774 default y if !ARCH_EBSA110
1775 select HAVE_PROC_CPU if PROC_FS
1777 ARM processors cannot fetch/store information which is not
1778 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1779 address divisible by 4. On 32-bit ARM processors, these non-aligned
1780 fetch/store instructions will be emulated in software if you say
1781 here, which has a severe performance impact. This is necessary for
1782 correct operation of some network protocols. With an IP-only
1783 configuration it is safe to say N, otherwise say Y.
1785 config UACCESS_WITH_MEMCPY
1786 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1787 depends on MMU && EXPERIMENTAL
1788 default y if CPU_FEROCEON
1790 Implement faster copy_to_user and clear_user methods for CPU
1791 cores where a 8-word STM instruction give significantly higher
1792 memory write throughput than a sequence of individual 32bit stores.
1794 A possible side effect is a slight increase in scheduling latency
1795 between threads sharing the same address space if they invoke
1796 such copy operations with large buffers.
1798 However, if the CPU data cache is using a write-allocate mode,
1799 this option is unlikely to provide any performance gain.
1803 prompt "Enable seccomp to safely compute untrusted bytecode"
1805 This kernel feature is useful for number crunching applications
1806 that may need to compute untrusted bytecode during their
1807 execution. By using pipes or other transports made available to
1808 the process as file descriptors supporting the read/write
1809 syscalls, it's possible to isolate those applications in
1810 their own address space using seccomp. Once seccomp is
1811 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1812 and the task is only allowed to execute a few safe syscalls
1813 defined by each seccomp mode.
1815 config CC_STACKPROTECTOR
1816 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1817 depends on EXPERIMENTAL
1819 This option turns on the -fstack-protector GCC feature. This
1820 feature puts, at the beginning of functions, a canary value on
1821 the stack just before the return address, and validates
1822 the value just before actually returning. Stack based buffer
1823 overflows (that need to overwrite this return address) now also
1824 overwrite the canary, which gets detected and the attack is then
1825 neutralized via a kernel panic.
1826 This feature requires gcc version 4.2 or above.
1828 config DEPRECATED_PARAM_STRUCT
1829 bool "Provide old way to pass kernel parameters"
1831 This was deprecated in 2001 and announced to live on for 5 years.
1832 Some old boot loaders still use this way.
1839 bool "Flattened Device Tree support"
1841 select OF_EARLY_FLATTREE
1844 Include support for flattened device tree machine descriptions.
1846 # Compressed boot loader in ROM. Yes, we really want to ask about
1847 # TEXT and BSS so we preserve their values in the config files.
1848 config ZBOOT_ROM_TEXT
1849 hex "Compressed ROM boot loader base address"
1852 The physical address at which the ROM-able zImage is to be
1853 placed in the target. Platforms which normally make use of
1854 ROM-able zImage formats normally set this to a suitable
1855 value in their defconfig file.
1857 If ZBOOT_ROM is not enabled, this has no effect.
1859 config ZBOOT_ROM_BSS
1860 hex "Compressed ROM boot loader BSS address"
1863 The base address of an area of read/write memory in the target
1864 for the ROM-able zImage which must be available while the
1865 decompressor is running. It must be large enough to hold the
1866 entire decompressed kernel plus an additional 128 KiB.
1867 Platforms which normally make use of ROM-able zImage formats
1868 normally set this to a suitable value in their defconfig file.
1870 If ZBOOT_ROM is not enabled, this has no effect.
1873 bool "Compressed boot loader in ROM/flash"
1874 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1876 Say Y here if you intend to execute your compressed kernel image
1877 (zImage) directly from ROM or flash. If unsure, say N.
1880 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1881 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1882 default ZBOOT_ROM_NONE
1884 Include experimental SD/MMC loading code in the ROM-able zImage.
1885 With this enabled it is possible to write the ROM-able zImage
1886 kernel image to an MMC or SD card and boot the kernel straight
1887 from the reset vector. At reset the processor Mask ROM will load
1888 the first part of the ROM-able zImage which in turn loads the
1889 rest the kernel image to RAM.
1891 config ZBOOT_ROM_NONE
1892 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1894 Do not load image from SD or MMC
1896 config ZBOOT_ROM_MMCIF
1897 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1899 Load image from MMCIF hardware block.
1901 config ZBOOT_ROM_SH_MOBILE_SDHI
1902 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1904 Load image from SDHI hardware block
1908 config ARM_APPENDED_DTB
1909 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1910 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1912 With this option, the boot code will look for a device tree binary
1913 (DTB) appended to zImage
1914 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1916 This is meant as a backward compatibility convenience for those
1917 systems with a bootloader that can't be upgraded to accommodate
1918 the documented boot protocol using a device tree.
1920 Beware that there is very little in terms of protection against
1921 this option being confused by leftover garbage in memory that might
1922 look like a DTB header after a reboot if no actual DTB is appended
1923 to zImage. Do not leave this option active in a production kernel
1924 if you don't intend to always append a DTB. Proper passing of the
1925 location into r2 of a bootloader provided DTB is always preferable
1928 config ARM_ATAG_DTB_COMPAT
1929 bool "Supplement the appended DTB with traditional ATAG information"
1930 depends on ARM_APPENDED_DTB
1932 Some old bootloaders can't be updated to a DTB capable one, yet
1933 they provide ATAGs with memory configuration, the ramdisk address,
1934 the kernel cmdline string, etc. Such information is dynamically
1935 provided by the bootloader and can't always be stored in a static
1936 DTB. To allow a device tree enabled kernel to be used with such
1937 bootloaders, this option allows zImage to extract the information
1938 from the ATAG list and store it at run time into the appended DTB.
1941 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1942 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1945 bool "Use bootloader kernel arguments if available"
1947 Uses the command-line options passed by the boot loader instead of
1948 the device tree bootargs property. If the boot loader doesn't provide
1949 any, the device tree bootargs property will be used.
1951 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1952 bool "Extend with bootloader kernel arguments"
1954 The command-line arguments provided by the boot loader will be
1955 appended to the the device tree bootargs property.
1960 string "Default kernel command string"
1963 On some architectures (EBSA110 and CATS), there is currently no way
1964 for the boot loader to pass arguments to the kernel. For these
1965 architectures, you should supply some command-line options at build
1966 time by entering them here. As a minimum, you should specify the
1967 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1970 prompt "Kernel command line type" if CMDLINE != ""
1971 default CMDLINE_FROM_BOOTLOADER
1973 config CMDLINE_FROM_BOOTLOADER
1974 bool "Use bootloader kernel arguments if available"
1976 Uses the command-line options passed by the boot loader. If
1977 the boot loader doesn't provide any, the default kernel command
1978 string provided in CMDLINE will be used.
1980 config CMDLINE_EXTEND
1981 bool "Extend bootloader kernel arguments"
1983 The command-line arguments provided by the boot loader will be
1984 appended to the default kernel command string.
1986 config CMDLINE_FORCE
1987 bool "Always use the default kernel command string"
1989 Always use the default kernel command string, even if the boot
1990 loader passes other arguments to the kernel.
1991 This is useful if you cannot or don't want to change the
1992 command-line options your boot loader passes to the kernel.
1996 bool "Kernel Execute-In-Place from ROM"
1997 depends on !ZBOOT_ROM && !ARM_LPAE
1999 Execute-In-Place allows the kernel to run from non-volatile storage
2000 directly addressable by the CPU, such as NOR flash. This saves RAM
2001 space since the text section of the kernel is not loaded from flash
2002 to RAM. Read-write sections, such as the data section and stack,
2003 are still copied to RAM. The XIP kernel is not compressed since
2004 it has to run directly from flash, so it will take more space to
2005 store it. The flash address used to link the kernel object files,
2006 and for storing it, is configuration dependent. Therefore, if you
2007 say Y here, you must know the proper physical address where to
2008 store the kernel image depending on your own flash memory usage.
2010 Also note that the make target becomes "make xipImage" rather than
2011 "make zImage" or "make Image". The final kernel binary to put in
2012 ROM memory will be arch/arm/boot/xipImage.
2016 config XIP_PHYS_ADDR
2017 hex "XIP Kernel Physical Location"
2018 depends on XIP_KERNEL
2019 default "0x00080000"
2021 This is the physical address in your flash memory the kernel will
2022 be linked for and stored to. This address is dependent on your
2026 bool "Kexec system call (EXPERIMENTAL)"
2027 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2029 kexec is a system call that implements the ability to shutdown your
2030 current kernel, and to start another kernel. It is like a reboot
2031 but it is independent of the system firmware. And like a reboot
2032 you can start any kernel with it, not just Linux.
2034 It is an ongoing process to be certain the hardware in a machine
2035 is properly shutdown, so do not be surprised if this code does not
2036 initially work for you. It may help to enable device hotplugging
2040 bool "Export atags in procfs"
2044 Should the atags used to boot the kernel be exported in an "atags"
2045 file in procfs. Useful with kexec.
2048 bool "Build kdump crash kernel (EXPERIMENTAL)"
2049 depends on EXPERIMENTAL
2051 Generate crash dump after being started by kexec. This should
2052 be normally only set in special crash dump kernels which are
2053 loaded in the main kernel with kexec-tools into a specially
2054 reserved region and then later executed after a crash by
2055 kdump/kexec. The crash dump kernel must be compiled to a
2056 memory address not used by the main kernel
2058 For more details see Documentation/kdump/kdump.txt
2060 config AUTO_ZRELADDR
2061 bool "Auto calculation of the decompressed kernel image address"
2062 depends on !ZBOOT_ROM && !ARCH_U300
2064 ZRELADDR is the physical address where the decompressed kernel
2065 image will be placed. If AUTO_ZRELADDR is selected, the address
2066 will be determined at run-time by masking the current IP with
2067 0xf8000000. This assumes the zImage being placed in the first 128MB
2068 from start of memory.
2072 menu "CPU Power Management"
2076 source "drivers/cpufreq/Kconfig"
2079 tristate "CPUfreq driver for i.MX CPUs"
2080 depends on ARCH_MXC && CPU_FREQ
2081 select CPU_FREQ_TABLE
2083 This enables the CPUfreq driver for i.MX CPUs.
2085 config CPU_FREQ_SA1100
2088 config CPU_FREQ_SA1110
2091 config CPU_FREQ_INTEGRATOR
2092 tristate "CPUfreq driver for ARM Integrator CPUs"
2093 depends on ARCH_INTEGRATOR && CPU_FREQ
2096 This enables the CPUfreq driver for ARM Integrator CPUs.
2098 For details, take a look at <file:Documentation/cpu-freq>.
2104 depends on CPU_FREQ && ARCH_PXA && PXA25x
2106 select CPU_FREQ_TABLE
2107 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2112 Internal configuration node for common cpufreq on Samsung SoC
2114 config CPU_FREQ_S3C24XX
2115 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2116 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2119 This enables the CPUfreq driver for the Samsung S3C24XX family
2122 For details, take a look at <file:Documentation/cpu-freq>.
2126 config CPU_FREQ_S3C24XX_PLL
2127 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2128 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2130 Compile in support for changing the PLL frequency from the
2131 S3C24XX series CPUfreq driver. The PLL takes time to settle
2132 after a frequency change, so by default it is not enabled.
2134 This also means that the PLL tables for the selected CPU(s) will
2135 be built which may increase the size of the kernel image.
2137 config CPU_FREQ_S3C24XX_DEBUG
2138 bool "Debug CPUfreq Samsung driver core"
2139 depends on CPU_FREQ_S3C24XX
2141 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2143 config CPU_FREQ_S3C24XX_IODEBUG
2144 bool "Debug CPUfreq Samsung driver IO timing"
2145 depends on CPU_FREQ_S3C24XX
2147 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2149 config CPU_FREQ_S3C24XX_DEBUGFS
2150 bool "Export debugfs for CPUFreq"
2151 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2153 Export status information via debugfs.
2157 source "drivers/cpuidle/Kconfig"
2161 menu "Floating point emulation"
2163 comment "At least one emulation must be selected"
2166 bool "NWFPE math emulation"
2167 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2169 Say Y to include the NWFPE floating point emulator in the kernel.
2170 This is necessary to run most binaries. Linux does not currently
2171 support floating point hardware so you need to say Y here even if
2172 your machine has an FPA or floating point co-processor podule.
2174 You may say N here if you are going to load the Acorn FPEmulator
2175 early in the bootup.
2178 bool "Support extended precision"
2179 depends on FPE_NWFPE
2181 Say Y to include 80-bit support in the kernel floating-point
2182 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2183 Note that gcc does not generate 80-bit operations by default,
2184 so in most cases this option only enlarges the size of the
2185 floating point emulator without any good reason.
2187 You almost surely want to say N here.
2190 bool "FastFPE math emulation (EXPERIMENTAL)"
2191 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2193 Say Y here to include the FAST floating point emulator in the kernel.
2194 This is an experimental much faster emulator which now also has full
2195 precision for the mantissa. It does not support any exceptions.
2196 It is very simple, and approximately 3-6 times faster than NWFPE.
2198 It should be sufficient for most programs. It may be not suitable
2199 for scientific calculations, but you have to check this for yourself.
2200 If you do not feel you need a faster FP emulation you should better
2204 bool "VFP-format floating point maths"
2205 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2207 Say Y to include VFP support code in the kernel. This is needed
2208 if your hardware includes a VFP unit.
2210 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2211 release notes and additional status information.
2213 Say N if your target does not have VFP hardware.
2221 bool "Advanced SIMD (NEON) Extension support"
2222 depends on VFPv3 && CPU_V7
2224 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2229 menu "Userspace binary formats"
2231 source "fs/Kconfig.binfmt"
2234 tristate "RISC OS personality"
2237 Say Y here to include the kernel code necessary if you want to run
2238 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2239 experimental; if this sounds frightening, say N and sleep in peace.
2240 You can also say M here to compile this support as a module (which
2241 will be called arthur).
2245 menu "Power management options"
2247 source "kernel/power/Kconfig"
2249 config ARCH_SUSPEND_POSSIBLE
2250 depends on !ARCH_S5PC100
2251 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2252 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2255 config ARM_CPU_SUSPEND
2260 source "net/Kconfig"
2262 source "drivers/Kconfig"
2266 source "arch/arm/Kconfig.debug"
2268 source "security/Kconfig"
2270 source "crypto/Kconfig"
2272 source "lib/Kconfig"