arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_IRQ_SHOW_LEVEL
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARCH_REALVIEW
 333         bool "ARM Ltd. RealView family"
 334         select ARCH_WANT_OPTIONAL_GPIOLIB
 335         select ARM_AMBA
 336         select ARM_TIMER_SP804
 337         select COMMON_CLK
 338         select COMMON_CLK_VERSATILE
 339         select GENERIC_CLOCKEVENTS
 340         select GPIO_PL061 if GPIOLIB
 341         select ICST
 342         select NEED_MACH_MEMORY_H
 343         select PLAT_VERSATILE
 344         select PLAT_VERSATILE_SCHED_CLOCK
 345         help
 346           This enables support for ARM Ltd RealView boards.
 347
 348 config ARCH_VERSATILE
 349         bool "ARM Ltd. Versatile family"
 350         select ARCH_WANT_OPTIONAL_GPIOLIB
 351         select ARM_AMBA
 352         select ARM_TIMER_SP804
 353         select ARM_VIC
 354         select CLKDEV_LOOKUP
 355         select GENERIC_CLOCKEVENTS
 356         select HAVE_MACH_CLKDEV
 357         select ICST
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_CLOCK
 360         select PLAT_VERSATILE_SCHED_CLOCK
 361         select VERSATILE_FPGA_IRQ
 362         help
 363           This enables support for ARM Ltd Versatile board.
 364
 365 config ARCH_CLPS711X
 366         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 367         select ARCH_REQUIRE_GPIOLIB
 368         select AUTO_ZRELADDR
 369         select CLKSRC_MMIO
 370         select COMMON_CLK
 371         select CPU_ARM720T
 372         select GENERIC_CLOCKEVENTS
 373         select MFD_SYSCON
 374         select SOC_BUS
 375         help
 376           Support for Cirrus Logic 711x/721x/731x based boards.
 377
 378 config ARCH_GEMINI
 379         bool "Cortina Systems Gemini"
 380         select ARCH_REQUIRE_GPIOLIB
 381         select CLKSRC_MMIO
 382         select CPU_FA526
 383         select GENERIC_CLOCKEVENTS
 384         help
 385           Support for the Cortina Systems Gemini family SoCs
 386
 387 config ARCH_EBSA110
 388         bool "EBSA-110"
 389         select ARCH_USES_GETTIMEOFFSET
 390         select CPU_SA110
 391         select ISA
 392         select NEED_MACH_IO_H
 393         select NEED_MACH_MEMORY_H
 394         select NO_IOPORT_MAP
 395         help
 396           This is an evaluation board for the StrongARM processor available
 397           from Digital. It has limited hardware on-board, including an
 398           Ethernet interface, two PCMCIA sockets, two serial ports and a
 399           parallel port.
 400
 401 config ARCH_EFM32
 402         bool "Energy Micro efm32"
 403         depends on !MMU
 404         select ARCH_REQUIRE_GPIOLIB
 405         select ARM_NVIC
 406         select AUTO_ZRELADDR
 407         select CLKSRC_OF
 408         select COMMON_CLK
 409         select CPU_V7M
 410         select GENERIC_CLOCKEVENTS
 411         select NO_DMA
 412         select NO_IOPORT_MAP
 413         select SPARSE_IRQ
 414         select USE_OF
 415         help
 416           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 417           processors.
 418
 419 config ARCH_EP93XX
 420         bool "EP93xx-based"
 421         select ARCH_HAS_HOLES_MEMORYMODEL
 422         select ARCH_REQUIRE_GPIOLIB
 423         select ARCH_USES_GETTIMEOFFSET
 424         select ARM_AMBA
 425         select ARM_VIC
 426         select CLKDEV_LOOKUP
 427         select CPU_ARM920T
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         help
 542           Support for the following Marvell Orion 5x series SoCs:
 543           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 544           Orion-2 (5281), Orion-1-90 (6183).
 545
 546 config ARCH_MMP
 547         bool "Marvell PXA168/910/MMP2"
 548         depends on MMU
 549         select ARCH_REQUIRE_GPIOLIB
 550         select CLKDEV_LOOKUP
 551         select GENERIC_ALLOCATOR
 552         select GENERIC_CLOCKEVENTS
 553         select GPIO_PXA
 554         select IRQ_DOMAIN
 555         select MULTI_IRQ_HANDLER
 556         select PINCTRL
 557         select PLAT_PXA
 558         select SPARSE_IRQ
 559         help
 560           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 561
 562 config ARCH_KS8695
 563         bool "Micrel/Kendin KS8695"
 564         select ARCH_REQUIRE_GPIOLIB
 565         select CLKSRC_MMIO
 566         select CPU_ARM922T
 567         select GENERIC_CLOCKEVENTS
 568         select NEED_MACH_MEMORY_H
 569         help
 570           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 571           System-on-Chip devices.
 572
 573 config ARCH_W90X900
 574         bool "Nuvoton W90X900 CPU"
 575         select ARCH_REQUIRE_GPIOLIB
 576         select CLKDEV_LOOKUP
 577         select CLKSRC_MMIO
 578         select CPU_ARM926T
 579         select GENERIC_CLOCKEVENTS
 580         help
 581           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 582           At present, the w90x900 has been renamed nuc900, regarding
 583           the ARM series product line, you can login the following
 584           link address to know more.
 585
 586           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 587                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 588
 589 config ARCH_LPC32XX
 590         bool "NXP LPC32XX"
 591         select ARCH_REQUIRE_GPIOLIB
 592         select ARM_AMBA
 593         select CLKDEV_LOOKUP
 594         select CLKSRC_MMIO
 595         select CPU_ARM926T
 596         select GENERIC_CLOCKEVENTS
 597         select HAVE_IDE
 598         select USE_OF
 599         help
 600           Support for the NXP LPC32XX family of processors
 601
 602 config ARCH_PXA
 603         bool "PXA2xx/PXA3xx-based"
 604         depends on MMU
 605         select ARCH_MTD_XIP
 606         select ARCH_REQUIRE_GPIOLIB
 607         select ARM_CPU_SUSPEND if PM
 608         select AUTO_ZRELADDR
 609         select COMMON_CLK
 610         select CLKDEV_LOOKUP
 611         select CLKSRC_MMIO
 612         select CLKSRC_OF
 613         select GENERIC_CLOCKEVENTS
 614         select GPIO_PXA
 615         select HAVE_IDE
 616         select IRQ_DOMAIN
 617         select MULTI_IRQ_HANDLER
 618         select PLAT_PXA
 619         select SPARSE_IRQ
 620         help
 621           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 622
 623 config ARCH_SHMOBILE_LEGACY
 624         bool "Renesas ARM SoCs (non-multiplatform)"
 625         select ARCH_SHMOBILE
 626         select ARM_PATCH_PHYS_VIRT if MMU
 627         select CLKDEV_LOOKUP
 628         select CPU_V7
 629         select GENERIC_CLOCKEVENTS
 630         select HAVE_ARM_SCU if SMP
 631         select HAVE_ARM_TWD if SMP
 632         select HAVE_SMP
 633         select MIGHT_HAVE_CACHE_L2X0
 634         select MULTI_IRQ_HANDLER
 635         select NO_IOPORT_MAP
 636         select PINCTRL
 637         select PM_GENERIC_DOMAINS if PM
 638         select SH_CLK_CPG
 639         select SPARSE_IRQ
 640         help
 641           Support for Renesas ARM SoC platforms using a non-multiplatform
 642           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 643           and RZ families.
 644
 645 config ARCH_RPC
 646         bool "RiscPC"
 647         select ARCH_ACORN
 648         select ARCH_MAY_HAVE_PC_FDC
 649         select ARCH_SPARSEMEM_ENABLE
 650         select ARCH_USES_GETTIMEOFFSET
 651         select CPU_SA110
 652         select FIQ
 653         select HAVE_IDE
 654         select HAVE_PATA_PLATFORM
 655         select ISA_DMA_API
 656         select NEED_MACH_IO_H
 657         select NEED_MACH_MEMORY_H
 658         select NO_IOPORT_MAP
 659         select VIRT_TO_BUS
 660         help
 661           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 662           CD-ROM interface, serial and parallel port, and the floppy drive.
 663
 664 config ARCH_SA1100
 665         bool "SA1100-based"
 666         select ARCH_MTD_XIP
 667         select ARCH_REQUIRE_GPIOLIB
 668         select ARCH_SPARSEMEM_ENABLE
 669         select CLKDEV_LOOKUP
 670         select CLKSRC_MMIO
 671         select CPU_FREQ
 672         select CPU_SA1100
 673         select GENERIC_CLOCKEVENTS
 674         select HAVE_IDE
 675         select IRQ_DOMAIN
 676         select ISA
 677         select MULTI_IRQ_HANDLER
 678         select NEED_MACH_MEMORY_H
 679         select SPARSE_IRQ
 680         help
 681           Support for StrongARM 11x0 based boards.
 682
 683 config ARCH_S3C24XX
 684         bool "Samsung S3C24XX SoCs"
 685         select ARCH_REQUIRE_GPIOLIB
 686         select ATAGS
 687         select CLKDEV_LOOKUP
 688         select CLKSRC_SAMSUNG_PWM
 689         select GENERIC_CLOCKEVENTS
 690         select GPIO_SAMSUNG
 691         select HAVE_S3C2410_I2C if I2C
 692         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 693         select HAVE_S3C_RTC if RTC_CLASS
 694         select MULTI_IRQ_HANDLER
 695         select NEED_MACH_IO_H
 696         select SAMSUNG_ATAGS
 697         help
 698           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 699           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 700           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 701           Samsung SMDK2410 development board (and derivatives).
 702
 703 config ARCH_S3C64XX
 704         bool "Samsung S3C64XX"
 705         select ARCH_REQUIRE_GPIOLIB
 706         select ARM_AMBA
 707         select ARM_VIC
 708         select ATAGS
 709         select CLKDEV_LOOKUP
 710         select CLKSRC_SAMSUNG_PWM
 711         select COMMON_CLK_SAMSUNG
 712         select CPU_V6K
 713         select GENERIC_CLOCKEVENTS
 714         select GPIO_SAMSUNG
 715         select HAVE_S3C2410_I2C if I2C
 716         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 717         select HAVE_TCM
 718         select NO_IOPORT_MAP
 719         select PLAT_SAMSUNG
 720         select PM_GENERIC_DOMAINS if PM
 721         select S3C_DEV_NAND
 722         select S3C_GPIO_TRACK
 723         select SAMSUNG_ATAGS
 724         select SAMSUNG_WAKEMASK
 725         select SAMSUNG_WDT_RESET
 726         help
 727           Samsung S3C64XX series based systems
 728
 729 config ARCH_DAVINCI
 730         bool "TI DaVinci"
 731         select ARCH_HAS_HOLES_MEMORYMODEL
 732         select ARCH_REQUIRE_GPIOLIB
 733         select CLKDEV_LOOKUP
 734         select GENERIC_ALLOCATOR
 735         select GENERIC_CLOCKEVENTS
 736         select GENERIC_IRQ_CHIP
 737         select HAVE_IDE
 738         select TI_PRIV_EDMA
 739         select USE_OF
 740         select ZONE_DMA
 741         help
 742           Support for TI's DaVinci platform.
 743
 744 config ARCH_OMAP1
 745         bool "TI OMAP1"
 746         depends on MMU
 747         select ARCH_HAS_HOLES_MEMORYMODEL
 748         select ARCH_OMAP
 749         select ARCH_REQUIRE_GPIOLIB
 750         select CLKDEV_LOOKUP
 751         select CLKSRC_MMIO
 752         select GENERIC_CLOCKEVENTS
 753         select GENERIC_IRQ_CHIP
 754         select HAVE_IDE
 755         select IRQ_DOMAIN
 756         select NEED_MACH_IO_H if PCCARD
 757         select NEED_MACH_MEMORY_H
 758         help
 759           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 760
 761 endchoice
 762
 763 menu "Multiple platform selection"
 764         depends on ARCH_MULTIPLATFORM
 765
 766 comment "CPU Core family selection"
 767
 768 config ARCH_MULTI_V4
 769         bool "ARMv4 based platforms (FA526)"
 770         depends on !ARCH_MULTI_V6_V7
 771         select ARCH_MULTI_V4_V5
 772         select CPU_FA526
 773
 774 config ARCH_MULTI_V4T
 775         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 776         depends on !ARCH_MULTI_V6_V7
 777         select ARCH_MULTI_V4_V5
 778         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 779                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 780                 CPU_ARM925T || CPU_ARM940T)
 781
 782 config ARCH_MULTI_V5
 783         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 784         depends on !ARCH_MULTI_V6_V7
 785         select ARCH_MULTI_V4_V5
 786         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 787                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 788                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 789
 790 config ARCH_MULTI_V4_V5
 791         bool
 792
 793 config ARCH_MULTI_V6
 794         bool "ARMv6 based platforms (ARM11)"
 795         select ARCH_MULTI_V6_V7
 796         select CPU_V6K
 797
 798 config ARCH_MULTI_V7
 799         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 800         default y
 801         select ARCH_MULTI_V6_V7
 802         select CPU_V7
 803         select HAVE_SMP
 804
 805 config ARCH_MULTI_V6_V7
 806         bool
 807         select MIGHT_HAVE_CACHE_L2X0
 808
 809 config ARCH_MULTI_CPU_AUTO
 810         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 811         select ARCH_MULTI_V5
 812
 813 endmenu
 814
 815 config ARCH_VIRT
 816         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 817         select ARM_AMBA
 818         select ARM_GIC
 819         select ARM_PSCI
 820         select HAVE_ARM_ARCH_TIMER
 821
 822 #
 823 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 824 # Kconfigs may be included either alphabetically (according to the
 825 # plat- suffix) or along side the corresponding mach-* source.
 826 #
 827 source "arch/arm/mach-mvebu/Kconfig"
 828
 829 source "arch/arm/mach-alpine/Kconfig"
 830
 831 source "arch/arm/mach-asm9260/Kconfig"
 832
 833 source "arch/arm/mach-at91/Kconfig"
 834
 835 source "arch/arm/mach-axxia/Kconfig"
 836
 837 source "arch/arm/mach-bcm/Kconfig"
 838
 839 source "arch/arm/mach-berlin/Kconfig"
 840
 841 source "arch/arm/mach-clps711x/Kconfig"
 842
 843 source "arch/arm/mach-cns3xxx/Kconfig"
 844
 845 source "arch/arm/mach-davinci/Kconfig"
 846
 847 source "arch/arm/mach-digicolor/Kconfig"
 848
 849 source "arch/arm/mach-dove/Kconfig"
 850
 851 source "arch/arm/mach-ep93xx/Kconfig"
 852
 853 source "arch/arm/mach-footbridge/Kconfig"
 854
 855 source "arch/arm/mach-gemini/Kconfig"
 856
 857 source "arch/arm/mach-highbank/Kconfig"
 858
 859 source "arch/arm/mach-hisi/Kconfig"
 860
 861 source "arch/arm/mach-integrator/Kconfig"
 862
 863 source "arch/arm/mach-iop32x/Kconfig"
 864
 865 source "arch/arm/mach-iop33x/Kconfig"
 866
 867 source "arch/arm/mach-iop13xx/Kconfig"
 868
 869 source "arch/arm/mach-ixp4xx/Kconfig"
 870
 871 source "arch/arm/mach-keystone/Kconfig"
 872
 873 source "arch/arm/mach-ks8695/Kconfig"
 874
 875 source "arch/arm/mach-meson/Kconfig"
 876
 877 source "arch/arm/mach-moxart/Kconfig"
 878
 879 source "arch/arm/mach-mv78xx0/Kconfig"
 880
 881 source "arch/arm/mach-imx/Kconfig"
 882
 883 source "arch/arm/mach-mediatek/Kconfig"
 884
 885 source "arch/arm/mach-mxs/Kconfig"
 886
 887 source "arch/arm/mach-netx/Kconfig"
 888
 889 source "arch/arm/mach-nomadik/Kconfig"
 890
 891 source "arch/arm/mach-nspire/Kconfig"
 892
 893 source "arch/arm/plat-omap/Kconfig"
 894
 895 source "arch/arm/mach-omap1/Kconfig"
 896
 897 source "arch/arm/mach-omap2/Kconfig"
 898
 899 source "arch/arm/mach-orion5x/Kconfig"
 900
 901 source "arch/arm/mach-picoxcell/Kconfig"
 902
 903 source "arch/arm/mach-pxa/Kconfig"
 904 source "arch/arm/plat-pxa/Kconfig"
 905
 906 source "arch/arm/mach-mmp/Kconfig"
 907
 908 source "arch/arm/mach-qcom/Kconfig"
 909
 910 source "arch/arm/mach-realview/Kconfig"
 911
 912 source "arch/arm/mach-rockchip/Kconfig"
 913
 914 source "arch/arm/mach-sa1100/Kconfig"
 915
 916 source "arch/arm/mach-socfpga/Kconfig"
 917
 918 source "arch/arm/mach-spear/Kconfig"
 919
 920 source "arch/arm/mach-sti/Kconfig"
 921
 922 source "arch/arm/mach-s3c24xx/Kconfig"
 923
 924 source "arch/arm/mach-s3c64xx/Kconfig"
 925
 926 source "arch/arm/mach-s5pv210/Kconfig"
 927
 928 source "arch/arm/mach-exynos/Kconfig"
 929 source "arch/arm/plat-samsung/Kconfig"
 930
 931 source "arch/arm/mach-shmobile/Kconfig"
 932
 933 source "arch/arm/mach-sunxi/Kconfig"
 934
 935 source "arch/arm/mach-prima2/Kconfig"
 936
 937 source "arch/arm/mach-tegra/Kconfig"
 938
 939 source "arch/arm/mach-u300/Kconfig"
 940
 941 source "arch/arm/mach-ux500/Kconfig"
 942
 943 source "arch/arm/mach-versatile/Kconfig"
 944
 945 source "arch/arm/mach-vexpress/Kconfig"
 946 source "arch/arm/plat-versatile/Kconfig"
 947
 948 source "arch/arm/mach-vt8500/Kconfig"
 949
 950 source "arch/arm/mach-w90x900/Kconfig"
 951
 952 source "arch/arm/mach-zynq/Kconfig"
 953
 954 # Definitions to make life easier
 955 config ARCH_ACORN
 956         bool
 957
 958 config PLAT_IOP
 959         bool
 960         select GENERIC_CLOCKEVENTS
 961
 962 config PLAT_ORION
 963         bool
 964         select CLKSRC_MMIO
 965         select COMMON_CLK
 966         select GENERIC_IRQ_CHIP
 967         select IRQ_DOMAIN
 968
 969 config PLAT_ORION_LEGACY
 970         bool
 971         select PLAT_ORION
 972
 973 config PLAT_PXA
 974         bool
 975
 976 config PLAT_VERSATILE
 977         bool
 978
 979 config ARM_TIMER_SP804
 980         bool
 981         select CLKSRC_MMIO
 982         select CLKSRC_OF if OF
 983
 984 source "arch/arm/firmware/Kconfig"
 985
 986 source arch/arm/mm/Kconfig
 987
 988 config IWMMXT
 989         bool "Enable iWMMXt support"
 990         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 991         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 992         help
 993           Enable support for iWMMXt context switching at run time if
 994           running on a CPU that supports it.
 995
 996 config MULTI_IRQ_HANDLER
 997         bool
 998         help
 999           Allow each machine to specify it's own IRQ handler at run time.
1000
1001 if !MMU
1002 source "arch/arm/Kconfig-nommu"
1003 endif
1004
1005 config PJ4B_ERRATA_4742
1006         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1007         depends on CPU_PJ4B && MACH_ARMADA_370
1008         default y
1009         help
1010           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1011           Event (WFE) IDLE states, a specific timing sensitivity exists between
1012           the retiring WFI/WFE instructions and the newly issued subsequent
1013           instructions.  This sensitivity can result in a CPU hang scenario.
1014           Workaround:
1015           The software must insert either a Data Synchronization Barrier (DSB)
1016           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1017           instruction
1018
1019 config ARM_ERRATA_326103
1020         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1021         depends on CPU_V6
1022         help
1023           Executing a SWP instruction to read-only memory does not set bit 11
1024           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1025           treat the access as a read, preventing a COW from occurring and
1026           causing the faulting task to livelock.
1027
1028 config ARM_ERRATA_411920
1029         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1030         depends on CPU_V6 || CPU_V6K
1031         help
1032           Invalidation of the Instruction Cache operation can
1033           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1034           It does not affect the MPCore. This option enables the ARM Ltd.
1035           recommended workaround.
1036
1037 config ARM_ERRATA_430973
1038         bool "ARM errata: Stale prediction on replaced interworking branch"
1039         depends on CPU_V7
1040         help
1041           This option enables the workaround for the 430973 Cortex-A8
1042           r1p* erratum. If a code sequence containing an ARM/Thumb
1043           interworking branch is replaced with another code sequence at the
1044           same virtual address, whether due to self-modifying code or virtual
1045           to physical address re-mapping, Cortex-A8 does not recover from the
1046           stale interworking branch prediction. This results in Cortex-A8
1047           executing the new code sequence in the incorrect ARM or Thumb state.
1048           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1049           and also flushes the branch target cache at every context switch.
1050           Note that setting specific bits in the ACTLR register may not be
1051           available in non-secure mode.
1052
1053 config ARM_ERRATA_458693
1054         bool "ARM errata: Processor deadlock when a false hazard is created"
1055         depends on CPU_V7
1056         depends on !ARCH_MULTIPLATFORM
1057         help
1058           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1059           erratum. For very specific sequences of memory operations, it is
1060           possible for a hazard condition intended for a cache line to instead
1061           be incorrectly associated with a different cache line. This false
1062           hazard might then cause a processor deadlock. The workaround enables
1063           the L1 caching of the NEON accesses and disables the PLD instruction
1064           in the ACTLR register. Note that setting specific bits in the ACTLR
1065           register may not be available in non-secure mode.
1066
1067 config ARM_ERRATA_460075
1068         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1069         depends on CPU_V7
1070         depends on !ARCH_MULTIPLATFORM
1071         help
1072           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1073           erratum. Any asynchronous access to the L2 cache may encounter a
1074           situation in which recent store transactions to the L2 cache are lost
1075           and overwritten with stale memory contents from external memory. The
1076           workaround disables the write-allocate mode for the L2 cache via the
1077           ACTLR register. Note that setting specific bits in the ACTLR register
1078           may not be available in non-secure mode.
1079
1080 config ARM_ERRATA_742230
1081         bool "ARM errata: DMB operation may be faulty"
1082         depends on CPU_V7 && SMP
1083         depends on !ARCH_MULTIPLATFORM
1084         help
1085           This option enables the workaround for the 742230 Cortex-A9
1086           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1087           between two write operations may not ensure the correct visibility
1088           ordering of the two writes. This workaround sets a specific bit in
1089           the diagnostic register of the Cortex-A9 which causes the DMB
1090           instruction to behave as a DSB, ensuring the correct behaviour of
1091           the two writes.
1092
1093 config ARM_ERRATA_742231
1094         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1095         depends on CPU_V7 && SMP
1096         depends on !ARCH_MULTIPLATFORM
1097         help
1098           This option enables the workaround for the 742231 Cortex-A9
1099           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1100           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1101           accessing some data located in the same cache line, may get corrupted
1102           data due to bad handling of the address hazard when the line gets
1103           replaced from one of the CPUs at the same time as another CPU is
1104           accessing it. This workaround sets specific bits in the diagnostic
1105           register of the Cortex-A9 which reduces the linefill issuing
1106           capabilities of the processor.
1107
1108 config ARM_ERRATA_643719
1109         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1110         depends on CPU_V7 && SMP
1111         default y
1112         help
1113           This option enables the workaround for the 643719 Cortex-A9 (prior to
1114           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1115           register returns zero when it should return one. The workaround
1116           corrects this value, ensuring cache maintenance operations which use
1117           it behave as intended and avoiding data corruption.
1118
1119 config ARM_ERRATA_720789
1120         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1121         depends on CPU_V7
1122         help
1123           This option enables the workaround for the 720789 Cortex-A9 (prior to
1124           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1125           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1126           As a consequence of this erratum, some TLB entries which should be
1127           invalidated are not, resulting in an incoherency in the system page
1128           tables. The workaround changes the TLB flushing routines to invalidate
1129           entries regardless of the ASID.
1130
1131 config ARM_ERRATA_743622
1132         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1133         depends on CPU_V7
1134         depends on !ARCH_MULTIPLATFORM
1135         help
1136           This option enables the workaround for the 743622 Cortex-A9
1137           (r2p*) erratum. Under very rare conditions, a faulty
1138           optimisation in the Cortex-A9 Store Buffer may lead to data
1139           corruption. This workaround sets a specific bit in the diagnostic
1140           register of the Cortex-A9 which disables the Store Buffer
1141           optimisation, preventing the defect from occurring. This has no
1142           visible impact on the overall performance or power consumption of the
1143           processor.
1144
1145 config ARM_ERRATA_751472
1146         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1147         depends on CPU_V7
1148         depends on !ARCH_MULTIPLATFORM
1149         help
1150           This option enables the workaround for the 751472 Cortex-A9 (prior
1151           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1152           completion of a following broadcasted operation if the second
1153           operation is received by a CPU before the ICIALLUIS has completed,
1154           potentially leading to corrupted entries in the cache or TLB.
1155
1156 config ARM_ERRATA_754322
1157         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1158         depends on CPU_V7
1159         help
1160           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1161           r3p*) erratum. A speculative memory access may cause a page table walk
1162           which starts prior to an ASID switch but completes afterwards. This
1163           can populate the micro-TLB with a stale entry which may be hit with
1164           the new ASID. This workaround places two dsb instructions in the mm
1165           switching code so that no page table walks can cross the ASID switch.
1166
1167 config ARM_ERRATA_754327
1168         bool "ARM errata: no automatic Store Buffer drain"
1169         depends on CPU_V7 && SMP
1170         help
1171           This option enables the workaround for the 754327 Cortex-A9 (prior to
1172           r2p0) erratum. The Store Buffer does not have any automatic draining
1173           mechanism and therefore a livelock may occur if an external agent
1174           continuously polls a memory location waiting to observe an update.
1175           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1176           written polling loops from denying visibility of updates to memory.
1177
1178 config ARM_ERRATA_364296
1179         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1180         depends on CPU_V6
1181         help
1182           This options enables the workaround for the 364296 ARM1136
1183           r0p2 erratum (possible cache data corruption with
1184           hit-under-miss enabled). It sets the undocumented bit 31 in
1185           the auxiliary control register and the FI bit in the control
1186           register, thus disabling hit-under-miss without putting the
1187           processor into full low interrupt latency mode. ARM11MPCore
1188           is not affected.
1189
1190 config ARM_ERRATA_764369
1191         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1192         depends on CPU_V7 && SMP
1193         help
1194           This option enables the workaround for erratum 764369
1195           affecting Cortex-A9 MPCore with two or more processors (all
1196           current revisions). Under certain timing circumstances, a data
1197           cache line maintenance operation by MVA targeting an Inner
1198           Shareable memory region may fail to proceed up to either the
1199           Point of Coherency or to the Point of Unification of the
1200           system. This workaround adds a DSB instruction before the
1201           relevant cache maintenance functions and sets a specific bit
1202           in the diagnostic control register of the SCU.
1203
1204 config ARM_ERRATA_775420
1205        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1206        depends on CPU_V7
1207        help
1208          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1209          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1210          operation aborts with MMU exception, it might cause the processor
1211          to deadlock. This workaround puts DSB before executing ISB if
1212          an abort may occur on cache maintenance.
1213
1214 config ARM_ERRATA_798181
1215         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1216         depends on CPU_V7 && SMP
1217         help
1218           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1219           adequately shooting down all use of the old entries. This
1220           option enables the Linux kernel workaround for this erratum
1221           which sends an IPI to the CPUs that are running the same ASID
1222           as the one being invalidated.
1223
1224 config ARM_ERRATA_773022
1225         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1226         depends on CPU_V7
1227         help
1228           This option enables the workaround for the 773022 Cortex-A15
1229           (up to r0p4) erratum. In certain rare sequences of code, the
1230           loop buffer may deliver incorrect instructions. This
1231           workaround disables the loop buffer to avoid the erratum.
1232
1233 endmenu
1234
1235 source "arch/arm/common/Kconfig"
1236
1237 menu "Bus support"
1238
1239 config ISA
1240         bool
1241         help
1242           Find out whether you have ISA slots on your motherboard.  ISA is the
1243           name of a bus system, i.e. the way the CPU talks to the other stuff
1244           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1245           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1246           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1247
1248 # Select ISA DMA controller support
1249 config ISA_DMA
1250         bool
1251         select ISA_DMA_API
1252
1253 # Select ISA DMA interface
1254 config ISA_DMA_API
1255         bool
1256
1257 config PCI
1258         bool "PCI support" if MIGHT_HAVE_PCI
1259         help
1260           Find out whether you have a PCI motherboard. PCI is the name of a
1261           bus system, i.e. the way the CPU talks to the other stuff inside
1262           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1263           VESA. If you have PCI, say Y, otherwise N.
1264
1265 config PCI_DOMAINS
1266         bool
1267         depends on PCI
1268
1269 config PCI_DOMAINS_GENERIC
1270         def_bool PCI_DOMAINS
1271
1272 config PCI_NANOENGINE
1273         bool "BSE nanoEngine PCI support"
1274         depends on SA1100_NANOENGINE
1275         help
1276           Enable PCI on the BSE nanoEngine board.
1277
1278 config PCI_SYSCALL
1279         def_bool PCI
1280
1281 config PCI_HOST_ITE8152
1282         bool
1283         depends on PCI && MACH_ARMCORE
1284         default y
1285         select DMABOUNCE
1286
1287 source "drivers/pci/Kconfig"
1288 source "drivers/pci/pcie/Kconfig"
1289
1290 source "drivers/pcmcia/Kconfig"
1291
1292 endmenu
1293
1294 menu "Kernel Features"
1295
1296 config HAVE_SMP
1297         bool
1298         help
1299           This option should be selected by machines which have an SMP-
1300           capable CPU.
1301
1302           The only effect of this option is to make the SMP-related
1303           options available to the user for configuration.
1304
1305 config SMP
1306         bool "Symmetric Multi-Processing"
1307         depends on CPU_V6K || CPU_V7
1308         depends on GENERIC_CLOCKEVENTS
1309         depends on HAVE_SMP
1310         depends on MMU || ARM_MPU
1311         help
1312           This enables support for systems with more than one CPU. If you have
1313           a system with only one CPU, say N. If you have a system with more
1314           than one CPU, say Y.
1315
1316           If you say N here, the kernel will run on uni- and multiprocessor
1317           machines, but will use only one CPU of a multiprocessor machine. If
1318           you say Y here, the kernel will run on many, but not all,
1319           uniprocessor machines. On a uniprocessor machine, the kernel
1320           will run faster if you say N here.
1321
1322           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1323           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1324           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1325
1326           If you don't know what to do here, say N.
1327
1328 config SMP_ON_UP
1329         bool "Allow booting SMP kernel on uniprocessor systems"
1330         depends on SMP && !XIP_KERNEL && MMU
1331         default y
1332         help
1333           SMP kernels contain instructions which fail on non-SMP processors.
1334           Enabling this option allows the kernel to modify itself to make
1335           these instructions safe.  Disabling it allows about 1K of space
1336           savings.
1337
1338           If you don't know what to do here, say Y.
1339
1340 config ARM_CPU_TOPOLOGY
1341         bool "Support cpu topology definition"
1342         depends on SMP && CPU_V7
1343         default y
1344         help
1345           Support ARM cpu topology definition. The MPIDR register defines
1346           affinity between processors which is then used to describe the cpu
1347           topology of an ARM System.
1348
1349 config SCHED_MC
1350         bool "Multi-core scheduler support"
1351         depends on ARM_CPU_TOPOLOGY
1352         help
1353           Multi-core scheduler support improves the CPU scheduler's decision
1354           making when dealing with multi-core CPU chips at a cost of slightly
1355           increased overhead in some places. If unsure say N here.
1356
1357 config SCHED_SMT
1358         bool "SMT scheduler support"
1359         depends on ARM_CPU_TOPOLOGY
1360         help
1361           Improves the CPU scheduler's decision making when dealing with
1362           MultiThreading at a cost of slightly increased overhead in some
1363           places. If unsure say N here.
1364
1365 config HAVE_ARM_SCU
1366         bool
1367         help
1368           This option enables support for the ARM system coherency unit
1369
1370 config HAVE_ARM_ARCH_TIMER
1371         bool "Architected timer support"
1372         depends on CPU_V7
1373         select ARM_ARCH_TIMER
1374         select GENERIC_CLOCKEVENTS
1375         help
1376           This option enables support for the ARM architected timer
1377
1378 config HAVE_ARM_TWD
1379         bool
1380         depends on SMP
1381         select CLKSRC_OF if OF
1382         help
1383           This options enables support for the ARM timer and watchdog unit
1384
1385 config MCPM
1386         bool "Multi-Cluster Power Management"
1387         depends on CPU_V7 && SMP
1388         help
1389           This option provides the common power management infrastructure
1390           for (multi-)cluster based systems, such as big.LITTLE based
1391           systems.
1392
1393 config MCPM_QUAD_CLUSTER
1394         bool
1395         depends on MCPM
1396         help
1397           To avoid wasting resources unnecessarily, MCPM only supports up
1398           to 2 clusters by default.
1399           Platforms with 3 or 4 clusters that use MCPM must select this
1400           option to allow the additional clusters to be managed.
1401
1402 config BIG_LITTLE
1403         bool "big.LITTLE support (Experimental)"
1404         depends on CPU_V7 && SMP
1405         select MCPM
1406         help
1407           This option enables support selections for the big.LITTLE
1408           system architecture.
1409
1410 config BL_SWITCHER
1411         bool "big.LITTLE switcher support"
1412         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1413         select ARM_CPU_SUSPEND
1414         select CPU_PM
1415         help
1416           The big.LITTLE "switcher" provides the core functionality to
1417           transparently handle transition between a cluster of A15's
1418           and a cluster of A7's in a big.LITTLE system.
1419
1420 config BL_SWITCHER_DUMMY_IF
1421         tristate "Simple big.LITTLE switcher user interface"
1422         depends on BL_SWITCHER && DEBUG_KERNEL
1423         help
1424           This is a simple and dummy char dev interface to control
1425           the big.LITTLE switcher core code.  It is meant for
1426           debugging purposes only.
1427
1428 choice
1429         prompt "Memory split"
1430         depends on MMU
1431         default VMSPLIT_3G
1432         help
1433           Select the desired split between kernel and user memory.
1434
1435           If you are not absolutely sure what you are doing, leave this
1436           option alone!
1437
1438         config VMSPLIT_3G
1439                 bool "3G/1G user/kernel split"
1440         config VMSPLIT_2G
1441                 bool "2G/2G user/kernel split"
1442         config VMSPLIT_1G
1443                 bool "1G/3G user/kernel split"
1444 endchoice
1445
1446 config PAGE_OFFSET
1447         hex
1448         default PHYS_OFFSET if !MMU
1449         default 0x40000000 if VMSPLIT_1G
1450         default 0x80000000 if VMSPLIT_2G
1451         default 0xC0000000
1452
1453 config NR_CPUS
1454         int "Maximum number of CPUs (2-32)"
1455         range 2 32
1456         depends on SMP
1457         default "4"
1458
1459 config HOTPLUG_CPU
1460         bool "Support for hot-pluggable CPUs"
1461         depends on SMP
1462         help
1463           Say Y here to experiment with turning CPUs off and on.  CPUs
1464           can be controlled through /sys/devices/system/cpu.
1465
1466 config ARM_PSCI
1467         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1468         depends on CPU_V7
1469         help
1470           Say Y here if you want Linux to communicate with system firmware
1471           implementing the PSCI specification for CPU-centric power
1472           management operations described in ARM document number ARM DEN
1473           0022A ("Power State Coordination Interface System Software on
1474           ARM processors").
1475
1476 # The GPIO number here must be sorted by descending number. In case of
1477 # a multiplatform kernel, we just want the highest value required by the
1478 # selected platforms.
1479 config ARCH_NR_GPIO
1480         int
1481         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1482         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1483                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1484         default 416 if ARCH_SUNXI
1485         default 392 if ARCH_U8500
1486         default 352 if ARCH_VT8500
1487         default 288 if ARCH_ROCKCHIP
1488         default 264 if MACH_H4700
1489         default 0
1490         help
1491           Maximum number of GPIOs in the system.
1492
1493           If unsure, leave the default value.
1494
1495 source kernel/Kconfig.preempt
1496
1497 config HZ_FIXED
1498         int
1499         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1500                 ARCH_S5PV210 || ARCH_EXYNOS4
1501         default 128 if SOC_AT91RM9200
1502         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1503         default 0
1504
1505 choice
1506         depends on HZ_FIXED = 0
1507         prompt "Timer frequency"
1508
1509 config HZ_100
1510         bool "100 Hz"
1511
1512 config HZ_200
1513         bool "200 Hz"
1514
1515 config HZ_250
1516         bool "250 Hz"
1517
1518 config HZ_300
1519         bool "300 Hz"
1520
1521 config HZ_500
1522         bool "500 Hz"
1523
1524 config HZ_1000
1525         bool "1000 Hz"
1526
1527 endchoice
1528
1529 config HZ
1530         int
1531         default HZ_FIXED if HZ_FIXED != 0
1532         default 100 if HZ_100
1533         default 200 if HZ_200
1534         default 250 if HZ_250
1535         default 300 if HZ_300
1536         default 500 if HZ_500
1537         default 1000
1538
1539 config SCHED_HRTICK
1540         def_bool HIGH_RES_TIMERS
1541
1542 config THUMB2_KERNEL
1543         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1544         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1545         default y if CPU_THUMBONLY
1546         select AEABI
1547         select ARM_ASM_UNIFIED
1548         select ARM_UNWIND
1549         help
1550           By enabling this option, the kernel will be compiled in
1551           Thumb-2 mode. A compiler/assembler that understand the unified
1552           ARM-Thumb syntax is needed.
1553
1554           If unsure, say N.
1555
1556 config THUMB2_AVOID_R_ARM_THM_JUMP11
1557         bool "Work around buggy Thumb-2 short branch relocations in gas"
1558         depends on THUMB2_KERNEL && MODULES
1559         default y
1560         help
1561           Various binutils versions can resolve Thumb-2 branches to
1562           locally-defined, preemptible global symbols as short-range "b.n"
1563           branch instructions.
1564
1565           This is a problem, because there's no guarantee the final
1566           destination of the symbol, or any candidate locations for a
1567           trampoline, are within range of the branch.  For this reason, the
1568           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1569           relocation in modules at all, and it makes little sense to add
1570           support.
1571
1572           The symptom is that the kernel fails with an "unsupported
1573           relocation" error when loading some modules.
1574
1575           Until fixed tools are available, passing
1576           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1577           code which hits this problem, at the cost of a bit of extra runtime
1578           stack usage in some cases.
1579
1580           The problem is described in more detail at:
1581               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1582
1583           Only Thumb-2 kernels are affected.
1584
1585           Unless you are sure your tools don't have this problem, say Y.
1586
1587 config ARM_ASM_UNIFIED
1588         bool
1589
1590 config AEABI
1591         bool "Use the ARM EABI to compile the kernel"
1592         help
1593           This option allows for the kernel to be compiled using the latest
1594           ARM ABI (aka EABI).  This is only useful if you are using a user
1595           space environment that is also compiled with EABI.
1596
1597           Since there are major incompatibilities between the legacy ABI and
1598           EABI, especially with regard to structure member alignment, this
1599           option also changes the kernel syscall calling convention to
1600           disambiguate both ABIs and allow for backward compatibility support
1601           (selected with CONFIG_OABI_COMPAT).
1602
1603           To use this you need GCC version 4.0.0 or later.
1604
1605 config OABI_COMPAT
1606         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1607         depends on AEABI && !THUMB2_KERNEL
1608         help
1609           This option preserves the old syscall interface along with the
1610           new (ARM EABI) one. It also provides a compatibility layer to
1611           intercept syscalls that have structure arguments which layout
1612           in memory differs between the legacy ABI and the new ARM EABI
1613           (only for non "thumb" binaries). This option adds a tiny
1614           overhead to all syscalls and produces a slightly larger kernel.
1615
1616           The seccomp filter system will not be available when this is
1617           selected, since there is no way yet to sensibly distinguish
1618           between calling conventions during filtering.
1619
1620           If you know you'll be using only pure EABI user space then you
1621           can say N here. If this option is not selected and you attempt
1622           to execute a legacy ABI binary then the result will be
1623           UNPREDICTABLE (in fact it can be predicted that it won't work
1624           at all). If in doubt say N.
1625
1626 config ARCH_HAS_HOLES_MEMORYMODEL
1627         bool
1628
1629 config ARCH_SPARSEMEM_ENABLE
1630         bool
1631
1632 config ARCH_SPARSEMEM_DEFAULT
1633         def_bool ARCH_SPARSEMEM_ENABLE
1634
1635 config ARCH_SELECT_MEMORY_MODEL
1636         def_bool ARCH_SPARSEMEM_ENABLE
1637
1638 config HAVE_ARCH_PFN_VALID
1639         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1640
1641 config HAVE_GENERIC_RCU_GUP
1642         def_bool y
1643         depends on ARM_LPAE
1644
1645 config HIGHMEM
1646         bool "High Memory Support"
1647         depends on MMU
1648         help
1649           The address space of ARM processors is only 4 Gigabytes large
1650           and it has to accommodate user address space, kernel address
1651           space as well as some memory mapped IO. That means that, if you
1652           have a large amount of physical memory and/or IO, not all of the
1653           memory can be "permanently mapped" by the kernel. The physical
1654           memory that is not permanently mapped is called "high memory".
1655
1656           Depending on the selected kernel/user memory split, minimum
1657           vmalloc space and actual amount of RAM, you may not need this
1658           option which should result in a slightly faster kernel.
1659
1660           If unsure, say n.
1661
1662 config HIGHPTE
1663         bool "Allocate 2nd-level pagetables from highmem"
1664         depends on HIGHMEM
1665
1666 config HW_PERF_EVENTS
1667         bool "Enable hardware performance counter support for perf events"
1668         depends on PERF_EVENTS
1669         default y
1670         help
1671           Enable hardware performance counter support for perf events. If
1672           disabled, perf events will use software events only.
1673
1674 config SYS_SUPPORTS_HUGETLBFS
1675        def_bool y
1676        depends on ARM_LPAE
1677
1678 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1679        def_bool y
1680        depends on ARM_LPAE
1681
1682 config ARCH_WANT_GENERAL_HUGETLB
1683         def_bool y
1684
1685 source "mm/Kconfig"
1686
1687 config FORCE_MAX_ZONEORDER
1688         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1689         range 11 64 if ARCH_SHMOBILE_LEGACY
1690         default "12" if SOC_AM33XX
1691         default "9" if SA1111 || ARCH_EFM32
1692         default "11"
1693         help
1694           The kernel memory allocator divides physically contiguous memory
1695           blocks into "zones", where each zone is a power of two number of
1696           pages.  This option selects the largest power of two that the kernel
1697           keeps in the memory allocator.  If you need to allocate very large
1698           blocks of physically contiguous memory, then you may need to
1699           increase this value.
1700
1701           This config option is actually maximum order plus one. For example,
1702           a value of 11 means that the largest free memory block is 2^10 pages.
1703
1704 config ALIGNMENT_TRAP
1705         bool
1706         depends on CPU_CP15_MMU
1707         default y if !ARCH_EBSA110
1708         select HAVE_PROC_CPU if PROC_FS
1709         help
1710           ARM processors cannot fetch/store information which is not
1711           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1712           address divisible by 4. On 32-bit ARM processors, these non-aligned
1713           fetch/store instructions will be emulated in software if you say
1714           here, which has a severe performance impact. This is necessary for
1715           correct operation of some network protocols. With an IP-only
1716           configuration it is safe to say N, otherwise say Y.
1717
1718 config UACCESS_WITH_MEMCPY
1719         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1720         depends on MMU
1721         default y if CPU_FEROCEON
1722         help
1723           Implement faster copy_to_user and clear_user methods for CPU
1724           cores where a 8-word STM instruction give significantly higher
1725           memory write throughput than a sequence of individual 32bit stores.
1726
1727           A possible side effect is a slight increase in scheduling latency
1728           between threads sharing the same address space if they invoke
1729           such copy operations with large buffers.
1730
1731           However, if the CPU data cache is using a write-allocate mode,
1732           this option is unlikely to provide any performance gain.
1733
1734 config SECCOMP
1735         bool
1736         prompt "Enable seccomp to safely compute untrusted bytecode"
1737         ---help---
1738           This kernel feature is useful for number crunching applications
1739           that may need to compute untrusted bytecode during their
1740           execution. By using pipes or other transports made available to
1741           the process as file descriptors supporting the read/write
1742           syscalls, it's possible to isolate those applications in
1743           their own address space using seccomp. Once seccomp is
1744           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1745           and the task is only allowed to execute a few safe syscalls
1746           defined by each seccomp mode.
1747
1748 config SWIOTLB
1749         def_bool y
1750
1751 config IOMMU_HELPER
1752         def_bool SWIOTLB
1753
1754 config XEN_DOM0
1755         def_bool y
1756         depends on XEN
1757
1758 config XEN
1759         bool "Xen guest support on ARM"
1760         depends on ARM && AEABI && OF
1761         depends on CPU_V7 && !CPU_V6
1762         depends on !GENERIC_ATOMIC64
1763         depends on MMU
1764         select ARCH_DMA_ADDR_T_64BIT
1765         select ARM_PSCI
1766         select SWIOTLB_XEN
1767         help
1768           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1769
1770 endmenu
1771
1772 menu "Boot options"
1773
1774 config USE_OF
1775         bool "Flattened Device Tree support"
1776         select IRQ_DOMAIN
1777         select OF
1778         select OF_EARLY_FLATTREE
1779         select OF_RESERVED_MEM
1780         help
1781           Include support for flattened device tree machine descriptions.
1782
1783 config ATAGS
1784         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1785         default y
1786         help
1787           This is the traditional way of passing data to the kernel at boot
1788           time. If you are solely relying on the flattened device tree (or
1789           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1790           to remove ATAGS support from your kernel binary.  If unsure,
1791           leave this to y.
1792
1793 config DEPRECATED_PARAM_STRUCT
1794         bool "Provide old way to pass kernel parameters"
1795         depends on ATAGS
1796         help
1797           This was deprecated in 2001 and announced to live on for 5 years.
1798           Some old boot loaders still use this way.
1799
1800 # Compressed boot loader in ROM.  Yes, we really want to ask about
1801 # TEXT and BSS so we preserve their values in the config files.
1802 config ZBOOT_ROM_TEXT
1803         hex "Compressed ROM boot loader base address"
1804         default "0"
1805         help
1806           The physical address at which the ROM-able zImage is to be
1807           placed in the target.  Platforms which normally make use of
1808           ROM-able zImage formats normally set this to a suitable
1809           value in their defconfig file.
1810
1811           If ZBOOT_ROM is not enabled, this has no effect.
1812
1813 config ZBOOT_ROM_BSS
1814         hex "Compressed ROM boot loader BSS address"
1815         default "0"
1816         help
1817           The base address of an area of read/write memory in the target
1818           for the ROM-able zImage which must be available while the
1819           decompressor is running. It must be large enough to hold the
1820           entire decompressed kernel plus an additional 128 KiB.
1821           Platforms which normally make use of ROM-able zImage formats
1822           normally set this to a suitable value in their defconfig file.
1823
1824           If ZBOOT_ROM is not enabled, this has no effect.
1825
1826 config ZBOOT_ROM
1827         bool "Compressed boot loader in ROM/flash"
1828         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1829         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1830         help
1831           Say Y here if you intend to execute your compressed kernel image
1832           (zImage) directly from ROM or flash.  If unsure, say N.
1833
1834 config ARM_APPENDED_DTB
1835         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1836         depends on OF
1837         help
1838           With this option, the boot code will look for a device tree binary
1839           (DTB) appended to zImage
1840           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1841
1842           This is meant as a backward compatibility convenience for those
1843           systems with a bootloader that can't be upgraded to accommodate
1844           the documented boot protocol using a device tree.
1845
1846           Beware that there is very little in terms of protection against
1847           this option being confused by leftover garbage in memory that might
1848           look like a DTB header after a reboot if no actual DTB is appended
1849           to zImage.  Do not leave this option active in a production kernel
1850           if you don't intend to always append a DTB.  Proper passing of the
1851           location into r2 of a bootloader provided DTB is always preferable
1852           to this option.
1853
1854 config ARM_ATAG_DTB_COMPAT
1855         bool "Supplement the appended DTB with traditional ATAG information"
1856         depends on ARM_APPENDED_DTB
1857         help
1858           Some old bootloaders can't be updated to a DTB capable one, yet
1859           they provide ATAGs with memory configuration, the ramdisk address,
1860           the kernel cmdline string, etc.  Such information is dynamically
1861           provided by the bootloader and can't always be stored in a static
1862           DTB.  To allow a device tree enabled kernel to be used with such
1863           bootloaders, this option allows zImage to extract the information
1864           from the ATAG list and store it at run time into the appended DTB.
1865
1866 choice
1867         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1868         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1869
1870 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1871         bool "Use bootloader kernel arguments if available"
1872         help
1873           Uses the command-line options passed by the boot loader instead of
1874           the device tree bootargs property. If the boot loader doesn't provide
1875           any, the device tree bootargs property will be used.
1876
1877 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1878         bool "Extend with bootloader kernel arguments"
1879         help
1880           The command-line arguments provided by the boot loader will be
1881           appended to the the device tree bootargs property.
1882
1883 endchoice
1884
1885 config CMDLINE
1886         string "Default kernel command string"
1887         default ""
1888         help
1889           On some architectures (EBSA110 and CATS), there is currently no way
1890           for the boot loader to pass arguments to the kernel. For these
1891           architectures, you should supply some command-line options at build
1892           time by entering them here. As a minimum, you should specify the
1893           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1894
1895 choice
1896         prompt "Kernel command line type" if CMDLINE != ""
1897         default CMDLINE_FROM_BOOTLOADER
1898         depends on ATAGS
1899
1900 config CMDLINE_FROM_BOOTLOADER
1901         bool "Use bootloader kernel arguments if available"
1902         help
1903           Uses the command-line options passed by the boot loader. If
1904           the boot loader doesn't provide any, the default kernel command
1905           string provided in CMDLINE will be used.
1906
1907 config CMDLINE_EXTEND
1908         bool "Extend bootloader kernel arguments"
1909         help
1910           The command-line arguments provided by the boot loader will be
1911           appended to the default kernel command string.
1912
1913 config CMDLINE_FORCE
1914         bool "Always use the default kernel command string"
1915         help
1916           Always use the default kernel command string, even if the boot
1917           loader passes other arguments to the kernel.
1918           This is useful if you cannot or don't want to change the
1919           command-line options your boot loader passes to the kernel.
1920 endchoice
1921
1922 config XIP_KERNEL
1923         bool "Kernel Execute-In-Place from ROM"
1924         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1925         help
1926           Execute-In-Place allows the kernel to run from non-volatile storage
1927           directly addressable by the CPU, such as NOR flash. This saves RAM
1928           space since the text section of the kernel is not loaded from flash
1929           to RAM.  Read-write sections, such as the data section and stack,
1930           are still copied to RAM.  The XIP kernel is not compressed since
1931           it has to run directly from flash, so it will take more space to
1932           store it.  The flash address used to link the kernel object files,
1933           and for storing it, is configuration dependent. Therefore, if you
1934           say Y here, you must know the proper physical address where to
1935           store the kernel image depending on your own flash memory usage.
1936
1937           Also note that the make target becomes "make xipImage" rather than
1938           "make zImage" or "make Image".  The final kernel binary to put in
1939           ROM memory will be arch/arm/boot/xipImage.
1940
1941           If unsure, say N.
1942
1943 config XIP_PHYS_ADDR
1944         hex "XIP Kernel Physical Location"
1945         depends on XIP_KERNEL
1946         default "0x00080000"
1947         help
1948           This is the physical address in your flash memory the kernel will
1949           be linked for and stored to.  This address is dependent on your
1950           own flash usage.
1951
1952 config KEXEC
1953         bool "Kexec system call (EXPERIMENTAL)"
1954         depends on (!SMP || PM_SLEEP_SMP)
1955         help
1956           kexec is a system call that implements the ability to shutdown your
1957           current kernel, and to start another kernel.  It is like a reboot
1958           but it is independent of the system firmware.   And like a reboot
1959           you can start any kernel with it, not just Linux.
1960
1961           It is an ongoing process to be certain the hardware in a machine
1962           is properly shutdown, so do not be surprised if this code does not
1963           initially work for you.
1964
1965 config ATAGS_PROC
1966         bool "Export atags in procfs"
1967         depends on ATAGS && KEXEC
1968         default y
1969         help
1970           Should the atags used to boot the kernel be exported in an "atags"
1971           file in procfs. Useful with kexec.
1972
1973 config CRASH_DUMP
1974         bool "Build kdump crash kernel (EXPERIMENTAL)"
1975         help
1976           Generate crash dump after being started by kexec. This should
1977           be normally only set in special crash dump kernels which are
1978           loaded in the main kernel with kexec-tools into a specially
1979           reserved region and then later executed after a crash by
1980           kdump/kexec. The crash dump kernel must be compiled to a
1981           memory address not used by the main kernel
1982
1983           For more details see Documentation/kdump/kdump.txt
1984
1985 config AUTO_ZRELADDR
1986         bool "Auto calculation of the decompressed kernel image address"
1987         help
1988           ZRELADDR is the physical address where the decompressed kernel
1989           image will be placed. If AUTO_ZRELADDR is selected, the address
1990           will be determined at run-time by masking the current IP with
1991           0xf8000000. This assumes the zImage being placed in the first 128MB
1992           from start of memory.
1993
1994 endmenu
1995
1996 menu "CPU Power Management"
1997
1998 source "drivers/cpufreq/Kconfig"
1999
2000 source "drivers/cpuidle/Kconfig"
2001
2002 endmenu
2003
2004 menu "Floating point emulation"
2005
2006 comment "At least one emulation must be selected"
2007
2008 config FPE_NWFPE
2009         bool "NWFPE math emulation"
2010         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2011         ---help---
2012           Say Y to include the NWFPE floating point emulator in the kernel.
2013           This is necessary to run most binaries. Linux does not currently
2014           support floating point hardware so you need to say Y here even if
2015           your machine has an FPA or floating point co-processor podule.
2016
2017           You may say N here if you are going to load the Acorn FPEmulator
2018           early in the bootup.
2019
2020 config FPE_NWFPE_XP
2021         bool "Support extended precision"
2022         depends on FPE_NWFPE
2023         help
2024           Say Y to include 80-bit support in the kernel floating-point
2025           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2026           Note that gcc does not generate 80-bit operations by default,
2027           so in most cases this option only enlarges the size of the
2028           floating point emulator without any good reason.
2029
2030           You almost surely want to say N here.
2031
2032 config FPE_FASTFPE
2033         bool "FastFPE math emulation (EXPERIMENTAL)"
2034         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2035         ---help---
2036           Say Y here to include the FAST floating point emulator in the kernel.
2037           This is an experimental much faster emulator which now also has full
2038           precision for the mantissa.  It does not support any exceptions.
2039           It is very simple, and approximately 3-6 times faster than NWFPE.
2040
2041           It should be sufficient for most programs.  It may be not suitable
2042           for scientific calculations, but you have to check this for yourself.
2043           If you do not feel you need a faster FP emulation you should better
2044           choose NWFPE.
2045
2046 config VFP
2047         bool "VFP-format floating point maths"
2048         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2049         help
2050           Say Y to include VFP support code in the kernel. This is needed
2051           if your hardware includes a VFP unit.
2052
2053           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2054           release notes and additional status information.
2055
2056           Say N if your target does not have VFP hardware.
2057
2058 config VFPv3
2059         bool
2060         depends on VFP
2061         default y if CPU_V7
2062
2063 config NEON
2064         bool "Advanced SIMD (NEON) Extension support"
2065         depends on VFPv3 && CPU_V7
2066         help
2067           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2068           Extension.
2069
2070 config KERNEL_MODE_NEON
2071         bool "Support for NEON in kernel mode"
2072         depends on NEON && AEABI
2073         help
2074           Say Y to include support for NEON in kernel mode.
2075
2076 endmenu
2077
2078 menu "Userspace binary formats"
2079
2080 source "fs/Kconfig.binfmt"
2081
2082 endmenu
2083
2084 menu "Power management options"
2085
2086 source "kernel/power/Kconfig"
2087
2088 config ARCH_SUSPEND_POSSIBLE
2089         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2090                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2091         def_bool y
2092
2093 config ARM_CPU_SUSPEND
2094         def_bool PM_SLEEP
2095
2096 config ARCH_HIBERNATION_POSSIBLE
2097         bool
2098         depends on MMU
2099         default y if ARCH_SUSPEND_POSSIBLE
2100
2101 endmenu
2102
2103 source "net/Kconfig"
2104
2105 source "drivers/Kconfig"
2106
2107 source "drivers/firmware/Kconfig"
2108
2109 source "fs/Kconfig"
2110
2111 source "arch/arm/Kconfig.debug"
2112
2113 source "security/Kconfig"
2114
2115 source "crypto/Kconfig"
2116 if CRYPTO
2117 source "arch/arm/crypto/Kconfig"
2118 endif
2119
2120 source "lib/Kconfig"
2121
2122 source "arch/arm/kvm/Kconfig"