arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
  37         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OF_EARLY_FLATTREE if OF
  80         select OF_RESERVED_MEM if OF
  81         select OLD_SIGACTION
  82         select OLD_SIGSUSPEND3
  83         select PERF_USE_VMALLOC
  84         select RTC_LIB
  85         select SYS_SUPPORTS_APM_EMULATION
  86         # Above selects are sorted alphabetically; please add new ones
  87         # according to that.  Thanks.
  88         help
  89           The ARM series is a line of low-power-consumption RISC chip designs
  90           licensed by ARM Ltd and targeted at embedded applications and
  91           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  92           manufactured, but legacy ARM-based PC hardware remains popular in
  93           Europe.  There is an ARM Linux project with a web page at
  94           <http://www.arm.linux.org.uk/>.
  95
  96 config ARM_HAS_SG_CHAIN
  97         select ARCH_HAS_SG_CHAIN
  98         bool
  99
 100 config NEED_SG_DMA_LENGTH
 101         bool
 102
 103 config ARM_DMA_USE_IOMMU
 104         bool
 105         select ARM_HAS_SG_CHAIN
 106         select NEED_SG_DMA_LENGTH
 107
 108 if ARM_DMA_USE_IOMMU
 109
 110 config ARM_DMA_IOMMU_ALIGNMENT
 111         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 112         range 4 9
 113         default 8
 114         help
 115           DMA mapping framework by default aligns all buffers to the smallest
 116           PAGE_SIZE order which is greater than or equal to the requested buffer
 117           size. This works well for buffers up to a few hundreds kilobytes, but
 118           for larger buffers it just a waste of address space. Drivers which has
 119           relatively small addressing window (like 64Mib) might run out of
 120           virtual space with just a few allocations.
 121
 122           With this parameter you can specify the maximum PAGE_SIZE order for
 123           DMA IOMMU buffers. Larger buffers will be aligned only to this
 124           specified order. The order is expressed as a power of two multiplied
 125           by the PAGE_SIZE.
 126
 127 endif
 128
 129 config MIGHT_HAVE_PCI
 130         bool
 131
 132 config SYS_SUPPORTS_APM_EMULATION
 133         bool
 134
 135 config HAVE_TCM
 136         bool
 137         select GENERIC_ALLOCATOR
 138
 139 config HAVE_PROC_CPU
 140         bool
 141
 142 config NO_IOPORT_MAP
 143         bool
 144
 145 config EISA
 146         bool
 147         ---help---
 148           The Extended Industry Standard Architecture (EISA) bus was
 149           developed as an open alternative to the IBM MicroChannel bus.
 150
 151           The EISA bus provided some of the features of the IBM MicroChannel
 152           bus while maintaining backward compatibility with cards made for
 153           the older ISA bus.  The EISA bus saw limited use between 1988 and
 154           1995 when it was made obsolete by the PCI bus.
 155
 156           Say Y here if you are building a kernel for an EISA-based machine.
 157
 158           Otherwise, say N.
 159
 160 config SBUS
 161         bool
 162
 163 config STACKTRACE_SUPPORT
 164         bool
 165         default y
 166
 167 config HAVE_LATENCYTOP_SUPPORT
 168         bool
 169         depends on !SMP
 170         default y
 171
 172 config LOCKDEP_SUPPORT
 173         bool
 174         default y
 175
 176 config TRACE_IRQFLAGS_SUPPORT
 177         bool
 178         default !CPU_V7M
 179
 180 config RWSEM_XCHGADD_ALGORITHM
 181         bool
 182         default y
 183
 184 config ARCH_HAS_ILOG2_U32
 185         bool
 186
 187 config ARCH_HAS_ILOG2_U64
 188         bool
 189
 190 config ARCH_HAS_BANDGAP
 191         bool
 192
 193 config FIX_EARLYCON_MEM
 194         def_bool y if MMU
 195
 196 config GENERIC_HWEIGHT
 197         bool
 198         default y
 199
 200 config GENERIC_CALIBRATE_DELAY
 201         bool
 202         default y
 203
 204 config ARCH_MAY_HAVE_PC_FDC
 205         bool
 206
 207 config ZONE_DMA
 208         bool
 209
 210 config NEED_DMA_MAP_STATE
 211        def_bool y
 212
 213 config ARCH_SUPPORTS_UPROBES
 214         def_bool y
 215
 216 config ARCH_HAS_DMA_SET_COHERENT_MASK
 217         bool
 218
 219 config GENERIC_ISA_DMA
 220         bool
 221
 222 config FIQ
 223         bool
 224
 225 config NEED_RET_TO_USER
 226         bool
 227
 228 config ARCH_MTD_XIP
 229         bool
 230
 231 config VECTORS_BASE
 232         hex
 233         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 234         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 235         default 0x00000000
 236         help
 237           The base address of exception vectors.  This must be two pages
 238           in size.
 239
 240 config ARM_PATCH_PHYS_VIRT
 241         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 242         default y
 243         depends on !XIP_KERNEL && MMU
 244         depends on !ARCH_REALVIEW || !SPARSEMEM
 245         help
 246           Patch phys-to-virt and virt-to-phys translation functions at
 247           boot and module load time according to the position of the
 248           kernel in system memory.
 249
 250           This can only be used with non-XIP MMU kernels where the base
 251           of physical memory is at a 16MB boundary.
 252
 253           Only disable this option if you know that you do not require
 254           this feature (eg, building a kernel for a single machine) and
 255           you need to shrink the kernel to the minimal size.
 256
 257 config NEED_MACH_IO_H
 258         bool
 259         help
 260           Select this when mach/io.h is required to provide special
 261           definitions for this platform.  The need for mach/io.h should
 262           be avoided when possible.
 263
 264 config NEED_MACH_MEMORY_H
 265         bool
 266         help
 267           Select this when mach/memory.h is required to provide special
 268           definitions for this platform.  The need for mach/memory.h should
 269           be avoided when possible.
 270
 271 config PHYS_OFFSET
 272         hex "Physical address of main memory" if MMU
 273         depends on !ARM_PATCH_PHYS_VIRT
 274         default DRAM_BASE if !MMU
 275         default 0x00000000 if ARCH_EBSA110 || \
 276                         ARCH_FOOTBRIDGE || \
 277                         ARCH_INTEGRATOR || \
 278                         ARCH_IOP13XX || \
 279                         ARCH_KS8695 || \
 280                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 281         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 282         default 0x20000000 if ARCH_S5PV210
 283         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 284         default 0xc0000000 if ARCH_SA1100
 285         help
 286           Please provide the physical address corresponding to the
 287           location of main memory in your system.
 288
 289 config GENERIC_BUG
 290         def_bool y
 291         depends on BUG
 292
 293 config PGTABLE_LEVELS
 294         int
 295         default 3 if ARM_LPAE
 296         default 2
 297
 298 source "init/Kconfig"
 299
 300 source "kernel/Kconfig.freezer"
 301
 302 menu "System Type"
 303
 304 config MMU
 305         bool "MMU-based Paged Memory Management Support"
 306         default y
 307         help
 308           Select if you want MMU-based virtualised addressing space
 309           support by paged memory management. If unsure, say 'Y'.
 310
 311 #
 312 # The "ARM system type" choice list is ordered alphabetically by option
 313 # text.  Please add new entries in the option alphabetic order.
 314 #
 315 choice
 316         prompt "ARM system type"
 317         default ARCH_VERSATILE if !MMU
 318         default ARCH_MULTIPLATFORM if MMU
 319
 320 config ARCH_MULTIPLATFORM
 321         bool "Allow multiple platforms to be selected"
 322         depends on MMU
 323         select ARCH_WANT_OPTIONAL_GPIOLIB
 324         select ARM_HAS_SG_CHAIN
 325         select ARM_PATCH_PHYS_VIRT
 326         select AUTO_ZRELADDR
 327         select CLKSRC_OF
 328         select COMMON_CLK
 329         select GENERIC_CLOCKEVENTS
 330         select MIGHT_HAVE_PCI
 331         select MULTI_IRQ_HANDLER
 332         select SPARSE_IRQ
 333         select USE_OF
 334
 335 config ARM_SINGLE_ARMV7M
 336         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 337         depends on !MMU
 338         select ARCH_WANT_OPTIONAL_GPIOLIB
 339         select ARM_NVIC
 340         select AUTO_ZRELADDR
 341         select CLKSRC_OF
 342         select COMMON_CLK
 343         select CPU_V7M
 344         select GENERIC_CLOCKEVENTS
 345         select NO_IOPORT_MAP
 346         select SPARSE_IRQ
 347         select USE_OF
 348
 349 config ARCH_REALVIEW
 350         bool "ARM Ltd. RealView family"
 351         select ARCH_WANT_OPTIONAL_GPIOLIB
 352         select ARM_AMBA
 353         select ARM_TIMER_SP804
 354         select COMMON_CLK
 355         select COMMON_CLK_VERSATILE
 356         select GENERIC_CLOCKEVENTS
 357         select GPIO_PL061 if GPIOLIB
 358         select ICST
 359         select NEED_MACH_MEMORY_H
 360         select PLAT_VERSATILE
 361         select PLAT_VERSATILE_SCHED_CLOCK
 362         help
 363           This enables support for ARM Ltd RealView boards.
 364
 365 config ARCH_VERSATILE
 366         bool "ARM Ltd. Versatile family"
 367         select ARCH_WANT_OPTIONAL_GPIOLIB
 368         select ARM_AMBA
 369         select ARM_TIMER_SP804
 370         select ARM_VIC
 371         select CLKSRC_VERSATILE
 372         select COMMON_CLK
 373         select COMMON_CLK_VERSATILE
 374         select CPU_ARM926T
 375         select GENERIC_CLOCKEVENTS
 376         select ICST
 377         select PLAT_VERSATILE
 378         select MIGHT_HAVE_PCI
 379         select SPARSE_IRQ
 380         select USE_OF
 381         select VERSATILE_FPGA_IRQ
 382         help
 383           This enables support for ARM Ltd Versatile board.
 384
 385 config ARCH_CLPS711X
 386         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select AUTO_ZRELADDR
 389         select CLKSRC_MMIO
 390         select COMMON_CLK
 391         select CPU_ARM720T
 392         select GENERIC_CLOCKEVENTS
 393         select MFD_SYSCON
 394         select SOC_BUS
 395         help
 396           Support for Cirrus Logic 711x/721x/731x based boards.
 397
 398 config ARCH_GEMINI
 399         bool "Cortina Systems Gemini"
 400         select ARCH_REQUIRE_GPIOLIB
 401         select CLKSRC_MMIO
 402         select CPU_FA526
 403         select GENERIC_CLOCKEVENTS
 404         help
 405           Support for the Cortina Systems Gemini family SoCs
 406
 407 config ARCH_EBSA110
 408         bool "EBSA-110"
 409         select ARCH_USES_GETTIMEOFFSET
 410         select CPU_SA110
 411         select ISA
 412         select NEED_MACH_IO_H
 413         select NEED_MACH_MEMORY_H
 414         select NO_IOPORT_MAP
 415         help
 416           This is an evaluation board for the StrongARM processor available
 417           from Digital. It has limited hardware on-board, including an
 418           Ethernet interface, two PCMCIA sockets, two serial ports and a
 419           parallel port.
 420
 421 config ARCH_EP93XX
 422         bool "EP93xx-based"
 423         select ARCH_HAS_HOLES_MEMORYMODEL
 424         select ARCH_REQUIRE_GPIOLIB
 425         select ARM_AMBA
 426         select ARM_PATCH_PHYS_VIRT
 427         select ARM_VIC
 428         select AUTO_ZRELADDR
 429         select CLKDEV_LOOKUP
 430         select CLKSRC_MMIO
 431         select CPU_ARM920T
 432         select GENERIC_CLOCKEVENTS
 433         help
 434           This enables support for the Cirrus EP93xx series of CPUs.
 435
 436 config ARCH_FOOTBRIDGE
 437         bool "FootBridge"
 438         select CPU_SA110
 439         select FOOTBRIDGE
 440         select GENERIC_CLOCKEVENTS
 441         select HAVE_IDE
 442         select NEED_MACH_IO_H if !MMU
 443         select NEED_MACH_MEMORY_H
 444         help
 445           Support for systems based on the DC21285 companion chip
 446           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 447
 448 config ARCH_NETX
 449         bool "Hilscher NetX based"
 450         select ARM_VIC
 451         select CLKSRC_MMIO
 452         select CPU_ARM926T
 453         select GENERIC_CLOCKEVENTS
 454         help
 455           This enables support for systems based on the Hilscher NetX Soc
 456
 457 config ARCH_IOP13XX
 458         bool "IOP13xx-based"
 459         depends on MMU
 460         select CPU_XSC3
 461         select NEED_MACH_MEMORY_H
 462         select NEED_RET_TO_USER
 463         select PCI
 464         select PLAT_IOP
 465         select VMSPLIT_1G
 466         select SPARSE_IRQ
 467         help
 468           Support for Intel's IOP13XX (XScale) family of processors.
 469
 470 config ARCH_IOP32X
 471         bool "IOP32x-based"
 472         depends on MMU
 473         select ARCH_REQUIRE_GPIOLIB
 474         select CPU_XSCALE
 475         select GPIO_IOP
 476         select NEED_RET_TO_USER
 477         select PCI
 478         select PLAT_IOP
 479         help
 480           Support for Intel's 80219 and IOP32X (XScale) family of
 481           processors.
 482
 483 config ARCH_IOP33X
 484         bool "IOP33x-based"
 485         depends on MMU
 486         select ARCH_REQUIRE_GPIOLIB
 487         select CPU_XSCALE
 488         select GPIO_IOP
 489         select NEED_RET_TO_USER
 490         select PCI
 491         select PLAT_IOP
 492         help
 493           Support for Intel's IOP33X (XScale) family of processors.
 494
 495 config ARCH_IXP4XX
 496         bool "IXP4xx-based"
 497         depends on MMU
 498         select ARCH_HAS_DMA_SET_COHERENT_MASK
 499         select ARCH_REQUIRE_GPIOLIB
 500         select ARCH_SUPPORTS_BIG_ENDIAN
 501         select CLKSRC_MMIO
 502         select CPU_XSCALE
 503         select DMABOUNCE if PCI
 504         select GENERIC_CLOCKEVENTS
 505         select MIGHT_HAVE_PCI
 506         select NEED_MACH_IO_H
 507         select USB_EHCI_BIG_ENDIAN_DESC
 508         select USB_EHCI_BIG_ENDIAN_MMIO
 509         help
 510           Support for Intel's IXP4XX (XScale) family of processors.
 511
 512 config ARCH_DOVE
 513         bool "Marvell Dove"
 514         select ARCH_REQUIRE_GPIOLIB
 515         select CPU_PJ4
 516         select GENERIC_CLOCKEVENTS
 517         select MIGHT_HAVE_PCI
 518         select MVEBU_MBUS
 519         select PINCTRL
 520         select PINCTRL_DOVE
 521         select PLAT_ORION_LEGACY
 522         help
 523           Support for the Marvell Dove SoC 88AP510
 524
 525 config ARCH_MV78XX0
 526         bool "Marvell MV78xx0"
 527         select ARCH_REQUIRE_GPIOLIB
 528         select CPU_FEROCEON
 529         select GENERIC_CLOCKEVENTS
 530         select MVEBU_MBUS
 531         select PCI
 532         select PLAT_ORION_LEGACY
 533         help
 534           Support for the following Marvell MV78xx0 series SoCs:
 535           MV781x0, MV782x0.
 536
 537 config ARCH_ORION5X
 538         bool "Marvell Orion"
 539         depends on MMU
 540         select ARCH_REQUIRE_GPIOLIB
 541         select CPU_FEROCEON
 542         select GENERIC_CLOCKEVENTS
 543         select MVEBU_MBUS
 544         select PCI
 545         select PLAT_ORION_LEGACY
 546         select MULTI_IRQ_HANDLER
 547         help
 548           Support for the following Marvell Orion 5x series SoCs:
 549           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 550           Orion-2 (5281), Orion-1-90 (6183).
 551
 552 config ARCH_MMP
 553         bool "Marvell PXA168/910/MMP2"
 554         depends on MMU
 555         select ARCH_REQUIRE_GPIOLIB
 556         select CLKDEV_LOOKUP
 557         select GENERIC_ALLOCATOR
 558         select GENERIC_CLOCKEVENTS
 559         select GPIO_PXA
 560         select IRQ_DOMAIN
 561         select MULTI_IRQ_HANDLER
 562         select PINCTRL
 563         select PLAT_PXA
 564         select SPARSE_IRQ
 565         help
 566           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 567
 568 config ARCH_KS8695
 569         bool "Micrel/Kendin KS8695"
 570         select ARCH_REQUIRE_GPIOLIB
 571         select CLKSRC_MMIO
 572         select CPU_ARM922T
 573         select GENERIC_CLOCKEVENTS
 574         select NEED_MACH_MEMORY_H
 575         help
 576           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 577           System-on-Chip devices.
 578
 579 config ARCH_W90X900
 580         bool "Nuvoton W90X900 CPU"
 581         select ARCH_REQUIRE_GPIOLIB
 582         select CLKDEV_LOOKUP
 583         select CLKSRC_MMIO
 584         select CPU_ARM926T
 585         select GENERIC_CLOCKEVENTS
 586         help
 587           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 588           At present, the w90x900 has been renamed nuc900, regarding
 589           the ARM series product line, you can login the following
 590           link address to know more.
 591
 592           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 593                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 594
 595 config ARCH_LPC32XX
 596         bool "NXP LPC32XX"
 597         select ARCH_REQUIRE_GPIOLIB
 598         select ARM_AMBA
 599         select CLKDEV_LOOKUP
 600         select CLKSRC_MMIO
 601         select CPU_ARM926T
 602         select GENERIC_CLOCKEVENTS
 603         select HAVE_IDE
 604         select USE_OF
 605         help
 606           Support for the NXP LPC32XX family of processors
 607
 608 config ARCH_PXA
 609         bool "PXA2xx/PXA3xx-based"
 610         depends on MMU
 611         select ARCH_MTD_XIP
 612         select ARCH_REQUIRE_GPIOLIB
 613         select ARM_CPU_SUSPEND if PM
 614         select AUTO_ZRELADDR
 615         select COMMON_CLK
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select IRQ_DOMAIN
 623         select MULTI_IRQ_HANDLER
 624         select PLAT_PXA
 625         select SPARSE_IRQ
 626         help
 627           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 628
 629 config ARCH_RPC
 630         bool "RiscPC"
 631         depends on MMU
 632         select ARCH_ACORN
 633         select ARCH_MAY_HAVE_PC_FDC
 634         select ARCH_SPARSEMEM_ENABLE
 635         select ARCH_USES_GETTIMEOFFSET
 636         select CPU_SA110
 637         select FIQ
 638         select HAVE_IDE
 639         select HAVE_PATA_PLATFORM
 640         select ISA_DMA_API
 641         select NEED_MACH_IO_H
 642         select NEED_MACH_MEMORY_H
 643         select NO_IOPORT_MAP
 644         select VIRT_TO_BUS
 645         help
 646           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 647           CD-ROM interface, serial and parallel port, and the floppy drive.
 648
 649 config ARCH_SA1100
 650         bool "SA1100-based"
 651         select ARCH_MTD_XIP
 652         select ARCH_REQUIRE_GPIOLIB
 653         select ARCH_SPARSEMEM_ENABLE
 654         select CLKDEV_LOOKUP
 655         select CLKSRC_MMIO
 656         select CPU_FREQ
 657         select CPU_SA1100
 658         select GENERIC_CLOCKEVENTS
 659         select HAVE_IDE
 660         select IRQ_DOMAIN
 661         select ISA
 662         select MULTI_IRQ_HANDLER
 663         select NEED_MACH_MEMORY_H
 664         select SPARSE_IRQ
 665         help
 666           Support for StrongARM 11x0 based boards.
 667
 668 config ARCH_S3C24XX
 669         bool "Samsung S3C24XX SoCs"
 670         select ARCH_REQUIRE_GPIOLIB
 671         select ATAGS
 672         select CLKDEV_LOOKUP
 673         select CLKSRC_SAMSUNG_PWM
 674         select GENERIC_CLOCKEVENTS
 675         select GPIO_SAMSUNG
 676         select HAVE_S3C2410_I2C if I2C
 677         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 678         select HAVE_S3C_RTC if RTC_CLASS
 679         select MULTI_IRQ_HANDLER
 680         select NEED_MACH_IO_H
 681         select SAMSUNG_ATAGS
 682         help
 683           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 684           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 685           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 686           Samsung SMDK2410 development board (and derivatives).
 687
 688 config ARCH_S3C64XX
 689         bool "Samsung S3C64XX"
 690         select ARCH_REQUIRE_GPIOLIB
 691         select ARM_AMBA
 692         select ARM_VIC
 693         select ATAGS
 694         select CLKDEV_LOOKUP
 695         select CLKSRC_SAMSUNG_PWM
 696         select COMMON_CLK_SAMSUNG
 697         select CPU_V6K
 698         select GENERIC_CLOCKEVENTS
 699         select GPIO_SAMSUNG
 700         select HAVE_S3C2410_I2C if I2C
 701         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 702         select HAVE_TCM
 703         select NO_IOPORT_MAP
 704         select PLAT_SAMSUNG
 705         select PM_GENERIC_DOMAINS if PM
 706         select S3C_DEV_NAND
 707         select S3C_GPIO_TRACK
 708         select SAMSUNG_ATAGS
 709         select SAMSUNG_WAKEMASK
 710         select SAMSUNG_WDT_RESET
 711         help
 712           Samsung S3C64XX series based systems
 713
 714 config ARCH_DAVINCI
 715         bool "TI DaVinci"
 716         select ARCH_HAS_HOLES_MEMORYMODEL
 717         select ARCH_REQUIRE_GPIOLIB
 718         select CLKDEV_LOOKUP
 719         select GENERIC_ALLOCATOR
 720         select GENERIC_CLOCKEVENTS
 721         select GENERIC_IRQ_CHIP
 722         select HAVE_IDE
 723         select USE_OF
 724         select ZONE_DMA
 725         help
 726           Support for TI's DaVinci platform.
 727
 728 config ARCH_OMAP1
 729         bool "TI OMAP1"
 730         depends on MMU
 731         select ARCH_HAS_HOLES_MEMORYMODEL
 732         select ARCH_OMAP
 733         select ARCH_REQUIRE_GPIOLIB
 734         select CLKDEV_LOOKUP
 735         select CLKSRC_MMIO
 736         select GENERIC_CLOCKEVENTS
 737         select GENERIC_IRQ_CHIP
 738         select HAVE_IDE
 739         select IRQ_DOMAIN
 740         select MULTI_IRQ_HANDLER
 741         select NEED_MACH_IO_H if PCCARD
 742         select NEED_MACH_MEMORY_H
 743         select SPARSE_IRQ
 744         help
 745           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 746
 747 endchoice
 748
 749 menu "Multiple platform selection"
 750         depends on ARCH_MULTIPLATFORM
 751
 752 comment "CPU Core family selection"
 753
 754 config ARCH_MULTI_V4
 755         bool "ARMv4 based platforms (FA526)"
 756         depends on !ARCH_MULTI_V6_V7
 757         select ARCH_MULTI_V4_V5
 758         select CPU_FA526
 759
 760 config ARCH_MULTI_V4T
 761         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 762         depends on !ARCH_MULTI_V6_V7
 763         select ARCH_MULTI_V4_V5
 764         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 765                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 766                 CPU_ARM925T || CPU_ARM940T)
 767
 768 config ARCH_MULTI_V5
 769         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 770         depends on !ARCH_MULTI_V6_V7
 771         select ARCH_MULTI_V4_V5
 772         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 773                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 774                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 775
 776 config ARCH_MULTI_V4_V5
 777         bool
 778
 779 config ARCH_MULTI_V6
 780         bool "ARMv6 based platforms (ARM11)"
 781         select ARCH_MULTI_V6_V7
 782         select CPU_V6K
 783
 784 config ARCH_MULTI_V7
 785         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 786         default y
 787         select ARCH_MULTI_V6_V7
 788         select CPU_V7
 789         select HAVE_SMP
 790
 791 config ARCH_MULTI_V6_V7
 792         bool
 793         select MIGHT_HAVE_CACHE_L2X0
 794
 795 config ARCH_MULTI_CPU_AUTO
 796         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 797         select ARCH_MULTI_V5
 798
 799 endmenu
 800
 801 config ARCH_VIRT
 802         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 803         select ARM_AMBA
 804         select ARM_GIC
 805         select ARM_GIC_V3
 806         select ARM_PSCI
 807         select HAVE_ARM_ARCH_TIMER
 808
 809 #
 810 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 811 # Kconfigs may be included either alphabetically (according to the
 812 # plat- suffix) or along side the corresponding mach-* source.
 813 #
 814 source "arch/arm/mach-mvebu/Kconfig"
 815
 816 source "arch/arm/mach-alpine/Kconfig"
 817
 818 source "arch/arm/mach-asm9260/Kconfig"
 819
 820 source "arch/arm/mach-at91/Kconfig"
 821
 822 source "arch/arm/mach-axxia/Kconfig"
 823
 824 source "arch/arm/mach-bcm/Kconfig"
 825
 826 source "arch/arm/mach-berlin/Kconfig"
 827
 828 source "arch/arm/mach-clps711x/Kconfig"
 829
 830 source "arch/arm/mach-cns3xxx/Kconfig"
 831
 832 source "arch/arm/mach-davinci/Kconfig"
 833
 834 source "arch/arm/mach-digicolor/Kconfig"
 835
 836 source "arch/arm/mach-dove/Kconfig"
 837
 838 source "arch/arm/mach-ep93xx/Kconfig"
 839
 840 source "arch/arm/mach-footbridge/Kconfig"
 841
 842 source "arch/arm/mach-gemini/Kconfig"
 843
 844 source "arch/arm/mach-highbank/Kconfig"
 845
 846 source "arch/arm/mach-hisi/Kconfig"
 847
 848 source "arch/arm/mach-integrator/Kconfig"
 849
 850 source "arch/arm/mach-iop32x/Kconfig"
 851
 852 source "arch/arm/mach-iop33x/Kconfig"
 853
 854 source "arch/arm/mach-iop13xx/Kconfig"
 855
 856 source "arch/arm/mach-ixp4xx/Kconfig"
 857
 858 source "arch/arm/mach-keystone/Kconfig"
 859
 860 source "arch/arm/mach-ks8695/Kconfig"
 861
 862 source "arch/arm/mach-meson/Kconfig"
 863
 864 source "arch/arm/mach-moxart/Kconfig"
 865
 866 source "arch/arm/mach-mv78xx0/Kconfig"
 867
 868 source "arch/arm/mach-imx/Kconfig"
 869
 870 source "arch/arm/mach-mediatek/Kconfig"
 871
 872 source "arch/arm/mach-mxs/Kconfig"
 873
 874 source "arch/arm/mach-netx/Kconfig"
 875
 876 source "arch/arm/mach-nomadik/Kconfig"
 877
 878 source "arch/arm/mach-nspire/Kconfig"
 879
 880 source "arch/arm/plat-omap/Kconfig"
 881
 882 source "arch/arm/mach-omap1/Kconfig"
 883
 884 source "arch/arm/mach-omap2/Kconfig"
 885
 886 source "arch/arm/mach-orion5x/Kconfig"
 887
 888 source "arch/arm/mach-picoxcell/Kconfig"
 889
 890 source "arch/arm/mach-pxa/Kconfig"
 891 source "arch/arm/plat-pxa/Kconfig"
 892
 893 source "arch/arm/mach-mmp/Kconfig"
 894
 895 source "arch/arm/mach-qcom/Kconfig"
 896
 897 source "arch/arm/mach-realview/Kconfig"
 898
 899 source "arch/arm/mach-rockchip/Kconfig"
 900
 901 source "arch/arm/mach-sa1100/Kconfig"
 902
 903 source "arch/arm/mach-socfpga/Kconfig"
 904
 905 source "arch/arm/mach-spear/Kconfig"
 906
 907 source "arch/arm/mach-sti/Kconfig"
 908
 909 source "arch/arm/mach-s3c24xx/Kconfig"
 910
 911 source "arch/arm/mach-s3c64xx/Kconfig"
 912
 913 source "arch/arm/mach-s5pv210/Kconfig"
 914
 915 source "arch/arm/mach-exynos/Kconfig"
 916 source "arch/arm/plat-samsung/Kconfig"
 917
 918 source "arch/arm/mach-shmobile/Kconfig"
 919
 920 source "arch/arm/mach-sunxi/Kconfig"
 921
 922 source "arch/arm/mach-prima2/Kconfig"
 923
 924 source "arch/arm/mach-tegra/Kconfig"
 925
 926 source "arch/arm/mach-u300/Kconfig"
 927
 928 source "arch/arm/mach-uniphier/Kconfig"
 929
 930 source "arch/arm/mach-ux500/Kconfig"
 931
 932 source "arch/arm/mach-vexpress/Kconfig"
 933 source "arch/arm/plat-versatile/Kconfig"
 934
 935 source "arch/arm/mach-vt8500/Kconfig"
 936
 937 source "arch/arm/mach-w90x900/Kconfig"
 938
 939 source "arch/arm/mach-zx/Kconfig"
 940
 941 source "arch/arm/mach-zynq/Kconfig"
 942
 943 # ARMv7-M architecture
 944 config ARCH_EFM32
 945         bool "Energy Micro efm32"
 946         depends on ARM_SINGLE_ARMV7M
 947         select ARCH_REQUIRE_GPIOLIB
 948         help
 949           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 950           processors.
 951
 952 config ARCH_LPC18XX
 953         bool "NXP LPC18xx/LPC43xx"
 954         depends on ARM_SINGLE_ARMV7M
 955         select ARCH_HAS_RESET_CONTROLLER
 956         select ARM_AMBA
 957         select CLKSRC_LPC32XX
 958         select PINCTRL
 959         help
 960           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 961           high performance microcontrollers.
 962
 963 config ARCH_STM32
 964         bool "STMicrolectronics STM32"
 965         depends on ARM_SINGLE_ARMV7M
 966         select ARCH_HAS_RESET_CONTROLLER
 967         select ARMV7M_SYSTICK
 968         select CLKSRC_STM32
 969         select RESET_CONTROLLER
 970         help
 971           Support for STMicroelectronics STM32 processors.
 972
 973 # Definitions to make life easier
 974 config ARCH_ACORN
 975         bool
 976
 977 config PLAT_IOP
 978         bool
 979         select GENERIC_CLOCKEVENTS
 980
 981 config PLAT_ORION
 982         bool
 983         select CLKSRC_MMIO
 984         select COMMON_CLK
 985         select GENERIC_IRQ_CHIP
 986         select IRQ_DOMAIN
 987
 988 config PLAT_ORION_LEGACY
 989         bool
 990         select PLAT_ORION
 991
 992 config PLAT_PXA
 993         bool
 994
 995 config PLAT_VERSATILE
 996         bool
 997
 998 source "arch/arm/firmware/Kconfig"
 999
1000 source arch/arm/mm/Kconfig
1001
1002 config IWMMXT
1003         bool "Enable iWMMXt support"
1004         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1005         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1006         help
1007           Enable support for iWMMXt context switching at run time if
1008           running on a CPU that supports it.
1009
1010 config MULTI_IRQ_HANDLER
1011         bool
1012         help
1013           Allow each machine to specify it's own IRQ handler at run time.
1014
1015 if !MMU
1016 source "arch/arm/Kconfig-nommu"
1017 endif
1018
1019 config PJ4B_ERRATA_4742
1020         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1021         depends on CPU_PJ4B && MACH_ARMADA_370
1022         default y
1023         help
1024           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1025           Event (WFE) IDLE states, a specific timing sensitivity exists between
1026           the retiring WFI/WFE instructions and the newly issued subsequent
1027           instructions.  This sensitivity can result in a CPU hang scenario.
1028           Workaround:
1029           The software must insert either a Data Synchronization Barrier (DSB)
1030           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1031           instruction
1032
1033 config ARM_ERRATA_326103
1034         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1035         depends on CPU_V6
1036         help
1037           Executing a SWP instruction to read-only memory does not set bit 11
1038           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1039           treat the access as a read, preventing a COW from occurring and
1040           causing the faulting task to livelock.
1041
1042 config ARM_ERRATA_411920
1043         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1044         depends on CPU_V6 || CPU_V6K
1045         help
1046           Invalidation of the Instruction Cache operation can
1047           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1048           It does not affect the MPCore. This option enables the ARM Ltd.
1049           recommended workaround.
1050
1051 config ARM_ERRATA_430973
1052         bool "ARM errata: Stale prediction on replaced interworking branch"
1053         depends on CPU_V7
1054         help
1055           This option enables the workaround for the 430973 Cortex-A8
1056           r1p* erratum. If a code sequence containing an ARM/Thumb
1057           interworking branch is replaced with another code sequence at the
1058           same virtual address, whether due to self-modifying code or virtual
1059           to physical address re-mapping, Cortex-A8 does not recover from the
1060           stale interworking branch prediction. This results in Cortex-A8
1061           executing the new code sequence in the incorrect ARM or Thumb state.
1062           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1063           and also flushes the branch target cache at every context switch.
1064           Note that setting specific bits in the ACTLR register may not be
1065           available in non-secure mode.
1066
1067 config ARM_ERRATA_458693
1068         bool "ARM errata: Processor deadlock when a false hazard is created"
1069         depends on CPU_V7
1070         depends on !ARCH_MULTIPLATFORM
1071         help
1072           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1073           erratum. For very specific sequences of memory operations, it is
1074           possible for a hazard condition intended for a cache line to instead
1075           be incorrectly associated with a different cache line. This false
1076           hazard might then cause a processor deadlock. The workaround enables
1077           the L1 caching of the NEON accesses and disables the PLD instruction
1078           in the ACTLR register. Note that setting specific bits in the ACTLR
1079           register may not be available in non-secure mode.
1080
1081 config ARM_ERRATA_460075
1082         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1083         depends on CPU_V7
1084         depends on !ARCH_MULTIPLATFORM
1085         help
1086           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1087           erratum. Any asynchronous access to the L2 cache may encounter a
1088           situation in which recent store transactions to the L2 cache are lost
1089           and overwritten with stale memory contents from external memory. The
1090           workaround disables the write-allocate mode for the L2 cache via the
1091           ACTLR register. Note that setting specific bits in the ACTLR register
1092           may not be available in non-secure mode.
1093
1094 config ARM_ERRATA_742230
1095         bool "ARM errata: DMB operation may be faulty"
1096         depends on CPU_V7 && SMP
1097         depends on !ARCH_MULTIPLATFORM
1098         help
1099           This option enables the workaround for the 742230 Cortex-A9
1100           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1101           between two write operations may not ensure the correct visibility
1102           ordering of the two writes. This workaround sets a specific bit in
1103           the diagnostic register of the Cortex-A9 which causes the DMB
1104           instruction to behave as a DSB, ensuring the correct behaviour of
1105           the two writes.
1106
1107 config ARM_ERRATA_742231
1108         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1109         depends on CPU_V7 && SMP
1110         depends on !ARCH_MULTIPLATFORM
1111         help
1112           This option enables the workaround for the 742231 Cortex-A9
1113           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1114           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1115           accessing some data located in the same cache line, may get corrupted
1116           data due to bad handling of the address hazard when the line gets
1117           replaced from one of the CPUs at the same time as another CPU is
1118           accessing it. This workaround sets specific bits in the diagnostic
1119           register of the Cortex-A9 which reduces the linefill issuing
1120           capabilities of the processor.
1121
1122 config ARM_ERRATA_643719
1123         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1124         depends on CPU_V7 && SMP
1125         default y
1126         help
1127           This option enables the workaround for the 643719 Cortex-A9 (prior to
1128           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1129           register returns zero when it should return one. The workaround
1130           corrects this value, ensuring cache maintenance operations which use
1131           it behave as intended and avoiding data corruption.
1132
1133 config ARM_ERRATA_720789
1134         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1135         depends on CPU_V7
1136         help
1137           This option enables the workaround for the 720789 Cortex-A9 (prior to
1138           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1139           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1140           As a consequence of this erratum, some TLB entries which should be
1141           invalidated are not, resulting in an incoherency in the system page
1142           tables. The workaround changes the TLB flushing routines to invalidate
1143           entries regardless of the ASID.
1144
1145 config ARM_ERRATA_743622
1146         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1147         depends on CPU_V7
1148         depends on !ARCH_MULTIPLATFORM
1149         help
1150           This option enables the workaround for the 743622 Cortex-A9
1151           (r2p*) erratum. Under very rare conditions, a faulty
1152           optimisation in the Cortex-A9 Store Buffer may lead to data
1153           corruption. This workaround sets a specific bit in the diagnostic
1154           register of the Cortex-A9 which disables the Store Buffer
1155           optimisation, preventing the defect from occurring. This has no
1156           visible impact on the overall performance or power consumption of the
1157           processor.
1158
1159 config ARM_ERRATA_751472
1160         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1161         depends on CPU_V7
1162         depends on !ARCH_MULTIPLATFORM
1163         help
1164           This option enables the workaround for the 751472 Cortex-A9 (prior
1165           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1166           completion of a following broadcasted operation if the second
1167           operation is received by a CPU before the ICIALLUIS has completed,
1168           potentially leading to corrupted entries in the cache or TLB.
1169
1170 config ARM_ERRATA_754322
1171         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1172         depends on CPU_V7
1173         help
1174           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1175           r3p*) erratum. A speculative memory access may cause a page table walk
1176           which starts prior to an ASID switch but completes afterwards. This
1177           can populate the micro-TLB with a stale entry which may be hit with
1178           the new ASID. This workaround places two dsb instructions in the mm
1179           switching code so that no page table walks can cross the ASID switch.
1180
1181 config ARM_ERRATA_754327
1182         bool "ARM errata: no automatic Store Buffer drain"
1183         depends on CPU_V7 && SMP
1184         help
1185           This option enables the workaround for the 754327 Cortex-A9 (prior to
1186           r2p0) erratum. The Store Buffer does not have any automatic draining
1187           mechanism and therefore a livelock may occur if an external agent
1188           continuously polls a memory location waiting to observe an update.
1189           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1190           written polling loops from denying visibility of updates to memory.
1191
1192 config ARM_ERRATA_364296
1193         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1194         depends on CPU_V6
1195         help
1196           This options enables the workaround for the 364296 ARM1136
1197           r0p2 erratum (possible cache data corruption with
1198           hit-under-miss enabled). It sets the undocumented bit 31 in
1199           the auxiliary control register and the FI bit in the control
1200           register, thus disabling hit-under-miss without putting the
1201           processor into full low interrupt latency mode. ARM11MPCore
1202           is not affected.
1203
1204 config ARM_ERRATA_764369
1205         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1206         depends on CPU_V7 && SMP
1207         help
1208           This option enables the workaround for erratum 764369
1209           affecting Cortex-A9 MPCore with two or more processors (all
1210           current revisions). Under certain timing circumstances, a data
1211           cache line maintenance operation by MVA targeting an Inner
1212           Shareable memory region may fail to proceed up to either the
1213           Point of Coherency or to the Point of Unification of the
1214           system. This workaround adds a DSB instruction before the
1215           relevant cache maintenance functions and sets a specific bit
1216           in the diagnostic control register of the SCU.
1217
1218 config ARM_ERRATA_775420
1219        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1220        depends on CPU_V7
1221        help
1222          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1223          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1224          operation aborts with MMU exception, it might cause the processor
1225          to deadlock. This workaround puts DSB before executing ISB if
1226          an abort may occur on cache maintenance.
1227
1228 config ARM_ERRATA_798181
1229         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1230         depends on CPU_V7 && SMP
1231         help
1232           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1233           adequately shooting down all use of the old entries. This
1234           option enables the Linux kernel workaround for this erratum
1235           which sends an IPI to the CPUs that are running the same ASID
1236           as the one being invalidated.
1237
1238 config ARM_ERRATA_773022
1239         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1240         depends on CPU_V7
1241         help
1242           This option enables the workaround for the 773022 Cortex-A15
1243           (up to r0p4) erratum. In certain rare sequences of code, the
1244           loop buffer may deliver incorrect instructions. This
1245           workaround disables the loop buffer to avoid the erratum.
1246
1247 endmenu
1248
1249 source "arch/arm/common/Kconfig"
1250
1251 menu "Bus support"
1252
1253 config ISA
1254         bool
1255         help
1256           Find out whether you have ISA slots on your motherboard.  ISA is the
1257           name of a bus system, i.e. the way the CPU talks to the other stuff
1258           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1259           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1260           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1261
1262 # Select ISA DMA controller support
1263 config ISA_DMA
1264         bool
1265         select ISA_DMA_API
1266
1267 # Select ISA DMA interface
1268 config ISA_DMA_API
1269         bool
1270
1271 config PCI
1272         bool "PCI support" if MIGHT_HAVE_PCI
1273         help
1274           Find out whether you have a PCI motherboard. PCI is the name of a
1275           bus system, i.e. the way the CPU talks to the other stuff inside
1276           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1277           VESA. If you have PCI, say Y, otherwise N.
1278
1279 config PCI_DOMAINS
1280         bool
1281         depends on PCI
1282
1283 config PCI_DOMAINS_GENERIC
1284         def_bool PCI_DOMAINS
1285
1286 config PCI_NANOENGINE
1287         bool "BSE nanoEngine PCI support"
1288         depends on SA1100_NANOENGINE
1289         help
1290           Enable PCI on the BSE nanoEngine board.
1291
1292 config PCI_SYSCALL
1293         def_bool PCI
1294
1295 config PCI_HOST_ITE8152
1296         bool
1297         depends on PCI && MACH_ARMCORE
1298         default y
1299         select DMABOUNCE
1300
1301 source "drivers/pci/Kconfig"
1302 source "drivers/pci/pcie/Kconfig"
1303
1304 source "drivers/pcmcia/Kconfig"
1305
1306 endmenu
1307
1308 menu "Kernel Features"
1309
1310 config HAVE_SMP
1311         bool
1312         help
1313           This option should be selected by machines which have an SMP-
1314           capable CPU.
1315
1316           The only effect of this option is to make the SMP-related
1317           options available to the user for configuration.
1318
1319 config SMP
1320         bool "Symmetric Multi-Processing"
1321         depends on CPU_V6K || CPU_V7
1322         depends on GENERIC_CLOCKEVENTS
1323         depends on HAVE_SMP
1324         depends on MMU || ARM_MPU
1325         select IRQ_WORK
1326         help
1327           This enables support for systems with more than one CPU. If you have
1328           a system with only one CPU, say N. If you have a system with more
1329           than one CPU, say Y.
1330
1331           If you say N here, the kernel will run on uni- and multiprocessor
1332           machines, but will use only one CPU of a multiprocessor machine. If
1333           you say Y here, the kernel will run on many, but not all,
1334           uniprocessor machines. On a uniprocessor machine, the kernel
1335           will run faster if you say N here.
1336
1337           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1338           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1339           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340
1341           If you don't know what to do here, say N.
1342
1343 config SMP_ON_UP
1344         bool "Allow booting SMP kernel on uniprocessor systems"
1345         depends on SMP && !XIP_KERNEL && MMU
1346         default y
1347         help
1348           SMP kernels contain instructions which fail on non-SMP processors.
1349           Enabling this option allows the kernel to modify itself to make
1350           these instructions safe.  Disabling it allows about 1K of space
1351           savings.
1352
1353           If you don't know what to do here, say Y.
1354
1355 config ARM_CPU_TOPOLOGY
1356         bool "Support cpu topology definition"
1357         depends on SMP && CPU_V7
1358         default y
1359         help
1360           Support ARM cpu topology definition. The MPIDR register defines
1361           affinity between processors which is then used to describe the cpu
1362           topology of an ARM System.
1363
1364 config SCHED_MC
1365         bool "Multi-core scheduler support"
1366         depends on ARM_CPU_TOPOLOGY
1367         help
1368           Multi-core scheduler support improves the CPU scheduler's decision
1369           making when dealing with multi-core CPU chips at a cost of slightly
1370           increased overhead in some places. If unsure say N here.
1371
1372 config SCHED_SMT
1373         bool "SMT scheduler support"
1374         depends on ARM_CPU_TOPOLOGY
1375         help
1376           Improves the CPU scheduler's decision making when dealing with
1377           MultiThreading at a cost of slightly increased overhead in some
1378           places. If unsure say N here.
1379
1380 config HAVE_ARM_SCU
1381         bool
1382         help
1383           This option enables support for the ARM system coherency unit
1384
1385 config HAVE_ARM_ARCH_TIMER
1386         bool "Architected timer support"
1387         depends on CPU_V7
1388         select ARM_ARCH_TIMER
1389         select GENERIC_CLOCKEVENTS
1390         help
1391           This option enables support for the ARM architected timer
1392
1393 config HAVE_ARM_TWD
1394         bool
1395         select CLKSRC_OF if OF
1396         help
1397           This options enables support for the ARM timer and watchdog unit
1398
1399 config MCPM
1400         bool "Multi-Cluster Power Management"
1401         depends on CPU_V7 && SMP
1402         help
1403           This option provides the common power management infrastructure
1404           for (multi-)cluster based systems, such as big.LITTLE based
1405           systems.
1406
1407 config MCPM_QUAD_CLUSTER
1408         bool
1409         depends on MCPM
1410         help
1411           To avoid wasting resources unnecessarily, MCPM only supports up
1412           to 2 clusters by default.
1413           Platforms with 3 or 4 clusters that use MCPM must select this
1414           option to allow the additional clusters to be managed.
1415
1416 config BIG_LITTLE
1417         bool "big.LITTLE support (Experimental)"
1418         depends on CPU_V7 && SMP
1419         select MCPM
1420         help
1421           This option enables support selections for the big.LITTLE
1422           system architecture.
1423
1424 config BL_SWITCHER
1425         bool "big.LITTLE switcher support"
1426         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1427         select ARM_CPU_SUSPEND
1428         select CPU_PM
1429         help
1430           The big.LITTLE "switcher" provides the core functionality to
1431           transparently handle transition between a cluster of A15's
1432           and a cluster of A7's in a big.LITTLE system.
1433
1434 config BL_SWITCHER_DUMMY_IF
1435         tristate "Simple big.LITTLE switcher user interface"
1436         depends on BL_SWITCHER && DEBUG_KERNEL
1437         help
1438           This is a simple and dummy char dev interface to control
1439           the big.LITTLE switcher core code.  It is meant for
1440           debugging purposes only.
1441
1442 choice
1443         prompt "Memory split"
1444         depends on MMU
1445         default VMSPLIT_3G
1446         help
1447           Select the desired split between kernel and user memory.
1448
1449           If you are not absolutely sure what you are doing, leave this
1450           option alone!
1451
1452         config VMSPLIT_3G
1453                 bool "3G/1G user/kernel split"
1454         config VMSPLIT_3G_OPT
1455                 bool "3G/1G user/kernel split (for full 1G low memory)"
1456         config VMSPLIT_2G
1457                 bool "2G/2G user/kernel split"
1458         config VMSPLIT_1G
1459                 bool "1G/3G user/kernel split"
1460 endchoice
1461
1462 config PAGE_OFFSET
1463         hex
1464         default PHYS_OFFSET if !MMU
1465         default 0x40000000 if VMSPLIT_1G
1466         default 0x80000000 if VMSPLIT_2G
1467         default 0xB0000000 if VMSPLIT_3G_OPT
1468         default 0xC0000000
1469
1470 config NR_CPUS
1471         int "Maximum number of CPUs (2-32)"
1472         range 2 32
1473         depends on SMP
1474         default "4"
1475
1476 config HOTPLUG_CPU
1477         bool "Support for hot-pluggable CPUs"
1478         depends on SMP
1479         help
1480           Say Y here to experiment with turning CPUs off and on.  CPUs
1481           can be controlled through /sys/devices/system/cpu.
1482
1483 config ARM_PSCI
1484         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1485         depends on CPU_V7
1486         select ARM_PSCI_FW
1487         help
1488           Say Y here if you want Linux to communicate with system firmware
1489           implementing the PSCI specification for CPU-centric power
1490           management operations described in ARM document number ARM DEN
1491           0022A ("Power State Coordination Interface System Software on
1492           ARM processors").
1493
1494 # The GPIO number here must be sorted by descending number. In case of
1495 # a multiplatform kernel, we just want the highest value required by the
1496 # selected platforms.
1497 config ARCH_NR_GPIO
1498         int
1499         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1500                 ARCH_ZYNQ
1501         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1502                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1503         default 416 if ARCH_SUNXI
1504         default 392 if ARCH_U8500
1505         default 352 if ARCH_VT8500
1506         default 288 if ARCH_ROCKCHIP
1507         default 264 if MACH_H4700
1508         default 0
1509         help
1510           Maximum number of GPIOs in the system.
1511
1512           If unsure, leave the default value.
1513
1514 source kernel/Kconfig.preempt
1515
1516 config HZ_FIXED
1517         int
1518         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1519                 ARCH_S5PV210 || ARCH_EXYNOS4
1520         default 128 if SOC_AT91RM9200
1521         default 0
1522
1523 choice
1524         depends on HZ_FIXED = 0
1525         prompt "Timer frequency"
1526
1527 config HZ_100
1528         bool "100 Hz"
1529
1530 config HZ_200
1531         bool "200 Hz"
1532
1533 config HZ_250
1534         bool "250 Hz"
1535
1536 config HZ_300
1537         bool "300 Hz"
1538
1539 config HZ_500
1540         bool "500 Hz"
1541
1542 config HZ_1000
1543         bool "1000 Hz"
1544
1545 endchoice
1546
1547 config HZ
1548         int
1549         default HZ_FIXED if HZ_FIXED != 0
1550         default 100 if HZ_100
1551         default 200 if HZ_200
1552         default 250 if HZ_250
1553         default 300 if HZ_300
1554         default 500 if HZ_500
1555         default 1000
1556
1557 config SCHED_HRTICK
1558         def_bool HIGH_RES_TIMERS
1559
1560 config THUMB2_KERNEL
1561         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1562         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1563         default y if CPU_THUMBONLY
1564         select AEABI
1565         select ARM_ASM_UNIFIED
1566         select ARM_UNWIND
1567         help
1568           By enabling this option, the kernel will be compiled in
1569           Thumb-2 mode. A compiler/assembler that understand the unified
1570           ARM-Thumb syntax is needed.
1571
1572           If unsure, say N.
1573
1574 config THUMB2_AVOID_R_ARM_THM_JUMP11
1575         bool "Work around buggy Thumb-2 short branch relocations in gas"
1576         depends on THUMB2_KERNEL && MODULES
1577         default y
1578         help
1579           Various binutils versions can resolve Thumb-2 branches to
1580           locally-defined, preemptible global symbols as short-range "b.n"
1581           branch instructions.
1582
1583           This is a problem, because there's no guarantee the final
1584           destination of the symbol, or any candidate locations for a
1585           trampoline, are within range of the branch.  For this reason, the
1586           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1587           relocation in modules at all, and it makes little sense to add
1588           support.
1589
1590           The symptom is that the kernel fails with an "unsupported
1591           relocation" error when loading some modules.
1592
1593           Until fixed tools are available, passing
1594           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1595           code which hits this problem, at the cost of a bit of extra runtime
1596           stack usage in some cases.
1597
1598           The problem is described in more detail at:
1599               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1600
1601           Only Thumb-2 kernels are affected.
1602
1603           Unless you are sure your tools don't have this problem, say Y.
1604
1605 config ARM_ASM_UNIFIED
1606         bool
1607
1608 config AEABI
1609         bool "Use the ARM EABI to compile the kernel"
1610         help
1611           This option allows for the kernel to be compiled using the latest
1612           ARM ABI (aka EABI).  This is only useful if you are using a user
1613           space environment that is also compiled with EABI.
1614
1615           Since there are major incompatibilities between the legacy ABI and
1616           EABI, especially with regard to structure member alignment, this
1617           option also changes the kernel syscall calling convention to
1618           disambiguate both ABIs and allow for backward compatibility support
1619           (selected with CONFIG_OABI_COMPAT).
1620
1621           To use this you need GCC version 4.0.0 or later.
1622
1623 config OABI_COMPAT
1624         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1625         depends on AEABI && !THUMB2_KERNEL
1626         help
1627           This option preserves the old syscall interface along with the
1628           new (ARM EABI) one. It also provides a compatibility layer to
1629           intercept syscalls that have structure arguments which layout
1630           in memory differs between the legacy ABI and the new ARM EABI
1631           (only for non "thumb" binaries). This option adds a tiny
1632           overhead to all syscalls and produces a slightly larger kernel.
1633
1634           The seccomp filter system will not be available when this is
1635           selected, since there is no way yet to sensibly distinguish
1636           between calling conventions during filtering.
1637
1638           If you know you'll be using only pure EABI user space then you
1639           can say N here. If this option is not selected and you attempt
1640           to execute a legacy ABI binary then the result will be
1641           UNPREDICTABLE (in fact it can be predicted that it won't work
1642           at all). If in doubt say N.
1643
1644 config ARCH_HAS_HOLES_MEMORYMODEL
1645         bool
1646
1647 config ARCH_SPARSEMEM_ENABLE
1648         bool
1649
1650 config ARCH_SPARSEMEM_DEFAULT
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config ARCH_SELECT_MEMORY_MODEL
1654         def_bool ARCH_SPARSEMEM_ENABLE
1655
1656 config HAVE_ARCH_PFN_VALID
1657         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1658
1659 config HAVE_GENERIC_RCU_GUP
1660         def_bool y
1661         depends on ARM_LPAE
1662
1663 config HIGHMEM
1664         bool "High Memory Support"
1665         depends on MMU
1666         help
1667           The address space of ARM processors is only 4 Gigabytes large
1668           and it has to accommodate user address space, kernel address
1669           space as well as some memory mapped IO. That means that, if you
1670           have a large amount of physical memory and/or IO, not all of the
1671           memory can be "permanently mapped" by the kernel. The physical
1672           memory that is not permanently mapped is called "high memory".
1673
1674           Depending on the selected kernel/user memory split, minimum
1675           vmalloc space and actual amount of RAM, you may not need this
1676           option which should result in a slightly faster kernel.
1677
1678           If unsure, say n.
1679
1680 config HIGHPTE
1681         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1682         depends on HIGHMEM
1683         default y
1684         help
1685           The VM uses one page of physical memory for each page table.
1686           For systems with a lot of processes, this can use a lot of
1687           precious low memory, eventually leading to low memory being
1688           consumed by page tables.  Setting this option will allow
1689           user-space 2nd level page tables to reside in high memory.
1690
1691 config CPU_SW_DOMAIN_PAN
1692         bool "Enable use of CPU domains to implement privileged no-access"
1693         depends on MMU && !ARM_LPAE
1694         default y
1695         help
1696           Increase kernel security by ensuring that normal kernel accesses
1697           are unable to access userspace addresses.  This can help prevent
1698           use-after-free bugs becoming an exploitable privilege escalation
1699           by ensuring that magic values (such as LIST_POISON) will always
1700           fault when dereferenced.
1701
1702           CPUs with low-vector mappings use a best-efforts implementation.
1703           Their lower 1MB needs to remain accessible for the vectors, but
1704           the remainder of userspace will become appropriately inaccessible.
1705
1706 config HW_PERF_EVENTS
1707         def_bool y
1708         depends on ARM_PMU
1709
1710 config SYS_SUPPORTS_HUGETLBFS
1711        def_bool y
1712        depends on ARM_LPAE
1713
1714 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1715        def_bool y
1716        depends on ARM_LPAE
1717
1718 config ARCH_WANT_GENERAL_HUGETLB
1719         def_bool y
1720
1721 config ARM_MODULE_PLTS
1722         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1723         depends on MODULES
1724         help
1725           Allocate PLTs when loading modules so that jumps and calls whose
1726           targets are too far away for their relative offsets to be encoded
1727           in the instructions themselves can be bounced via veneers in the
1728           module's PLT. This allows modules to be allocated in the generic
1729           vmalloc area after the dedicated module memory area has been
1730           exhausted. The modules will use slightly more memory, but after
1731           rounding up to page size, the actual memory footprint is usually
1732           the same.
1733
1734           Say y if you are getting out of memory errors while loading modules
1735
1736 source "mm/Kconfig"
1737
1738 config FORCE_MAX_ZONEORDER
1739         int "Maximum zone order"
1740         default "12" if SOC_AM33XX
1741         default "9" if SA1111 || ARCH_EFM32
1742         default "11"
1743         help
1744           The kernel memory allocator divides physically contiguous memory
1745           blocks into "zones", where each zone is a power of two number of
1746           pages.  This option selects the largest power of two that the kernel
1747           keeps in the memory allocator.  If you need to allocate very large
1748           blocks of physically contiguous memory, then you may need to
1749           increase this value.
1750
1751           This config option is actually maximum order plus one. For example,
1752           a value of 11 means that the largest free memory block is 2^10 pages.
1753
1754 config ALIGNMENT_TRAP
1755         bool
1756         depends on CPU_CP15_MMU
1757         default y if !ARCH_EBSA110
1758         select HAVE_PROC_CPU if PROC_FS
1759         help
1760           ARM processors cannot fetch/store information which is not
1761           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1762           address divisible by 4. On 32-bit ARM processors, these non-aligned
1763           fetch/store instructions will be emulated in software if you say
1764           here, which has a severe performance impact. This is necessary for
1765           correct operation of some network protocols. With an IP-only
1766           configuration it is safe to say N, otherwise say Y.
1767
1768 config UACCESS_WITH_MEMCPY
1769         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1770         depends on MMU
1771         default y if CPU_FEROCEON
1772         help
1773           Implement faster copy_to_user and clear_user methods for CPU
1774           cores where a 8-word STM instruction give significantly higher
1775           memory write throughput than a sequence of individual 32bit stores.
1776
1777           A possible side effect is a slight increase in scheduling latency
1778           between threads sharing the same address space if they invoke
1779           such copy operations with large buffers.
1780
1781           However, if the CPU data cache is using a write-allocate mode,
1782           this option is unlikely to provide any performance gain.
1783
1784 config SECCOMP
1785         bool
1786         prompt "Enable seccomp to safely compute untrusted bytecode"
1787         ---help---
1788           This kernel feature is useful for number crunching applications
1789           that may need to compute untrusted bytecode during their
1790           execution. By using pipes or other transports made available to
1791           the process as file descriptors supporting the read/write
1792           syscalls, it's possible to isolate those applications in
1793           their own address space using seccomp. Once seccomp is
1794           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1795           and the task is only allowed to execute a few safe syscalls
1796           defined by each seccomp mode.
1797
1798 config SWIOTLB
1799         def_bool y
1800
1801 config IOMMU_HELPER
1802         def_bool SWIOTLB
1803
1804 config XEN_DOM0
1805         def_bool y
1806         depends on XEN
1807
1808 config XEN
1809         bool "Xen guest support on ARM"
1810         depends on ARM && AEABI && OF
1811         depends on CPU_V7 && !CPU_V6
1812         depends on !GENERIC_ATOMIC64
1813         depends on MMU
1814         select ARCH_DMA_ADDR_T_64BIT
1815         select ARM_PSCI
1816         select SWIOTLB_XEN
1817         help
1818           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1819
1820 endmenu
1821
1822 menu "Boot options"
1823
1824 config USE_OF
1825         bool "Flattened Device Tree support"
1826         select IRQ_DOMAIN
1827         select OF
1828         help
1829           Include support for flattened device tree machine descriptions.
1830
1831 config ATAGS
1832         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1833         default y
1834         help
1835           This is the traditional way of passing data to the kernel at boot
1836           time. If you are solely relying on the flattened device tree (or
1837           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1838           to remove ATAGS support from your kernel binary.  If unsure,
1839           leave this to y.
1840
1841 config DEPRECATED_PARAM_STRUCT
1842         bool "Provide old way to pass kernel parameters"
1843         depends on ATAGS
1844         help
1845           This was deprecated in 2001 and announced to live on for 5 years.
1846           Some old boot loaders still use this way.
1847
1848 # Compressed boot loader in ROM.  Yes, we really want to ask about
1849 # TEXT and BSS so we preserve their values in the config files.
1850 config ZBOOT_ROM_TEXT
1851         hex "Compressed ROM boot loader base address"
1852         default "0"
1853         help
1854           The physical address at which the ROM-able zImage is to be
1855           placed in the target.  Platforms which normally make use of
1856           ROM-able zImage formats normally set this to a suitable
1857           value in their defconfig file.
1858
1859           If ZBOOT_ROM is not enabled, this has no effect.
1860
1861 config ZBOOT_ROM_BSS
1862         hex "Compressed ROM boot loader BSS address"
1863         default "0"
1864         help
1865           The base address of an area of read/write memory in the target
1866           for the ROM-able zImage which must be available while the
1867           decompressor is running. It must be large enough to hold the
1868           entire decompressed kernel plus an additional 128 KiB.
1869           Platforms which normally make use of ROM-able zImage formats
1870           normally set this to a suitable value in their defconfig file.
1871
1872           If ZBOOT_ROM is not enabled, this has no effect.
1873
1874 config ZBOOT_ROM
1875         bool "Compressed boot loader in ROM/flash"
1876         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1877         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1878         help
1879           Say Y here if you intend to execute your compressed kernel image
1880           (zImage) directly from ROM or flash.  If unsure, say N.
1881
1882 config ARM_APPENDED_DTB
1883         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1884         depends on OF
1885         help
1886           With this option, the boot code will look for a device tree binary
1887           (DTB) appended to zImage
1888           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1889
1890           This is meant as a backward compatibility convenience for those
1891           systems with a bootloader that can't be upgraded to accommodate
1892           the documented boot protocol using a device tree.
1893
1894           Beware that there is very little in terms of protection against
1895           this option being confused by leftover garbage in memory that might
1896           look like a DTB header after a reboot if no actual DTB is appended
1897           to zImage.  Do not leave this option active in a production kernel
1898           if you don't intend to always append a DTB.  Proper passing of the
1899           location into r2 of a bootloader provided DTB is always preferable
1900           to this option.
1901
1902 config ARM_ATAG_DTB_COMPAT
1903         bool "Supplement the appended DTB with traditional ATAG information"
1904         depends on ARM_APPENDED_DTB
1905         help
1906           Some old bootloaders can't be updated to a DTB capable one, yet
1907           they provide ATAGs with memory configuration, the ramdisk address,
1908           the kernel cmdline string, etc.  Such information is dynamically
1909           provided by the bootloader and can't always be stored in a static
1910           DTB.  To allow a device tree enabled kernel to be used with such
1911           bootloaders, this option allows zImage to extract the information
1912           from the ATAG list and store it at run time into the appended DTB.
1913
1914 choice
1915         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1916         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1917
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919         bool "Use bootloader kernel arguments if available"
1920         help
1921           Uses the command-line options passed by the boot loader instead of
1922           the device tree bootargs property. If the boot loader doesn't provide
1923           any, the device tree bootargs property will be used.
1924
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1926         bool "Extend with bootloader kernel arguments"
1927         help
1928           The command-line arguments provided by the boot loader will be
1929           appended to the the device tree bootargs property.
1930
1931 endchoice
1932
1933 config CMDLINE
1934         string "Default kernel command string"
1935         default ""
1936         help
1937           On some architectures (EBSA110 and CATS), there is currently no way
1938           for the boot loader to pass arguments to the kernel. For these
1939           architectures, you should supply some command-line options at build
1940           time by entering them here. As a minimum, you should specify the
1941           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1942
1943 choice
1944         prompt "Kernel command line type" if CMDLINE != ""
1945         default CMDLINE_FROM_BOOTLOADER
1946         depends on ATAGS
1947
1948 config CMDLINE_FROM_BOOTLOADER
1949         bool "Use bootloader kernel arguments if available"
1950         help
1951           Uses the command-line options passed by the boot loader. If
1952           the boot loader doesn't provide any, the default kernel command
1953           string provided in CMDLINE will be used.
1954
1955 config CMDLINE_EXTEND
1956         bool "Extend bootloader kernel arguments"
1957         help
1958           The command-line arguments provided by the boot loader will be
1959           appended to the default kernel command string.
1960
1961 config CMDLINE_FORCE
1962         bool "Always use the default kernel command string"
1963         help
1964           Always use the default kernel command string, even if the boot
1965           loader passes other arguments to the kernel.
1966           This is useful if you cannot or don't want to change the
1967           command-line options your boot loader passes to the kernel.
1968 endchoice
1969
1970 config XIP_KERNEL
1971         bool "Kernel Execute-In-Place from ROM"
1972         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1973         help
1974           Execute-In-Place allows the kernel to run from non-volatile storage
1975           directly addressable by the CPU, such as NOR flash. This saves RAM
1976           space since the text section of the kernel is not loaded from flash
1977           to RAM.  Read-write sections, such as the data section and stack,
1978           are still copied to RAM.  The XIP kernel is not compressed since
1979           it has to run directly from flash, so it will take more space to
1980           store it.  The flash address used to link the kernel object files,
1981           and for storing it, is configuration dependent. Therefore, if you
1982           say Y here, you must know the proper physical address where to
1983           store the kernel image depending on your own flash memory usage.
1984
1985           Also note that the make target becomes "make xipImage" rather than
1986           "make zImage" or "make Image".  The final kernel binary to put in
1987           ROM memory will be arch/arm/boot/xipImage.
1988
1989           If unsure, say N.
1990
1991 config XIP_PHYS_ADDR
1992         hex "XIP Kernel Physical Location"
1993         depends on XIP_KERNEL
1994         default "0x00080000"
1995         help
1996           This is the physical address in your flash memory the kernel will
1997           be linked for and stored to.  This address is dependent on your
1998           own flash usage.
1999
2000 config KEXEC
2001         bool "Kexec system call (EXPERIMENTAL)"
2002         depends on (!SMP || PM_SLEEP_SMP)
2003         depends on !CPU_V7M
2004         select KEXEC_CORE
2005         help
2006           kexec is a system call that implements the ability to shutdown your
2007           current kernel, and to start another kernel.  It is like a reboot
2008           but it is independent of the system firmware.   And like a reboot
2009           you can start any kernel with it, not just Linux.
2010
2011           It is an ongoing process to be certain the hardware in a machine
2012           is properly shutdown, so do not be surprised if this code does not
2013           initially work for you.
2014
2015 config ATAGS_PROC
2016         bool "Export atags in procfs"
2017         depends on ATAGS && KEXEC
2018         default y
2019         help
2020           Should the atags used to boot the kernel be exported in an "atags"
2021           file in procfs. Useful with kexec.
2022
2023 config CRASH_DUMP
2024         bool "Build kdump crash kernel (EXPERIMENTAL)"
2025         help
2026           Generate crash dump after being started by kexec. This should
2027           be normally only set in special crash dump kernels which are
2028           loaded in the main kernel with kexec-tools into a specially
2029           reserved region and then later executed after a crash by
2030           kdump/kexec. The crash dump kernel must be compiled to a
2031           memory address not used by the main kernel
2032
2033           For more details see Documentation/kdump/kdump.txt
2034
2035 config AUTO_ZRELADDR
2036         bool "Auto calculation of the decompressed kernel image address"
2037         help
2038           ZRELADDR is the physical address where the decompressed kernel
2039           image will be placed. If AUTO_ZRELADDR is selected, the address
2040           will be determined at run-time by masking the current IP with
2041           0xf8000000. This assumes the zImage being placed in the first 128MB
2042           from start of memory.
2043
2044 endmenu
2045
2046 menu "CPU Power Management"
2047
2048 source "drivers/cpufreq/Kconfig"
2049
2050 source "drivers/cpuidle/Kconfig"
2051
2052 endmenu
2053
2054 menu "Floating point emulation"
2055
2056 comment "At least one emulation must be selected"
2057
2058 config FPE_NWFPE
2059         bool "NWFPE math emulation"
2060         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2061         ---help---
2062           Say Y to include the NWFPE floating point emulator in the kernel.
2063           This is necessary to run most binaries. Linux does not currently
2064           support floating point hardware so you need to say Y here even if
2065           your machine has an FPA or floating point co-processor podule.
2066
2067           You may say N here if you are going to load the Acorn FPEmulator
2068           early in the bootup.
2069
2070 config FPE_NWFPE_XP
2071         bool "Support extended precision"
2072         depends on FPE_NWFPE
2073         help
2074           Say Y to include 80-bit support in the kernel floating-point
2075           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2076           Note that gcc does not generate 80-bit operations by default,
2077           so in most cases this option only enlarges the size of the
2078           floating point emulator without any good reason.
2079
2080           You almost surely want to say N here.
2081
2082 config FPE_FASTFPE
2083         bool "FastFPE math emulation (EXPERIMENTAL)"
2084         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2085         ---help---
2086           Say Y here to include the FAST floating point emulator in the kernel.
2087           This is an experimental much faster emulator which now also has full
2088           precision for the mantissa.  It does not support any exceptions.
2089           It is very simple, and approximately 3-6 times faster than NWFPE.
2090
2091           It should be sufficient for most programs.  It may be not suitable
2092           for scientific calculations, but you have to check this for yourself.
2093           If you do not feel you need a faster FP emulation you should better
2094           choose NWFPE.
2095
2096 config VFP
2097         bool "VFP-format floating point maths"
2098         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2099         help
2100           Say Y to include VFP support code in the kernel. This is needed
2101           if your hardware includes a VFP unit.
2102
2103           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2104           release notes and additional status information.
2105
2106           Say N if your target does not have VFP hardware.
2107
2108 config VFPv3
2109         bool
2110         depends on VFP
2111         default y if CPU_V7
2112
2113 config NEON
2114         bool "Advanced SIMD (NEON) Extension support"
2115         depends on VFPv3 && CPU_V7
2116         help
2117           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2118           Extension.
2119
2120 config KERNEL_MODE_NEON
2121         bool "Support for NEON in kernel mode"
2122         depends on NEON && AEABI
2123         help
2124           Say Y to include support for NEON in kernel mode.
2125
2126 endmenu
2127
2128 menu "Userspace binary formats"
2129
2130 source "fs/Kconfig.binfmt"
2131
2132 endmenu
2133
2134 menu "Power management options"
2135
2136 source "kernel/power/Kconfig"
2137
2138 config ARCH_SUSPEND_POSSIBLE
2139         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2140                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2141         def_bool y
2142
2143 config ARM_CPU_SUSPEND
2144         def_bool PM_SLEEP
2145
2146 config ARCH_HIBERNATION_POSSIBLE
2147         bool
2148         depends on MMU
2149         default y if ARCH_SUSPEND_POSSIBLE
2150
2151 endmenu
2152
2153 source "net/Kconfig"
2154
2155 source "drivers/Kconfig"
2156
2157 source "drivers/firmware/Kconfig"
2158
2159 source "fs/Kconfig"
2160
2161 source "arch/arm/Kconfig.debug"
2162
2163 source "security/Kconfig"
2164
2165 source "crypto/Kconfig"
2166 if CRYPTO
2167 source "arch/arm/crypto/Kconfig"
2168 endif
2169
2170 source "lib/Kconfig"
2171
2172 source "arch/arm/kvm/Kconfig"