4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_CLOCK
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_IO_H
266 select NEED_MACH_MEMORY_H
268 select MULTI_IRQ_HANDLER
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLOCK
282 select PLAT_VERSATILE_CLCD
283 select ARM_TIMER_SP804
284 select GPIO_PL061 if GPIOLIB
285 select NEED_MACH_MEMORY_H
287 This enables support for ARM Ltd RealView boards.
289 config ARCH_VERSATILE
290 bool "ARM Ltd. Versatile family"
294 select HAVE_MACH_CLKDEV
296 select GENERIC_CLOCKEVENTS
297 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select NEED_MACH_IO_H if PCI
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select PLAT_VERSATILE_FPGA_IRQ
303 select ARM_TIMER_SP804
305 This enables support for ARM Ltd Versatile board.
308 bool "ARM Ltd. Versatile Express family"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_TIMER_SP804
314 select GENERIC_CLOCKEVENTS
316 select HAVE_PATA_PLATFORM
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select REGULATOR_FIXED_VOLTAGE if REGULATOR
323 This enables support for the ARM Ltd Versatile Express boards.
327 select ARCH_REQUIRE_GPIOLIB
331 select NEED_MACH_IO_H if PCCARD
333 This enables support for systems based on Atmel
334 AT91RM9200 and AT91SAM9* processors.
337 bool "Broadcom BCMRING"
341 select ARM_TIMER_SP804
343 select GENERIC_CLOCKEVENTS
344 select ARCH_WANT_OPTIONAL_GPIOLIB
346 Support for Broadcom's BCMRing platform.
349 bool "Calxeda Highbank-based"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
353 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
363 Support for the Calxeda Highbank SoC based boards.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_USES_GETTIMEOFFSET
369 select NEED_MACH_MEMORY_H
371 Support for Cirrus Logic 711x/721x/731x based boards.
374 bool "Cavium Networks CNS3XXX family"
376 select GENERIC_CLOCKEVENTS
378 select MIGHT_HAVE_CACHE_L2X0
379 select MIGHT_HAVE_PCI
380 select PCI_DOMAINS if PCI
382 Support for Cavium Networks CNS3XXX platform.
385 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
390 Support for the Cortina Systems Gemini family SoCs
393 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
396 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFSoC ARM Cortex A9 Platform
412 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_HAS_HOLES_MEMORYMODEL
429 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXC/iMX-based"
448 select GENERIC_CLOCKEVENTS
449 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_IRQ_CHIP
453 select MULTI_IRQ_HANDLER
455 Support for Freescale MXC/iMX-based family of processors
458 bool "Freescale MXS-based"
459 select GENERIC_CLOCKEVENTS
460 select ARCH_REQUIRE_GPIOLIB
464 select HAVE_CLK_PREPARE
468 Support for Freescale MXS-based family of processors
471 bool "Hilscher NetX based"
475 select GENERIC_CLOCKEVENTS
477 This enables support for systems based on the Hilscher NetX Soc
480 bool "Hynix HMS720x-based"
483 select ARCH_USES_GETTIMEOFFSET
485 This enables support for systems based on the Hynix HMS720x
493 select ARCH_SUPPORTS_MSI
495 select NEED_MACH_IO_H
496 select NEED_MACH_MEMORY_H
497 select NEED_RET_TO_USER
499 Support for Intel's IOP13XX (XScale) family of processors.
505 select NEED_MACH_IO_H
506 select NEED_RET_TO_USER
509 select ARCH_REQUIRE_GPIOLIB
511 Support for Intel's 80219 and IOP32X (XScale) family of
518 select NEED_MACH_IO_H
519 select NEED_RET_TO_USER
522 select ARCH_REQUIRE_GPIOLIB
524 Support for Intel's IOP33X (XScale) family of processors.
529 select ARCH_HAS_DMA_SET_COHERENT_MASK
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
535 select NEED_MACH_IO_H
536 select DMABOUNCE if PCI
538 Support for Intel's IXP4XX (XScale) family of processors.
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select NEED_MACH_IO_H
549 Support for the Marvell Dove SoC 88AP510
552 bool "Marvell Kirkwood"
555 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select NEED_MACH_IO_H
560 Support for the following Marvell Kirkwood series SoCs:
561 88F6180, 88F6192 and 88F6281.
567 select ARCH_REQUIRE_GPIOLIB
570 select USB_ARCH_HAS_OHCI
572 select GENERIC_CLOCKEVENTS
576 Support for the NXP LPC32XX family of processors
579 bool "Marvell MV78xx0"
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
584 select NEED_MACH_IO_H
587 Support for the following Marvell MV78xx0 series SoCs:
595 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
597 select NEED_MACH_IO_H
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
614 select GENERIC_ALLOCATOR
616 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
619 bool "Micrel/Kendin KS8695"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARCH_USES_GETTIMEOFFSET
623 select NEED_MACH_MEMORY_H
625 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
626 System-on-Chip devices.
629 bool "Nuvoton W90X900 CPU"
631 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
637 At present, the w90x900 has been renamed nuc900, regarding
638 the ARM series product line, you can login the following
639 link address to know more.
641 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
642 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
648 select GENERIC_CLOCKEVENTS
652 select MIGHT_HAVE_CACHE_L2X0
653 select NEED_MACH_IO_H if PCI
654 select ARCH_HAS_CPUFREQ
656 This enables support for NVIDIA Tegra based systems (Tegra APX,
657 Tegra 6xx and Tegra 2 series).
659 config ARCH_PICOXCELL
660 bool "Picochip picoXcell"
661 select ARCH_REQUIRE_GPIOLIB
662 select ARM_PATCH_PHYS_VIRT
666 select DW_APB_TIMER_OF
667 select GENERIC_CLOCKEVENTS
674 This enables support for systems based on the Picochip picoXcell
675 family of Femtocell devices. The picoxcell support requires device tree
679 bool "Philips Nexperia PNX4008 Mobile"
682 select ARCH_USES_GETTIMEOFFSET
684 This enables support for Philips PNX4008 mobile platform.
687 bool "PXA2xx/PXA3xx-based"
690 select ARCH_HAS_CPUFREQ
693 select ARCH_REQUIRE_GPIOLIB
694 select GENERIC_CLOCKEVENTS
699 select MULTI_IRQ_HANDLER
700 select ARM_CPU_SUSPEND if PM
703 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
708 select GENERIC_CLOCKEVENTS
709 select ARCH_REQUIRE_GPIOLIB
712 Support for Qualcomm MSM/QSD based systems. This runs on the
713 apps processor of the MSM/QSD and depends on a shared memory
714 interface to the modem processor which runs the baseband
715 stack and controls some vital subsystems
716 (clock and power control, etc).
719 bool "Renesas SH-Mobile / R-Mobile"
722 select HAVE_MACH_CLKDEV
724 select GENERIC_CLOCKEVENTS
725 select MIGHT_HAVE_CACHE_L2X0
728 select MULTI_IRQ_HANDLER
729 select PM_GENERIC_DOMAINS if PM
730 select NEED_MACH_MEMORY_H
732 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
738 select ARCH_MAY_HAVE_PC_FDC
739 select HAVE_PATA_PLATFORM
742 select ARCH_SPARSEMEM_ENABLE
743 select ARCH_USES_GETTIMEOFFSET
745 select NEED_MACH_IO_H
746 select NEED_MACH_MEMORY_H
748 On the Acorn Risc-PC, Linux can support the internal IDE disk and
749 CD-ROM interface, serial and parallel port, and the floppy drive.
756 select ARCH_SPARSEMEM_ENABLE
758 select ARCH_HAS_CPUFREQ
760 select GENERIC_CLOCKEVENTS
762 select ARCH_REQUIRE_GPIOLIB
764 select NEED_MACH_MEMORY_H
767 Support for StrongARM 11x0 based boards.
770 bool "Samsung S3C24XX SoCs"
772 select ARCH_HAS_CPUFREQ
775 select ARCH_USES_GETTIMEOFFSET
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C_RTC if RTC_CLASS
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select NEED_MACH_IO_H
781 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
782 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
783 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
784 Samsung SMDK2410 development board (and derivatives).
787 bool "Samsung S3C64XX"
795 select ARCH_USES_GETTIMEOFFSET
796 select ARCH_HAS_CPUFREQ
797 select ARCH_REQUIRE_GPIOLIB
798 select SAMSUNG_CLKSRC
799 select SAMSUNG_IRQ_VIC_TIMER
800 select S3C_GPIO_TRACK
802 select USB_ARCH_HAS_OHCI
803 select SAMSUNG_GPIOLIB_4BIT
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
807 Samsung S3C64XX series based systems
810 bool "Samsung S5P6440 S5P6450"
816 select HAVE_S3C2410_WATCHDOG if WATCHDOG
817 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C_RTC if RTC_CLASS
821 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
825 bool "Samsung S5PC100"
830 select ARCH_USES_GETTIMEOFFSET
831 select HAVE_S3C2410_I2C if I2C
832 select HAVE_S3C_RTC if RTC_CLASS
833 select HAVE_S3C2410_WATCHDOG if WATCHDOG
835 Samsung S5PC100 series based systems
838 bool "Samsung S5PV210/S5PC110"
840 select ARCH_SPARSEMEM_ENABLE
841 select ARCH_HAS_HOLES_MEMORYMODEL
846 select ARCH_HAS_CPUFREQ
847 select GENERIC_CLOCKEVENTS
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
851 select NEED_MACH_MEMORY_H
853 Samsung S5PV210/S5PC110 series based systems
856 bool "SAMSUNG EXYNOS"
858 select ARCH_SPARSEMEM_ENABLE
859 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_HAS_CPUFREQ
864 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C_RTC if RTC_CLASS
866 select HAVE_S3C2410_I2C if I2C
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select NEED_MACH_MEMORY_H
870 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
879 select ARCH_USES_GETTIMEOFFSET
880 select NEED_MACH_MEMORY_H
881 select NEED_MACH_IO_H
883 Support for the StrongARM based Digital DNARD machine, also known
884 as "Shark" (<http://www.shark-linux.de/shark.html>).
887 bool "ST-Ericsson U300 Series"
893 select ARM_PATCH_PHYS_VIRT
895 select GENERIC_CLOCKEVENTS
897 select HAVE_MACH_CLKDEV
899 select ARCH_REQUIRE_GPIOLIB
901 Support for ST-Ericsson U300 series mobile platforms.
904 bool "ST-Ericsson U8500 Series"
908 select GENERIC_CLOCKEVENTS
910 select ARCH_REQUIRE_GPIOLIB
911 select ARCH_HAS_CPUFREQ
913 select MIGHT_HAVE_CACHE_L2X0
915 Support for ST-Ericsson's Ux500 architecture
918 bool "STMicroelectronics Nomadik"
923 select GENERIC_CLOCKEVENTS
925 select MIGHT_HAVE_CACHE_L2X0
926 select ARCH_REQUIRE_GPIOLIB
928 Support for the Nomadik platform by ST-Ericsson
932 select GENERIC_CLOCKEVENTS
933 select ARCH_REQUIRE_GPIOLIB
937 select GENERIC_ALLOCATOR
938 select GENERIC_IRQ_CHIP
939 select ARCH_HAS_HOLES_MEMORYMODEL
941 Support for TI's DaVinci platform.
947 select ARCH_REQUIRE_GPIOLIB
948 select ARCH_HAS_CPUFREQ
950 select GENERIC_CLOCKEVENTS
951 select ARCH_HAS_HOLES_MEMORYMODEL
953 Support for TI's OMAP platform (OMAP1/2/3/4).
958 select ARCH_REQUIRE_GPIOLIB
962 select GENERIC_CLOCKEVENTS
965 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
968 bool "VIA/WonderMedia 85xx"
971 select ARCH_HAS_CPUFREQ
972 select GENERIC_CLOCKEVENTS
973 select ARCH_REQUIRE_GPIOLIB
976 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
979 bool "Xilinx Zynq ARM Cortex A9 Platform"
981 select GENERIC_CLOCKEVENTS
986 select MIGHT_HAVE_CACHE_L2X0
989 Support for Xilinx Zynq ARM Cortex A9 Platform
993 # This is sorted alphabetically by mach-* pathname. However, plat-*
994 # Kconfigs may be included either alphabetically (according to the
995 # plat- suffix) or along side the corresponding mach-* source.
997 source "arch/arm/mach-at91/Kconfig"
999 source "arch/arm/mach-bcmring/Kconfig"
1001 source "arch/arm/mach-clps711x/Kconfig"
1003 source "arch/arm/mach-cns3xxx/Kconfig"
1005 source "arch/arm/mach-davinci/Kconfig"
1007 source "arch/arm/mach-dove/Kconfig"
1009 source "arch/arm/mach-ep93xx/Kconfig"
1011 source "arch/arm/mach-footbridge/Kconfig"
1013 source "arch/arm/mach-gemini/Kconfig"
1015 source "arch/arm/mach-h720x/Kconfig"
1017 source "arch/arm/mach-integrator/Kconfig"
1019 source "arch/arm/mach-iop32x/Kconfig"
1021 source "arch/arm/mach-iop33x/Kconfig"
1023 source "arch/arm/mach-iop13xx/Kconfig"
1025 source "arch/arm/mach-ixp4xx/Kconfig"
1027 source "arch/arm/mach-kirkwood/Kconfig"
1029 source "arch/arm/mach-ks8695/Kconfig"
1031 source "arch/arm/mach-msm/Kconfig"
1033 source "arch/arm/mach-mv78xx0/Kconfig"
1035 source "arch/arm/plat-mxc/Kconfig"
1037 source "arch/arm/mach-mxs/Kconfig"
1039 source "arch/arm/mach-netx/Kconfig"
1041 source "arch/arm/mach-nomadik/Kconfig"
1042 source "arch/arm/plat-nomadik/Kconfig"
1044 source "arch/arm/plat-omap/Kconfig"
1046 source "arch/arm/mach-omap1/Kconfig"
1048 source "arch/arm/mach-omap2/Kconfig"
1050 source "arch/arm/mach-orion5x/Kconfig"
1052 source "arch/arm/mach-pxa/Kconfig"
1053 source "arch/arm/plat-pxa/Kconfig"
1055 source "arch/arm/mach-mmp/Kconfig"
1057 source "arch/arm/mach-realview/Kconfig"
1059 source "arch/arm/mach-sa1100/Kconfig"
1061 source "arch/arm/plat-samsung/Kconfig"
1062 source "arch/arm/plat-s3c24xx/Kconfig"
1064 source "arch/arm/plat-spear/Kconfig"
1066 source "arch/arm/mach-s3c24xx/Kconfig"
1068 source "arch/arm/mach-s3c2412/Kconfig"
1069 source "arch/arm/mach-s3c2440/Kconfig"
1073 source "arch/arm/mach-s3c64xx/Kconfig"
1076 source "arch/arm/mach-s5p64x0/Kconfig"
1078 source "arch/arm/mach-s5pc100/Kconfig"
1080 source "arch/arm/mach-s5pv210/Kconfig"
1082 source "arch/arm/mach-exynos/Kconfig"
1084 source "arch/arm/mach-shmobile/Kconfig"
1086 source "arch/arm/mach-tegra/Kconfig"
1088 source "arch/arm/mach-u300/Kconfig"
1090 source "arch/arm/mach-ux500/Kconfig"
1092 source "arch/arm/mach-versatile/Kconfig"
1094 source "arch/arm/mach-vexpress/Kconfig"
1095 source "arch/arm/plat-versatile/Kconfig"
1097 source "arch/arm/mach-vt8500/Kconfig"
1099 source "arch/arm/mach-w90x900/Kconfig"
1101 # Definitions to make life easier
1107 select GENERIC_CLOCKEVENTS
1112 select GENERIC_IRQ_CHIP
1118 config PLAT_VERSATILE
1121 config ARM_TIMER_SP804
1124 select HAVE_SCHED_CLOCK
1126 source arch/arm/mm/Kconfig
1130 default 16 if ARCH_EP93XX
1134 bool "Enable iWMMXt support"
1135 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1136 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1138 Enable support for iWMMXt context switching at run time if
1139 running on a CPU that supports it.
1143 depends on CPU_XSCALE
1147 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1148 (!ARCH_OMAP3 || OMAP3_EMU)
1152 config MULTI_IRQ_HANDLER
1155 Allow each machine to specify it's own IRQ handler at run time.
1158 source "arch/arm/Kconfig-nommu"
1161 config ARM_ERRATA_326103
1162 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1165 Executing a SWP instruction to read-only memory does not set bit 11
1166 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1167 treat the access as a read, preventing a COW from occurring and
1168 causing the faulting task to livelock.
1170 config ARM_ERRATA_411920
1171 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1172 depends on CPU_V6 || CPU_V6K
1174 Invalidation of the Instruction Cache operation can
1175 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1176 It does not affect the MPCore. This option enables the ARM Ltd.
1177 recommended workaround.
1179 config ARM_ERRATA_430973
1180 bool "ARM errata: Stale prediction on replaced interworking branch"
1183 This option enables the workaround for the 430973 Cortex-A8
1184 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1185 interworking branch is replaced with another code sequence at the
1186 same virtual address, whether due to self-modifying code or virtual
1187 to physical address re-mapping, Cortex-A8 does not recover from the
1188 stale interworking branch prediction. This results in Cortex-A8
1189 executing the new code sequence in the incorrect ARM or Thumb state.
1190 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1191 and also flushes the branch target cache at every context switch.
1192 Note that setting specific bits in the ACTLR register may not be
1193 available in non-secure mode.
1195 config ARM_ERRATA_458693
1196 bool "ARM errata: Processor deadlock when a false hazard is created"
1199 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1200 erratum. For very specific sequences of memory operations, it is
1201 possible for a hazard condition intended for a cache line to instead
1202 be incorrectly associated with a different cache line. This false
1203 hazard might then cause a processor deadlock. The workaround enables
1204 the L1 caching of the NEON accesses and disables the PLD instruction
1205 in the ACTLR register. Note that setting specific bits in the ACTLR
1206 register may not be available in non-secure mode.
1208 config ARM_ERRATA_460075
1209 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1212 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1213 erratum. Any asynchronous access to the L2 cache may encounter a
1214 situation in which recent store transactions to the L2 cache are lost
1215 and overwritten with stale memory contents from external memory. The
1216 workaround disables the write-allocate mode for the L2 cache via the
1217 ACTLR register. Note that setting specific bits in the ACTLR register
1218 may not be available in non-secure mode.
1220 config ARM_ERRATA_742230
1221 bool "ARM errata: DMB operation may be faulty"
1222 depends on CPU_V7 && SMP
1224 This option enables the workaround for the 742230 Cortex-A9
1225 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1226 between two write operations may not ensure the correct visibility
1227 ordering of the two writes. This workaround sets a specific bit in
1228 the diagnostic register of the Cortex-A9 which causes the DMB
1229 instruction to behave as a DSB, ensuring the correct behaviour of
1232 config ARM_ERRATA_742231
1233 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for the 742231 Cortex-A9
1237 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1238 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1239 accessing some data located in the same cache line, may get corrupted
1240 data due to bad handling of the address hazard when the line gets
1241 replaced from one of the CPUs at the same time as another CPU is
1242 accessing it. This workaround sets specific bits in the diagnostic
1243 register of the Cortex-A9 which reduces the linefill issuing
1244 capabilities of the processor.
1246 config PL310_ERRATA_588369
1247 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1248 depends on CACHE_L2X0
1250 The PL310 L2 cache controller implements three types of Clean &
1251 Invalidate maintenance operations: by Physical Address
1252 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1253 They are architecturally defined to behave as the execution of a
1254 clean operation followed immediately by an invalidate operation,
1255 both performing to the same memory location. This functionality
1256 is not correctly implemented in PL310 as clean lines are not
1257 invalidated as a result of these operations.
1259 config ARM_ERRATA_720789
1260 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1263 This option enables the workaround for the 720789 Cortex-A9 (prior to
1264 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1265 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1266 As a consequence of this erratum, some TLB entries which should be
1267 invalidated are not, resulting in an incoherency in the system page
1268 tables. The workaround changes the TLB flushing routines to invalidate
1269 entries regardless of the ASID.
1271 config PL310_ERRATA_727915
1272 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1273 depends on CACHE_L2X0
1275 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1276 operation (offset 0x7FC). This operation runs in background so that
1277 PL310 can handle normal accesses while it is in progress. Under very
1278 rare circumstances, due to this erratum, write data can be lost when
1279 PL310 treats a cacheable write transaction during a Clean &
1280 Invalidate by Way operation.
1282 config ARM_ERRATA_743622
1283 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1286 This option enables the workaround for the 743622 Cortex-A9
1287 (r2p*) erratum. Under very rare conditions, a faulty
1288 optimisation in the Cortex-A9 Store Buffer may lead to data
1289 corruption. This workaround sets a specific bit in the diagnostic
1290 register of the Cortex-A9 which disables the Store Buffer
1291 optimisation, preventing the defect from occurring. This has no
1292 visible impact on the overall performance or power consumption of the
1295 config ARM_ERRATA_751472
1296 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1299 This option enables the workaround for the 751472 Cortex-A9 (prior
1300 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1301 completion of a following broadcasted operation if the second
1302 operation is received by a CPU before the ICIALLUIS has completed,
1303 potentially leading to corrupted entries in the cache or TLB.
1305 config PL310_ERRATA_753970
1306 bool "PL310 errata: cache sync operation may be faulty"
1307 depends on CACHE_PL310
1309 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1311 Under some condition the effect of cache sync operation on
1312 the store buffer still remains when the operation completes.
1313 This means that the store buffer is always asked to drain and
1314 this prevents it from merging any further writes. The workaround
1315 is to replace the normal offset of cache sync operation (0x730)
1316 by another offset targeting an unmapped PL310 register 0x740.
1317 This has the same effect as the cache sync operation: store buffer
1318 drain and waiting for all buffers empty.
1320 config ARM_ERRATA_754322
1321 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1324 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1325 r3p*) erratum. A speculative memory access may cause a page table walk
1326 which starts prior to an ASID switch but completes afterwards. This
1327 can populate the micro-TLB with a stale entry which may be hit with
1328 the new ASID. This workaround places two dsb instructions in the mm
1329 switching code so that no page table walks can cross the ASID switch.
1331 config ARM_ERRATA_754327
1332 bool "ARM errata: no automatic Store Buffer drain"
1333 depends on CPU_V7 && SMP
1335 This option enables the workaround for the 754327 Cortex-A9 (prior to
1336 r2p0) erratum. The Store Buffer does not have any automatic draining
1337 mechanism and therefore a livelock may occur if an external agent
1338 continuously polls a memory location waiting to observe an update.
1339 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1340 written polling loops from denying visibility of updates to memory.
1342 config ARM_ERRATA_364296
1343 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1344 depends on CPU_V6 && !SMP
1346 This options enables the workaround for the 364296 ARM1136
1347 r0p2 erratum (possible cache data corruption with
1348 hit-under-miss enabled). It sets the undocumented bit 31 in
1349 the auxiliary control register and the FI bit in the control
1350 register, thus disabling hit-under-miss without putting the
1351 processor into full low interrupt latency mode. ARM11MPCore
1354 config ARM_ERRATA_764369
1355 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1356 depends on CPU_V7 && SMP
1358 This option enables the workaround for erratum 764369
1359 affecting Cortex-A9 MPCore with two or more processors (all
1360 current revisions). Under certain timing circumstances, a data
1361 cache line maintenance operation by MVA targeting an Inner
1362 Shareable memory region may fail to proceed up to either the
1363 Point of Coherency or to the Point of Unification of the
1364 system. This workaround adds a DSB instruction before the
1365 relevant cache maintenance functions and sets a specific bit
1366 in the diagnostic control register of the SCU.
1368 config PL310_ERRATA_769419
1369 bool "PL310 errata: no automatic Store Buffer drain"
1370 depends on CACHE_L2X0
1372 On revisions of the PL310 prior to r3p2, the Store Buffer does
1373 not automatically drain. This can cause normal, non-cacheable
1374 writes to be retained when the memory system is idle, leading
1375 to suboptimal I/O performance for drivers using coherent DMA.
1376 This option adds a write barrier to the cpu_idle loop so that,
1377 on systems with an outer cache, the store buffer is drained
1382 source "arch/arm/common/Kconfig"
1392 Find out whether you have ISA slots on your motherboard. ISA is the
1393 name of a bus system, i.e. the way the CPU talks to the other stuff
1394 inside your box. Other bus systems are PCI, EISA, MicroChannel
1395 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1396 newer boards don't support it. If you have ISA, say Y, otherwise N.
1398 # Select ISA DMA controller support
1403 # Select ISA DMA interface
1408 bool "PCI support" if MIGHT_HAVE_PCI
1410 Find out whether you have a PCI motherboard. PCI is the name of a
1411 bus system, i.e. the way the CPU talks to the other stuff inside
1412 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1413 VESA. If you have PCI, say Y, otherwise N.
1419 config PCI_NANOENGINE
1420 bool "BSE nanoEngine PCI support"
1421 depends on SA1100_NANOENGINE
1423 Enable PCI on the BSE nanoEngine board.
1428 # Select the host bridge type
1429 config PCI_HOST_VIA82C505
1431 depends on PCI && ARCH_SHARK
1434 config PCI_HOST_ITE8152
1436 depends on PCI && MACH_ARMCORE
1440 source "drivers/pci/Kconfig"
1442 source "drivers/pcmcia/Kconfig"
1446 menu "Kernel Features"
1451 This option should be selected by machines which have an SMP-
1454 The only effect of this option is to make the SMP-related
1455 options available to the user for configuration.
1458 bool "Symmetric Multi-Processing"
1459 depends on CPU_V6K || CPU_V7
1460 depends on GENERIC_CLOCKEVENTS
1463 select USE_GENERIC_SMP_HELPERS
1464 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1466 This enables support for systems with more than one CPU. If you have
1467 a system with only one CPU, like most personal computers, say N. If
1468 you have a system with more than one CPU, say Y.
1470 If you say N here, the kernel will run on single and multiprocessor
1471 machines, but will use only one CPU of a multiprocessor machine. If
1472 you say Y here, the kernel will run on many, but not all, single
1473 processor machines. On a single processor machine, the kernel will
1474 run faster if you say N here.
1476 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1477 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1478 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1480 If you don't know what to do here, say N.
1483 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1484 depends on EXPERIMENTAL
1485 depends on SMP && !XIP_KERNEL
1488 SMP kernels contain instructions which fail on non-SMP processors.
1489 Enabling this option allows the kernel to modify itself to make
1490 these instructions safe. Disabling it allows about 1K of space
1493 If you don't know what to do here, say Y.
1495 config ARM_CPU_TOPOLOGY
1496 bool "Support cpu topology definition"
1497 depends on SMP && CPU_V7
1500 Support ARM cpu topology definition. The MPIDR register defines
1501 affinity between processors which is then used to describe the cpu
1502 topology of an ARM System.
1505 bool "Multi-core scheduler support"
1506 depends on ARM_CPU_TOPOLOGY
1508 Multi-core scheduler support improves the CPU scheduler's decision
1509 making when dealing with multi-core CPU chips at a cost of slightly
1510 increased overhead in some places. If unsure say N here.
1513 bool "SMT scheduler support"
1514 depends on ARM_CPU_TOPOLOGY
1516 Improves the CPU scheduler's decision making when dealing with
1517 MultiThreading at a cost of slightly increased overhead in some
1518 places. If unsure say N here.
1523 This option enables support for the ARM system coherency unit
1525 config ARM_ARCH_TIMER
1526 bool "Architected timer support"
1529 This option enables support for the ARM architected timer
1535 This options enables support for the ARM timer and watchdog unit
1538 prompt "Memory split"
1541 Select the desired split between kernel and user memory.
1543 If you are not absolutely sure what you are doing, leave this
1547 bool "3G/1G user/kernel split"
1549 bool "2G/2G user/kernel split"
1551 bool "1G/3G user/kernel split"
1556 default 0x40000000 if VMSPLIT_1G
1557 default 0x80000000 if VMSPLIT_2G
1561 int "Maximum number of CPUs (2-32)"
1567 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1568 depends on SMP && HOTPLUG && EXPERIMENTAL
1570 Say Y here to experiment with turning CPUs off and on. CPUs
1571 can be controlled through /sys/devices/system/cpu.
1574 bool "Use local timer interrupts"
1577 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1579 Enable support for local timers on SMP platforms, rather then the
1580 legacy IPI broadcast method. Local timers allows the system
1581 accounting to be spread across the timer interval, preventing a
1582 "thundering herd" at every timer tick.
1586 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1587 default 355 if ARCH_U8500
1588 default 264 if MACH_H4700
1591 Maximum number of GPIOs in the system.
1593 If unsure, leave the default value.
1595 source kernel/Kconfig.preempt
1599 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1600 ARCH_S5PV210 || ARCH_EXYNOS4
1601 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1602 default AT91_TIMER_HZ if ARCH_AT91
1603 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1606 config THUMB2_KERNEL
1607 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1608 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1610 select ARM_ASM_UNIFIED
1613 By enabling this option, the kernel will be compiled in
1614 Thumb-2 mode. A compiler/assembler that understand the unified
1615 ARM-Thumb syntax is needed.
1619 config THUMB2_AVOID_R_ARM_THM_JUMP11
1620 bool "Work around buggy Thumb-2 short branch relocations in gas"
1621 depends on THUMB2_KERNEL && MODULES
1624 Various binutils versions can resolve Thumb-2 branches to
1625 locally-defined, preemptible global symbols as short-range "b.n"
1626 branch instructions.
1628 This is a problem, because there's no guarantee the final
1629 destination of the symbol, or any candidate locations for a
1630 trampoline, are within range of the branch. For this reason, the
1631 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1632 relocation in modules at all, and it makes little sense to add
1635 The symptom is that the kernel fails with an "unsupported
1636 relocation" error when loading some modules.
1638 Until fixed tools are available, passing
1639 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1640 code which hits this problem, at the cost of a bit of extra runtime
1641 stack usage in some cases.
1643 The problem is described in more detail at:
1644 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1646 Only Thumb-2 kernels are affected.
1648 Unless you are sure your tools don't have this problem, say Y.
1650 config ARM_ASM_UNIFIED
1654 bool "Use the ARM EABI to compile the kernel"
1656 This option allows for the kernel to be compiled using the latest
1657 ARM ABI (aka EABI). This is only useful if you are using a user
1658 space environment that is also compiled with EABI.
1660 Since there are major incompatibilities between the legacy ABI and
1661 EABI, especially with regard to structure member alignment, this
1662 option also changes the kernel syscall calling convention to
1663 disambiguate both ABIs and allow for backward compatibility support
1664 (selected with CONFIG_OABI_COMPAT).
1666 To use this you need GCC version 4.0.0 or later.
1669 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1670 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1673 This option preserves the old syscall interface along with the
1674 new (ARM EABI) one. It also provides a compatibility layer to
1675 intercept syscalls that have structure arguments which layout
1676 in memory differs between the legacy ABI and the new ARM EABI
1677 (only for non "thumb" binaries). This option adds a tiny
1678 overhead to all syscalls and produces a slightly larger kernel.
1679 If you know you'll be using only pure EABI user space then you
1680 can say N here. If this option is not selected and you attempt
1681 to execute a legacy ABI binary then the result will be
1682 UNPREDICTABLE (in fact it can be predicted that it won't work
1683 at all). If in doubt say Y.
1685 config ARCH_HAS_HOLES_MEMORYMODEL
1688 config ARCH_SPARSEMEM_ENABLE
1691 config ARCH_SPARSEMEM_DEFAULT
1692 def_bool ARCH_SPARSEMEM_ENABLE
1694 config ARCH_SELECT_MEMORY_MODEL
1695 def_bool ARCH_SPARSEMEM_ENABLE
1697 config HAVE_ARCH_PFN_VALID
1698 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1701 bool "High Memory Support"
1704 The address space of ARM processors is only 4 Gigabytes large
1705 and it has to accommodate user address space, kernel address
1706 space as well as some memory mapped IO. That means that, if you
1707 have a large amount of physical memory and/or IO, not all of the
1708 memory can be "permanently mapped" by the kernel. The physical
1709 memory that is not permanently mapped is called "high memory".
1711 Depending on the selected kernel/user memory split, minimum
1712 vmalloc space and actual amount of RAM, you may not need this
1713 option which should result in a slightly faster kernel.
1718 bool "Allocate 2nd-level pagetables from highmem"
1721 config HW_PERF_EVENTS
1722 bool "Enable hardware performance counter support for perf events"
1723 depends on PERF_EVENTS && CPU_HAS_PMU
1726 Enable hardware performance counter support for perf events. If
1727 disabled, perf events will use software events only.
1731 config FORCE_MAX_ZONEORDER
1732 int "Maximum zone order" if ARCH_SHMOBILE
1733 range 11 64 if ARCH_SHMOBILE
1734 default "9" if SA1111
1737 The kernel memory allocator divides physically contiguous memory
1738 blocks into "zones", where each zone is a power of two number of
1739 pages. This option selects the largest power of two that the kernel
1740 keeps in the memory allocator. If you need to allocate very large
1741 blocks of physically contiguous memory, then you may need to
1742 increase this value.
1744 This config option is actually maximum order plus one. For example,
1745 a value of 11 means that the largest free memory block is 2^10 pages.
1748 bool "Timer and CPU usage LEDs"
1749 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1750 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1751 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1752 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1753 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1754 ARCH_AT91 || ARCH_DAVINCI || \
1755 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1757 If you say Y here, the LEDs on your machine will be used
1758 to provide useful information about your current system status.
1760 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1761 be able to select which LEDs are active using the options below. If
1762 you are compiling a kernel for the EBSA-110 or the LART however, the
1763 red LED will simply flash regularly to indicate that the system is
1764 still functional. It is safe to say Y here if you have a CATS
1765 system, but the driver will do nothing.
1768 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1769 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1770 || MACH_OMAP_PERSEUS2
1772 depends on !GENERIC_CLOCKEVENTS
1773 default y if ARCH_EBSA110
1775 If you say Y here, one of the system LEDs (the green one on the
1776 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1777 will flash regularly to indicate that the system is still
1778 operational. This is mainly useful to kernel hackers who are
1779 debugging unstable kernels.
1781 The LART uses the same LED for both Timer LED and CPU usage LED
1782 functions. You may choose to use both, but the Timer LED function
1783 will overrule the CPU usage LED.
1786 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1788 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1789 || MACH_OMAP_PERSEUS2
1792 If you say Y here, the red LED will be used to give a good real
1793 time indication of CPU usage, by lighting whenever the idle task
1794 is not currently executing.
1796 The LART uses the same LED for both Timer LED and CPU usage LED
1797 functions. You may choose to use both, but the Timer LED function
1798 will overrule the CPU usage LED.
1800 config ALIGNMENT_TRAP
1802 depends on CPU_CP15_MMU
1803 default y if !ARCH_EBSA110
1804 select HAVE_PROC_CPU if PROC_FS
1806 ARM processors cannot fetch/store information which is not
1807 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1808 address divisible by 4. On 32-bit ARM processors, these non-aligned
1809 fetch/store instructions will be emulated in software if you say
1810 here, which has a severe performance impact. This is necessary for
1811 correct operation of some network protocols. With an IP-only
1812 configuration it is safe to say N, otherwise say Y.
1814 config UACCESS_WITH_MEMCPY
1815 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1816 depends on MMU && EXPERIMENTAL
1817 default y if CPU_FEROCEON
1819 Implement faster copy_to_user and clear_user methods for CPU
1820 cores where a 8-word STM instruction give significantly higher
1821 memory write throughput than a sequence of individual 32bit stores.
1823 A possible side effect is a slight increase in scheduling latency
1824 between threads sharing the same address space if they invoke
1825 such copy operations with large buffers.
1827 However, if the CPU data cache is using a write-allocate mode,
1828 this option is unlikely to provide any performance gain.
1832 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 This kernel feature is useful for number crunching applications
1835 that may need to compute untrusted bytecode during their
1836 execution. By using pipes or other transports made available to
1837 the process as file descriptors supporting the read/write
1838 syscalls, it's possible to isolate those applications in
1839 their own address space using seccomp. Once seccomp is
1840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1841 and the task is only allowed to execute a few safe syscalls
1842 defined by each seccomp mode.
1844 config CC_STACKPROTECTOR
1845 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1846 depends on EXPERIMENTAL
1848 This option turns on the -fstack-protector GCC feature. This
1849 feature puts, at the beginning of functions, a canary value on
1850 the stack just before the return address, and validates
1851 the value just before actually returning. Stack based buffer
1852 overflows (that need to overwrite this return address) now also
1853 overwrite the canary, which gets detected and the attack is then
1854 neutralized via a kernel panic.
1855 This feature requires gcc version 4.2 or above.
1857 config DEPRECATED_PARAM_STRUCT
1858 bool "Provide old way to pass kernel parameters"
1860 This was deprecated in 2001 and announced to live on for 5 years.
1861 Some old boot loaders still use this way.
1868 bool "Flattened Device Tree support"
1870 select OF_EARLY_FLATTREE
1873 Include support for flattened device tree machine descriptions.
1875 # Compressed boot loader in ROM. Yes, we really want to ask about
1876 # TEXT and BSS so we preserve their values in the config files.
1877 config ZBOOT_ROM_TEXT
1878 hex "Compressed ROM boot loader base address"
1881 The physical address at which the ROM-able zImage is to be
1882 placed in the target. Platforms which normally make use of
1883 ROM-able zImage formats normally set this to a suitable
1884 value in their defconfig file.
1886 If ZBOOT_ROM is not enabled, this has no effect.
1888 config ZBOOT_ROM_BSS
1889 hex "Compressed ROM boot loader BSS address"
1892 The base address of an area of read/write memory in the target
1893 for the ROM-able zImage which must be available while the
1894 decompressor is running. It must be large enough to hold the
1895 entire decompressed kernel plus an additional 128 KiB.
1896 Platforms which normally make use of ROM-able zImage formats
1897 normally set this to a suitable value in their defconfig file.
1899 If ZBOOT_ROM is not enabled, this has no effect.
1902 bool "Compressed boot loader in ROM/flash"
1903 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1905 Say Y here if you intend to execute your compressed kernel image
1906 (zImage) directly from ROM or flash. If unsure, say N.
1909 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1910 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1911 default ZBOOT_ROM_NONE
1913 Include experimental SD/MMC loading code in the ROM-able zImage.
1914 With this enabled it is possible to write the ROM-able zImage
1915 kernel image to an MMC or SD card and boot the kernel straight
1916 from the reset vector. At reset the processor Mask ROM will load
1917 the first part of the ROM-able zImage which in turn loads the
1918 rest the kernel image to RAM.
1920 config ZBOOT_ROM_NONE
1921 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1923 Do not load image from SD or MMC
1925 config ZBOOT_ROM_MMCIF
1926 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1928 Load image from MMCIF hardware block.
1930 config ZBOOT_ROM_SH_MOBILE_SDHI
1931 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1933 Load image from SDHI hardware block
1937 config ARM_APPENDED_DTB
1938 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1939 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1941 With this option, the boot code will look for a device tree binary
1942 (DTB) appended to zImage
1943 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1945 This is meant as a backward compatibility convenience for those
1946 systems with a bootloader that can't be upgraded to accommodate
1947 the documented boot protocol using a device tree.
1949 Beware that there is very little in terms of protection against
1950 this option being confused by leftover garbage in memory that might
1951 look like a DTB header after a reboot if no actual DTB is appended
1952 to zImage. Do not leave this option active in a production kernel
1953 if you don't intend to always append a DTB. Proper passing of the
1954 location into r2 of a bootloader provided DTB is always preferable
1957 config ARM_ATAG_DTB_COMPAT
1958 bool "Supplement the appended DTB with traditional ATAG information"
1959 depends on ARM_APPENDED_DTB
1961 Some old bootloaders can't be updated to a DTB capable one, yet
1962 they provide ATAGs with memory configuration, the ramdisk address,
1963 the kernel cmdline string, etc. Such information is dynamically
1964 provided by the bootloader and can't always be stored in a static
1965 DTB. To allow a device tree enabled kernel to be used with such
1966 bootloaders, this option allows zImage to extract the information
1967 from the ATAG list and store it at run time into the appended DTB.
1970 string "Default kernel command string"
1973 On some architectures (EBSA110 and CATS), there is currently no way
1974 for the boot loader to pass arguments to the kernel. For these
1975 architectures, you should supply some command-line options at build
1976 time by entering them here. As a minimum, you should specify the
1977 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1980 prompt "Kernel command line type" if CMDLINE != ""
1981 default CMDLINE_FROM_BOOTLOADER
1983 config CMDLINE_FROM_BOOTLOADER
1984 bool "Use bootloader kernel arguments if available"
1986 Uses the command-line options passed by the boot loader. If
1987 the boot loader doesn't provide any, the default kernel command
1988 string provided in CMDLINE will be used.
1990 config CMDLINE_EXTEND
1991 bool "Extend bootloader kernel arguments"
1993 The command-line arguments provided by the boot loader will be
1994 appended to the default kernel command string.
1996 config CMDLINE_FORCE
1997 bool "Always use the default kernel command string"
1999 Always use the default kernel command string, even if the boot
2000 loader passes other arguments to the kernel.
2001 This is useful if you cannot or don't want to change the
2002 command-line options your boot loader passes to the kernel.
2006 bool "Kernel Execute-In-Place from ROM"
2007 depends on !ZBOOT_ROM && !ARM_LPAE
2009 Execute-In-Place allows the kernel to run from non-volatile storage
2010 directly addressable by the CPU, such as NOR flash. This saves RAM
2011 space since the text section of the kernel is not loaded from flash
2012 to RAM. Read-write sections, such as the data section and stack,
2013 are still copied to RAM. The XIP kernel is not compressed since
2014 it has to run directly from flash, so it will take more space to
2015 store it. The flash address used to link the kernel object files,
2016 and for storing it, is configuration dependent. Therefore, if you
2017 say Y here, you must know the proper physical address where to
2018 store the kernel image depending on your own flash memory usage.
2020 Also note that the make target becomes "make xipImage" rather than
2021 "make zImage" or "make Image". The final kernel binary to put in
2022 ROM memory will be arch/arm/boot/xipImage.
2026 config XIP_PHYS_ADDR
2027 hex "XIP Kernel Physical Location"
2028 depends on XIP_KERNEL
2029 default "0x00080000"
2031 This is the physical address in your flash memory the kernel will
2032 be linked for and stored to. This address is dependent on your
2036 bool "Kexec system call (EXPERIMENTAL)"
2037 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2039 kexec is a system call that implements the ability to shutdown your
2040 current kernel, and to start another kernel. It is like a reboot
2041 but it is independent of the system firmware. And like a reboot
2042 you can start any kernel with it, not just Linux.
2044 It is an ongoing process to be certain the hardware in a machine
2045 is properly shutdown, so do not be surprised if this code does not
2046 initially work for you. It may help to enable device hotplugging
2050 bool "Export atags in procfs"
2054 Should the atags used to boot the kernel be exported in an "atags"
2055 file in procfs. Useful with kexec.
2058 bool "Build kdump crash kernel (EXPERIMENTAL)"
2059 depends on EXPERIMENTAL
2061 Generate crash dump after being started by kexec. This should
2062 be normally only set in special crash dump kernels which are
2063 loaded in the main kernel with kexec-tools into a specially
2064 reserved region and then later executed after a crash by
2065 kdump/kexec. The crash dump kernel must be compiled to a
2066 memory address not used by the main kernel
2068 For more details see Documentation/kdump/kdump.txt
2070 config AUTO_ZRELADDR
2071 bool "Auto calculation of the decompressed kernel image address"
2072 depends on !ZBOOT_ROM && !ARCH_U300
2074 ZRELADDR is the physical address where the decompressed kernel
2075 image will be placed. If AUTO_ZRELADDR is selected, the address
2076 will be determined at run-time by masking the current IP with
2077 0xf8000000. This assumes the zImage being placed in the first 128MB
2078 from start of memory.
2082 menu "CPU Power Management"
2086 source "drivers/cpufreq/Kconfig"
2089 tristate "CPUfreq driver for i.MX CPUs"
2090 depends on ARCH_MXC && CPU_FREQ
2092 This enables the CPUfreq driver for i.MX CPUs.
2094 config CPU_FREQ_SA1100
2097 config CPU_FREQ_SA1110
2100 config CPU_FREQ_INTEGRATOR
2101 tristate "CPUfreq driver for ARM Integrator CPUs"
2102 depends on ARCH_INTEGRATOR && CPU_FREQ
2105 This enables the CPUfreq driver for ARM Integrator CPUs.
2107 For details, take a look at <file:Documentation/cpu-freq>.
2113 depends on CPU_FREQ && ARCH_PXA && PXA25x
2115 select CPU_FREQ_TABLE
2116 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2121 Internal configuration node for common cpufreq on Samsung SoC
2123 config CPU_FREQ_S3C24XX
2124 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2125 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2128 This enables the CPUfreq driver for the Samsung S3C24XX family
2131 For details, take a look at <file:Documentation/cpu-freq>.
2135 config CPU_FREQ_S3C24XX_PLL
2136 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2137 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2139 Compile in support for changing the PLL frequency from the
2140 S3C24XX series CPUfreq driver. The PLL takes time to settle
2141 after a frequency change, so by default it is not enabled.
2143 This also means that the PLL tables for the selected CPU(s) will
2144 be built which may increase the size of the kernel image.
2146 config CPU_FREQ_S3C24XX_DEBUG
2147 bool "Debug CPUfreq Samsung driver core"
2148 depends on CPU_FREQ_S3C24XX
2150 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2152 config CPU_FREQ_S3C24XX_IODEBUG
2153 bool "Debug CPUfreq Samsung driver IO timing"
2154 depends on CPU_FREQ_S3C24XX
2156 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2158 config CPU_FREQ_S3C24XX_DEBUGFS
2159 bool "Export debugfs for CPUFreq"
2160 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2162 Export status information via debugfs.
2166 source "drivers/cpuidle/Kconfig"
2170 menu "Floating point emulation"
2172 comment "At least one emulation must be selected"
2175 bool "NWFPE math emulation"
2176 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2178 Say Y to include the NWFPE floating point emulator in the kernel.
2179 This is necessary to run most binaries. Linux does not currently
2180 support floating point hardware so you need to say Y here even if
2181 your machine has an FPA or floating point co-processor podule.
2183 You may say N here if you are going to load the Acorn FPEmulator
2184 early in the bootup.
2187 bool "Support extended precision"
2188 depends on FPE_NWFPE
2190 Say Y to include 80-bit support in the kernel floating-point
2191 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2192 Note that gcc does not generate 80-bit operations by default,
2193 so in most cases this option only enlarges the size of the
2194 floating point emulator without any good reason.
2196 You almost surely want to say N here.
2199 bool "FastFPE math emulation (EXPERIMENTAL)"
2200 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2202 Say Y here to include the FAST floating point emulator in the kernel.
2203 This is an experimental much faster emulator which now also has full
2204 precision for the mantissa. It does not support any exceptions.
2205 It is very simple, and approximately 3-6 times faster than NWFPE.
2207 It should be sufficient for most programs. It may be not suitable
2208 for scientific calculations, but you have to check this for yourself.
2209 If you do not feel you need a faster FP emulation you should better
2213 bool "VFP-format floating point maths"
2214 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2216 Say Y to include VFP support code in the kernel. This is needed
2217 if your hardware includes a VFP unit.
2219 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2220 release notes and additional status information.
2222 Say N if your target does not have VFP hardware.
2230 bool "Advanced SIMD (NEON) Extension support"
2231 depends on VFPv3 && CPU_V7
2233 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2238 menu "Userspace binary formats"
2240 source "fs/Kconfig.binfmt"
2243 tristate "RISC OS personality"
2246 Say Y here to include the kernel code necessary if you want to run
2247 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2248 experimental; if this sounds frightening, say N and sleep in peace.
2249 You can also say M here to compile this support as a module (which
2250 will be called arthur).
2254 menu "Power management options"
2256 source "kernel/power/Kconfig"
2258 config ARCH_SUSPEND_POSSIBLE
2259 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2260 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2261 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2264 config ARM_CPU_SUSPEND
2269 source "net/Kconfig"
2271 source "drivers/Kconfig"
2275 source "arch/arm/Kconfig.debug"
2277 source "security/Kconfig"
2279 source "crypto/Kconfig"
2281 source "lib/Kconfig"