4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select MODULES_USE_ELF_REL
55 The ARM series is a line of low-power-consumption RISC chip designs
56 licensed by ARM Ltd and targeted at embedded applications and
57 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
58 manufactured, but legacy ARM-based PC hardware remains popular in
59 Europe. There is an ARM Linux project with a web page at
60 <http://www.arm.linux.org.uk/>.
62 config ARM_HAS_SG_CHAIN
65 config NEED_SG_DMA_LENGTH
68 config ARM_DMA_USE_IOMMU
69 select NEED_SG_DMA_LENGTH
70 select ARM_HAS_SG_CHAIN
79 config SYS_SUPPORTS_APM_EMULATION
87 select GENERIC_ALLOCATOR
98 The Extended Industry Standard Architecture (EISA) bus was
99 developed as an open alternative to the IBM MicroChannel bus.
101 The EISA bus provided some of the features of the IBM MicroChannel
102 bus while maintaining backward compatibility with cards made for
103 the older ISA bus. The EISA bus saw limited use between 1988 and
104 1995 when it was made obsolete by the PCI bus.
106 Say Y here if you are building a kernel for an EISA-based machine.
113 config STACKTRACE_SUPPORT
117 config HAVE_LATENCYTOP_SUPPORT
122 config LOCKDEP_SUPPORT
126 config TRACE_IRQFLAGS_SUPPORT
130 config RWSEM_GENERIC_SPINLOCK
134 config RWSEM_XCHGADD_ALGORITHM
137 config ARCH_HAS_ILOG2_U32
140 config ARCH_HAS_ILOG2_U64
143 config ARCH_HAS_CPUFREQ
146 Internal node to signify that the ARCH has CPUFREQ support
147 and that the relevant menu configurations are displayed for
150 config GENERIC_HWEIGHT
154 config GENERIC_CALIBRATE_DELAY
158 config ARCH_MAY_HAVE_PC_FDC
164 config NEED_DMA_MAP_STATE
167 config ARCH_HAS_DMA_SET_COHERENT_MASK
170 config GENERIC_ISA_DMA
176 config NEED_RET_TO_USER
184 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
185 default DRAM_BASE if REMAP_VECTORS_TO_RAM
188 The base address of exception vectors.
190 config ARM_PATCH_PHYS_VIRT
191 bool "Patch physical to virtual translations at runtime" if EMBEDDED
193 depends on !XIP_KERNEL && MMU
194 depends on !ARCH_REALVIEW || !SPARSEMEM
196 Patch phys-to-virt and virt-to-phys translation functions at
197 boot and module load time according to the position of the
198 kernel in system memory.
200 This can only be used with non-XIP MMU kernels where the base
201 of physical memory is at a 16MB boundary.
203 Only disable this option if you know that you do not require
204 this feature (eg, building a kernel for a single machine) and
205 you need to shrink the kernel to the minimal size.
207 config NEED_MACH_IO_H
210 Select this when mach/io.h is required to provide special
211 definitions for this platform. The need for mach/io.h should
212 be avoided when possible.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory" if MMU
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
224 default DRAM_BASE if !MMU
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
255 bool "Altera SOCFPGA family"
256 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select DW_APB_TIMER_OF
265 select GENERIC_CLOCKEVENTS
266 select GPIO_PL061 if GPIOLIB
271 This enables support for Altera SOCFPGA Cyclone V platform
273 config ARCH_INTEGRATOR
274 bool "ARM Ltd. Integrator family"
276 select ARCH_HAS_CPUFREQ
281 select GENERIC_CLOCKEVENTS
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_FPGA_IRQ
284 select NEED_MACH_IO_H
285 select NEED_MACH_MEMORY_H
287 select MULTI_IRQ_HANDLER
289 Support for ARM's Integrator platform.
292 bool "ARM Ltd. RealView family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select ARM_TIMER_SP804
303 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
313 select HAVE_MACH_CLKDEV
315 select GENERIC_CLOCKEVENTS
316 select ARCH_WANT_OPTIONAL_GPIOLIB
317 select NEED_MACH_IO_H if PCI
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLOCK
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_FPGA_IRQ
322 select ARM_TIMER_SP804
324 This enables support for ARM Ltd Versatile board.
327 bool "ARM Ltd. Versatile Express family"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
335 select HAVE_PATA_PLATFORM
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLCD
340 select REGULATOR_FIXED_VOLTAGE if REGULATOR
342 This enables support for the ARM Ltd Versatile Express boards.
346 select ARCH_REQUIRE_GPIOLIB
350 select NEED_MACH_IO_H if PCCARD
352 This enables support for systems based on Atmel
353 AT91RM9200 and AT91SAM9* processors.
356 bool "Broadcom BCMRING"
360 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 Support for Broadcom's BCMRing platform.
368 bool "Calxeda Highbank-based"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
372 select ARM_TIMER_SP804
377 select GENERIC_CLOCKEVENTS
383 Support for the Calxeda Highbank SoC based boards.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
388 select ARCH_USES_GETTIMEOFFSET
389 select NEED_MACH_MEMORY_H
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cavium Networks CNS3XXX family"
396 select GENERIC_CLOCKEVENTS
398 select MIGHT_HAVE_CACHE_L2X0
399 select MIGHT_HAVE_PCI
400 select PCI_DOMAINS if PCI
402 Support for Cavium Networks CNS3XXX platform.
405 bool "Cortina Systems Gemini"
407 select ARCH_REQUIRE_GPIOLIB
408 select ARCH_USES_GETTIMEOFFSET
410 Support for the Cortina Systems Gemini family SoCs
413 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
416 select ARCH_REQUIRE_GPIOLIB
417 select GENERIC_CLOCKEVENTS
419 select GENERIC_IRQ_CHIP
420 select MIGHT_HAVE_CACHE_L2X0
426 Support for CSR SiRFSoC ARM Cortex A9 Platform
433 select ARCH_USES_GETTIMEOFFSET
434 select NEED_MACH_IO_H
435 select NEED_MACH_MEMORY_H
437 This is an evaluation board for the StrongARM processor available
438 from Digital. It has limited hardware on-board, including an
439 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_REQUIRE_GPIOLIB
449 select ARCH_HAS_HOLES_MEMORYMODEL
450 select ARCH_USES_GETTIMEOFFSET
451 select NEED_MACH_MEMORY_H
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Freescale MXC/iMX-based"
469 select GENERIC_CLOCKEVENTS
470 select ARCH_REQUIRE_GPIOLIB
473 select GENERIC_IRQ_CHIP
474 select MULTI_IRQ_HANDLER
478 Support for Freescale MXC/iMX-based family of processors
481 bool "Freescale MXS-based"
482 select GENERIC_CLOCKEVENTS
483 select ARCH_REQUIRE_GPIOLIB
487 select HAVE_CLK_PREPARE
491 Support for Freescale MXS-based family of processors
494 bool "Hilscher NetX based"
498 select GENERIC_CLOCKEVENTS
500 This enables support for systems based on the Hilscher NetX Soc
503 bool "Hynix HMS720x-based"
506 select ARCH_USES_GETTIMEOFFSET
508 This enables support for systems based on the Hynix HMS720x
516 select ARCH_SUPPORTS_MSI
518 select NEED_MACH_IO_H
519 select NEED_MACH_MEMORY_H
520 select NEED_RET_TO_USER
522 Support for Intel's IOP13XX (XScale) family of processors.
528 select NEED_MACH_IO_H
529 select NEED_RET_TO_USER
532 select ARCH_REQUIRE_GPIOLIB
534 Support for Intel's 80219 and IOP32X (XScale) family of
541 select NEED_MACH_IO_H
542 select NEED_RET_TO_USER
545 select ARCH_REQUIRE_GPIOLIB
547 Support for Intel's IOP33X (XScale) family of processors.
552 select ARCH_HAS_DMA_SET_COHERENT_MASK
555 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select MIGHT_HAVE_PCI
558 select NEED_MACH_IO_H
559 select DMABOUNCE if PCI
561 Support for Intel's IXP4XX (XScale) family of processors.
564 bool "Marvell SOCs with Device Tree support"
565 select GENERIC_CLOCKEVENTS
566 select MULTI_IRQ_HANDLER
569 select GENERIC_IRQ_CHIP
573 Support for the Marvell SoC Family with device tree support
579 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_IO_H
584 Support for the Marvell Dove SoC 88AP510
587 bool "Marvell Kirkwood"
590 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
592 select NEED_MACH_IO_H
595 Support for the following Marvell Kirkwood series SoCs:
596 88F6180, 88F6192 and 88F6281.
602 select ARCH_REQUIRE_GPIOLIB
605 select USB_ARCH_HAS_OHCI
607 select GENERIC_CLOCKEVENTS
611 Support for the NXP LPC32XX family of processors
614 bool "Marvell MV78xx0"
617 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
619 select NEED_MACH_IO_H
622 Support for the following Marvell MV78xx0 series SoCs:
630 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
632 select NEED_MACH_IO_H
635 Support for the following Marvell Orion 5x series SoCs:
636 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
637 Orion-2 (5281), Orion-1-90 (6183).
640 bool "Marvell PXA168/910/MMP2"
642 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
649 select GENERIC_ALLOCATOR
651 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
654 bool "Micrel/Kendin KS8695"
656 select ARCH_REQUIRE_GPIOLIB
657 select ARCH_USES_GETTIMEOFFSET
658 select NEED_MACH_MEMORY_H
660 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
661 System-on-Chip devices.
664 bool "Nuvoton W90X900 CPU"
666 select ARCH_REQUIRE_GPIOLIB
669 select GENERIC_CLOCKEVENTS
671 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
672 At present, the w90x900 has been renamed nuc900, regarding
673 the ARM series product line, you can login the following
674 link address to know more.
676 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
677 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
683 select GENERIC_CLOCKEVENTS
687 select MIGHT_HAVE_CACHE_L2X0
688 select NEED_MACH_IO_H if PCI
689 select ARCH_HAS_CPUFREQ
692 This enables support for NVIDIA Tegra based systems (Tegra APX,
693 Tegra 6xx and Tegra 2 series).
695 config ARCH_PICOXCELL
696 bool "Picochip picoXcell"
697 select ARCH_REQUIRE_GPIOLIB
698 select ARM_PATCH_PHYS_VIRT
702 select DW_APB_TIMER_OF
703 select GENERIC_CLOCKEVENTS
710 This enables support for systems based on the Picochip picoXcell
711 family of Femtocell devices. The picoxcell support requires device tree
715 bool "Philips Nexperia PNX4008 Mobile"
718 select ARCH_USES_GETTIMEOFFSET
720 This enables support for Philips PNX4008 mobile platform.
723 bool "PXA2xx/PXA3xx-based"
726 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
730 select GENERIC_CLOCKEVENTS
735 select MULTI_IRQ_HANDLER
736 select ARM_CPU_SUSPEND if PM
739 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
744 select GENERIC_CLOCKEVENTS
745 select ARCH_REQUIRE_GPIOLIB
748 Support for Qualcomm MSM/QSD based systems. This runs on the
749 apps processor of the MSM/QSD and depends on a shared memory
750 interface to the modem processor which runs the baseband
751 stack and controls some vital subsystems
752 (clock and power control, etc).
755 bool "Renesas SH-Mobile / R-Mobile"
758 select HAVE_MACH_CLKDEV
760 select GENERIC_CLOCKEVENTS
761 select MIGHT_HAVE_CACHE_L2X0
764 select MULTI_IRQ_HANDLER
765 select PM_GENERIC_DOMAINS if PM
766 select NEED_MACH_MEMORY_H
768 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
774 select ARCH_MAY_HAVE_PC_FDC
775 select HAVE_PATA_PLATFORM
778 select ARCH_SPARSEMEM_ENABLE
779 select ARCH_USES_GETTIMEOFFSET
781 select NEED_MACH_IO_H
782 select NEED_MACH_MEMORY_H
784 On the Acorn Risc-PC, Linux can support the internal IDE disk and
785 CD-ROM interface, serial and parallel port, and the floppy drive.
792 select ARCH_SPARSEMEM_ENABLE
794 select ARCH_HAS_CPUFREQ
796 select GENERIC_CLOCKEVENTS
798 select ARCH_REQUIRE_GPIOLIB
800 select NEED_MACH_MEMORY_H
803 Support for StrongARM 11x0 based boards.
806 bool "Samsung S3C24XX SoCs"
808 select ARCH_HAS_CPUFREQ
811 select ARCH_USES_GETTIMEOFFSET
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C_RTC if RTC_CLASS
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select NEED_MACH_IO_H
817 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
818 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
819 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
820 Samsung SMDK2410 development board (and derivatives).
823 bool "Samsung S3C64XX"
831 select ARCH_USES_GETTIMEOFFSET
832 select ARCH_HAS_CPUFREQ
833 select ARCH_REQUIRE_GPIOLIB
834 select SAMSUNG_CLKSRC
835 select SAMSUNG_IRQ_VIC_TIMER
836 select S3C_GPIO_TRACK
838 select USB_ARCH_HAS_OHCI
839 select SAMSUNG_GPIOLIB_4BIT
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 Samsung S3C64XX series based systems
846 bool "Samsung S5P6440 S5P6450"
852 select HAVE_S3C2410_WATCHDOG if WATCHDOG
853 select GENERIC_CLOCKEVENTS
854 select HAVE_S3C2410_I2C if I2C
855 select HAVE_S3C_RTC if RTC_CLASS
857 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
861 bool "Samsung S5PC100"
866 select ARCH_USES_GETTIMEOFFSET
867 select HAVE_S3C2410_I2C if I2C
868 select HAVE_S3C_RTC if RTC_CLASS
869 select HAVE_S3C2410_WATCHDOG if WATCHDOG
871 Samsung S5PC100 series based systems
874 bool "Samsung S5PV210/S5PC110"
876 select ARCH_SPARSEMEM_ENABLE
877 select ARCH_HAS_HOLES_MEMORYMODEL
882 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select HAVE_S3C2410_I2C if I2C
885 select HAVE_S3C_RTC if RTC_CLASS
886 select HAVE_S3C2410_WATCHDOG if WATCHDOG
887 select NEED_MACH_MEMORY_H
889 Samsung S5PV210/S5PC110 series based systems
892 bool "SAMSUNG EXYNOS"
894 select ARCH_SPARSEMEM_ENABLE
895 select ARCH_HAS_HOLES_MEMORYMODEL
899 select ARCH_HAS_CPUFREQ
900 select GENERIC_CLOCKEVENTS
901 select HAVE_S3C_RTC if RTC_CLASS
902 select HAVE_S3C2410_I2C if I2C
903 select HAVE_S3C2410_WATCHDOG if WATCHDOG
904 select NEED_MACH_MEMORY_H
906 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
915 select ARCH_USES_GETTIMEOFFSET
916 select NEED_MACH_MEMORY_H
917 select NEED_MACH_IO_H
919 Support for the StrongARM based Digital DNARD machine, also known
920 as "Shark" (<http://www.shark-linux.de/shark.html>).
923 bool "ST-Ericsson U300 Series"
929 select ARM_PATCH_PHYS_VIRT
931 select GENERIC_CLOCKEVENTS
935 select ARCH_REQUIRE_GPIOLIB
937 Support for ST-Ericsson U300 series mobile platforms.
940 bool "ST-Ericsson U8500 Series"
944 select GENERIC_CLOCKEVENTS
946 select ARCH_REQUIRE_GPIOLIB
947 select ARCH_HAS_CPUFREQ
949 select MIGHT_HAVE_CACHE_L2X0
951 Support for ST-Ericsson's Ux500 architecture
954 bool "STMicroelectronics Nomadik"
959 select GENERIC_CLOCKEVENTS
961 select MIGHT_HAVE_CACHE_L2X0
962 select ARCH_REQUIRE_GPIOLIB
964 Support for the Nomadik platform by ST-Ericsson
968 select GENERIC_CLOCKEVENTS
969 select ARCH_REQUIRE_GPIOLIB
973 select GENERIC_ALLOCATOR
974 select GENERIC_IRQ_CHIP
975 select ARCH_HAS_HOLES_MEMORYMODEL
977 Support for TI's DaVinci platform.
983 select ARCH_REQUIRE_GPIOLIB
984 select ARCH_HAS_CPUFREQ
986 select GENERIC_CLOCKEVENTS
987 select ARCH_HAS_HOLES_MEMORYMODEL
989 Support for TI's OMAP platform (OMAP1/2/3/4).
994 select ARCH_REQUIRE_GPIOLIB
998 select GENERIC_CLOCKEVENTS
1001 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1004 bool "VIA/WonderMedia 85xx"
1007 select ARCH_HAS_CPUFREQ
1008 select GENERIC_CLOCKEVENTS
1009 select ARCH_REQUIRE_GPIOLIB
1011 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1014 bool "Xilinx Zynq ARM Cortex A9 Platform"
1016 select GENERIC_CLOCKEVENTS
1017 select CLKDEV_LOOKUP
1021 select MIGHT_HAVE_CACHE_L2X0
1024 Support for Xilinx Zynq ARM Cortex A9 Platform
1028 # This is sorted alphabetically by mach-* pathname. However, plat-*
1029 # Kconfigs may be included either alphabetically (according to the
1030 # plat- suffix) or along side the corresponding mach-* source.
1032 source "arch/arm/mach-mvebu/Kconfig"
1034 source "arch/arm/mach-at91/Kconfig"
1036 source "arch/arm/mach-bcmring/Kconfig"
1038 source "arch/arm/mach-clps711x/Kconfig"
1040 source "arch/arm/mach-cns3xxx/Kconfig"
1042 source "arch/arm/mach-davinci/Kconfig"
1044 source "arch/arm/mach-dove/Kconfig"
1046 source "arch/arm/mach-ep93xx/Kconfig"
1048 source "arch/arm/mach-footbridge/Kconfig"
1050 source "arch/arm/mach-gemini/Kconfig"
1052 source "arch/arm/mach-h720x/Kconfig"
1054 source "arch/arm/mach-integrator/Kconfig"
1056 source "arch/arm/mach-iop32x/Kconfig"
1058 source "arch/arm/mach-iop33x/Kconfig"
1060 source "arch/arm/mach-iop13xx/Kconfig"
1062 source "arch/arm/mach-ixp4xx/Kconfig"
1064 source "arch/arm/mach-kirkwood/Kconfig"
1066 source "arch/arm/mach-ks8695/Kconfig"
1068 source "arch/arm/mach-msm/Kconfig"
1070 source "arch/arm/mach-mv78xx0/Kconfig"
1072 source "arch/arm/plat-mxc/Kconfig"
1074 source "arch/arm/mach-mxs/Kconfig"
1076 source "arch/arm/mach-netx/Kconfig"
1078 source "arch/arm/mach-nomadik/Kconfig"
1079 source "arch/arm/plat-nomadik/Kconfig"
1081 source "arch/arm/plat-omap/Kconfig"
1083 source "arch/arm/mach-omap1/Kconfig"
1085 source "arch/arm/mach-omap2/Kconfig"
1087 source "arch/arm/mach-orion5x/Kconfig"
1089 source "arch/arm/mach-pxa/Kconfig"
1090 source "arch/arm/plat-pxa/Kconfig"
1092 source "arch/arm/mach-mmp/Kconfig"
1094 source "arch/arm/mach-realview/Kconfig"
1096 source "arch/arm/mach-sa1100/Kconfig"
1098 source "arch/arm/plat-samsung/Kconfig"
1099 source "arch/arm/plat-s3c24xx/Kconfig"
1101 source "arch/arm/plat-spear/Kconfig"
1103 source "arch/arm/mach-s3c24xx/Kconfig"
1105 source "arch/arm/mach-s3c2412/Kconfig"
1106 source "arch/arm/mach-s3c2440/Kconfig"
1110 source "arch/arm/mach-s3c64xx/Kconfig"
1113 source "arch/arm/mach-s5p64x0/Kconfig"
1115 source "arch/arm/mach-s5pc100/Kconfig"
1117 source "arch/arm/mach-s5pv210/Kconfig"
1119 source "arch/arm/mach-exynos/Kconfig"
1121 source "arch/arm/mach-shmobile/Kconfig"
1123 source "arch/arm/mach-tegra/Kconfig"
1125 source "arch/arm/mach-u300/Kconfig"
1127 source "arch/arm/mach-ux500/Kconfig"
1129 source "arch/arm/mach-versatile/Kconfig"
1131 source "arch/arm/mach-vexpress/Kconfig"
1132 source "arch/arm/plat-versatile/Kconfig"
1134 source "arch/arm/mach-vt8500/Kconfig"
1136 source "arch/arm/mach-w90x900/Kconfig"
1138 # Definitions to make life easier
1144 select GENERIC_CLOCKEVENTS
1149 select GENERIC_IRQ_CHIP
1156 config PLAT_VERSATILE
1159 config ARM_TIMER_SP804
1162 select HAVE_SCHED_CLOCK
1164 source arch/arm/mm/Kconfig
1168 default 16 if ARCH_EP93XX
1172 bool "Enable iWMMXt support"
1173 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1174 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1176 Enable support for iWMMXt context switching at run time if
1177 running on a CPU that supports it.
1181 depends on CPU_XSCALE
1185 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1186 (!ARCH_OMAP3 || OMAP3_EMU)
1190 config MULTI_IRQ_HANDLER
1193 Allow each machine to specify it's own IRQ handler at run time.
1196 source "arch/arm/Kconfig-nommu"
1199 config ARM_ERRATA_326103
1200 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1203 Executing a SWP instruction to read-only memory does not set bit 11
1204 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1205 treat the access as a read, preventing a COW from occurring and
1206 causing the faulting task to livelock.
1208 config ARM_ERRATA_411920
1209 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1210 depends on CPU_V6 || CPU_V6K
1212 Invalidation of the Instruction Cache operation can
1213 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1214 It does not affect the MPCore. This option enables the ARM Ltd.
1215 recommended workaround.
1217 config ARM_ERRATA_430973
1218 bool "ARM errata: Stale prediction on replaced interworking branch"
1221 This option enables the workaround for the 430973 Cortex-A8
1222 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1223 interworking branch is replaced with another code sequence at the
1224 same virtual address, whether due to self-modifying code or virtual
1225 to physical address re-mapping, Cortex-A8 does not recover from the
1226 stale interworking branch prediction. This results in Cortex-A8
1227 executing the new code sequence in the incorrect ARM or Thumb state.
1228 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1229 and also flushes the branch target cache at every context switch.
1230 Note that setting specific bits in the ACTLR register may not be
1231 available in non-secure mode.
1233 config ARM_ERRATA_458693
1234 bool "ARM errata: Processor deadlock when a false hazard is created"
1237 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1238 erratum. For very specific sequences of memory operations, it is
1239 possible for a hazard condition intended for a cache line to instead
1240 be incorrectly associated with a different cache line. This false
1241 hazard might then cause a processor deadlock. The workaround enables
1242 the L1 caching of the NEON accesses and disables the PLD instruction
1243 in the ACTLR register. Note that setting specific bits in the ACTLR
1244 register may not be available in non-secure mode.
1246 config ARM_ERRATA_460075
1247 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1250 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1251 erratum. Any asynchronous access to the L2 cache may encounter a
1252 situation in which recent store transactions to the L2 cache are lost
1253 and overwritten with stale memory contents from external memory. The
1254 workaround disables the write-allocate mode for the L2 cache via the
1255 ACTLR register. Note that setting specific bits in the ACTLR register
1256 may not be available in non-secure mode.
1258 config ARM_ERRATA_742230
1259 bool "ARM errata: DMB operation may be faulty"
1260 depends on CPU_V7 && SMP
1262 This option enables the workaround for the 742230 Cortex-A9
1263 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1264 between two write operations may not ensure the correct visibility
1265 ordering of the two writes. This workaround sets a specific bit in
1266 the diagnostic register of the Cortex-A9 which causes the DMB
1267 instruction to behave as a DSB, ensuring the correct behaviour of
1270 config ARM_ERRATA_742231
1271 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1272 depends on CPU_V7 && SMP
1274 This option enables the workaround for the 742231 Cortex-A9
1275 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1276 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1277 accessing some data located in the same cache line, may get corrupted
1278 data due to bad handling of the address hazard when the line gets
1279 replaced from one of the CPUs at the same time as another CPU is
1280 accessing it. This workaround sets specific bits in the diagnostic
1281 register of the Cortex-A9 which reduces the linefill issuing
1282 capabilities of the processor.
1284 config PL310_ERRATA_588369
1285 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1286 depends on CACHE_L2X0
1288 The PL310 L2 cache controller implements three types of Clean &
1289 Invalidate maintenance operations: by Physical Address
1290 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1291 They are architecturally defined to behave as the execution of a
1292 clean operation followed immediately by an invalidate operation,
1293 both performing to the same memory location. This functionality
1294 is not correctly implemented in PL310 as clean lines are not
1295 invalidated as a result of these operations.
1297 config ARM_ERRATA_720789
1298 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1301 This option enables the workaround for the 720789 Cortex-A9 (prior to
1302 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1303 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1304 As a consequence of this erratum, some TLB entries which should be
1305 invalidated are not, resulting in an incoherency in the system page
1306 tables. The workaround changes the TLB flushing routines to invalidate
1307 entries regardless of the ASID.
1309 config PL310_ERRATA_727915
1310 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1311 depends on CACHE_L2X0
1313 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1314 operation (offset 0x7FC). This operation runs in background so that
1315 PL310 can handle normal accesses while it is in progress. Under very
1316 rare circumstances, due to this erratum, write data can be lost when
1317 PL310 treats a cacheable write transaction during a Clean &
1318 Invalidate by Way operation.
1320 config ARM_ERRATA_743622
1321 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1324 This option enables the workaround for the 743622 Cortex-A9
1325 (r2p*) erratum. Under very rare conditions, a faulty
1326 optimisation in the Cortex-A9 Store Buffer may lead to data
1327 corruption. This workaround sets a specific bit in the diagnostic
1328 register of the Cortex-A9 which disables the Store Buffer
1329 optimisation, preventing the defect from occurring. This has no
1330 visible impact on the overall performance or power consumption of the
1333 config ARM_ERRATA_751472
1334 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1337 This option enables the workaround for the 751472 Cortex-A9 (prior
1338 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1339 completion of a following broadcasted operation if the second
1340 operation is received by a CPU before the ICIALLUIS has completed,
1341 potentially leading to corrupted entries in the cache or TLB.
1343 config PL310_ERRATA_753970
1344 bool "PL310 errata: cache sync operation may be faulty"
1345 depends on CACHE_PL310
1347 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1349 Under some condition the effect of cache sync operation on
1350 the store buffer still remains when the operation completes.
1351 This means that the store buffer is always asked to drain and
1352 this prevents it from merging any further writes. The workaround
1353 is to replace the normal offset of cache sync operation (0x730)
1354 by another offset targeting an unmapped PL310 register 0x740.
1355 This has the same effect as the cache sync operation: store buffer
1356 drain and waiting for all buffers empty.
1358 config ARM_ERRATA_754322
1359 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1362 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1363 r3p*) erratum. A speculative memory access may cause a page table walk
1364 which starts prior to an ASID switch but completes afterwards. This
1365 can populate the micro-TLB with a stale entry which may be hit with
1366 the new ASID. This workaround places two dsb instructions in the mm
1367 switching code so that no page table walks can cross the ASID switch.
1369 config ARM_ERRATA_754327
1370 bool "ARM errata: no automatic Store Buffer drain"
1371 depends on CPU_V7 && SMP
1373 This option enables the workaround for the 754327 Cortex-A9 (prior to
1374 r2p0) erratum. The Store Buffer does not have any automatic draining
1375 mechanism and therefore a livelock may occur if an external agent
1376 continuously polls a memory location waiting to observe an update.
1377 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1378 written polling loops from denying visibility of updates to memory.
1380 config ARM_ERRATA_364296
1381 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1382 depends on CPU_V6 && !SMP
1384 This options enables the workaround for the 364296 ARM1136
1385 r0p2 erratum (possible cache data corruption with
1386 hit-under-miss enabled). It sets the undocumented bit 31 in
1387 the auxiliary control register and the FI bit in the control
1388 register, thus disabling hit-under-miss without putting the
1389 processor into full low interrupt latency mode. ARM11MPCore
1392 config ARM_ERRATA_764369
1393 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1394 depends on CPU_V7 && SMP
1396 This option enables the workaround for erratum 764369
1397 affecting Cortex-A9 MPCore with two or more processors (all
1398 current revisions). Under certain timing circumstances, a data
1399 cache line maintenance operation by MVA targeting an Inner
1400 Shareable memory region may fail to proceed up to either the
1401 Point of Coherency or to the Point of Unification of the
1402 system. This workaround adds a DSB instruction before the
1403 relevant cache maintenance functions and sets a specific bit
1404 in the diagnostic control register of the SCU.
1406 config PL310_ERRATA_769419
1407 bool "PL310 errata: no automatic Store Buffer drain"
1408 depends on CACHE_L2X0
1410 On revisions of the PL310 prior to r3p2, the Store Buffer does
1411 not automatically drain. This can cause normal, non-cacheable
1412 writes to be retained when the memory system is idle, leading
1413 to suboptimal I/O performance for drivers using coherent DMA.
1414 This option adds a write barrier to the cpu_idle loop so that,
1415 on systems with an outer cache, the store buffer is drained
1420 source "arch/arm/common/Kconfig"
1430 Find out whether you have ISA slots on your motherboard. ISA is the
1431 name of a bus system, i.e. the way the CPU talks to the other stuff
1432 inside your box. Other bus systems are PCI, EISA, MicroChannel
1433 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1434 newer boards don't support it. If you have ISA, say Y, otherwise N.
1436 # Select ISA DMA controller support
1441 # Select ISA DMA interface
1446 bool "PCI support" if MIGHT_HAVE_PCI
1448 Find out whether you have a PCI motherboard. PCI is the name of a
1449 bus system, i.e. the way the CPU talks to the other stuff inside
1450 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1451 VESA. If you have PCI, say Y, otherwise N.
1457 config PCI_NANOENGINE
1458 bool "BSE nanoEngine PCI support"
1459 depends on SA1100_NANOENGINE
1461 Enable PCI on the BSE nanoEngine board.
1466 # Select the host bridge type
1467 config PCI_HOST_VIA82C505
1469 depends on PCI && ARCH_SHARK
1472 config PCI_HOST_ITE8152
1474 depends on PCI && MACH_ARMCORE
1478 source "drivers/pci/Kconfig"
1480 source "drivers/pcmcia/Kconfig"
1484 menu "Kernel Features"
1489 This option should be selected by machines which have an SMP-
1492 The only effect of this option is to make the SMP-related
1493 options available to the user for configuration.
1496 bool "Symmetric Multi-Processing"
1497 depends on CPU_V6K || CPU_V7
1498 depends on GENERIC_CLOCKEVENTS
1501 select USE_GENERIC_SMP_HELPERS
1502 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1504 This enables support for systems with more than one CPU. If you have
1505 a system with only one CPU, like most personal computers, say N. If
1506 you have a system with more than one CPU, say Y.
1508 If you say N here, the kernel will run on single and multiprocessor
1509 machines, but will use only one CPU of a multiprocessor machine. If
1510 you say Y here, the kernel will run on many, but not all, single
1511 processor machines. On a single processor machine, the kernel will
1512 run faster if you say N here.
1514 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1515 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1516 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1518 If you don't know what to do here, say N.
1521 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1522 depends on EXPERIMENTAL
1523 depends on SMP && !XIP_KERNEL
1526 SMP kernels contain instructions which fail on non-SMP processors.
1527 Enabling this option allows the kernel to modify itself to make
1528 these instructions safe. Disabling it allows about 1K of space
1531 If you don't know what to do here, say Y.
1533 config ARM_CPU_TOPOLOGY
1534 bool "Support cpu topology definition"
1535 depends on SMP && CPU_V7
1538 Support ARM cpu topology definition. The MPIDR register defines
1539 affinity between processors which is then used to describe the cpu
1540 topology of an ARM System.
1543 bool "Multi-core scheduler support"
1544 depends on ARM_CPU_TOPOLOGY
1546 Multi-core scheduler support improves the CPU scheduler's decision
1547 making when dealing with multi-core CPU chips at a cost of slightly
1548 increased overhead in some places. If unsure say N here.
1551 bool "SMT scheduler support"
1552 depends on ARM_CPU_TOPOLOGY
1554 Improves the CPU scheduler's decision making when dealing with
1555 MultiThreading at a cost of slightly increased overhead in some
1556 places. If unsure say N here.
1561 This option enables support for the ARM system coherency unit
1563 config ARM_ARCH_TIMER
1564 bool "Architected timer support"
1567 This option enables support for the ARM architected timer
1573 This options enables support for the ARM timer and watchdog unit
1576 prompt "Memory split"
1579 Select the desired split between kernel and user memory.
1581 If you are not absolutely sure what you are doing, leave this
1585 bool "3G/1G user/kernel split"
1587 bool "2G/2G user/kernel split"
1589 bool "1G/3G user/kernel split"
1594 default 0x40000000 if VMSPLIT_1G
1595 default 0x80000000 if VMSPLIT_2G
1599 int "Maximum number of CPUs (2-32)"
1605 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1606 depends on SMP && HOTPLUG && EXPERIMENTAL
1608 Say Y here to experiment with turning CPUs off and on. CPUs
1609 can be controlled through /sys/devices/system/cpu.
1612 bool "Use local timer interrupts"
1615 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1617 Enable support for local timers on SMP platforms, rather then the
1618 legacy IPI broadcast method. Local timers allows the system
1619 accounting to be spread across the timer interval, preventing a
1620 "thundering herd" at every timer tick.
1624 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1625 default 355 if ARCH_U8500
1626 default 264 if MACH_H4700
1627 default 512 if SOC_OMAP5
1630 Maximum number of GPIOs in the system.
1632 If unsure, leave the default value.
1634 source kernel/Kconfig.preempt
1638 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1639 ARCH_S5PV210 || ARCH_EXYNOS4
1640 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1641 default AT91_TIMER_HZ if ARCH_AT91
1642 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1645 config THUMB2_KERNEL
1646 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1647 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1649 select ARM_ASM_UNIFIED
1652 By enabling this option, the kernel will be compiled in
1653 Thumb-2 mode. A compiler/assembler that understand the unified
1654 ARM-Thumb syntax is needed.
1658 config THUMB2_AVOID_R_ARM_THM_JUMP11
1659 bool "Work around buggy Thumb-2 short branch relocations in gas"
1660 depends on THUMB2_KERNEL && MODULES
1663 Various binutils versions can resolve Thumb-2 branches to
1664 locally-defined, preemptible global symbols as short-range "b.n"
1665 branch instructions.
1667 This is a problem, because there's no guarantee the final
1668 destination of the symbol, or any candidate locations for a
1669 trampoline, are within range of the branch. For this reason, the
1670 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1671 relocation in modules at all, and it makes little sense to add
1674 The symptom is that the kernel fails with an "unsupported
1675 relocation" error when loading some modules.
1677 Until fixed tools are available, passing
1678 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1679 code which hits this problem, at the cost of a bit of extra runtime
1680 stack usage in some cases.
1682 The problem is described in more detail at:
1683 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1685 Only Thumb-2 kernels are affected.
1687 Unless you are sure your tools don't have this problem, say Y.
1689 config ARM_ASM_UNIFIED
1693 bool "Use the ARM EABI to compile the kernel"
1695 This option allows for the kernel to be compiled using the latest
1696 ARM ABI (aka EABI). This is only useful if you are using a user
1697 space environment that is also compiled with EABI.
1699 Since there are major incompatibilities between the legacy ABI and
1700 EABI, especially with regard to structure member alignment, this
1701 option also changes the kernel syscall calling convention to
1702 disambiguate both ABIs and allow for backward compatibility support
1703 (selected with CONFIG_OABI_COMPAT).
1705 To use this you need GCC version 4.0.0 or later.
1708 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1709 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1712 This option preserves the old syscall interface along with the
1713 new (ARM EABI) one. It also provides a compatibility layer to
1714 intercept syscalls that have structure arguments which layout
1715 in memory differs between the legacy ABI and the new ARM EABI
1716 (only for non "thumb" binaries). This option adds a tiny
1717 overhead to all syscalls and produces a slightly larger kernel.
1718 If you know you'll be using only pure EABI user space then you
1719 can say N here. If this option is not selected and you attempt
1720 to execute a legacy ABI binary then the result will be
1721 UNPREDICTABLE (in fact it can be predicted that it won't work
1722 at all). If in doubt say Y.
1724 config ARCH_HAS_HOLES_MEMORYMODEL
1727 config ARCH_SPARSEMEM_ENABLE
1730 config ARCH_SPARSEMEM_DEFAULT
1731 def_bool ARCH_SPARSEMEM_ENABLE
1733 config ARCH_SELECT_MEMORY_MODEL
1734 def_bool ARCH_SPARSEMEM_ENABLE
1736 config HAVE_ARCH_PFN_VALID
1737 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1740 bool "High Memory Support"
1743 The address space of ARM processors is only 4 Gigabytes large
1744 and it has to accommodate user address space, kernel address
1745 space as well as some memory mapped IO. That means that, if you
1746 have a large amount of physical memory and/or IO, not all of the
1747 memory can be "permanently mapped" by the kernel. The physical
1748 memory that is not permanently mapped is called "high memory".
1750 Depending on the selected kernel/user memory split, minimum
1751 vmalloc space and actual amount of RAM, you may not need this
1752 option which should result in a slightly faster kernel.
1757 bool "Allocate 2nd-level pagetables from highmem"
1760 config HW_PERF_EVENTS
1761 bool "Enable hardware performance counter support for perf events"
1762 depends on PERF_EVENTS && CPU_HAS_PMU
1765 Enable hardware performance counter support for perf events. If
1766 disabled, perf events will use software events only.
1770 config FORCE_MAX_ZONEORDER
1771 int "Maximum zone order" if ARCH_SHMOBILE
1772 range 11 64 if ARCH_SHMOBILE
1773 default "9" if SA1111
1776 The kernel memory allocator divides physically contiguous memory
1777 blocks into "zones", where each zone is a power of two number of
1778 pages. This option selects the largest power of two that the kernel
1779 keeps in the memory allocator. If you need to allocate very large
1780 blocks of physically contiguous memory, then you may need to
1781 increase this value.
1783 This config option is actually maximum order plus one. For example,
1784 a value of 11 means that the largest free memory block is 2^10 pages.
1787 bool "Timer and CPU usage LEDs"
1788 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1789 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1790 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1791 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1792 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1793 ARCH_AT91 || ARCH_DAVINCI || \
1794 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1796 If you say Y here, the LEDs on your machine will be used
1797 to provide useful information about your current system status.
1799 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1800 be able to select which LEDs are active using the options below. If
1801 you are compiling a kernel for the EBSA-110 or the LART however, the
1802 red LED will simply flash regularly to indicate that the system is
1803 still functional. It is safe to say Y here if you have a CATS
1804 system, but the driver will do nothing.
1807 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1808 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1809 || MACH_OMAP_PERSEUS2
1811 depends on !GENERIC_CLOCKEVENTS
1812 default y if ARCH_EBSA110
1814 If you say Y here, one of the system LEDs (the green one on the
1815 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1816 will flash regularly to indicate that the system is still
1817 operational. This is mainly useful to kernel hackers who are
1818 debugging unstable kernels.
1820 The LART uses the same LED for both Timer LED and CPU usage LED
1821 functions. You may choose to use both, but the Timer LED function
1822 will overrule the CPU usage LED.
1825 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1827 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1828 || MACH_OMAP_PERSEUS2
1831 If you say Y here, the red LED will be used to give a good real
1832 time indication of CPU usage, by lighting whenever the idle task
1833 is not currently executing.
1835 The LART uses the same LED for both Timer LED and CPU usage LED
1836 functions. You may choose to use both, but the Timer LED function
1837 will overrule the CPU usage LED.
1839 config ALIGNMENT_TRAP
1841 depends on CPU_CP15_MMU
1842 default y if !ARCH_EBSA110
1843 select HAVE_PROC_CPU if PROC_FS
1845 ARM processors cannot fetch/store information which is not
1846 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1847 address divisible by 4. On 32-bit ARM processors, these non-aligned
1848 fetch/store instructions will be emulated in software if you say
1849 here, which has a severe performance impact. This is necessary for
1850 correct operation of some network protocols. With an IP-only
1851 configuration it is safe to say N, otherwise say Y.
1853 config UACCESS_WITH_MEMCPY
1854 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1855 depends on MMU && EXPERIMENTAL
1856 default y if CPU_FEROCEON
1858 Implement faster copy_to_user and clear_user methods for CPU
1859 cores where a 8-word STM instruction give significantly higher
1860 memory write throughput than a sequence of individual 32bit stores.
1862 A possible side effect is a slight increase in scheduling latency
1863 between threads sharing the same address space if they invoke
1864 such copy operations with large buffers.
1866 However, if the CPU data cache is using a write-allocate mode,
1867 this option is unlikely to provide any performance gain.
1871 prompt "Enable seccomp to safely compute untrusted bytecode"
1873 This kernel feature is useful for number crunching applications
1874 that may need to compute untrusted bytecode during their
1875 execution. By using pipes or other transports made available to
1876 the process as file descriptors supporting the read/write
1877 syscalls, it's possible to isolate those applications in
1878 their own address space using seccomp. Once seccomp is
1879 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1880 and the task is only allowed to execute a few safe syscalls
1881 defined by each seccomp mode.
1883 config CC_STACKPROTECTOR
1884 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1885 depends on EXPERIMENTAL
1887 This option turns on the -fstack-protector GCC feature. This
1888 feature puts, at the beginning of functions, a canary value on
1889 the stack just before the return address, and validates
1890 the value just before actually returning. Stack based buffer
1891 overflows (that need to overwrite this return address) now also
1892 overwrite the canary, which gets detected and the attack is then
1893 neutralized via a kernel panic.
1894 This feature requires gcc version 4.2 or above.
1896 config DEPRECATED_PARAM_STRUCT
1897 bool "Provide old way to pass kernel parameters"
1899 This was deprecated in 2001 and announced to live on for 5 years.
1900 Some old boot loaders still use this way.
1907 bool "Flattened Device Tree support"
1909 select OF_EARLY_FLATTREE
1912 Include support for flattened device tree machine descriptions.
1914 # Compressed boot loader in ROM. Yes, we really want to ask about
1915 # TEXT and BSS so we preserve their values in the config files.
1916 config ZBOOT_ROM_TEXT
1917 hex "Compressed ROM boot loader base address"
1920 The physical address at which the ROM-able zImage is to be
1921 placed in the target. Platforms which normally make use of
1922 ROM-able zImage formats normally set this to a suitable
1923 value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1927 config ZBOOT_ROM_BSS
1928 hex "Compressed ROM boot loader BSS address"
1931 The base address of an area of read/write memory in the target
1932 for the ROM-able zImage which must be available while the
1933 decompressor is running. It must be large enough to hold the
1934 entire decompressed kernel plus an additional 128 KiB.
1935 Platforms which normally make use of ROM-able zImage formats
1936 normally set this to a suitable value in their defconfig file.
1938 If ZBOOT_ROM is not enabled, this has no effect.
1941 bool "Compressed boot loader in ROM/flash"
1942 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1944 Say Y here if you intend to execute your compressed kernel image
1945 (zImage) directly from ROM or flash. If unsure, say N.
1948 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1949 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1950 default ZBOOT_ROM_NONE
1952 Include experimental SD/MMC loading code in the ROM-able zImage.
1953 With this enabled it is possible to write the ROM-able zImage
1954 kernel image to an MMC or SD card and boot the kernel straight
1955 from the reset vector. At reset the processor Mask ROM will load
1956 the first part of the ROM-able zImage which in turn loads the
1957 rest the kernel image to RAM.
1959 config ZBOOT_ROM_NONE
1960 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1962 Do not load image from SD or MMC
1964 config ZBOOT_ROM_MMCIF
1965 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1967 Load image from MMCIF hardware block.
1969 config ZBOOT_ROM_SH_MOBILE_SDHI
1970 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1972 Load image from SDHI hardware block
1976 config ARM_APPENDED_DTB
1977 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1978 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1980 With this option, the boot code will look for a device tree binary
1981 (DTB) appended to zImage
1982 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1984 This is meant as a backward compatibility convenience for those
1985 systems with a bootloader that can't be upgraded to accommodate
1986 the documented boot protocol using a device tree.
1988 Beware that there is very little in terms of protection against
1989 this option being confused by leftover garbage in memory that might
1990 look like a DTB header after a reboot if no actual DTB is appended
1991 to zImage. Do not leave this option active in a production kernel
1992 if you don't intend to always append a DTB. Proper passing of the
1993 location into r2 of a bootloader provided DTB is always preferable
1996 config ARM_ATAG_DTB_COMPAT
1997 bool "Supplement the appended DTB with traditional ATAG information"
1998 depends on ARM_APPENDED_DTB
2000 Some old bootloaders can't be updated to a DTB capable one, yet
2001 they provide ATAGs with memory configuration, the ramdisk address,
2002 the kernel cmdline string, etc. Such information is dynamically
2003 provided by the bootloader and can't always be stored in a static
2004 DTB. To allow a device tree enabled kernel to be used with such
2005 bootloaders, this option allows zImage to extract the information
2006 from the ATAG list and store it at run time into the appended DTB.
2009 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2010 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2013 bool "Use bootloader kernel arguments if available"
2015 Uses the command-line options passed by the boot loader instead of
2016 the device tree bootargs property. If the boot loader doesn't provide
2017 any, the device tree bootargs property will be used.
2019 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2020 bool "Extend with bootloader kernel arguments"
2022 The command-line arguments provided by the boot loader will be
2023 appended to the the device tree bootargs property.
2028 string "Default kernel command string"
2031 On some architectures (EBSA110 and CATS), there is currently no way
2032 for the boot loader to pass arguments to the kernel. For these
2033 architectures, you should supply some command-line options at build
2034 time by entering them here. As a minimum, you should specify the
2035 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2038 prompt "Kernel command line type" if CMDLINE != ""
2039 default CMDLINE_FROM_BOOTLOADER
2041 config CMDLINE_FROM_BOOTLOADER
2042 bool "Use bootloader kernel arguments if available"
2044 Uses the command-line options passed by the boot loader. If
2045 the boot loader doesn't provide any, the default kernel command
2046 string provided in CMDLINE will be used.
2048 config CMDLINE_EXTEND
2049 bool "Extend bootloader kernel arguments"
2051 The command-line arguments provided by the boot loader will be
2052 appended to the default kernel command string.
2054 config CMDLINE_FORCE
2055 bool "Always use the default kernel command string"
2057 Always use the default kernel command string, even if the boot
2058 loader passes other arguments to the kernel.
2059 This is useful if you cannot or don't want to change the
2060 command-line options your boot loader passes to the kernel.
2064 bool "Kernel Execute-In-Place from ROM"
2065 depends on !ZBOOT_ROM && !ARM_LPAE
2067 Execute-In-Place allows the kernel to run from non-volatile storage
2068 directly addressable by the CPU, such as NOR flash. This saves RAM
2069 space since the text section of the kernel is not loaded from flash
2070 to RAM. Read-write sections, such as the data section and stack,
2071 are still copied to RAM. The XIP kernel is not compressed since
2072 it has to run directly from flash, so it will take more space to
2073 store it. The flash address used to link the kernel object files,
2074 and for storing it, is configuration dependent. Therefore, if you
2075 say Y here, you must know the proper physical address where to
2076 store the kernel image depending on your own flash memory usage.
2078 Also note that the make target becomes "make xipImage" rather than
2079 "make zImage" or "make Image". The final kernel binary to put in
2080 ROM memory will be arch/arm/boot/xipImage.
2084 config XIP_PHYS_ADDR
2085 hex "XIP Kernel Physical Location"
2086 depends on XIP_KERNEL
2087 default "0x00080000"
2089 This is the physical address in your flash memory the kernel will
2090 be linked for and stored to. This address is dependent on your
2094 bool "Kexec system call (EXPERIMENTAL)"
2095 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2097 kexec is a system call that implements the ability to shutdown your
2098 current kernel, and to start another kernel. It is like a reboot
2099 but it is independent of the system firmware. And like a reboot
2100 you can start any kernel with it, not just Linux.
2102 It is an ongoing process to be certain the hardware in a machine
2103 is properly shutdown, so do not be surprised if this code does not
2104 initially work for you. It may help to enable device hotplugging
2108 bool "Export atags in procfs"
2112 Should the atags used to boot the kernel be exported in an "atags"
2113 file in procfs. Useful with kexec.
2116 bool "Build kdump crash kernel (EXPERIMENTAL)"
2117 depends on EXPERIMENTAL
2119 Generate crash dump after being started by kexec. This should
2120 be normally only set in special crash dump kernels which are
2121 loaded in the main kernel with kexec-tools into a specially
2122 reserved region and then later executed after a crash by
2123 kdump/kexec. The crash dump kernel must be compiled to a
2124 memory address not used by the main kernel
2126 For more details see Documentation/kdump/kdump.txt
2128 config AUTO_ZRELADDR
2129 bool "Auto calculation of the decompressed kernel image address"
2130 depends on !ZBOOT_ROM && !ARCH_U300
2132 ZRELADDR is the physical address where the decompressed kernel
2133 image will be placed. If AUTO_ZRELADDR is selected, the address
2134 will be determined at run-time by masking the current IP with
2135 0xf8000000. This assumes the zImage being placed in the first 128MB
2136 from start of memory.
2140 menu "CPU Power Management"
2144 source "drivers/cpufreq/Kconfig"
2147 tristate "CPUfreq driver for i.MX CPUs"
2148 depends on ARCH_MXC && CPU_FREQ
2149 select CPU_FREQ_TABLE
2151 This enables the CPUfreq driver for i.MX CPUs.
2153 config CPU_FREQ_SA1100
2156 config CPU_FREQ_SA1110
2159 config CPU_FREQ_INTEGRATOR
2160 tristate "CPUfreq driver for ARM Integrator CPUs"
2161 depends on ARCH_INTEGRATOR && CPU_FREQ
2164 This enables the CPUfreq driver for ARM Integrator CPUs.
2166 For details, take a look at <file:Documentation/cpu-freq>.
2172 depends on CPU_FREQ && ARCH_PXA && PXA25x
2174 select CPU_FREQ_TABLE
2175 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2180 Internal configuration node for common cpufreq on Samsung SoC
2182 config CPU_FREQ_S3C24XX
2183 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2184 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2187 This enables the CPUfreq driver for the Samsung S3C24XX family
2190 For details, take a look at <file:Documentation/cpu-freq>.
2194 config CPU_FREQ_S3C24XX_PLL
2195 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2196 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2198 Compile in support for changing the PLL frequency from the
2199 S3C24XX series CPUfreq driver. The PLL takes time to settle
2200 after a frequency change, so by default it is not enabled.
2202 This also means that the PLL tables for the selected CPU(s) will
2203 be built which may increase the size of the kernel image.
2205 config CPU_FREQ_S3C24XX_DEBUG
2206 bool "Debug CPUfreq Samsung driver core"
2207 depends on CPU_FREQ_S3C24XX
2209 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2211 config CPU_FREQ_S3C24XX_IODEBUG
2212 bool "Debug CPUfreq Samsung driver IO timing"
2213 depends on CPU_FREQ_S3C24XX
2215 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2217 config CPU_FREQ_S3C24XX_DEBUGFS
2218 bool "Export debugfs for CPUFreq"
2219 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2221 Export status information via debugfs.
2225 source "drivers/cpuidle/Kconfig"
2229 menu "Floating point emulation"
2231 comment "At least one emulation must be selected"
2234 bool "NWFPE math emulation"
2235 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2237 Say Y to include the NWFPE floating point emulator in the kernel.
2238 This is necessary to run most binaries. Linux does not currently
2239 support floating point hardware so you need to say Y here even if
2240 your machine has an FPA or floating point co-processor podule.
2242 You may say N here if you are going to load the Acorn FPEmulator
2243 early in the bootup.
2246 bool "Support extended precision"
2247 depends on FPE_NWFPE
2249 Say Y to include 80-bit support in the kernel floating-point
2250 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2251 Note that gcc does not generate 80-bit operations by default,
2252 so in most cases this option only enlarges the size of the
2253 floating point emulator without any good reason.
2255 You almost surely want to say N here.
2258 bool "FastFPE math emulation (EXPERIMENTAL)"
2259 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2261 Say Y here to include the FAST floating point emulator in the kernel.
2262 This is an experimental much faster emulator which now also has full
2263 precision for the mantissa. It does not support any exceptions.
2264 It is very simple, and approximately 3-6 times faster than NWFPE.
2266 It should be sufficient for most programs. It may be not suitable
2267 for scientific calculations, but you have to check this for yourself.
2268 If you do not feel you need a faster FP emulation you should better
2272 bool "VFP-format floating point maths"
2273 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2275 Say Y to include VFP support code in the kernel. This is needed
2276 if your hardware includes a VFP unit.
2278 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2279 release notes and additional status information.
2281 Say N if your target does not have VFP hardware.
2289 bool "Advanced SIMD (NEON) Extension support"
2290 depends on VFPv3 && CPU_V7
2292 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2297 menu "Userspace binary formats"
2299 source "fs/Kconfig.binfmt"
2302 tristate "RISC OS personality"
2305 Say Y here to include the kernel code necessary if you want to run
2306 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2307 experimental; if this sounds frightening, say N and sleep in peace.
2308 You can also say M here to compile this support as a module (which
2309 will be called arthur).
2313 menu "Power management options"
2315 source "kernel/power/Kconfig"
2317 config ARCH_SUSPEND_POSSIBLE
2318 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2319 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2320 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2323 config ARM_CPU_SUSPEND
2328 source "net/Kconfig"
2330 source "drivers/Kconfig"
2334 source "arch/arm/Kconfig.debug"
2336 source "security/Kconfig"
2338 source "crypto/Kconfig"
2340 source "lib/Kconfig"