arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_MMAP_RND_BITS if MMU
  41         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  42         select HAVE_ARCH_TRACEHOOK
  43         select HAVE_ARM_SMCCC if CPU_V7
  44         select HAVE_BPF_JIT
  45         select HAVE_CC_STACKPROTECTOR
  46         select HAVE_CONTEXT_TRACKING
  47         select HAVE_C_RECORDMCOUNT
  48         select HAVE_DEBUG_KMEMLEAK
  49         select HAVE_DMA_API_DEBUG
  50         select HAVE_DMA_CONTIGUOUS if MMU
  51         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  53         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  54         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  55         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  56         select HAVE_GENERIC_DMA_COHERENT
  57         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  58         select HAVE_IDE if PCI || ISA || PCMCIA
  59         select HAVE_IRQ_TIME_ACCOUNTING
  60         select HAVE_KERNEL_GZIP
  61         select HAVE_KERNEL_LZ4
  62         select HAVE_KERNEL_LZMA
  63         select HAVE_KERNEL_LZO
  64         select HAVE_KERNEL_XZ
  65         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  66         select HAVE_KRETPROBES if (HAVE_KPROBES)
  67         select HAVE_MEMBLOCK
  68         select HAVE_MOD_ARCH_SPECIFIC
  69         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  70         select HAVE_OPTPROBES if !THUMB2_KERNEL
  71         select HAVE_PERF_EVENTS
  72         select HAVE_PERF_REGS
  73         select HAVE_PERF_USER_STACK_DUMP
  74         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  75         select HAVE_REGS_AND_STACK_ACCESS_API
  76         select HAVE_SYSCALL_TRACEPOINTS
  77         select HAVE_UID16
  78         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  79         select IRQ_FORCED_THREADING
  80         select MODULES_USE_ELF_REL
  81         select NO_BOOTMEM
  82         select OF_EARLY_FLATTREE if OF
  83         select OF_RESERVED_MEM if OF
  84         select OLD_SIGACTION
  85         select OLD_SIGSUSPEND3
  86         select PERF_USE_VMALLOC
  87         select RTC_LIB
  88         select SYS_SUPPORTS_APM_EMULATION
  89         # Above selects are sorted alphabetically; please add new ones
  90         # according to that.  Thanks.
  91         help
  92           The ARM series is a line of low-power-consumption RISC chip designs
  93           licensed by ARM Ltd and targeted at embedded applications and
  94           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  95           manufactured, but legacy ARM-based PC hardware remains popular in
  96           Europe.  There is an ARM Linux project with a web page at
  97           <http://www.arm.linux.org.uk/>.
  98
  99 config ARM_HAS_SG_CHAIN
 100         select ARCH_HAS_SG_CHAIN
 101         bool
 102
 103 config NEED_SG_DMA_LENGTH
 104         bool
 105
 106 config ARM_DMA_USE_IOMMU
 107         bool
 108         select ARM_HAS_SG_CHAIN
 109         select NEED_SG_DMA_LENGTH
 110
 111 if ARM_DMA_USE_IOMMU
 112
 113 config ARM_DMA_IOMMU_ALIGNMENT
 114         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 115         range 4 9
 116         default 8
 117         help
 118           DMA mapping framework by default aligns all buffers to the smallest
 119           PAGE_SIZE order which is greater than or equal to the requested buffer
 120           size. This works well for buffers up to a few hundreds kilobytes, but
 121           for larger buffers it just a waste of address space. Drivers which has
 122           relatively small addressing window (like 64Mib) might run out of
 123           virtual space with just a few allocations.
 124
 125           With this parameter you can specify the maximum PAGE_SIZE order for
 126           DMA IOMMU buffers. Larger buffers will be aligned only to this
 127           specified order. The order is expressed as a power of two multiplied
 128           by the PAGE_SIZE.
 129
 130 endif
 131
 132 config MIGHT_HAVE_PCI
 133         bool
 134
 135 config SYS_SUPPORTS_APM_EMULATION
 136         bool
 137
 138 config HAVE_TCM
 139         bool
 140         select GENERIC_ALLOCATOR
 141
 142 config HAVE_PROC_CPU
 143         bool
 144
 145 config NO_IOPORT_MAP
 146         bool
 147
 148 config EISA
 149         bool
 150         ---help---
 151           The Extended Industry Standard Architecture (EISA) bus was
 152           developed as an open alternative to the IBM MicroChannel bus.
 153
 154           The EISA bus provided some of the features of the IBM MicroChannel
 155           bus while maintaining backward compatibility with cards made for
 156           the older ISA bus.  The EISA bus saw limited use between 1988 and
 157           1995 when it was made obsolete by the PCI bus.
 158
 159           Say Y here if you are building a kernel for an EISA-based machine.
 160
 161           Otherwise, say N.
 162
 163 config SBUS
 164         bool
 165
 166 config STACKTRACE_SUPPORT
 167         bool
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         help
 243           Patch phys-to-virt and virt-to-phys translation functions at
 244           boot and module load time according to the position of the
 245           kernel in system memory.
 246
 247           This can only be used with non-XIP MMU kernels where the base
 248           of physical memory is at a 16MB boundary.
 249
 250           Only disable this option if you know that you do not require
 251           this feature (eg, building a kernel for a single machine) and
 252           you need to shrink the kernel to the minimal size.
 253
 254 config NEED_MACH_IO_H
 255         bool
 256         help
 257           Select this when mach/io.h is required to provide special
 258           definitions for this platform.  The need for mach/io.h should
 259           be avoided when possible.
 260
 261 config NEED_MACH_MEMORY_H
 262         bool
 263         help
 264           Select this when mach/memory.h is required to provide special
 265           definitions for this platform.  The need for mach/memory.h should
 266           be avoided when possible.
 267
 268 config PHYS_OFFSET
 269         hex "Physical address of main memory" if MMU
 270         depends on !ARM_PATCH_PHYS_VIRT
 271         default DRAM_BASE if !MMU
 272         default 0x00000000 if ARCH_EBSA110 || \
 273                         ARCH_FOOTBRIDGE || \
 274                         ARCH_INTEGRATOR || \
 275                         ARCH_IOP13XX || \
 276                         ARCH_KS8695 || \
 277                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 278         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 279         default 0x20000000 if ARCH_S5PV210
 280         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 281         default 0xc0000000 if ARCH_SA1100
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 config ARCH_MMAP_RND_BITS_MIN
 309         default 8
 310
 311 config ARCH_MMAP_RND_BITS_MAX
 312         default 14 if PAGE_OFFSET=0x40000000
 313         default 15 if PAGE_OFFSET=0x80000000
 314         default 16
 315
 316 #
 317 # The "ARM system type" choice list is ordered alphabetically by option
 318 # text.  Please add new entries in the option alphabetic order.
 319 #
 320 choice
 321         prompt "ARM system type"
 322         default ARM_SINGLE_ARMV7M if !MMU
 323         default ARCH_MULTIPLATFORM if MMU
 324
 325 config ARCH_MULTIPLATFORM
 326         bool "Allow multiple platforms to be selected"
 327         depends on MMU
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_HAS_SG_CHAIN
 330         select ARM_PATCH_PHYS_VIRT
 331         select AUTO_ZRELADDR
 332         select CLKSRC_OF
 333         select COMMON_CLK
 334         select GENERIC_CLOCKEVENTS
 335         select MIGHT_HAVE_PCI
 336         select MULTI_IRQ_HANDLER
 337         select SPARSE_IRQ
 338         select USE_OF
 339
 340 config ARM_SINGLE_ARMV7M
 341         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 342         depends on !MMU
 343         select ARCH_WANT_OPTIONAL_GPIOLIB
 344         select ARM_NVIC
 345         select AUTO_ZRELADDR
 346         select CLKSRC_OF
 347         select COMMON_CLK
 348         select CPU_V7M
 349         select GENERIC_CLOCKEVENTS
 350         select NO_IOPORT_MAP
 351         select SPARSE_IRQ
 352         select USE_OF
 353
 354
 355 config ARCH_CLPS711X
 356         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 357         select ARCH_REQUIRE_GPIOLIB
 358         select AUTO_ZRELADDR
 359         select CLKSRC_MMIO
 360         select COMMON_CLK
 361         select CPU_ARM720T
 362         select GENERIC_CLOCKEVENTS
 363         select MFD_SYSCON
 364         select SOC_BUS
 365         help
 366           Support for Cirrus Logic 711x/721x/731x based boards.
 367
 368 config ARCH_GEMINI
 369         bool "Cortina Systems Gemini"
 370         select ARCH_REQUIRE_GPIOLIB
 371         select CLKSRC_MMIO
 372         select CPU_FA526
 373         select GENERIC_CLOCKEVENTS
 374         help
 375           Support for the Cortina Systems Gemini family SoCs
 376
 377 config ARCH_EBSA110
 378         bool "EBSA-110"
 379         select ARCH_USES_GETTIMEOFFSET
 380         select CPU_SA110
 381         select ISA
 382         select NEED_MACH_IO_H
 383         select NEED_MACH_MEMORY_H
 384         select NO_IOPORT_MAP
 385         help
 386           This is an evaluation board for the StrongARM processor available
 387           from Digital. It has limited hardware on-board, including an
 388           Ethernet interface, two PCMCIA sockets, two serial ports and a
 389           parallel port.
 390
 391 config ARCH_EP93XX
 392         bool "EP93xx-based"
 393         select ARCH_HAS_HOLES_MEMORYMODEL
 394         select ARCH_REQUIRE_GPIOLIB
 395         select ARM_AMBA
 396         select ARM_PATCH_PHYS_VIRT
 397         select ARM_VIC
 398         select AUTO_ZRELADDR
 399         select CLKDEV_LOOKUP
 400         select CLKSRC_MMIO
 401         select CPU_ARM920T
 402         select GENERIC_CLOCKEVENTS
 403         help
 404           This enables support for the Cirrus EP93xx series of CPUs.
 405
 406 config ARCH_FOOTBRIDGE
 407         bool "FootBridge"
 408         select CPU_SA110
 409         select FOOTBRIDGE
 410         select GENERIC_CLOCKEVENTS
 411         select HAVE_IDE
 412         select NEED_MACH_IO_H if !MMU
 413         select NEED_MACH_MEMORY_H
 414         help
 415           Support for systems based on the DC21285 companion chip
 416           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 417
 418 config ARCH_NETX
 419         bool "Hilscher NetX based"
 420         select ARM_VIC
 421         select CLKSRC_MMIO
 422         select CPU_ARM926T
 423         select GENERIC_CLOCKEVENTS
 424         help
 425           This enables support for systems based on the Hilscher NetX Soc
 426
 427 config ARCH_IOP13XX
 428         bool "IOP13xx-based"
 429         depends on MMU
 430         select CPU_XSC3
 431         select NEED_MACH_MEMORY_H
 432         select NEED_RET_TO_USER
 433         select PCI
 434         select PLAT_IOP
 435         select VMSPLIT_1G
 436         select SPARSE_IRQ
 437         help
 438           Support for Intel's IOP13XX (XScale) family of processors.
 439
 440 config ARCH_IOP32X
 441         bool "IOP32x-based"
 442         depends on MMU
 443         select ARCH_REQUIRE_GPIOLIB
 444         select CPU_XSCALE
 445         select GPIO_IOP
 446         select NEED_RET_TO_USER
 447         select PCI
 448         select PLAT_IOP
 449         help
 450           Support for Intel's 80219 and IOP32X (XScale) family of
 451           processors.
 452
 453 config ARCH_IOP33X
 454         bool "IOP33x-based"
 455         depends on MMU
 456         select ARCH_REQUIRE_GPIOLIB
 457         select CPU_XSCALE
 458         select GPIO_IOP
 459         select NEED_RET_TO_USER
 460         select PCI
 461         select PLAT_IOP
 462         help
 463           Support for Intel's IOP33X (XScale) family of processors.
 464
 465 config ARCH_IXP4XX
 466         bool "IXP4xx-based"
 467         depends on MMU
 468         select ARCH_HAS_DMA_SET_COHERENT_MASK
 469         select ARCH_REQUIRE_GPIOLIB
 470         select ARCH_SUPPORTS_BIG_ENDIAN
 471         select CLKSRC_MMIO
 472         select CPU_XSCALE
 473         select DMABOUNCE if PCI
 474         select GENERIC_CLOCKEVENTS
 475         select MIGHT_HAVE_PCI
 476         select NEED_MACH_IO_H
 477         select USB_EHCI_BIG_ENDIAN_DESC
 478         select USB_EHCI_BIG_ENDIAN_MMIO
 479         help
 480           Support for Intel's IXP4XX (XScale) family of processors.
 481
 482 config ARCH_DOVE
 483         bool "Marvell Dove"
 484         select ARCH_REQUIRE_GPIOLIB
 485         select CPU_PJ4
 486         select GENERIC_CLOCKEVENTS
 487         select MIGHT_HAVE_PCI
 488         select MULTI_IRQ_HANDLER
 489         select MVEBU_MBUS
 490         select PINCTRL
 491         select PINCTRL_DOVE
 492         select PLAT_ORION_LEGACY
 493         select SPARSE_IRQ
 494         select PM_GENERIC_DOMAINS if PM
 495         help
 496           Support for the Marvell Dove SoC 88AP510
 497
 498 config ARCH_KS8695
 499         bool "Micrel/Kendin KS8695"
 500         select ARCH_REQUIRE_GPIOLIB
 501         select CLKSRC_MMIO
 502         select CPU_ARM922T
 503         select GENERIC_CLOCKEVENTS
 504         select NEED_MACH_MEMORY_H
 505         help
 506           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 507           System-on-Chip devices.
 508
 509 config ARCH_W90X900
 510         bool "Nuvoton W90X900 CPU"
 511         select ARCH_REQUIRE_GPIOLIB
 512         select CLKDEV_LOOKUP
 513         select CLKSRC_MMIO
 514         select CPU_ARM926T
 515         select GENERIC_CLOCKEVENTS
 516         help
 517           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 518           At present, the w90x900 has been renamed nuc900, regarding
 519           the ARM series product line, you can login the following
 520           link address to know more.
 521
 522           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 523                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 524
 525 config ARCH_LPC32XX
 526         bool "NXP LPC32XX"
 527         select ARCH_REQUIRE_GPIOLIB
 528         select ARM_AMBA
 529         select CLKDEV_LOOKUP
 530         select CLKSRC_MMIO
 531         select CPU_ARM926T
 532         select GENERIC_CLOCKEVENTS
 533         select HAVE_IDE
 534         select USE_OF
 535         help
 536           Support for the NXP LPC32XX family of processors
 537
 538 config ARCH_PXA
 539         bool "PXA2xx/PXA3xx-based"
 540         depends on MMU
 541         select ARCH_MTD_XIP
 542         select ARCH_REQUIRE_GPIOLIB
 543         select ARM_CPU_SUSPEND if PM
 544         select AUTO_ZRELADDR
 545         select COMMON_CLK
 546         select CLKDEV_LOOKUP
 547         select CLKSRC_PXA
 548         select CLKSRC_MMIO
 549         select CLKSRC_OF
 550         select GENERIC_CLOCKEVENTS
 551         select GPIO_PXA
 552         select HAVE_IDE
 553         select IRQ_DOMAIN
 554         select MULTI_IRQ_HANDLER
 555         select PLAT_PXA
 556         select SPARSE_IRQ
 557         help
 558           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 559
 560 config ARCH_RPC
 561         bool "RiscPC"
 562         depends on MMU
 563         select ARCH_ACORN
 564         select ARCH_MAY_HAVE_PC_FDC
 565         select ARCH_SPARSEMEM_ENABLE
 566         select ARCH_USES_GETTIMEOFFSET
 567         select CPU_SA110
 568         select FIQ
 569         select HAVE_IDE
 570         select HAVE_PATA_PLATFORM
 571         select ISA_DMA_API
 572         select NEED_MACH_IO_H
 573         select NEED_MACH_MEMORY_H
 574         select NO_IOPORT_MAP
 575         select VIRT_TO_BUS
 576         help
 577           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 578           CD-ROM interface, serial and parallel port, and the floppy drive.
 579
 580 config ARCH_SA1100
 581         bool "SA1100-based"
 582         select ARCH_MTD_XIP
 583         select ARCH_REQUIRE_GPIOLIB
 584         select ARCH_SPARSEMEM_ENABLE
 585         select CLKDEV_LOOKUP
 586         select CLKSRC_MMIO
 587         select CLKSRC_PXA
 588         select CLKSRC_OF if OF
 589         select CPU_FREQ
 590         select CPU_SA1100
 591         select GENERIC_CLOCKEVENTS
 592         select HAVE_IDE
 593         select IRQ_DOMAIN
 594         select ISA
 595         select MULTI_IRQ_HANDLER
 596         select NEED_MACH_MEMORY_H
 597         select SPARSE_IRQ
 598         help
 599           Support for StrongARM 11x0 based boards.
 600
 601 config ARCH_S3C24XX
 602         bool "Samsung S3C24XX SoCs"
 603         select ARCH_REQUIRE_GPIOLIB
 604         select ATAGS
 605         select CLKDEV_LOOKUP
 606         select CLKSRC_SAMSUNG_PWM
 607         select GENERIC_CLOCKEVENTS
 608         select GPIO_SAMSUNG
 609         select HAVE_S3C2410_I2C if I2C
 610         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 611         select HAVE_S3C_RTC if RTC_CLASS
 612         select MULTI_IRQ_HANDLER
 613         select NEED_MACH_IO_H
 614         select SAMSUNG_ATAGS
 615         help
 616           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 617           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 618           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 619           Samsung SMDK2410 development board (and derivatives).
 620
 621 config ARCH_DAVINCI
 622         bool "TI DaVinci"
 623         select ARCH_HAS_HOLES_MEMORYMODEL
 624         select ARCH_REQUIRE_GPIOLIB
 625         select CLKDEV_LOOKUP
 626         select GENERIC_ALLOCATOR
 627         select GENERIC_CLOCKEVENTS
 628         select GENERIC_IRQ_CHIP
 629         select HAVE_IDE
 630         select USE_OF
 631         select ZONE_DMA
 632         help
 633           Support for TI's DaVinci platform.
 634
 635 config ARCH_OMAP1
 636         bool "TI OMAP1"
 637         depends on MMU
 638         select ARCH_HAS_HOLES_MEMORYMODEL
 639         select ARCH_OMAP
 640         select ARCH_REQUIRE_GPIOLIB
 641         select CLKDEV_LOOKUP
 642         select CLKSRC_MMIO
 643         select GENERIC_CLOCKEVENTS
 644         select GENERIC_IRQ_CHIP
 645         select HAVE_IDE
 646         select IRQ_DOMAIN
 647         select MULTI_IRQ_HANDLER
 648         select NEED_MACH_IO_H if PCCARD
 649         select NEED_MACH_MEMORY_H
 650         select SPARSE_IRQ
 651         help
 652           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 653
 654 endchoice
 655
 656 menu "Multiple platform selection"
 657         depends on ARCH_MULTIPLATFORM
 658
 659 comment "CPU Core family selection"
 660
 661 config ARCH_MULTI_V4
 662         bool "ARMv4 based platforms (FA526)"
 663         depends on !ARCH_MULTI_V6_V7
 664         select ARCH_MULTI_V4_V5
 665         select CPU_FA526
 666
 667 config ARCH_MULTI_V4T
 668         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 669         depends on !ARCH_MULTI_V6_V7
 670         select ARCH_MULTI_V4_V5
 671         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 672                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 673                 CPU_ARM925T || CPU_ARM940T)
 674
 675 config ARCH_MULTI_V5
 676         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 677         depends on !ARCH_MULTI_V6_V7
 678         select ARCH_MULTI_V4_V5
 679         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 680                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 681                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 682
 683 config ARCH_MULTI_V4_V5
 684         bool
 685
 686 config ARCH_MULTI_V6
 687         bool "ARMv6 based platforms (ARM11)"
 688         select ARCH_MULTI_V6_V7
 689         select CPU_V6K
 690
 691 config ARCH_MULTI_V7
 692         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 693         default y
 694         select ARCH_MULTI_V6_V7
 695         select CPU_V7
 696         select HAVE_SMP
 697
 698 config ARCH_MULTI_V6_V7
 699         bool
 700         select MIGHT_HAVE_CACHE_L2X0
 701
 702 config ARCH_MULTI_CPU_AUTO
 703         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 704         select ARCH_MULTI_V5
 705
 706 endmenu
 707
 708 config ARCH_VIRT
 709         bool "Dummy Virtual Machine"
 710         depends on ARCH_MULTI_V7
 711         select ARM_AMBA
 712         select ARM_GIC
 713         select ARM_GIC_V2M if PCI_MSI
 714         select ARM_GIC_V3
 715         select ARM_PSCI
 716         select HAVE_ARM_ARCH_TIMER
 717
 718 #
 719 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 720 # Kconfigs may be included either alphabetically (according to the
 721 # plat- suffix) or along side the corresponding mach-* source.
 722 #
 723 source "arch/arm/mach-mvebu/Kconfig"
 724
 725 source "arch/arm/mach-alpine/Kconfig"
 726
 727 source "arch/arm/mach-artpec/Kconfig"
 728
 729 source "arch/arm/mach-asm9260/Kconfig"
 730
 731 source "arch/arm/mach-at91/Kconfig"
 732
 733 source "arch/arm/mach-axxia/Kconfig"
 734
 735 source "arch/arm/mach-bcm/Kconfig"
 736
 737 source "arch/arm/mach-berlin/Kconfig"
 738
 739 source "arch/arm/mach-clps711x/Kconfig"
 740
 741 source "arch/arm/mach-cns3xxx/Kconfig"
 742
 743 source "arch/arm/mach-davinci/Kconfig"
 744
 745 source "arch/arm/mach-digicolor/Kconfig"
 746
 747 source "arch/arm/mach-dove/Kconfig"
 748
 749 source "arch/arm/mach-ep93xx/Kconfig"
 750
 751 source "arch/arm/mach-footbridge/Kconfig"
 752
 753 source "arch/arm/mach-gemini/Kconfig"
 754
 755 source "arch/arm/mach-highbank/Kconfig"
 756
 757 source "arch/arm/mach-hisi/Kconfig"
 758
 759 source "arch/arm/mach-integrator/Kconfig"
 760
 761 source "arch/arm/mach-iop32x/Kconfig"
 762
 763 source "arch/arm/mach-iop33x/Kconfig"
 764
 765 source "arch/arm/mach-iop13xx/Kconfig"
 766
 767 source "arch/arm/mach-ixp4xx/Kconfig"
 768
 769 source "arch/arm/mach-keystone/Kconfig"
 770
 771 source "arch/arm/mach-ks8695/Kconfig"
 772
 773 source "arch/arm/mach-meson/Kconfig"
 774
 775 source "arch/arm/mach-moxart/Kconfig"
 776
 777 source "arch/arm/mach-mv78xx0/Kconfig"
 778
 779 source "arch/arm/mach-imx/Kconfig"
 780
 781 source "arch/arm/mach-mediatek/Kconfig"
 782
 783 source "arch/arm/mach-mxs/Kconfig"
 784
 785 source "arch/arm/mach-netx/Kconfig"
 786
 787 source "arch/arm/mach-nomadik/Kconfig"
 788
 789 source "arch/arm/mach-nspire/Kconfig"
 790
 791 source "arch/arm/plat-omap/Kconfig"
 792
 793 source "arch/arm/mach-omap1/Kconfig"
 794
 795 source "arch/arm/mach-omap2/Kconfig"
 796
 797 source "arch/arm/mach-orion5x/Kconfig"
 798
 799 source "arch/arm/mach-picoxcell/Kconfig"
 800
 801 source "arch/arm/mach-pxa/Kconfig"
 802 source "arch/arm/plat-pxa/Kconfig"
 803
 804 source "arch/arm/mach-mmp/Kconfig"
 805
 806 source "arch/arm/mach-qcom/Kconfig"
 807
 808 source "arch/arm/mach-realview/Kconfig"
 809
 810 source "arch/arm/mach-rockchip/Kconfig"
 811
 812 source "arch/arm/mach-sa1100/Kconfig"
 813
 814 source "arch/arm/mach-socfpga/Kconfig"
 815
 816 source "arch/arm/mach-spear/Kconfig"
 817
 818 source "arch/arm/mach-sti/Kconfig"
 819
 820 source "arch/arm/mach-s3c24xx/Kconfig"
 821
 822 source "arch/arm/mach-s3c64xx/Kconfig"
 823
 824 source "arch/arm/mach-s5pv210/Kconfig"
 825
 826 source "arch/arm/mach-exynos/Kconfig"
 827 source "arch/arm/plat-samsung/Kconfig"
 828
 829 source "arch/arm/mach-shmobile/Kconfig"
 830
 831 source "arch/arm/mach-sunxi/Kconfig"
 832
 833 source "arch/arm/mach-prima2/Kconfig"
 834
 835 source "arch/arm/mach-tango/Kconfig"
 836
 837 source "arch/arm/mach-tegra/Kconfig"
 838
 839 source "arch/arm/mach-u300/Kconfig"
 840
 841 source "arch/arm/mach-uniphier/Kconfig"
 842
 843 source "arch/arm/mach-ux500/Kconfig"
 844
 845 source "arch/arm/mach-versatile/Kconfig"
 846
 847 source "arch/arm/mach-vexpress/Kconfig"
 848 source "arch/arm/plat-versatile/Kconfig"
 849
 850 source "arch/arm/mach-vt8500/Kconfig"
 851
 852 source "arch/arm/mach-w90x900/Kconfig"
 853
 854 source "arch/arm/mach-zx/Kconfig"
 855
 856 source "arch/arm/mach-zynq/Kconfig"
 857
 858 # ARMv7-M architecture
 859 config ARCH_EFM32
 860         bool "Energy Micro efm32"
 861         depends on ARM_SINGLE_ARMV7M
 862         select ARCH_REQUIRE_GPIOLIB
 863         help
 864           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 865           processors.
 866
 867 config ARCH_LPC18XX
 868         bool "NXP LPC18xx/LPC43xx"
 869         depends on ARM_SINGLE_ARMV7M
 870         select ARCH_HAS_RESET_CONTROLLER
 871         select ARM_AMBA
 872         select CLKSRC_LPC32XX
 873         select PINCTRL
 874         help
 875           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 876           high performance microcontrollers.
 877
 878 config ARCH_STM32
 879         bool "STMicrolectronics STM32"
 880         depends on ARM_SINGLE_ARMV7M
 881         select ARCH_HAS_RESET_CONTROLLER
 882         select ARMV7M_SYSTICK
 883         select CLKSRC_STM32
 884         select PINCTRL
 885         select RESET_CONTROLLER
 886         help
 887           Support for STMicroelectronics STM32 processors.
 888
 889 config MACH_STM32F429
 890         bool "STMicrolectronics STM32F429"
 891         depends on ARCH_STM32
 892         default y
 893
 894 # Definitions to make life easier
 895 config ARCH_ACORN
 896         bool
 897
 898 config PLAT_IOP
 899         bool
 900         select GENERIC_CLOCKEVENTS
 901
 902 config PLAT_ORION
 903         bool
 904         select CLKSRC_MMIO
 905         select COMMON_CLK
 906         select GENERIC_IRQ_CHIP
 907         select IRQ_DOMAIN
 908
 909 config PLAT_ORION_LEGACY
 910         bool
 911         select PLAT_ORION
 912
 913 config PLAT_PXA
 914         bool
 915
 916 config PLAT_VERSATILE
 917         bool
 918
 919 source "arch/arm/firmware/Kconfig"
 920
 921 source arch/arm/mm/Kconfig
 922
 923 config IWMMXT
 924         bool "Enable iWMMXt support"
 925         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 926         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 927         help
 928           Enable support for iWMMXt context switching at run time if
 929           running on a CPU that supports it.
 930
 931 config MULTI_IRQ_HANDLER
 932         bool
 933         help
 934           Allow each machine to specify it's own IRQ handler at run time.
 935
 936 if !MMU
 937 source "arch/arm/Kconfig-nommu"
 938 endif
 939
 940 config PJ4B_ERRATA_4742
 941         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 942         depends on CPU_PJ4B && MACH_ARMADA_370
 943         default y
 944         help
 945           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 946           Event (WFE) IDLE states, a specific timing sensitivity exists between
 947           the retiring WFI/WFE instructions and the newly issued subsequent
 948           instructions.  This sensitivity can result in a CPU hang scenario.
 949           Workaround:
 950           The software must insert either a Data Synchronization Barrier (DSB)
 951           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 952           instruction
 953
 954 config ARM_ERRATA_326103
 955         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 956         depends on CPU_V6
 957         help
 958           Executing a SWP instruction to read-only memory does not set bit 11
 959           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 960           treat the access as a read, preventing a COW from occurring and
 961           causing the faulting task to livelock.
 962
 963 config ARM_ERRATA_411920
 964         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 965         depends on CPU_V6 || CPU_V6K
 966         help
 967           Invalidation of the Instruction Cache operation can
 968           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 969           It does not affect the MPCore. This option enables the ARM Ltd.
 970           recommended workaround.
 971
 972 config ARM_ERRATA_430973
 973         bool "ARM errata: Stale prediction on replaced interworking branch"
 974         depends on CPU_V7
 975         help
 976           This option enables the workaround for the 430973 Cortex-A8
 977           r1p* erratum. If a code sequence containing an ARM/Thumb
 978           interworking branch is replaced with another code sequence at the
 979           same virtual address, whether due to self-modifying code or virtual
 980           to physical address re-mapping, Cortex-A8 does not recover from the
 981           stale interworking branch prediction. This results in Cortex-A8
 982           executing the new code sequence in the incorrect ARM or Thumb state.
 983           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 984           and also flushes the branch target cache at every context switch.
 985           Note that setting specific bits in the ACTLR register may not be
 986           available in non-secure mode.
 987
 988 config ARM_ERRATA_458693
 989         bool "ARM errata: Processor deadlock when a false hazard is created"
 990         depends on CPU_V7
 991         depends on !ARCH_MULTIPLATFORM
 992         help
 993           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 994           erratum. For very specific sequences of memory operations, it is
 995           possible for a hazard condition intended for a cache line to instead
 996           be incorrectly associated with a different cache line. This false
 997           hazard might then cause a processor deadlock. The workaround enables
 998           the L1 caching of the NEON accesses and disables the PLD instruction
 999           in the ACTLR register. Note that setting specific bits in the ACTLR
1000           register may not be available in non-secure mode.
1001
1002 config ARM_ERRATA_460075
1003         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1004         depends on CPU_V7
1005         depends on !ARCH_MULTIPLATFORM
1006         help
1007           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1008           erratum. Any asynchronous access to the L2 cache may encounter a
1009           situation in which recent store transactions to the L2 cache are lost
1010           and overwritten with stale memory contents from external memory. The
1011           workaround disables the write-allocate mode for the L2 cache via the
1012           ACTLR register. Note that setting specific bits in the ACTLR register
1013           may not be available in non-secure mode.
1014
1015 config ARM_ERRATA_742230
1016         bool "ARM errata: DMB operation may be faulty"
1017         depends on CPU_V7 && SMP
1018         depends on !ARCH_MULTIPLATFORM
1019         help
1020           This option enables the workaround for the 742230 Cortex-A9
1021           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1022           between two write operations may not ensure the correct visibility
1023           ordering of the two writes. This workaround sets a specific bit in
1024           the diagnostic register of the Cortex-A9 which causes the DMB
1025           instruction to behave as a DSB, ensuring the correct behaviour of
1026           the two writes.
1027
1028 config ARM_ERRATA_742231
1029         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1030         depends on CPU_V7 && SMP
1031         depends on !ARCH_MULTIPLATFORM
1032         help
1033           This option enables the workaround for the 742231 Cortex-A9
1034           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1035           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1036           accessing some data located in the same cache line, may get corrupted
1037           data due to bad handling of the address hazard when the line gets
1038           replaced from one of the CPUs at the same time as another CPU is
1039           accessing it. This workaround sets specific bits in the diagnostic
1040           register of the Cortex-A9 which reduces the linefill issuing
1041           capabilities of the processor.
1042
1043 config ARM_ERRATA_643719
1044         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1045         depends on CPU_V7 && SMP
1046         default y
1047         help
1048           This option enables the workaround for the 643719 Cortex-A9 (prior to
1049           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1050           register returns zero when it should return one. The workaround
1051           corrects this value, ensuring cache maintenance operations which use
1052           it behave as intended and avoiding data corruption.
1053
1054 config ARM_ERRATA_720789
1055         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1056         depends on CPU_V7
1057         help
1058           This option enables the workaround for the 720789 Cortex-A9 (prior to
1059           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1060           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1061           As a consequence of this erratum, some TLB entries which should be
1062           invalidated are not, resulting in an incoherency in the system page
1063           tables. The workaround changes the TLB flushing routines to invalidate
1064           entries regardless of the ASID.
1065
1066 config ARM_ERRATA_743622
1067         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1068         depends on CPU_V7
1069         depends on !ARCH_MULTIPLATFORM
1070         help
1071           This option enables the workaround for the 743622 Cortex-A9
1072           (r2p*) erratum. Under very rare conditions, a faulty
1073           optimisation in the Cortex-A9 Store Buffer may lead to data
1074           corruption. This workaround sets a specific bit in the diagnostic
1075           register of the Cortex-A9 which disables the Store Buffer
1076           optimisation, preventing the defect from occurring. This has no
1077           visible impact on the overall performance or power consumption of the
1078           processor.
1079
1080 config ARM_ERRATA_751472
1081         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1082         depends on CPU_V7
1083         depends on !ARCH_MULTIPLATFORM
1084         help
1085           This option enables the workaround for the 751472 Cortex-A9 (prior
1086           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1087           completion of a following broadcasted operation if the second
1088           operation is received by a CPU before the ICIALLUIS has completed,
1089           potentially leading to corrupted entries in the cache or TLB.
1090
1091 config ARM_ERRATA_754322
1092         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1093         depends on CPU_V7
1094         help
1095           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1096           r3p*) erratum. A speculative memory access may cause a page table walk
1097           which starts prior to an ASID switch but completes afterwards. This
1098           can populate the micro-TLB with a stale entry which may be hit with
1099           the new ASID. This workaround places two dsb instructions in the mm
1100           switching code so that no page table walks can cross the ASID switch.
1101
1102 config ARM_ERRATA_754327
1103         bool "ARM errata: no automatic Store Buffer drain"
1104         depends on CPU_V7 && SMP
1105         help
1106           This option enables the workaround for the 754327 Cortex-A9 (prior to
1107           r2p0) erratum. The Store Buffer does not have any automatic draining
1108           mechanism and therefore a livelock may occur if an external agent
1109           continuously polls a memory location waiting to observe an update.
1110           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1111           written polling loops from denying visibility of updates to memory.
1112
1113 config ARM_ERRATA_364296
1114         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1115         depends on CPU_V6
1116         help
1117           This options enables the workaround for the 364296 ARM1136
1118           r0p2 erratum (possible cache data corruption with
1119           hit-under-miss enabled). It sets the undocumented bit 31 in
1120           the auxiliary control register and the FI bit in the control
1121           register, thus disabling hit-under-miss without putting the
1122           processor into full low interrupt latency mode. ARM11MPCore
1123           is not affected.
1124
1125 config ARM_ERRATA_764369
1126         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1127         depends on CPU_V7 && SMP
1128         help
1129           This option enables the workaround for erratum 764369
1130           affecting Cortex-A9 MPCore with two or more processors (all
1131           current revisions). Under certain timing circumstances, a data
1132           cache line maintenance operation by MVA targeting an Inner
1133           Shareable memory region may fail to proceed up to either the
1134           Point of Coherency or to the Point of Unification of the
1135           system. This workaround adds a DSB instruction before the
1136           relevant cache maintenance functions and sets a specific bit
1137           in the diagnostic control register of the SCU.
1138
1139 config ARM_ERRATA_775420
1140        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1141        depends on CPU_V7
1142        help
1143          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1144          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1145          operation aborts with MMU exception, it might cause the processor
1146          to deadlock. This workaround puts DSB before executing ISB if
1147          an abort may occur on cache maintenance.
1148
1149 config ARM_ERRATA_798181
1150         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1151         depends on CPU_V7 && SMP
1152         help
1153           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1154           adequately shooting down all use of the old entries. This
1155           option enables the Linux kernel workaround for this erratum
1156           which sends an IPI to the CPUs that are running the same ASID
1157           as the one being invalidated.
1158
1159 config ARM_ERRATA_773022
1160         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1161         depends on CPU_V7
1162         help
1163           This option enables the workaround for the 773022 Cortex-A15
1164           (up to r0p4) erratum. In certain rare sequences of code, the
1165           loop buffer may deliver incorrect instructions. This
1166           workaround disables the loop buffer to avoid the erratum.
1167
1168 endmenu
1169
1170 source "arch/arm/common/Kconfig"
1171
1172 menu "Bus support"
1173
1174 config ISA
1175         bool
1176         help
1177           Find out whether you have ISA slots on your motherboard.  ISA is the
1178           name of a bus system, i.e. the way the CPU talks to the other stuff
1179           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1180           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1181           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1182
1183 # Select ISA DMA controller support
1184 config ISA_DMA
1185         bool
1186         select ISA_DMA_API
1187
1188 # Select ISA DMA interface
1189 config ISA_DMA_API
1190         bool
1191
1192 config PCI
1193         bool "PCI support" if MIGHT_HAVE_PCI
1194         help
1195           Find out whether you have a PCI motherboard. PCI is the name of a
1196           bus system, i.e. the way the CPU talks to the other stuff inside
1197           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1198           VESA. If you have PCI, say Y, otherwise N.
1199
1200 config PCI_DOMAINS
1201         bool
1202         depends on PCI
1203
1204 config PCI_DOMAINS_GENERIC
1205         def_bool PCI_DOMAINS
1206
1207 config PCI_NANOENGINE
1208         bool "BSE nanoEngine PCI support"
1209         depends on SA1100_NANOENGINE
1210         help
1211           Enable PCI on the BSE nanoEngine board.
1212
1213 config PCI_SYSCALL
1214         def_bool PCI
1215
1216 config PCI_HOST_ITE8152
1217         bool
1218         depends on PCI && MACH_ARMCORE
1219         default y
1220         select DMABOUNCE
1221
1222 source "drivers/pci/Kconfig"
1223 source "drivers/pci/pcie/Kconfig"
1224
1225 source "drivers/pcmcia/Kconfig"
1226
1227 endmenu
1228
1229 menu "Kernel Features"
1230
1231 config HAVE_SMP
1232         bool
1233         help
1234           This option should be selected by machines which have an SMP-
1235           capable CPU.
1236
1237           The only effect of this option is to make the SMP-related
1238           options available to the user for configuration.
1239
1240 config SMP
1241         bool "Symmetric Multi-Processing"
1242         depends on CPU_V6K || CPU_V7
1243         depends on GENERIC_CLOCKEVENTS
1244         depends on HAVE_SMP
1245         depends on MMU || ARM_MPU
1246         select IRQ_WORK
1247         help
1248           This enables support for systems with more than one CPU. If you have
1249           a system with only one CPU, say N. If you have a system with more
1250           than one CPU, say Y.
1251
1252           If you say N here, the kernel will run on uni- and multiprocessor
1253           machines, but will use only one CPU of a multiprocessor machine. If
1254           you say Y here, the kernel will run on many, but not all,
1255           uniprocessor machines. On a uniprocessor machine, the kernel
1256           will run faster if you say N here.
1257
1258           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1259           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1260           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1261
1262           If you don't know what to do here, say N.
1263
1264 config SMP_ON_UP
1265         bool "Allow booting SMP kernel on uniprocessor systems"
1266         depends on SMP && !XIP_KERNEL && MMU
1267         default y
1268         help
1269           SMP kernels contain instructions which fail on non-SMP processors.
1270           Enabling this option allows the kernel to modify itself to make
1271           these instructions safe.  Disabling it allows about 1K of space
1272           savings.
1273
1274           If you don't know what to do here, say Y.
1275
1276 config ARM_CPU_TOPOLOGY
1277         bool "Support cpu topology definition"
1278         depends on SMP && CPU_V7
1279         default y
1280         help
1281           Support ARM cpu topology definition. The MPIDR register defines
1282           affinity between processors which is then used to describe the cpu
1283           topology of an ARM System.
1284
1285 config SCHED_MC
1286         bool "Multi-core scheduler support"
1287         depends on ARM_CPU_TOPOLOGY
1288         help
1289           Multi-core scheduler support improves the CPU scheduler's decision
1290           making when dealing with multi-core CPU chips at a cost of slightly
1291           increased overhead in some places. If unsure say N here.
1292
1293 config SCHED_SMT
1294         bool "SMT scheduler support"
1295         depends on ARM_CPU_TOPOLOGY
1296         help
1297           Improves the CPU scheduler's decision making when dealing with
1298           MultiThreading at a cost of slightly increased overhead in some
1299           places. If unsure say N here.
1300
1301 config HAVE_ARM_SCU
1302         bool
1303         help
1304           This option enables support for the ARM system coherency unit
1305
1306 config HAVE_ARM_ARCH_TIMER
1307         bool "Architected timer support"
1308         depends on CPU_V7
1309         select ARM_ARCH_TIMER
1310         select GENERIC_CLOCKEVENTS
1311         help
1312           This option enables support for the ARM architected timer
1313
1314 config HAVE_ARM_TWD
1315         bool
1316         select CLKSRC_OF if OF
1317         help
1318           This options enables support for the ARM timer and watchdog unit
1319
1320 config MCPM
1321         bool "Multi-Cluster Power Management"
1322         depends on CPU_V7 && SMP
1323         help
1324           This option provides the common power management infrastructure
1325           for (multi-)cluster based systems, such as big.LITTLE based
1326           systems.
1327
1328 config MCPM_QUAD_CLUSTER
1329         bool
1330         depends on MCPM
1331         help
1332           To avoid wasting resources unnecessarily, MCPM only supports up
1333           to 2 clusters by default.
1334           Platforms with 3 or 4 clusters that use MCPM must select this
1335           option to allow the additional clusters to be managed.
1336
1337 config BIG_LITTLE
1338         bool "big.LITTLE support (Experimental)"
1339         depends on CPU_V7 && SMP
1340         select MCPM
1341         help
1342           This option enables support selections for the big.LITTLE
1343           system architecture.
1344
1345 config BL_SWITCHER
1346         bool "big.LITTLE switcher support"
1347         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1348         select ARM_CPU_SUSPEND
1349         select CPU_PM
1350         help
1351           The big.LITTLE "switcher" provides the core functionality to
1352           transparently handle transition between a cluster of A15's
1353           and a cluster of A7's in a big.LITTLE system.
1354
1355 config BL_SWITCHER_DUMMY_IF
1356         tristate "Simple big.LITTLE switcher user interface"
1357         depends on BL_SWITCHER && DEBUG_KERNEL
1358         help
1359           This is a simple and dummy char dev interface to control
1360           the big.LITTLE switcher core code.  It is meant for
1361           debugging purposes only.
1362
1363 choice
1364         prompt "Memory split"
1365         depends on MMU
1366         default VMSPLIT_3G
1367         help
1368           Select the desired split between kernel and user memory.
1369
1370           If you are not absolutely sure what you are doing, leave this
1371           option alone!
1372
1373         config VMSPLIT_3G
1374                 bool "3G/1G user/kernel split"
1375         config VMSPLIT_3G_OPT
1376                 bool "3G/1G user/kernel split (for full 1G low memory)"
1377         config VMSPLIT_2G
1378                 bool "2G/2G user/kernel split"
1379         config VMSPLIT_1G
1380                 bool "1G/3G user/kernel split"
1381 endchoice
1382
1383 config PAGE_OFFSET
1384         hex
1385         default PHYS_OFFSET if !MMU
1386         default 0x40000000 if VMSPLIT_1G
1387         default 0x80000000 if VMSPLIT_2G
1388         default 0xB0000000 if VMSPLIT_3G_OPT
1389         default 0xC0000000
1390
1391 config NR_CPUS
1392         int "Maximum number of CPUs (2-32)"
1393         range 2 32
1394         depends on SMP
1395         default "4"
1396
1397 config HOTPLUG_CPU
1398         bool "Support for hot-pluggable CPUs"
1399         depends on SMP
1400         help
1401           Say Y here to experiment with turning CPUs off and on.  CPUs
1402           can be controlled through /sys/devices/system/cpu.
1403
1404 config ARM_PSCI
1405         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1406         depends on HAVE_ARM_SMCCC
1407         select ARM_PSCI_FW
1408         help
1409           Say Y here if you want Linux to communicate with system firmware
1410           implementing the PSCI specification for CPU-centric power
1411           management operations described in ARM document number ARM DEN
1412           0022A ("Power State Coordination Interface System Software on
1413           ARM processors").
1414
1415 # The GPIO number here must be sorted by descending number. In case of
1416 # a multiplatform kernel, we just want the highest value required by the
1417 # selected platforms.
1418 config ARCH_NR_GPIO
1419         int
1420         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1421                 ARCH_ZYNQ
1422         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1423                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1424         default 416 if ARCH_SUNXI
1425         default 392 if ARCH_U8500
1426         default 352 if ARCH_VT8500
1427         default 288 if ARCH_ROCKCHIP
1428         default 264 if MACH_H4700
1429         default 0
1430         help
1431           Maximum number of GPIOs in the system.
1432
1433           If unsure, leave the default value.
1434
1435 source kernel/Kconfig.preempt
1436
1437 config HZ_FIXED
1438         int
1439         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1440                 ARCH_S5PV210 || ARCH_EXYNOS4
1441         default 128 if SOC_AT91RM9200
1442         default 0
1443
1444 choice
1445         depends on HZ_FIXED = 0
1446         prompt "Timer frequency"
1447
1448 config HZ_100
1449         bool "100 Hz"
1450
1451 config HZ_200
1452         bool "200 Hz"
1453
1454 config HZ_250
1455         bool "250 Hz"
1456
1457 config HZ_300
1458         bool "300 Hz"
1459
1460 config HZ_500
1461         bool "500 Hz"
1462
1463 config HZ_1000
1464         bool "1000 Hz"
1465
1466 endchoice
1467
1468 config HZ
1469         int
1470         default HZ_FIXED if HZ_FIXED != 0
1471         default 100 if HZ_100
1472         default 200 if HZ_200
1473         default 250 if HZ_250
1474         default 300 if HZ_300
1475         default 500 if HZ_500
1476         default 1000
1477
1478 config SCHED_HRTICK
1479         def_bool HIGH_RES_TIMERS
1480
1481 config THUMB2_KERNEL
1482         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1483         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1484         default y if CPU_THUMBONLY
1485         select AEABI
1486         select ARM_ASM_UNIFIED
1487         select ARM_UNWIND
1488         help
1489           By enabling this option, the kernel will be compiled in
1490           Thumb-2 mode. A compiler/assembler that understand the unified
1491           ARM-Thumb syntax is needed.
1492
1493           If unsure, say N.
1494
1495 config THUMB2_AVOID_R_ARM_THM_JUMP11
1496         bool "Work around buggy Thumb-2 short branch relocations in gas"
1497         depends on THUMB2_KERNEL && MODULES
1498         default y
1499         help
1500           Various binutils versions can resolve Thumb-2 branches to
1501           locally-defined, preemptible global symbols as short-range "b.n"
1502           branch instructions.
1503
1504           This is a problem, because there's no guarantee the final
1505           destination of the symbol, or any candidate locations for a
1506           trampoline, are within range of the branch.  For this reason, the
1507           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1508           relocation in modules at all, and it makes little sense to add
1509           support.
1510
1511           The symptom is that the kernel fails with an "unsupported
1512           relocation" error when loading some modules.
1513
1514           Until fixed tools are available, passing
1515           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1516           code which hits this problem, at the cost of a bit of extra runtime
1517           stack usage in some cases.
1518
1519           The problem is described in more detail at:
1520               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1521
1522           Only Thumb-2 kernels are affected.
1523
1524           Unless you are sure your tools don't have this problem, say Y.
1525
1526 config ARM_ASM_UNIFIED
1527         bool
1528
1529 config ARM_PATCH_IDIV
1530         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1531         depends on CPU_32v7 && !XIP_KERNEL
1532         default y
1533         help
1534           The ARM compiler inserts calls to __aeabi_idiv() and
1535           __aeabi_uidiv() when it needs to perform division on signed
1536           and unsigned integers. Some v7 CPUs have support for the sdiv
1537           and udiv instructions that can be used to implement those
1538           functions.
1539
1540           Enabling this option allows the kernel to modify itself to
1541           replace the first two instructions of these library functions
1542           with the sdiv or udiv plus "bx lr" instructions when the CPU
1543           it is running on supports them. Typically this will be faster
1544           and less power intensive than running the original library
1545           code to do integer division.
1546
1547 config AEABI
1548         bool "Use the ARM EABI to compile the kernel"
1549         help
1550           This option allows for the kernel to be compiled using the latest
1551           ARM ABI (aka EABI).  This is only useful if you are using a user
1552           space environment that is also compiled with EABI.
1553
1554           Since there are major incompatibilities between the legacy ABI and
1555           EABI, especially with regard to structure member alignment, this
1556           option also changes the kernel syscall calling convention to
1557           disambiguate both ABIs and allow for backward compatibility support
1558           (selected with CONFIG_OABI_COMPAT).
1559
1560           To use this you need GCC version 4.0.0 or later.
1561
1562 config OABI_COMPAT
1563         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1564         depends on AEABI && !THUMB2_KERNEL
1565         help
1566           This option preserves the old syscall interface along with the
1567           new (ARM EABI) one. It also provides a compatibility layer to
1568           intercept syscalls that have structure arguments which layout
1569           in memory differs between the legacy ABI and the new ARM EABI
1570           (only for non "thumb" binaries). This option adds a tiny
1571           overhead to all syscalls and produces a slightly larger kernel.
1572
1573           The seccomp filter system will not be available when this is
1574           selected, since there is no way yet to sensibly distinguish
1575           between calling conventions during filtering.
1576
1577           If you know you'll be using only pure EABI user space then you
1578           can say N here. If this option is not selected and you attempt
1579           to execute a legacy ABI binary then the result will be
1580           UNPREDICTABLE (in fact it can be predicted that it won't work
1581           at all). If in doubt say N.
1582
1583 config ARCH_HAS_HOLES_MEMORYMODEL
1584         bool
1585
1586 config ARCH_SPARSEMEM_ENABLE
1587         bool
1588
1589 config ARCH_SPARSEMEM_DEFAULT
1590         def_bool ARCH_SPARSEMEM_ENABLE
1591
1592 config ARCH_SELECT_MEMORY_MODEL
1593         def_bool ARCH_SPARSEMEM_ENABLE
1594
1595 config HAVE_ARCH_PFN_VALID
1596         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1597
1598 config HAVE_GENERIC_RCU_GUP
1599         def_bool y
1600         depends on ARM_LPAE
1601
1602 config HIGHMEM
1603         bool "High Memory Support"
1604         depends on MMU
1605         help
1606           The address space of ARM processors is only 4 Gigabytes large
1607           and it has to accommodate user address space, kernel address
1608           space as well as some memory mapped IO. That means that, if you
1609           have a large amount of physical memory and/or IO, not all of the
1610           memory can be "permanently mapped" by the kernel. The physical
1611           memory that is not permanently mapped is called "high memory".
1612
1613           Depending on the selected kernel/user memory split, minimum
1614           vmalloc space and actual amount of RAM, you may not need this
1615           option which should result in a slightly faster kernel.
1616
1617           If unsure, say n.
1618
1619 config HIGHPTE
1620         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1621         depends on HIGHMEM
1622         default y
1623         help
1624           The VM uses one page of physical memory for each page table.
1625           For systems with a lot of processes, this can use a lot of
1626           precious low memory, eventually leading to low memory being
1627           consumed by page tables.  Setting this option will allow
1628           user-space 2nd level page tables to reside in high memory.
1629
1630 config CPU_SW_DOMAIN_PAN
1631         bool "Enable use of CPU domains to implement privileged no-access"
1632         depends on MMU && !ARM_LPAE
1633         default y
1634         help
1635           Increase kernel security by ensuring that normal kernel accesses
1636           are unable to access userspace addresses.  This can help prevent
1637           use-after-free bugs becoming an exploitable privilege escalation
1638           by ensuring that magic values (such as LIST_POISON) will always
1639           fault when dereferenced.
1640
1641           CPUs with low-vector mappings use a best-efforts implementation.
1642           Their lower 1MB needs to remain accessible for the vectors, but
1643           the remainder of userspace will become appropriately inaccessible.
1644
1645 config HW_PERF_EVENTS
1646         def_bool y
1647         depends on ARM_PMU
1648
1649 config SYS_SUPPORTS_HUGETLBFS
1650        def_bool y
1651        depends on ARM_LPAE
1652
1653 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1654        def_bool y
1655        depends on ARM_LPAE
1656
1657 config ARCH_WANT_GENERAL_HUGETLB
1658         def_bool y
1659
1660 config ARM_MODULE_PLTS
1661         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1662         depends on MODULES
1663         help
1664           Allocate PLTs when loading modules so that jumps and calls whose
1665           targets are too far away for their relative offsets to be encoded
1666           in the instructions themselves can be bounced via veneers in the
1667           module's PLT. This allows modules to be allocated in the generic
1668           vmalloc area after the dedicated module memory area has been
1669           exhausted. The modules will use slightly more memory, but after
1670           rounding up to page size, the actual memory footprint is usually
1671           the same.
1672
1673           Say y if you are getting out of memory errors while loading modules
1674
1675 source "mm/Kconfig"
1676
1677 config FORCE_MAX_ZONEORDER
1678         int "Maximum zone order"
1679         default "12" if SOC_AM33XX
1680         default "9" if SA1111 || ARCH_EFM32
1681         default "11"
1682         help
1683           The kernel memory allocator divides physically contiguous memory
1684           blocks into "zones", where each zone is a power of two number of
1685           pages.  This option selects the largest power of two that the kernel
1686           keeps in the memory allocator.  If you need to allocate very large
1687           blocks of physically contiguous memory, then you may need to
1688           increase this value.
1689
1690           This config option is actually maximum order plus one. For example,
1691           a value of 11 means that the largest free memory block is 2^10 pages.
1692
1693 config ALIGNMENT_TRAP
1694         bool
1695         depends on CPU_CP15_MMU
1696         default y if !ARCH_EBSA110
1697         select HAVE_PROC_CPU if PROC_FS
1698         help
1699           ARM processors cannot fetch/store information which is not
1700           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1701           address divisible by 4. On 32-bit ARM processors, these non-aligned
1702           fetch/store instructions will be emulated in software if you say
1703           here, which has a severe performance impact. This is necessary for
1704           correct operation of some network protocols. With an IP-only
1705           configuration it is safe to say N, otherwise say Y.
1706
1707 config UACCESS_WITH_MEMCPY
1708         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1709         depends on MMU
1710         default y if CPU_FEROCEON
1711         help
1712           Implement faster copy_to_user and clear_user methods for CPU
1713           cores where a 8-word STM instruction give significantly higher
1714           memory write throughput than a sequence of individual 32bit stores.
1715
1716           A possible side effect is a slight increase in scheduling latency
1717           between threads sharing the same address space if they invoke
1718           such copy operations with large buffers.
1719
1720           However, if the CPU data cache is using a write-allocate mode,
1721           this option is unlikely to provide any performance gain.
1722
1723 config SECCOMP
1724         bool
1725         prompt "Enable seccomp to safely compute untrusted bytecode"
1726         ---help---
1727           This kernel feature is useful for number crunching applications
1728           that may need to compute untrusted bytecode during their
1729           execution. By using pipes or other transports made available to
1730           the process as file descriptors supporting the read/write
1731           syscalls, it's possible to isolate those applications in
1732           their own address space using seccomp. Once seccomp is
1733           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1734           and the task is only allowed to execute a few safe syscalls
1735           defined by each seccomp mode.
1736
1737 config SWIOTLB
1738         def_bool y
1739
1740 config IOMMU_HELPER
1741         def_bool SWIOTLB
1742
1743 config PARAVIRT
1744         bool "Enable paravirtualization code"
1745         help
1746           This changes the kernel so it can modify itself when it is run
1747           under a hypervisor, potentially improving performance significantly
1748           over full virtualization.
1749
1750 config PARAVIRT_TIME_ACCOUNTING
1751         bool "Paravirtual steal time accounting"
1752         select PARAVIRT
1753         default n
1754         help
1755           Select this option to enable fine granularity task steal time
1756           accounting. Time spent executing other tasks in parallel with
1757           the current vCPU is discounted from the vCPU power. To account for
1758           that, there can be a small performance impact.
1759
1760           If in doubt, say N here.
1761
1762 config XEN_DOM0
1763         def_bool y
1764         depends on XEN
1765
1766 config XEN
1767         bool "Xen guest support on ARM"
1768         depends on ARM && AEABI && OF
1769         depends on CPU_V7 && !CPU_V6
1770         depends on !GENERIC_ATOMIC64
1771         depends on MMU
1772         select ARCH_DMA_ADDR_T_64BIT
1773         select ARM_PSCI
1774         select SWIOTLB_XEN
1775         select PARAVIRT
1776         help
1777           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1778
1779 endmenu
1780
1781 menu "Boot options"
1782
1783 config USE_OF
1784         bool "Flattened Device Tree support"
1785         select IRQ_DOMAIN
1786         select OF
1787         help
1788           Include support for flattened device tree machine descriptions.
1789
1790 config ATAGS
1791         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1792         default y
1793         help
1794           This is the traditional way of passing data to the kernel at boot
1795           time. If you are solely relying on the flattened device tree (or
1796           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1797           to remove ATAGS support from your kernel binary.  If unsure,
1798           leave this to y.
1799
1800 config DEPRECATED_PARAM_STRUCT
1801         bool "Provide old way to pass kernel parameters"
1802         depends on ATAGS
1803         help
1804           This was deprecated in 2001 and announced to live on for 5 years.
1805           Some old boot loaders still use this way.
1806
1807 # Compressed boot loader in ROM.  Yes, we really want to ask about
1808 # TEXT and BSS so we preserve their values in the config files.
1809 config ZBOOT_ROM_TEXT
1810         hex "Compressed ROM boot loader base address"
1811         default "0"
1812         help
1813           The physical address at which the ROM-able zImage is to be
1814           placed in the target.  Platforms which normally make use of
1815           ROM-able zImage formats normally set this to a suitable
1816           value in their defconfig file.
1817
1818           If ZBOOT_ROM is not enabled, this has no effect.
1819
1820 config ZBOOT_ROM_BSS
1821         hex "Compressed ROM boot loader BSS address"
1822         default "0"
1823         help
1824           The base address of an area of read/write memory in the target
1825           for the ROM-able zImage which must be available while the
1826           decompressor is running. It must be large enough to hold the
1827           entire decompressed kernel plus an additional 128 KiB.
1828           Platforms which normally make use of ROM-able zImage formats
1829           normally set this to a suitable value in their defconfig file.
1830
1831           If ZBOOT_ROM is not enabled, this has no effect.
1832
1833 config ZBOOT_ROM
1834         bool "Compressed boot loader in ROM/flash"
1835         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1836         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1837         help
1838           Say Y here if you intend to execute your compressed kernel image
1839           (zImage) directly from ROM or flash.  If unsure, say N.
1840
1841 config ARM_APPENDED_DTB
1842         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1843         depends on OF
1844         help
1845           With this option, the boot code will look for a device tree binary
1846           (DTB) appended to zImage
1847           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1848
1849           This is meant as a backward compatibility convenience for those
1850           systems with a bootloader that can't be upgraded to accommodate
1851           the documented boot protocol using a device tree.
1852
1853           Beware that there is very little in terms of protection against
1854           this option being confused by leftover garbage in memory that might
1855           look like a DTB header after a reboot if no actual DTB is appended
1856           to zImage.  Do not leave this option active in a production kernel
1857           if you don't intend to always append a DTB.  Proper passing of the
1858           location into r2 of a bootloader provided DTB is always preferable
1859           to this option.
1860
1861 config ARM_ATAG_DTB_COMPAT
1862         bool "Supplement the appended DTB with traditional ATAG information"
1863         depends on ARM_APPENDED_DTB
1864         help
1865           Some old bootloaders can't be updated to a DTB capable one, yet
1866           they provide ATAGs with memory configuration, the ramdisk address,
1867           the kernel cmdline string, etc.  Such information is dynamically
1868           provided by the bootloader and can't always be stored in a static
1869           DTB.  To allow a device tree enabled kernel to be used with such
1870           bootloaders, this option allows zImage to extract the information
1871           from the ATAG list and store it at run time into the appended DTB.
1872
1873 choice
1874         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1875         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1876
1877 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1878         bool "Use bootloader kernel arguments if available"
1879         help
1880           Uses the command-line options passed by the boot loader instead of
1881           the device tree bootargs property. If the boot loader doesn't provide
1882           any, the device tree bootargs property will be used.
1883
1884 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1885         bool "Extend with bootloader kernel arguments"
1886         help
1887           The command-line arguments provided by the boot loader will be
1888           appended to the the device tree bootargs property.
1889
1890 endchoice
1891
1892 config CMDLINE
1893         string "Default kernel command string"
1894         default ""
1895         help
1896           On some architectures (EBSA110 and CATS), there is currently no way
1897           for the boot loader to pass arguments to the kernel. For these
1898           architectures, you should supply some command-line options at build
1899           time by entering them here. As a minimum, you should specify the
1900           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1901
1902 choice
1903         prompt "Kernel command line type" if CMDLINE != ""
1904         default CMDLINE_FROM_BOOTLOADER
1905         depends on ATAGS
1906
1907 config CMDLINE_FROM_BOOTLOADER
1908         bool "Use bootloader kernel arguments if available"
1909         help
1910           Uses the command-line options passed by the boot loader. If
1911           the boot loader doesn't provide any, the default kernel command
1912           string provided in CMDLINE will be used.
1913
1914 config CMDLINE_EXTEND
1915         bool "Extend bootloader kernel arguments"
1916         help
1917           The command-line arguments provided by the boot loader will be
1918           appended to the default kernel command string.
1919
1920 config CMDLINE_FORCE
1921         bool "Always use the default kernel command string"
1922         help
1923           Always use the default kernel command string, even if the boot
1924           loader passes other arguments to the kernel.
1925           This is useful if you cannot or don't want to change the
1926           command-line options your boot loader passes to the kernel.
1927 endchoice
1928
1929 config XIP_KERNEL
1930         bool "Kernel Execute-In-Place from ROM"
1931         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1932         help
1933           Execute-In-Place allows the kernel to run from non-volatile storage
1934           directly addressable by the CPU, such as NOR flash. This saves RAM
1935           space since the text section of the kernel is not loaded from flash
1936           to RAM.  Read-write sections, such as the data section and stack,
1937           are still copied to RAM.  The XIP kernel is not compressed since
1938           it has to run directly from flash, so it will take more space to
1939           store it.  The flash address used to link the kernel object files,
1940           and for storing it, is configuration dependent. Therefore, if you
1941           say Y here, you must know the proper physical address where to
1942           store the kernel image depending on your own flash memory usage.
1943
1944           Also note that the make target becomes "make xipImage" rather than
1945           "make zImage" or "make Image".  The final kernel binary to put in
1946           ROM memory will be arch/arm/boot/xipImage.
1947
1948           If unsure, say N.
1949
1950 config XIP_PHYS_ADDR
1951         hex "XIP Kernel Physical Location"
1952         depends on XIP_KERNEL
1953         default "0x00080000"
1954         help
1955           This is the physical address in your flash memory the kernel will
1956           be linked for and stored to.  This address is dependent on your
1957           own flash usage.
1958
1959 config KEXEC
1960         bool "Kexec system call (EXPERIMENTAL)"
1961         depends on (!SMP || PM_SLEEP_SMP)
1962         depends on !CPU_V7M
1963         select KEXEC_CORE
1964         help
1965           kexec is a system call that implements the ability to shutdown your
1966           current kernel, and to start another kernel.  It is like a reboot
1967           but it is independent of the system firmware.   And like a reboot
1968           you can start any kernel with it, not just Linux.
1969
1970           It is an ongoing process to be certain the hardware in a machine
1971           is properly shutdown, so do not be surprised if this code does not
1972           initially work for you.
1973
1974 config ATAGS_PROC
1975         bool "Export atags in procfs"
1976         depends on ATAGS && KEXEC
1977         default y
1978         help
1979           Should the atags used to boot the kernel be exported in an "atags"
1980           file in procfs. Useful with kexec.
1981
1982 config CRASH_DUMP
1983         bool "Build kdump crash kernel (EXPERIMENTAL)"
1984         help
1985           Generate crash dump after being started by kexec. This should
1986           be normally only set in special crash dump kernels which are
1987           loaded in the main kernel with kexec-tools into a specially
1988           reserved region and then later executed after a crash by
1989           kdump/kexec. The crash dump kernel must be compiled to a
1990           memory address not used by the main kernel
1991
1992           For more details see Documentation/kdump/kdump.txt
1993
1994 config AUTO_ZRELADDR
1995         bool "Auto calculation of the decompressed kernel image address"
1996         help
1997           ZRELADDR is the physical address where the decompressed kernel
1998           image will be placed. If AUTO_ZRELADDR is selected, the address
1999           will be determined at run-time by masking the current IP with
2000           0xf8000000. This assumes the zImage being placed in the first 128MB
2001           from start of memory.
2002
2003 config EFI_STUB
2004         bool
2005
2006 config EFI
2007         bool "UEFI runtime support"
2008         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2009         select UCS2_STRING
2010         select EFI_PARAMS_FROM_FDT
2011         select EFI_STUB
2012         select EFI_ARMSTUB
2013         select EFI_RUNTIME_WRAPPERS
2014         ---help---
2015           This option provides support for runtime services provided
2016           by UEFI firmware (such as non-volatile variables, realtime
2017           clock, and platform reset). A UEFI stub is also provided to
2018           allow the kernel to be booted as an EFI application. This
2019           is only useful for kernels that may run on systems that have
2020           UEFI firmware.
2021
2022 endmenu
2023
2024 menu "CPU Power Management"
2025
2026 source "drivers/cpufreq/Kconfig"
2027
2028 source "drivers/cpuidle/Kconfig"
2029
2030 endmenu
2031
2032 menu "Floating point emulation"
2033
2034 comment "At least one emulation must be selected"
2035
2036 config FPE_NWFPE
2037         bool "NWFPE math emulation"
2038         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2039         ---help---
2040           Say Y to include the NWFPE floating point emulator in the kernel.
2041           This is necessary to run most binaries. Linux does not currently
2042           support floating point hardware so you need to say Y here even if
2043           your machine has an FPA or floating point co-processor podule.
2044
2045           You may say N here if you are going to load the Acorn FPEmulator
2046           early in the bootup.
2047
2048 config FPE_NWFPE_XP
2049         bool "Support extended precision"
2050         depends on FPE_NWFPE
2051         help
2052           Say Y to include 80-bit support in the kernel floating-point
2053           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2054           Note that gcc does not generate 80-bit operations by default,
2055           so in most cases this option only enlarges the size of the
2056           floating point emulator without any good reason.
2057
2058           You almost surely want to say N here.
2059
2060 config FPE_FASTFPE
2061         bool "FastFPE math emulation (EXPERIMENTAL)"
2062         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2063         ---help---
2064           Say Y here to include the FAST floating point emulator in the kernel.
2065           This is an experimental much faster emulator which now also has full
2066           precision for the mantissa.  It does not support any exceptions.
2067           It is very simple, and approximately 3-6 times faster than NWFPE.
2068
2069           It should be sufficient for most programs.  It may be not suitable
2070           for scientific calculations, but you have to check this for yourself.
2071           If you do not feel you need a faster FP emulation you should better
2072           choose NWFPE.
2073
2074 config VFP
2075         bool "VFP-format floating point maths"
2076         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2077         help
2078           Say Y to include VFP support code in the kernel. This is needed
2079           if your hardware includes a VFP unit.
2080
2081           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2082           release notes and additional status information.
2083
2084           Say N if your target does not have VFP hardware.
2085
2086 config VFPv3
2087         bool
2088         depends on VFP
2089         default y if CPU_V7
2090
2091 config NEON
2092         bool "Advanced SIMD (NEON) Extension support"
2093         depends on VFPv3 && CPU_V7
2094         help
2095           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2096           Extension.
2097
2098 config KERNEL_MODE_NEON
2099         bool "Support for NEON in kernel mode"
2100         depends on NEON && AEABI
2101         help
2102           Say Y to include support for NEON in kernel mode.
2103
2104 endmenu
2105
2106 menu "Userspace binary formats"
2107
2108 source "fs/Kconfig.binfmt"
2109
2110 endmenu
2111
2112 menu "Power management options"
2113
2114 source "kernel/power/Kconfig"
2115
2116 config ARCH_SUSPEND_POSSIBLE
2117         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2118                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2119         def_bool y
2120
2121 config ARM_CPU_SUSPEND
2122         def_bool PM_SLEEP
2123
2124 config ARCH_HIBERNATION_POSSIBLE
2125         bool
2126         depends on MMU
2127         default y if ARCH_SUSPEND_POSSIBLE
2128
2129 endmenu
2130
2131 source "net/Kconfig"
2132
2133 source "drivers/Kconfig"
2134
2135 source "drivers/firmware/Kconfig"
2136
2137 source "fs/Kconfig"
2138
2139 source "arch/arm/Kconfig.debug"
2140
2141 source "security/Kconfig"
2142
2143 source "crypto/Kconfig"
2144 if CRYPTO
2145 source "arch/arm/crypto/Kconfig"
2146 endif
2147
2148 source "lib/Kconfig"
2149
2150 source "arch/arm/kvm/Kconfig"