arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_WANT_IPC_PARSE_VERSION
   9         select BUILDTIME_EXTABLE_SORT if MMU
  10         select CPU_PM if (SUSPEND || CPU_IDLE)
  11         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  12         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  13         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  14         select GENERIC_IRQ_PROBE
  15         select GENERIC_IRQ_SHOW
  16         select GENERIC_PCI_IOMAP
  17         select GENERIC_SMP_IDLE_THREAD
  18         select GENERIC_IDLE_POLL_SETUP
  19         select GENERIC_STRNCPY_FROM_USER
  20         select GENERIC_STRNLEN_USER
  21         select HARDIRQS_SW_RESEND
  22         select HAVE_AOUT
  23         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  24         select HAVE_ARCH_KGDB
  25         select HAVE_ARCH_SECCOMP_FILTER
  26         select HAVE_ARCH_TRACEHOOK
  27         select HAVE_BPF_JIT
  28         select HAVE_C_RECORDMCOUNT
  29         select HAVE_DEBUG_KMEMLEAK
  30         select HAVE_DMA_API_DEBUG
  31         select HAVE_DMA_ATTRS
  32         select HAVE_DMA_CONTIGUOUS if MMU
  33         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  34         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  35         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  36         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  37         select HAVE_GENERIC_DMA_COHERENT
  38         select HAVE_GENERIC_HARDIRQS
  39         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  40         select HAVE_IDE if PCI || ISA || PCMCIA
  41         select HAVE_KERNEL_GZIP
  42         select HAVE_KERNEL_LZMA
  43         select HAVE_KERNEL_LZO
  44         select HAVE_KERNEL_XZ
  45         select HAVE_KPROBES if !XIP_KERNEL
  46         select HAVE_KRETPROBES if (HAVE_KPROBES)
  47         select HAVE_MEMBLOCK
  48         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  49         select HAVE_PERF_EVENTS
  50         select HAVE_REGS_AND_STACK_ACCESS_API
  51         select HAVE_SYSCALL_TRACEPOINTS
  52         select HAVE_UID16
  53         select KTIME_SCALAR
  54         select PERF_USE_VMALLOC
  55         select RTC_LIB
  56         select SYS_SUPPORTS_APM_EMULATION
  57         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  58         select MODULES_USE_ELF_REL
  59         select CLONE_BACKWARDS
  60         select OLD_SIGSUSPEND3
  61         select OLD_SIGACTION
  62         select HAVE_CONTEXT_TRACKING
  63         help
  64           The ARM series is a line of low-power-consumption RISC chip designs
  65           licensed by ARM Ltd and targeted at embedded applications and
  66           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  67           manufactured, but legacy ARM-based PC hardware remains popular in
  68           Europe.  There is an ARM Linux project with a web page at
  69           <http://www.arm.linux.org.uk/>.
  70
  71 config ARM_HAS_SG_CHAIN
  72         bool
  73
  74 config NEED_SG_DMA_LENGTH
  75         bool
  76
  77 config ARM_DMA_USE_IOMMU
  78         bool
  79         select ARM_HAS_SG_CHAIN
  80         select NEED_SG_DMA_LENGTH
  81
  82 if ARM_DMA_USE_IOMMU
  83
  84 config ARM_DMA_IOMMU_ALIGNMENT
  85         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  86         range 4 9
  87         default 8
  88         help
  89           DMA mapping framework by default aligns all buffers to the smallest
  90           PAGE_SIZE order which is greater than or equal to the requested buffer
  91           size. This works well for buffers up to a few hundreds kilobytes, but
  92           for larger buffers it just a waste of address space. Drivers which has
  93           relatively small addressing window (like 64Mib) might run out of
  94           virtual space with just a few allocations.
  95
  96           With this parameter you can specify the maximum PAGE_SIZE order for
  97           DMA IOMMU buffers. Larger buffers will be aligned only to this
  98           specified order. The order is expressed as a power of two multiplied
  99           by the PAGE_SIZE.
 100
 101 endif
 102
 103 config HAVE_PWM
 104         bool
 105
 106 config MIGHT_HAVE_PCI
 107         bool
 108
 109 config SYS_SUPPORTS_APM_EMULATION
 110         bool
 111
 112 config HAVE_TCM
 113         bool
 114         select GENERIC_ALLOCATOR
 115
 116 config HAVE_PROC_CPU
 117         bool
 118
 119 config NO_IOPORT
 120         bool
 121
 122 config EISA
 123         bool
 124         ---help---
 125           The Extended Industry Standard Architecture (EISA) bus was
 126           developed as an open alternative to the IBM MicroChannel bus.
 127
 128           The EISA bus provided some of the features of the IBM MicroChannel
 129           bus while maintaining backward compatibility with cards made for
 130           the older ISA bus.  The EISA bus saw limited use between 1988 and
 131           1995 when it was made obsolete by the PCI bus.
 132
 133           Say Y here if you are building a kernel for an EISA-based machine.
 134
 135           Otherwise, say N.
 136
 137 config SBUS
 138         bool
 139
 140 config STACKTRACE_SUPPORT
 141         bool
 142         default y
 143
 144 config HAVE_LATENCYTOP_SUPPORT
 145         bool
 146         depends on !SMP
 147         default y
 148
 149 config LOCKDEP_SUPPORT
 150         bool
 151         default y
 152
 153 config TRACE_IRQFLAGS_SUPPORT
 154         bool
 155         default y
 156
 157 config RWSEM_GENERIC_SPINLOCK
 158         bool
 159         default y
 160
 161 config RWSEM_XCHGADD_ALGORITHM
 162         bool
 163
 164 config ARCH_HAS_ILOG2_U32
 165         bool
 166
 167 config ARCH_HAS_ILOG2_U64
 168         bool
 169
 170 config ARCH_HAS_CPUFREQ
 171         bool
 172         help
 173           Internal node to signify that the ARCH has CPUFREQ support
 174           and that the relevant menu configurations are displayed for
 175           it.
 176
 177 config ARCH_HAS_BANDGAP
 178         bool
 179
 180 config GENERIC_HWEIGHT
 181         bool
 182         default y
 183
 184 config GENERIC_CALIBRATE_DELAY
 185         bool
 186         default y
 187
 188 config ARCH_MAY_HAVE_PC_FDC
 189         bool
 190
 191 config ZONE_DMA
 192         bool
 193
 194 config NEED_DMA_MAP_STATE
 195        def_bool y
 196
 197 config ARCH_HAS_DMA_SET_COHERENT_MASK
 198         bool
 199
 200 config GENERIC_ISA_DMA
 201         bool
 202
 203 config FIQ
 204         bool
 205
 206 config NEED_RET_TO_USER
 207         bool
 208
 209 config ARCH_MTD_XIP
 210         bool
 211
 212 config VECTORS_BASE
 213         hex
 214         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 215         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 216         default 0x00000000
 217         help
 218           The base address of exception vectors.
 219
 220 config ARM_PATCH_PHYS_VIRT
 221         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 222         default y
 223         depends on !XIP_KERNEL && MMU
 224         depends on !ARCH_REALVIEW || !SPARSEMEM
 225         help
 226           Patch phys-to-virt and virt-to-phys translation functions at
 227           boot and module load time according to the position of the
 228           kernel in system memory.
 229
 230           This can only be used with non-XIP MMU kernels where the base
 231           of physical memory is at a 16MB boundary.
 232
 233           Only disable this option if you know that you do not require
 234           this feature (eg, building a kernel for a single machine) and
 235           you need to shrink the kernel to the minimal size.
 236
 237 config NEED_MACH_GPIO_H
 238         bool
 239         help
 240           Select this when mach/gpio.h is required to provide special
 241           definitions for this platform. The need for mach/gpio.h should
 242           be avoided when possible.
 243
 244 config NEED_MACH_IO_H
 245         bool
 246         help
 247           Select this when mach/io.h is required to provide special
 248           definitions for this platform.  The need for mach/io.h should
 249           be avoided when possible.
 250
 251 config NEED_MACH_MEMORY_H
 252         bool
 253         help
 254           Select this when mach/memory.h is required to provide special
 255           definitions for this platform.  The need for mach/memory.h should
 256           be avoided when possible.
 257
 258 config PHYS_OFFSET
 259         hex "Physical address of main memory" if MMU
 260         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 261         default DRAM_BASE if !MMU
 262         help
 263           Please provide the physical address corresponding to the
 264           location of main memory in your system.
 265
 266 config GENERIC_BUG
 267         def_bool y
 268         depends on BUG
 269
 270 source "init/Kconfig"
 271
 272 source "kernel/Kconfig.freezer"
 273
 274 menu "System Type"
 275
 276 config MMU
 277         bool "MMU-based Paged Memory Management Support"
 278         default y
 279         help
 280           Select if you want MMU-based virtualised addressing space
 281           support by paged memory management. If unsure, say 'Y'.
 282
 283 #
 284 # The "ARM system type" choice list is ordered alphabetically by option
 285 # text.  Please add new entries in the option alphabetic order.
 286 #
 287 choice
 288         prompt "ARM system type"
 289         default ARCH_VERSATILE if !MMU
 290         default ARCH_MULTIPLATFORM if MMU
 291
 292 config ARCH_MULTIPLATFORM
 293         bool "Allow multiple platforms to be selected"
 294         depends on MMU
 295         select ARM_PATCH_PHYS_VIRT
 296         select AUTO_ZRELADDR
 297         select COMMON_CLK
 298         select MULTI_IRQ_HANDLER
 299         select SPARSE_IRQ
 300         select USE_OF
 301
 302 config ARCH_INTEGRATOR
 303         bool "ARM Ltd. Integrator family"
 304         select ARCH_HAS_CPUFREQ
 305         select ARM_AMBA
 306         select COMMON_CLK
 307         select COMMON_CLK_VERSATILE
 308         select GENERIC_CLOCKEVENTS
 309         select HAVE_TCM
 310         select ICST
 311         select MULTI_IRQ_HANDLER
 312         select NEED_MACH_MEMORY_H
 313         select PLAT_VERSATILE
 314         select SPARSE_IRQ
 315         select VERSATILE_FPGA_IRQ
 316         help
 317           Support for ARM's Integrator platform.
 318
 319 config ARCH_REALVIEW
 320         bool "ARM Ltd. RealView family"
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_AMBA
 323         select ARM_TIMER_SP804
 324         select COMMON_CLK
 325         select COMMON_CLK_VERSATILE
 326         select GENERIC_CLOCKEVENTS
 327         select GPIO_PL061 if GPIOLIB
 328         select ICST
 329         select NEED_MACH_MEMORY_H
 330         select PLAT_VERSATILE
 331         select PLAT_VERSATILE_CLCD
 332         help
 333           This enables support for ARM Ltd RealView boards.
 334
 335 config ARCH_VERSATILE
 336         bool "ARM Ltd. Versatile family"
 337         select ARCH_WANT_OPTIONAL_GPIOLIB
 338         select ARM_AMBA
 339         select ARM_TIMER_SP804
 340         select ARM_VIC
 341         select CLKDEV_LOOKUP
 342         select GENERIC_CLOCKEVENTS
 343         select HAVE_MACH_CLKDEV
 344         select ICST
 345         select PLAT_VERSATILE
 346         select PLAT_VERSATILE_CLCD
 347         select PLAT_VERSATILE_CLOCK
 348         select VERSATILE_FPGA_IRQ
 349         help
 350           This enables support for ARM Ltd Versatile board.
 351
 352 config ARCH_AT91
 353         bool "Atmel AT91"
 354         select ARCH_REQUIRE_GPIOLIB
 355         select CLKDEV_LOOKUP
 356         select HAVE_CLK
 357         select IRQ_DOMAIN
 358         select NEED_MACH_GPIO_H
 359         select NEED_MACH_IO_H if PCCARD
 360         select PINCTRL
 361         select PINCTRL_AT91 if USE_OF
 362         help
 363           This enables support for systems based on Atmel
 364           AT91RM9200 and AT91SAM9* processors.
 365
 366 config ARCH_CLPS711X
 367         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 368         select ARCH_REQUIRE_GPIOLIB
 369         select AUTO_ZRELADDR
 370         select CLKDEV_LOOKUP
 371         select COMMON_CLK
 372         select CPU_ARM720T
 373         select GENERIC_CLOCKEVENTS
 374         select MULTI_IRQ_HANDLER
 375         select NEED_MACH_MEMORY_H
 376         select SPARSE_IRQ
 377         help
 378           Support for Cirrus Logic 711x/721x/731x based boards.
 379
 380 config ARCH_GEMINI
 381         bool "Cortina Systems Gemini"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select ARCH_USES_GETTIMEOFFSET
 384         select NEED_MACH_GPIO_H
 385         select CPU_FA526
 386         help
 387           Support for the Cortina Systems Gemini family SoCs
 388
 389 config ARCH_EBSA110
 390         bool "EBSA-110"
 391         select ARCH_USES_GETTIMEOFFSET
 392         select CPU_SA110
 393         select ISA
 394         select NEED_MACH_IO_H
 395         select NEED_MACH_MEMORY_H
 396         select NO_IOPORT
 397         help
 398           This is an evaluation board for the StrongARM processor available
 399           from Digital. It has limited hardware on-board, including an
 400           Ethernet interface, two PCMCIA sockets, two serial ports and a
 401           parallel port.
 402
 403 config ARCH_EP93XX
 404         bool "EP93xx-based"
 405         select ARCH_HAS_HOLES_MEMORYMODEL
 406         select ARCH_REQUIRE_GPIOLIB
 407         select ARCH_USES_GETTIMEOFFSET
 408         select ARM_AMBA
 409         select ARM_VIC
 410         select CLKDEV_LOOKUP
 411         select CPU_ARM920T
 412         select NEED_MACH_MEMORY_H
 413         help
 414           This enables support for the Cirrus EP93xx series of CPUs.
 415
 416 config ARCH_FOOTBRIDGE
 417         bool "FootBridge"
 418         select CPU_SA110
 419         select FOOTBRIDGE
 420         select GENERIC_CLOCKEVENTS
 421         select HAVE_IDE
 422         select NEED_MACH_IO_H if !MMU
 423         select NEED_MACH_MEMORY_H
 424         help
 425           Support for systems based on the DC21285 companion chip
 426           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 427
 428 config ARCH_NETX
 429         bool "Hilscher NetX based"
 430         select ARM_VIC
 431         select CLKSRC_MMIO
 432         select CPU_ARM926T
 433         select GENERIC_CLOCKEVENTS
 434         help
 435           This enables support for systems based on the Hilscher NetX Soc
 436
 437 config ARCH_IOP13XX
 438         bool "IOP13xx-based"
 439         depends on MMU
 440         select ARCH_SUPPORTS_MSI
 441         select CPU_XSC3
 442         select NEED_MACH_MEMORY_H
 443         select NEED_RET_TO_USER
 444         select PCI
 445         select PLAT_IOP
 446         select VMSPLIT_1G
 447         help
 448           Support for Intel's IOP13XX (XScale) family of processors.
 449
 450 config ARCH_IOP32X
 451         bool "IOP32x-based"
 452         depends on MMU
 453         select ARCH_REQUIRE_GPIOLIB
 454         select CPU_XSCALE
 455         select NEED_MACH_GPIO_H
 456         select NEED_RET_TO_USER
 457         select PCI
 458         select PLAT_IOP
 459         help
 460           Support for Intel's 80219 and IOP32X (XScale) family of
 461           processors.
 462
 463 config ARCH_IOP33X
 464         bool "IOP33x-based"
 465         depends on MMU
 466         select ARCH_REQUIRE_GPIOLIB
 467         select CPU_XSCALE
 468         select NEED_MACH_GPIO_H
 469         select NEED_RET_TO_USER
 470         select PCI
 471         select PLAT_IOP
 472         help
 473           Support for Intel's IOP33X (XScale) family of processors.
 474
 475 config ARCH_IXP4XX
 476         bool "IXP4xx-based"
 477         depends on MMU
 478         select ARCH_HAS_DMA_SET_COHERENT_MASK
 479         select ARCH_REQUIRE_GPIOLIB
 480         select CLKSRC_MMIO
 481         select CPU_XSCALE
 482         select DMABOUNCE if PCI
 483         select GENERIC_CLOCKEVENTS
 484         select MIGHT_HAVE_PCI
 485         select NEED_MACH_IO_H
 486         select USB_EHCI_BIG_ENDIAN_MMIO
 487         select USB_EHCI_BIG_ENDIAN_DESC
 488         help
 489           Support for Intel's IXP4XX (XScale) family of processors.
 490
 491 config ARCH_DOVE
 492         bool "Marvell Dove"
 493         select ARCH_REQUIRE_GPIOLIB
 494         select CPU_V7
 495         select GENERIC_CLOCKEVENTS
 496         select MIGHT_HAVE_PCI
 497         select PINCTRL
 498         select PINCTRL_DOVE
 499         select PLAT_ORION_LEGACY
 500         select USB_ARCH_HAS_EHCI
 501         select MVEBU_MBUS
 502         help
 503           Support for the Marvell Dove SoC 88AP510
 504
 505 config ARCH_KIRKWOOD
 506         bool "Marvell Kirkwood"
 507         select ARCH_REQUIRE_GPIOLIB
 508         select CPU_FEROCEON
 509         select GENERIC_CLOCKEVENTS
 510         select PCI
 511         select PCI_QUIRKS
 512         select PINCTRL
 513         select PINCTRL_KIRKWOOD
 514         select PLAT_ORION_LEGACY
 515         select MVEBU_MBUS
 516         help
 517           Support for the following Marvell Kirkwood series SoCs:
 518           88F6180, 88F6192 and 88F6281.
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select PCI
 526         select PLAT_ORION_LEGACY
 527         select MVEBU_MBUS
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select PCI
 539         select PLAT_ORION_LEGACY
 540         select MVEBU_MBUS
 541         help
 542           Support for the following Marvell Orion 5x series SoCs:
 543           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 544           Orion-2 (5281), Orion-1-90 (6183).
 545
 546 config ARCH_MMP
 547         bool "Marvell PXA168/910/MMP2"
 548         depends on MMU
 549         select ARCH_REQUIRE_GPIOLIB
 550         select CLKDEV_LOOKUP
 551         select GENERIC_ALLOCATOR
 552         select GENERIC_CLOCKEVENTS
 553         select GPIO_PXA
 554         select IRQ_DOMAIN
 555         select NEED_MACH_GPIO_H
 556         select PINCTRL
 557         select PLAT_PXA
 558         select SPARSE_IRQ
 559         help
 560           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 561
 562 config ARCH_KS8695
 563         bool "Micrel/Kendin KS8695"
 564         select ARCH_REQUIRE_GPIOLIB
 565         select CLKSRC_MMIO
 566         select CPU_ARM922T
 567         select GENERIC_CLOCKEVENTS
 568         select NEED_MACH_MEMORY_H
 569         help
 570           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 571           System-on-Chip devices.
 572
 573 config ARCH_W90X900
 574         bool "Nuvoton W90X900 CPU"
 575         select ARCH_REQUIRE_GPIOLIB
 576         select CLKDEV_LOOKUP
 577         select CLKSRC_MMIO
 578         select CPU_ARM926T
 579         select GENERIC_CLOCKEVENTS
 580         help
 581           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 582           At present, the w90x900 has been renamed nuc900, regarding
 583           the ARM series product line, you can login the following
 584           link address to know more.
 585
 586           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 587                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 588
 589 config ARCH_LPC32XX
 590         bool "NXP LPC32XX"
 591         select ARCH_REQUIRE_GPIOLIB
 592         select ARM_AMBA
 593         select CLKDEV_LOOKUP
 594         select CLKSRC_MMIO
 595         select CPU_ARM926T
 596         select GENERIC_CLOCKEVENTS
 597         select HAVE_IDE
 598         select HAVE_PWM
 599         select USB_ARCH_HAS_OHCI
 600         select USE_OF
 601         help
 602           Support for the NXP LPC32XX family of processors
 603
 604 config ARCH_PXA
 605         bool "PXA2xx/PXA3xx-based"
 606         depends on MMU
 607         select ARCH_HAS_CPUFREQ
 608         select ARCH_MTD_XIP
 609         select ARCH_REQUIRE_GPIOLIB
 610         select ARM_CPU_SUSPEND if PM
 611         select AUTO_ZRELADDR
 612         select CLKDEV_LOOKUP
 613         select CLKSRC_MMIO
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select MULTI_IRQ_HANDLER
 618         select NEED_MACH_GPIO_H
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_MSM
 625         bool "Qualcomm MSM"
 626         select ARCH_REQUIRE_GPIOLIB
 627         select CLKDEV_LOOKUP
 628         select GENERIC_CLOCKEVENTS
 629         select HAVE_CLK
 630         help
 631           Support for Qualcomm MSM/QSD based systems.  This runs on the
 632           apps processor of the MSM/QSD and depends on a shared memory
 633           interface to the modem processor which runs the baseband
 634           stack and controls some vital subsystems
 635           (clock and power control, etc).
 636
 637 config ARCH_SHMOBILE
 638         bool "Renesas SH-Mobile / R-Mobile"
 639         select CLKDEV_LOOKUP
 640         select GENERIC_CLOCKEVENTS
 641         select HAVE_ARM_SCU if SMP
 642         select HAVE_ARM_TWD if LOCAL_TIMERS
 643         select HAVE_CLK
 644         select HAVE_MACH_CLKDEV
 645         select HAVE_SMP
 646         select MIGHT_HAVE_CACHE_L2X0
 647         select MULTI_IRQ_HANDLER
 648         select NEED_MACH_MEMORY_H
 649         select NO_IOPORT
 650         select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
 651         select PM_GENERIC_DOMAINS if PM
 652         select SPARSE_IRQ
 653         help
 654           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 655
 656 config ARCH_RPC
 657         bool "RiscPC"
 658         select ARCH_ACORN
 659         select ARCH_MAY_HAVE_PC_FDC
 660         select ARCH_SPARSEMEM_ENABLE
 661         select ARCH_USES_GETTIMEOFFSET
 662         select FIQ
 663         select HAVE_IDE
 664         select HAVE_PATA_PLATFORM
 665         select ISA_DMA_API
 666         select NEED_MACH_IO_H
 667         select NEED_MACH_MEMORY_H
 668         select NO_IOPORT
 669         select VIRT_TO_BUS
 670         help
 671           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 672           CD-ROM interface, serial and parallel port, and the floppy drive.
 673
 674 config ARCH_SA1100
 675         bool "SA1100-based"
 676         select ARCH_HAS_CPUFREQ
 677         select ARCH_MTD_XIP
 678         select ARCH_REQUIRE_GPIOLIB
 679         select ARCH_SPARSEMEM_ENABLE
 680         select CLKDEV_LOOKUP
 681         select CLKSRC_MMIO
 682         select CPU_FREQ
 683         select CPU_SA1100
 684         select GENERIC_CLOCKEVENTS
 685         select HAVE_IDE
 686         select ISA
 687         select NEED_MACH_GPIO_H
 688         select NEED_MACH_MEMORY_H
 689         select SPARSE_IRQ
 690         help
 691           Support for StrongARM 11x0 based boards.
 692
 693 config ARCH_S3C24XX
 694         bool "Samsung S3C24XX SoCs"
 695         select ARCH_HAS_CPUFREQ
 696         select ARCH_REQUIRE_GPIOLIB
 697         select CLKDEV_LOOKUP
 698         select CLKSRC_MMIO
 699         select GENERIC_CLOCKEVENTS
 700         select HAVE_CLK
 701         select HAVE_S3C2410_I2C if I2C
 702         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 703         select HAVE_S3C_RTC if RTC_CLASS
 704         select MULTI_IRQ_HANDLER
 705         select NEED_MACH_GPIO_H
 706         select NEED_MACH_IO_H
 707         help
 708           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 709           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 710           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 711           Samsung SMDK2410 development board (and derivatives).
 712
 713 config ARCH_S3C64XX
 714         bool "Samsung S3C64XX"
 715         select ARCH_HAS_CPUFREQ
 716         select ARCH_REQUIRE_GPIOLIB
 717         select ARM_VIC
 718         select CLKDEV_LOOKUP
 719         select CLKSRC_MMIO
 720         select CPU_V6
 721         select GENERIC_CLOCKEVENTS
 722         select HAVE_CLK
 723         select HAVE_S3C2410_I2C if I2C
 724         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 725         select HAVE_TCM
 726         select NEED_MACH_GPIO_H
 727         select NO_IOPORT
 728         select PLAT_SAMSUNG
 729         select S3C_DEV_NAND
 730         select S3C_GPIO_TRACK
 731         select SAMSUNG_CLKSRC
 732         select SAMSUNG_GPIOLIB_4BIT
 733         select SAMSUNG_IRQ_VIC_TIMER
 734         select USB_ARCH_HAS_OHCI
 735         help
 736           Samsung S3C64XX series based systems
 737
 738 config ARCH_S5P64X0
 739         bool "Samsung S5P6440 S5P6450"
 740         select CLKDEV_LOOKUP
 741         select CLKSRC_MMIO
 742         select CPU_V6
 743         select GENERIC_CLOCKEVENTS
 744         select HAVE_CLK
 745         select HAVE_S3C2410_I2C if I2C
 746         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 747         select HAVE_S3C_RTC if RTC_CLASS
 748         select NEED_MACH_GPIO_H
 749         help
 750           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 751           SMDK6450.
 752
 753 config ARCH_S5PC100
 754         bool "Samsung S5PC100"
 755         select ARCH_REQUIRE_GPIOLIB
 756         select CLKDEV_LOOKUP
 757         select CLKSRC_MMIO
 758         select CPU_V7
 759         select GENERIC_CLOCKEVENTS
 760         select HAVE_CLK
 761         select HAVE_S3C2410_I2C if I2C
 762         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 763         select HAVE_S3C_RTC if RTC_CLASS
 764         select NEED_MACH_GPIO_H
 765         help
 766           Samsung S5PC100 series based systems
 767
 768 config ARCH_S5PV210
 769         bool "Samsung S5PV210/S5PC110"
 770         select ARCH_HAS_CPUFREQ
 771         select ARCH_HAS_HOLES_MEMORYMODEL
 772         select ARCH_SPARSEMEM_ENABLE
 773         select CLKDEV_LOOKUP
 774         select CLKSRC_MMIO
 775         select CPU_V7
 776         select GENERIC_CLOCKEVENTS
 777         select HAVE_CLK
 778         select HAVE_S3C2410_I2C if I2C
 779         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 780         select HAVE_S3C_RTC if RTC_CLASS
 781         select NEED_MACH_GPIO_H
 782         select NEED_MACH_MEMORY_H
 783         help
 784           Samsung S5PV210/S5PC110 series based systems
 785
 786 config ARCH_EXYNOS
 787         bool "Samsung EXYNOS"
 788         select ARCH_HAS_CPUFREQ
 789         select ARCH_HAS_HOLES_MEMORYMODEL
 790         select ARCH_SPARSEMEM_ENABLE
 791         select CLKDEV_LOOKUP
 792         select COMMON_CLK
 793         select CPU_V7
 794         select GENERIC_CLOCKEVENTS
 795         select HAVE_CLK
 796         select HAVE_S3C2410_I2C if I2C
 797         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 798         select HAVE_S3C_RTC if RTC_CLASS
 799         select NEED_MACH_GPIO_H
 800         select NEED_MACH_MEMORY_H
 801         help
 802           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 803
 804 config ARCH_SHARK
 805         bool "Shark"
 806         select ARCH_USES_GETTIMEOFFSET
 807         select CPU_SA110
 808         select ISA
 809         select ISA_DMA
 810         select NEED_MACH_MEMORY_H
 811         select PCI
 812         select VIRT_TO_BUS
 813         select ZONE_DMA
 814         help
 815           Support for the StrongARM based Digital DNARD machine, also known
 816           as "Shark" (<http://www.shark-linux.de/shark.html>).
 817
 818 config ARCH_U300
 819         bool "ST-Ericsson U300 Series"
 820         depends on MMU
 821         select ARCH_REQUIRE_GPIOLIB
 822         select ARM_AMBA
 823         select ARM_PATCH_PHYS_VIRT
 824         select ARM_VIC
 825         select CLKDEV_LOOKUP
 826         select CLKSRC_MMIO
 827         select COMMON_CLK
 828         select CPU_ARM926T
 829         select GENERIC_CLOCKEVENTS
 830         select HAVE_TCM
 831         select SPARSE_IRQ
 832         help
 833           Support for ST-Ericsson U300 series mobile platforms.
 834
 835 config ARCH_DAVINCI
 836         bool "TI DaVinci"
 837         select ARCH_HAS_HOLES_MEMORYMODEL
 838         select ARCH_REQUIRE_GPIOLIB
 839         select CLKDEV_LOOKUP
 840         select GENERIC_ALLOCATOR
 841         select GENERIC_CLOCKEVENTS
 842         select GENERIC_IRQ_CHIP
 843         select HAVE_IDE
 844         select NEED_MACH_GPIO_H
 845         select USE_OF
 846         select ZONE_DMA
 847         help
 848           Support for TI's DaVinci platform.
 849
 850 config ARCH_OMAP1
 851         bool "TI OMAP1"
 852         depends on MMU
 853         select ARCH_HAS_CPUFREQ
 854         select ARCH_HAS_HOLES_MEMORYMODEL
 855         select ARCH_OMAP
 856         select ARCH_REQUIRE_GPIOLIB
 857         select CLKDEV_LOOKUP
 858         select CLKSRC_MMIO
 859         select GENERIC_CLOCKEVENTS
 860         select GENERIC_IRQ_CHIP
 861         select HAVE_CLK
 862         select HAVE_IDE
 863         select IRQ_DOMAIN
 864         select NEED_MACH_IO_H if PCCARD
 865         select NEED_MACH_MEMORY_H
 866         help
 867           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 868
 869 endchoice
 870
 871 menu "Multiple platform selection"
 872         depends on ARCH_MULTIPLATFORM
 873
 874 comment "CPU Core family selection"
 875
 876 config ARCH_MULTI_V4
 877         bool "ARMv4 based platforms (FA526, StrongARM)"
 878         depends on !ARCH_MULTI_V6_V7
 879         select ARCH_MULTI_V4_V5
 880
 881 config ARCH_MULTI_V4T
 882         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 883         depends on !ARCH_MULTI_V6_V7
 884         select ARCH_MULTI_V4_V5
 885
 886 config ARCH_MULTI_V5
 887         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 888         depends on !ARCH_MULTI_V6_V7
 889         select ARCH_MULTI_V4_V5
 890
 891 config ARCH_MULTI_V4_V5
 892         bool
 893
 894 config ARCH_MULTI_V6
 895         bool "ARMv6 based platforms (ARM11)"
 896         select ARCH_MULTI_V6_V7
 897         select CPU_V6
 898
 899 config ARCH_MULTI_V7
 900         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 901         default y
 902         select ARCH_MULTI_V6_V7
 903         select CPU_V7
 904
 905 config ARCH_MULTI_V6_V7
 906         bool
 907
 908 config ARCH_MULTI_CPU_AUTO
 909         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 910         select ARCH_MULTI_V5
 911
 912 endmenu
 913
 914 #
 915 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 916 # Kconfigs may be included either alphabetically (according to the
 917 # plat- suffix) or along side the corresponding mach-* source.
 918 #
 919 source "arch/arm/mach-mvebu/Kconfig"
 920
 921 source "arch/arm/mach-at91/Kconfig"
 922
 923 source "arch/arm/mach-bcm/Kconfig"
 924
 925 source "arch/arm/mach-bcm2835/Kconfig"
 926
 927 source "arch/arm/mach-clps711x/Kconfig"
 928
 929 source "arch/arm/mach-cns3xxx/Kconfig"
 930
 931 source "arch/arm/mach-davinci/Kconfig"
 932
 933 source "arch/arm/mach-dove/Kconfig"
 934
 935 source "arch/arm/mach-ep93xx/Kconfig"
 936
 937 source "arch/arm/mach-footbridge/Kconfig"
 938
 939 source "arch/arm/mach-gemini/Kconfig"
 940
 941 source "arch/arm/mach-highbank/Kconfig"
 942
 943 source "arch/arm/mach-integrator/Kconfig"
 944
 945 source "arch/arm/mach-iop32x/Kconfig"
 946
 947 source "arch/arm/mach-iop33x/Kconfig"
 948
 949 source "arch/arm/mach-iop13xx/Kconfig"
 950
 951 source "arch/arm/mach-ixp4xx/Kconfig"
 952
 953 source "arch/arm/mach-kirkwood/Kconfig"
 954
 955 source "arch/arm/mach-ks8695/Kconfig"
 956
 957 source "arch/arm/mach-msm/Kconfig"
 958
 959 source "arch/arm/mach-mv78xx0/Kconfig"
 960
 961 source "arch/arm/mach-imx/Kconfig"
 962
 963 source "arch/arm/mach-mxs/Kconfig"
 964
 965 source "arch/arm/mach-netx/Kconfig"
 966
 967 source "arch/arm/mach-nomadik/Kconfig"
 968
 969 source "arch/arm/plat-omap/Kconfig"
 970
 971 source "arch/arm/mach-omap1/Kconfig"
 972
 973 source "arch/arm/mach-omap2/Kconfig"
 974
 975 source "arch/arm/mach-orion5x/Kconfig"
 976
 977 source "arch/arm/mach-picoxcell/Kconfig"
 978
 979 source "arch/arm/mach-pxa/Kconfig"
 980 source "arch/arm/plat-pxa/Kconfig"
 981
 982 source "arch/arm/mach-mmp/Kconfig"
 983
 984 source "arch/arm/mach-realview/Kconfig"
 985
 986 source "arch/arm/mach-sa1100/Kconfig"
 987
 988 source "arch/arm/plat-samsung/Kconfig"
 989
 990 source "arch/arm/mach-socfpga/Kconfig"
 991
 992 source "arch/arm/mach-spear/Kconfig"
 993
 994 source "arch/arm/mach-s3c24xx/Kconfig"
 995
 996 if ARCH_S3C64XX
 997 source "arch/arm/mach-s3c64xx/Kconfig"
 998 endif
 999
1000 source "arch/arm/mach-s5p64x0/Kconfig"
1001
1002 source "arch/arm/mach-s5pc100/Kconfig"
1003
1004 source "arch/arm/mach-s5pv210/Kconfig"
1005
1006 source "arch/arm/mach-exynos/Kconfig"
1007
1008 source "arch/arm/mach-shmobile/Kconfig"
1009
1010 source "arch/arm/mach-sunxi/Kconfig"
1011
1012 source "arch/arm/mach-prima2/Kconfig"
1013
1014 source "arch/arm/mach-tegra/Kconfig"
1015
1016 source "arch/arm/mach-u300/Kconfig"
1017
1018 source "arch/arm/mach-ux500/Kconfig"
1019
1020 source "arch/arm/mach-versatile/Kconfig"
1021
1022 source "arch/arm/mach-vexpress/Kconfig"
1023 source "arch/arm/plat-versatile/Kconfig"
1024
1025 source "arch/arm/mach-virt/Kconfig"
1026
1027 source "arch/arm/mach-vt8500/Kconfig"
1028
1029 source "arch/arm/mach-w90x900/Kconfig"
1030
1031 source "arch/arm/mach-zynq/Kconfig"
1032
1033 # Definitions to make life easier
1034 config ARCH_ACORN
1035         bool
1036
1037 config PLAT_IOP
1038         bool
1039         select GENERIC_CLOCKEVENTS
1040
1041 config PLAT_ORION
1042         bool
1043         select CLKSRC_MMIO
1044         select COMMON_CLK
1045         select GENERIC_IRQ_CHIP
1046         select IRQ_DOMAIN
1047
1048 config PLAT_ORION_LEGACY
1049         bool
1050         select PLAT_ORION
1051
1052 config PLAT_PXA
1053         bool
1054
1055 config PLAT_VERSATILE
1056         bool
1057
1058 config ARM_TIMER_SP804
1059         bool
1060         select CLKSRC_MMIO
1061         select CLKSRC_OF if OF
1062
1063 source arch/arm/mm/Kconfig
1064
1065 config ARM_NR_BANKS
1066         int
1067         default 16 if ARCH_EP93XX
1068         default 8
1069
1070 config IWMMXT
1071         bool "Enable iWMMXt support" if !CPU_PJ4
1072         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1073         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1074         help
1075           Enable support for iWMMXt context switching at run time if
1076           running on a CPU that supports it.
1077
1078 config XSCALE_PMU
1079         bool
1080         depends on CPU_XSCALE
1081         default y
1082
1083 config MULTI_IRQ_HANDLER
1084         bool
1085         help
1086           Allow each machine to specify it's own IRQ handler at run time.
1087
1088 if !MMU
1089 source "arch/arm/Kconfig-nommu"
1090 endif
1091
1092 config ARM_ERRATA_326103
1093         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1094         depends on CPU_V6
1095         help
1096           Executing a SWP instruction to read-only memory does not set bit 11
1097           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1098           treat the access as a read, preventing a COW from occurring and
1099           causing the faulting task to livelock.
1100
1101 config ARM_ERRATA_411920
1102         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1103         depends on CPU_V6 || CPU_V6K
1104         help
1105           Invalidation of the Instruction Cache operation can
1106           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1107           It does not affect the MPCore. This option enables the ARM Ltd.
1108           recommended workaround.
1109
1110 config ARM_ERRATA_430973
1111         bool "ARM errata: Stale prediction on replaced interworking branch"
1112         depends on CPU_V7
1113         help
1114           This option enables the workaround for the 430973 Cortex-A8
1115           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1116           interworking branch is replaced with another code sequence at the
1117           same virtual address, whether due to self-modifying code or virtual
1118           to physical address re-mapping, Cortex-A8 does not recover from the
1119           stale interworking branch prediction. This results in Cortex-A8
1120           executing the new code sequence in the incorrect ARM or Thumb state.
1121           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1122           and also flushes the branch target cache at every context switch.
1123           Note that setting specific bits in the ACTLR register may not be
1124           available in non-secure mode.
1125
1126 config ARM_ERRATA_458693
1127         bool "ARM errata: Processor deadlock when a false hazard is created"
1128         depends on CPU_V7
1129         depends on !ARCH_MULTIPLATFORM
1130         help
1131           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1132           erratum. For very specific sequences of memory operations, it is
1133           possible for a hazard condition intended for a cache line to instead
1134           be incorrectly associated with a different cache line. This false
1135           hazard might then cause a processor deadlock. The workaround enables
1136           the L1 caching of the NEON accesses and disables the PLD instruction
1137           in the ACTLR register. Note that setting specific bits in the ACTLR
1138           register may not be available in non-secure mode.
1139
1140 config ARM_ERRATA_460075
1141         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1142         depends on CPU_V7
1143         depends on !ARCH_MULTIPLATFORM
1144         help
1145           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1146           erratum. Any asynchronous access to the L2 cache may encounter a
1147           situation in which recent store transactions to the L2 cache are lost
1148           and overwritten with stale memory contents from external memory. The
1149           workaround disables the write-allocate mode for the L2 cache via the
1150           ACTLR register. Note that setting specific bits in the ACTLR register
1151           may not be available in non-secure mode.
1152
1153 config ARM_ERRATA_742230
1154         bool "ARM errata: DMB operation may be faulty"
1155         depends on CPU_V7 && SMP
1156         depends on !ARCH_MULTIPLATFORM
1157         help
1158           This option enables the workaround for the 742230 Cortex-A9
1159           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1160           between two write operations may not ensure the correct visibility
1161           ordering of the two writes. This workaround sets a specific bit in
1162           the diagnostic register of the Cortex-A9 which causes the DMB
1163           instruction to behave as a DSB, ensuring the correct behaviour of
1164           the two writes.
1165
1166 config ARM_ERRATA_742231
1167         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1168         depends on CPU_V7 && SMP
1169         depends on !ARCH_MULTIPLATFORM
1170         help
1171           This option enables the workaround for the 742231 Cortex-A9
1172           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1173           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1174           accessing some data located in the same cache line, may get corrupted
1175           data due to bad handling of the address hazard when the line gets
1176           replaced from one of the CPUs at the same time as another CPU is
1177           accessing it. This workaround sets specific bits in the diagnostic
1178           register of the Cortex-A9 which reduces the linefill issuing
1179           capabilities of the processor.
1180
1181 config PL310_ERRATA_588369
1182         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1183         depends on CACHE_L2X0
1184         help
1185            The PL310 L2 cache controller implements three types of Clean &
1186            Invalidate maintenance operations: by Physical Address
1187            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1188            They are architecturally defined to behave as the execution of a
1189            clean operation followed immediately by an invalidate operation,
1190            both performing to the same memory location. This functionality
1191            is not correctly implemented in PL310 as clean lines are not
1192            invalidated as a result of these operations.
1193
1194 config ARM_ERRATA_720789
1195         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1196         depends on CPU_V7
1197         help
1198           This option enables the workaround for the 720789 Cortex-A9 (prior to
1199           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1200           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1201           As a consequence of this erratum, some TLB entries which should be
1202           invalidated are not, resulting in an incoherency in the system page
1203           tables. The workaround changes the TLB flushing routines to invalidate
1204           entries regardless of the ASID.
1205
1206 config PL310_ERRATA_727915
1207         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1208         depends on CACHE_L2X0
1209         help
1210           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1211           operation (offset 0x7FC). This operation runs in background so that
1212           PL310 can handle normal accesses while it is in progress. Under very
1213           rare circumstances, due to this erratum, write data can be lost when
1214           PL310 treats a cacheable write transaction during a Clean &
1215           Invalidate by Way operation.
1216
1217 config ARM_ERRATA_743622
1218         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1219         depends on CPU_V7
1220         depends on !ARCH_MULTIPLATFORM
1221         help
1222           This option enables the workaround for the 743622 Cortex-A9
1223           (r2p*) erratum. Under very rare conditions, a faulty
1224           optimisation in the Cortex-A9 Store Buffer may lead to data
1225           corruption. This workaround sets a specific bit in the diagnostic
1226           register of the Cortex-A9 which disables the Store Buffer
1227           optimisation, preventing the defect from occurring. This has no
1228           visible impact on the overall performance or power consumption of the
1229           processor.
1230
1231 config ARM_ERRATA_751472
1232         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1233         depends on CPU_V7
1234         depends on !ARCH_MULTIPLATFORM
1235         help
1236           This option enables the workaround for the 751472 Cortex-A9 (prior
1237           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1238           completion of a following broadcasted operation if the second
1239           operation is received by a CPU before the ICIALLUIS has completed,
1240           potentially leading to corrupted entries in the cache or TLB.
1241
1242 config PL310_ERRATA_753970
1243         bool "PL310 errata: cache sync operation may be faulty"
1244         depends on CACHE_PL310
1245         help
1246           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1247
1248           Under some condition the effect of cache sync operation on
1249           the store buffer still remains when the operation completes.
1250           This means that the store buffer is always asked to drain and
1251           this prevents it from merging any further writes. The workaround
1252           is to replace the normal offset of cache sync operation (0x730)
1253           by another offset targeting an unmapped PL310 register 0x740.
1254           This has the same effect as the cache sync operation: store buffer
1255           drain and waiting for all buffers empty.
1256
1257 config ARM_ERRATA_754322
1258         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1259         depends on CPU_V7
1260         help
1261           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1262           r3p*) erratum. A speculative memory access may cause a page table walk
1263           which starts prior to an ASID switch but completes afterwards. This
1264           can populate the micro-TLB with a stale entry which may be hit with
1265           the new ASID. This workaround places two dsb instructions in the mm
1266           switching code so that no page table walks can cross the ASID switch.
1267
1268 config ARM_ERRATA_754327
1269         bool "ARM errata: no automatic Store Buffer drain"
1270         depends on CPU_V7 && SMP
1271         help
1272           This option enables the workaround for the 754327 Cortex-A9 (prior to
1273           r2p0) erratum. The Store Buffer does not have any automatic draining
1274           mechanism and therefore a livelock may occur if an external agent
1275           continuously polls a memory location waiting to observe an update.
1276           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1277           written polling loops from denying visibility of updates to memory.
1278
1279 config ARM_ERRATA_364296
1280         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1281         depends on CPU_V6 && !SMP
1282         help
1283           This options enables the workaround for the 364296 ARM1136
1284           r0p2 erratum (possible cache data corruption with
1285           hit-under-miss enabled). It sets the undocumented bit 31 in
1286           the auxiliary control register and the FI bit in the control
1287           register, thus disabling hit-under-miss without putting the
1288           processor into full low interrupt latency mode. ARM11MPCore
1289           is not affected.
1290
1291 config ARM_ERRATA_764369
1292         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1293         depends on CPU_V7 && SMP
1294         help
1295           This option enables the workaround for erratum 764369
1296           affecting Cortex-A9 MPCore with two or more processors (all
1297           current revisions). Under certain timing circumstances, a data
1298           cache line maintenance operation by MVA targeting an Inner
1299           Shareable memory region may fail to proceed up to either the
1300           Point of Coherency or to the Point of Unification of the
1301           system. This workaround adds a DSB instruction before the
1302           relevant cache maintenance functions and sets a specific bit
1303           in the diagnostic control register of the SCU.
1304
1305 config PL310_ERRATA_769419
1306         bool "PL310 errata: no automatic Store Buffer drain"
1307         depends on CACHE_L2X0
1308         help
1309           On revisions of the PL310 prior to r3p2, the Store Buffer does
1310           not automatically drain. This can cause normal, non-cacheable
1311           writes to be retained when the memory system is idle, leading
1312           to suboptimal I/O performance for drivers using coherent DMA.
1313           This option adds a write barrier to the cpu_idle loop so that,
1314           on systems with an outer cache, the store buffer is drained
1315           explicitly.
1316
1317 config ARM_ERRATA_775420
1318        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1319        depends on CPU_V7
1320        help
1321          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1322          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1323          operation aborts with MMU exception, it might cause the processor
1324          to deadlock. This workaround puts DSB before executing ISB if
1325          an abort may occur on cache maintenance.
1326
1327 config ARM_ERRATA_798181
1328         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1329         depends on CPU_V7 && SMP
1330         help
1331           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1332           adequately shooting down all use of the old entries. This
1333           option enables the Linux kernel workaround for this erratum
1334           which sends an IPI to the CPUs that are running the same ASID
1335           as the one being invalidated.
1336
1337 endmenu
1338
1339 source "arch/arm/common/Kconfig"
1340
1341 menu "Bus support"
1342
1343 config ARM_AMBA
1344         bool
1345
1346 config ISA
1347         bool
1348         help
1349           Find out whether you have ISA slots on your motherboard.  ISA is the
1350           name of a bus system, i.e. the way the CPU talks to the other stuff
1351           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1352           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1353           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1354
1355 # Select ISA DMA controller support
1356 config ISA_DMA
1357         bool
1358         select ISA_DMA_API
1359
1360 # Select ISA DMA interface
1361 config ISA_DMA_API
1362         bool
1363
1364 config PCI
1365         bool "PCI support" if MIGHT_HAVE_PCI
1366         help
1367           Find out whether you have a PCI motherboard. PCI is the name of a
1368           bus system, i.e. the way the CPU talks to the other stuff inside
1369           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1370           VESA. If you have PCI, say Y, otherwise N.
1371
1372 config PCI_DOMAINS
1373         bool
1374         depends on PCI
1375
1376 config PCI_NANOENGINE
1377         bool "BSE nanoEngine PCI support"
1378         depends on SA1100_NANOENGINE
1379         help
1380           Enable PCI on the BSE nanoEngine board.
1381
1382 config PCI_SYSCALL
1383         def_bool PCI
1384
1385 # Select the host bridge type
1386 config PCI_HOST_VIA82C505
1387         bool
1388         depends on PCI && ARCH_SHARK
1389         default y
1390
1391 config PCI_HOST_ITE8152
1392         bool
1393         depends on PCI && MACH_ARMCORE
1394         default y
1395         select DMABOUNCE
1396
1397 source "drivers/pci/Kconfig"
1398
1399 source "drivers/pcmcia/Kconfig"
1400
1401 endmenu
1402
1403 menu "Kernel Features"
1404
1405 config HAVE_SMP
1406         bool
1407         help
1408           This option should be selected by machines which have an SMP-
1409           capable CPU.
1410
1411           The only effect of this option is to make the SMP-related
1412           options available to the user for configuration.
1413
1414 config SMP
1415         bool "Symmetric Multi-Processing"
1416         depends on CPU_V6K || CPU_V7
1417         depends on GENERIC_CLOCKEVENTS
1418         depends on HAVE_SMP
1419         depends on MMU
1420         select USE_GENERIC_SMP_HELPERS
1421         help
1422           This enables support for systems with more than one CPU. If you have
1423           a system with only one CPU, like most personal computers, say N. If
1424           you have a system with more than one CPU, say Y.
1425
1426           If you say N here, the kernel will run on single and multiprocessor
1427           machines, but will use only one CPU of a multiprocessor machine. If
1428           you say Y here, the kernel will run on many, but not all, single
1429           processor machines. On a single processor machine, the kernel will
1430           run faster if you say N here.
1431
1432           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1433           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1434           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1435
1436           If you don't know what to do here, say N.
1437
1438 config SMP_ON_UP
1439         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1440         depends on SMP && !XIP_KERNEL
1441         default y
1442         help
1443           SMP kernels contain instructions which fail on non-SMP processors.
1444           Enabling this option allows the kernel to modify itself to make
1445           these instructions safe.  Disabling it allows about 1K of space
1446           savings.
1447
1448           If you don't know what to do here, say Y.
1449
1450 config ARM_CPU_TOPOLOGY
1451         bool "Support cpu topology definition"
1452         depends on SMP && CPU_V7
1453         default y
1454         help
1455           Support ARM cpu topology definition. The MPIDR register defines
1456           affinity between processors which is then used to describe the cpu
1457           topology of an ARM System.
1458
1459 config SCHED_MC
1460         bool "Multi-core scheduler support"
1461         depends on ARM_CPU_TOPOLOGY
1462         help
1463           Multi-core scheduler support improves the CPU scheduler's decision
1464           making when dealing with multi-core CPU chips at a cost of slightly
1465           increased overhead in some places. If unsure say N here.
1466
1467 config SCHED_SMT
1468         bool "SMT scheduler support"
1469         depends on ARM_CPU_TOPOLOGY
1470         help
1471           Improves the CPU scheduler's decision making when dealing with
1472           MultiThreading at a cost of slightly increased overhead in some
1473           places. If unsure say N here.
1474
1475 config HAVE_ARM_SCU
1476         bool
1477         help
1478           This option enables support for the ARM system coherency unit
1479
1480 config HAVE_ARM_ARCH_TIMER
1481         bool "Architected timer support"
1482         depends on CPU_V7
1483         select ARM_ARCH_TIMER
1484         help
1485           This option enables support for the ARM architected timer
1486
1487 config HAVE_ARM_TWD
1488         bool
1489         depends on SMP
1490         select CLKSRC_OF if OF
1491         help
1492           This options enables support for the ARM timer and watchdog unit
1493
1494 config MCPM
1495         bool "Multi-Cluster Power Management"
1496         depends on CPU_V7 && SMP
1497         help
1498           This option provides the common power management infrastructure
1499           for (multi-)cluster based systems, such as big.LITTLE based
1500           systems.
1501
1502 choice
1503         prompt "Memory split"
1504         default VMSPLIT_3G
1505         help
1506           Select the desired split between kernel and user memory.
1507
1508           If you are not absolutely sure what you are doing, leave this
1509           option alone!
1510
1511         config VMSPLIT_3G
1512                 bool "3G/1G user/kernel split"
1513         config VMSPLIT_2G
1514                 bool "2G/2G user/kernel split"
1515         config VMSPLIT_1G
1516                 bool "1G/3G user/kernel split"
1517 endchoice
1518
1519 config PAGE_OFFSET
1520         hex
1521         default 0x40000000 if VMSPLIT_1G
1522         default 0x80000000 if VMSPLIT_2G
1523         default 0xC0000000
1524
1525 config NR_CPUS
1526         int "Maximum number of CPUs (2-32)"
1527         range 2 32
1528         depends on SMP
1529         default "4"
1530
1531 config HOTPLUG_CPU
1532         bool "Support for hot-pluggable CPUs"
1533         depends on SMP && HOTPLUG
1534         help
1535           Say Y here to experiment with turning CPUs off and on.  CPUs
1536           can be controlled through /sys/devices/system/cpu.
1537
1538 config ARM_PSCI
1539         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1540         depends on CPU_V7
1541         help
1542           Say Y here if you want Linux to communicate with system firmware
1543           implementing the PSCI specification for CPU-centric power
1544           management operations described in ARM document number ARM DEN
1545           0022A ("Power State Coordination Interface System Software on
1546           ARM processors").
1547
1548 config LOCAL_TIMERS
1549         bool "Use local timer interrupts"
1550         depends on SMP
1551         default y
1552         help
1553           Enable support for local timers on SMP platforms, rather then the
1554           legacy IPI broadcast method.  Local timers allows the system
1555           accounting to be spread across the timer interval, preventing a
1556           "thundering herd" at every timer tick.
1557
1558 # The GPIO number here must be sorted by descending number. In case of
1559 # a multiplatform kernel, we just want the highest value required by the
1560 # selected platforms.
1561 config ARCH_NR_GPIO
1562         int
1563         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1564         default 512 if SOC_OMAP5
1565         default 392 if ARCH_U8500
1566         default 352 if ARCH_VT8500
1567         default 288 if ARCH_SUNXI
1568         default 264 if MACH_H4700
1569         default 0
1570         help
1571           Maximum number of GPIOs in the system.
1572
1573           If unsure, leave the default value.
1574
1575 source kernel/Kconfig.preempt
1576
1577 config HZ
1578         int
1579         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1580                 ARCH_S5PV210 || ARCH_EXYNOS4
1581         default AT91_TIMER_HZ if ARCH_AT91
1582         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1583         default 100
1584
1585 config SCHED_HRTICK
1586         def_bool HIGH_RES_TIMERS
1587
1588 config THUMB2_KERNEL
1589         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1590         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1591         default y if CPU_THUMBONLY
1592         select AEABI
1593         select ARM_ASM_UNIFIED
1594         select ARM_UNWIND
1595         help
1596           By enabling this option, the kernel will be compiled in
1597           Thumb-2 mode. A compiler/assembler that understand the unified
1598           ARM-Thumb syntax is needed.
1599
1600           If unsure, say N.
1601
1602 config THUMB2_AVOID_R_ARM_THM_JUMP11
1603         bool "Work around buggy Thumb-2 short branch relocations in gas"
1604         depends on THUMB2_KERNEL && MODULES
1605         default y
1606         help
1607           Various binutils versions can resolve Thumb-2 branches to
1608           locally-defined, preemptible global symbols as short-range "b.n"
1609           branch instructions.
1610
1611           This is a problem, because there's no guarantee the final
1612           destination of the symbol, or any candidate locations for a
1613           trampoline, are within range of the branch.  For this reason, the
1614           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1615           relocation in modules at all, and it makes little sense to add
1616           support.
1617
1618           The symptom is that the kernel fails with an "unsupported
1619           relocation" error when loading some modules.
1620
1621           Until fixed tools are available, passing
1622           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1623           code which hits this problem, at the cost of a bit of extra runtime
1624           stack usage in some cases.
1625
1626           The problem is described in more detail at:
1627               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1628
1629           Only Thumb-2 kernels are affected.
1630
1631           Unless you are sure your tools don't have this problem, say Y.
1632
1633 config ARM_ASM_UNIFIED
1634         bool
1635
1636 config AEABI
1637         bool "Use the ARM EABI to compile the kernel"
1638         help
1639           This option allows for the kernel to be compiled using the latest
1640           ARM ABI (aka EABI).  This is only useful if you are using a user
1641           space environment that is also compiled with EABI.
1642
1643           Since there are major incompatibilities between the legacy ABI and
1644           EABI, especially with regard to structure member alignment, this
1645           option also changes the kernel syscall calling convention to
1646           disambiguate both ABIs and allow for backward compatibility support
1647           (selected with CONFIG_OABI_COMPAT).
1648
1649           To use this you need GCC version 4.0.0 or later.
1650
1651 config OABI_COMPAT
1652         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1653         depends on AEABI && !THUMB2_KERNEL
1654         default y
1655         help
1656           This option preserves the old syscall interface along with the
1657           new (ARM EABI) one. It also provides a compatibility layer to
1658           intercept syscalls that have structure arguments which layout
1659           in memory differs between the legacy ABI and the new ARM EABI
1660           (only for non "thumb" binaries). This option adds a tiny
1661           overhead to all syscalls and produces a slightly larger kernel.
1662           If you know you'll be using only pure EABI user space then you
1663           can say N here. If this option is not selected and you attempt
1664           to execute a legacy ABI binary then the result will be
1665           UNPREDICTABLE (in fact it can be predicted that it won't work
1666           at all). If in doubt say Y.
1667
1668 config ARCH_HAS_HOLES_MEMORYMODEL
1669         bool
1670
1671 config ARCH_SPARSEMEM_ENABLE
1672         bool
1673
1674 config ARCH_SPARSEMEM_DEFAULT
1675         def_bool ARCH_SPARSEMEM_ENABLE
1676
1677 config ARCH_SELECT_MEMORY_MODEL
1678         def_bool ARCH_SPARSEMEM_ENABLE
1679
1680 config HAVE_ARCH_PFN_VALID
1681         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1682
1683 config HIGHMEM
1684         bool "High Memory Support"
1685         depends on MMU
1686         help
1687           The address space of ARM processors is only 4 Gigabytes large
1688           and it has to accommodate user address space, kernel address
1689           space as well as some memory mapped IO. That means that, if you
1690           have a large amount of physical memory and/or IO, not all of the
1691           memory can be "permanently mapped" by the kernel. The physical
1692           memory that is not permanently mapped is called "high memory".
1693
1694           Depending on the selected kernel/user memory split, minimum
1695           vmalloc space and actual amount of RAM, you may not need this
1696           option which should result in a slightly faster kernel.
1697
1698           If unsure, say n.
1699
1700 config HIGHPTE
1701         bool "Allocate 2nd-level pagetables from highmem"
1702         depends on HIGHMEM
1703
1704 config HW_PERF_EVENTS
1705         bool "Enable hardware performance counter support for perf events"
1706         depends on PERF_EVENTS
1707         default y
1708         help
1709           Enable hardware performance counter support for perf events. If
1710           disabled, perf events will use software events only.
1711
1712 source "mm/Kconfig"
1713
1714 config FORCE_MAX_ZONEORDER
1715         int "Maximum zone order" if ARCH_SHMOBILE
1716         range 11 64 if ARCH_SHMOBILE
1717         default "12" if SOC_AM33XX
1718         default "9" if SA1111
1719         default "11"
1720         help
1721           The kernel memory allocator divides physically contiguous memory
1722           blocks into "zones", where each zone is a power of two number of
1723           pages.  This option selects the largest power of two that the kernel
1724           keeps in the memory allocator.  If you need to allocate very large
1725           blocks of physically contiguous memory, then you may need to
1726           increase this value.
1727
1728           This config option is actually maximum order plus one. For example,
1729           a value of 11 means that the largest free memory block is 2^10 pages.
1730
1731 config ALIGNMENT_TRAP
1732         bool
1733         depends on CPU_CP15_MMU
1734         default y if !ARCH_EBSA110
1735         select HAVE_PROC_CPU if PROC_FS
1736         help
1737           ARM processors cannot fetch/store information which is not
1738           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1739           address divisible by 4. On 32-bit ARM processors, these non-aligned
1740           fetch/store instructions will be emulated in software if you say
1741           here, which has a severe performance impact. This is necessary for
1742           correct operation of some network protocols. With an IP-only
1743           configuration it is safe to say N, otherwise say Y.
1744
1745 config UACCESS_WITH_MEMCPY
1746         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1747         depends on MMU
1748         default y if CPU_FEROCEON
1749         help
1750           Implement faster copy_to_user and clear_user methods for CPU
1751           cores where a 8-word STM instruction give significantly higher
1752           memory write throughput than a sequence of individual 32bit stores.
1753
1754           A possible side effect is a slight increase in scheduling latency
1755           between threads sharing the same address space if they invoke
1756           such copy operations with large buffers.
1757
1758           However, if the CPU data cache is using a write-allocate mode,
1759           this option is unlikely to provide any performance gain.
1760
1761 config SECCOMP
1762         bool
1763         prompt "Enable seccomp to safely compute untrusted bytecode"
1764         ---help---
1765           This kernel feature is useful for number crunching applications
1766           that may need to compute untrusted bytecode during their
1767           execution. By using pipes or other transports made available to
1768           the process as file descriptors supporting the read/write
1769           syscalls, it's possible to isolate those applications in
1770           their own address space using seccomp. Once seccomp is
1771           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1772           and the task is only allowed to execute a few safe syscalls
1773           defined by each seccomp mode.
1774
1775 config CC_STACKPROTECTOR
1776         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1777         help
1778           This option turns on the -fstack-protector GCC feature. This
1779           feature puts, at the beginning of functions, a canary value on
1780           the stack just before the return address, and validates
1781           the value just before actually returning.  Stack based buffer
1782           overflows (that need to overwrite this return address) now also
1783           overwrite the canary, which gets detected and the attack is then
1784           neutralized via a kernel panic.
1785           This feature requires gcc version 4.2 or above.
1786
1787 config XEN_DOM0
1788         def_bool y
1789         depends on XEN
1790
1791 config XEN
1792         bool "Xen guest support on ARM (EXPERIMENTAL)"
1793         depends on ARM && AEABI && OF
1794         depends on CPU_V7 && !CPU_V6
1795         depends on !GENERIC_ATOMIC64
1796         select ARM_PSCI
1797         help
1798           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1799
1800 endmenu
1801
1802 menu "Boot options"
1803
1804 config USE_OF
1805         bool "Flattened Device Tree support"
1806         select IRQ_DOMAIN
1807         select OF
1808         select OF_EARLY_FLATTREE
1809         help
1810           Include support for flattened device tree machine descriptions.
1811
1812 config ATAGS
1813         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1814         default y
1815         help
1816           This is the traditional way of passing data to the kernel at boot
1817           time. If you are solely relying on the flattened device tree (or
1818           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1819           to remove ATAGS support from your kernel binary.  If unsure,
1820           leave this to y.
1821
1822 config DEPRECATED_PARAM_STRUCT
1823         bool "Provide old way to pass kernel parameters"
1824         depends on ATAGS
1825         help
1826           This was deprecated in 2001 and announced to live on for 5 years.
1827           Some old boot loaders still use this way.
1828
1829 # Compressed boot loader in ROM.  Yes, we really want to ask about
1830 # TEXT and BSS so we preserve their values in the config files.
1831 config ZBOOT_ROM_TEXT
1832         hex "Compressed ROM boot loader base address"
1833         default "0"
1834         help
1835           The physical address at which the ROM-able zImage is to be
1836           placed in the target.  Platforms which normally make use of
1837           ROM-able zImage formats normally set this to a suitable
1838           value in their defconfig file.
1839
1840           If ZBOOT_ROM is not enabled, this has no effect.
1841
1842 config ZBOOT_ROM_BSS
1843         hex "Compressed ROM boot loader BSS address"
1844         default "0"
1845         help
1846           The base address of an area of read/write memory in the target
1847           for the ROM-able zImage which must be available while the
1848           decompressor is running. It must be large enough to hold the
1849           entire decompressed kernel plus an additional 128 KiB.
1850           Platforms which normally make use of ROM-able zImage formats
1851           normally set this to a suitable value in their defconfig file.
1852
1853           If ZBOOT_ROM is not enabled, this has no effect.
1854
1855 config ZBOOT_ROM
1856         bool "Compressed boot loader in ROM/flash"
1857         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1858         help
1859           Say Y here if you intend to execute your compressed kernel image
1860           (zImage) directly from ROM or flash.  If unsure, say N.
1861
1862 choice
1863         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1864         depends on ZBOOT_ROM && ARCH_SH7372
1865         default ZBOOT_ROM_NONE
1866         help
1867           Include experimental SD/MMC loading code in the ROM-able zImage.
1868           With this enabled it is possible to write the ROM-able zImage
1869           kernel image to an MMC or SD card and boot the kernel straight
1870           from the reset vector. At reset the processor Mask ROM will load
1871           the first part of the ROM-able zImage which in turn loads the
1872           rest the kernel image to RAM.
1873
1874 config ZBOOT_ROM_NONE
1875         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1876         help
1877           Do not load image from SD or MMC
1878
1879 config ZBOOT_ROM_MMCIF
1880         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1881         help
1882           Load image from MMCIF hardware block.
1883
1884 config ZBOOT_ROM_SH_MOBILE_SDHI
1885         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1886         help
1887           Load image from SDHI hardware block
1888
1889 endchoice
1890
1891 config ARM_APPENDED_DTB
1892         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1893         depends on OF && !ZBOOT_ROM
1894         help
1895           With this option, the boot code will look for a device tree binary
1896           (DTB) appended to zImage
1897           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1898
1899           This is meant as a backward compatibility convenience for those
1900           systems with a bootloader that can't be upgraded to accommodate
1901           the documented boot protocol using a device tree.
1902
1903           Beware that there is very little in terms of protection against
1904           this option being confused by leftover garbage in memory that might
1905           look like a DTB header after a reboot if no actual DTB is appended
1906           to zImage.  Do not leave this option active in a production kernel
1907           if you don't intend to always append a DTB.  Proper passing of the
1908           location into r2 of a bootloader provided DTB is always preferable
1909           to this option.
1910
1911 config ARM_ATAG_DTB_COMPAT
1912         bool "Supplement the appended DTB with traditional ATAG information"
1913         depends on ARM_APPENDED_DTB
1914         help
1915           Some old bootloaders can't be updated to a DTB capable one, yet
1916           they provide ATAGs with memory configuration, the ramdisk address,
1917           the kernel cmdline string, etc.  Such information is dynamically
1918           provided by the bootloader and can't always be stored in a static
1919           DTB.  To allow a device tree enabled kernel to be used with such
1920           bootloaders, this option allows zImage to extract the information
1921           from the ATAG list and store it at run time into the appended DTB.
1922
1923 choice
1924         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1925         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1928         bool "Use bootloader kernel arguments if available"
1929         help
1930           Uses the command-line options passed by the boot loader instead of
1931           the device tree bootargs property. If the boot loader doesn't provide
1932           any, the device tree bootargs property will be used.
1933
1934 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1935         bool "Extend with bootloader kernel arguments"
1936         help
1937           The command-line arguments provided by the boot loader will be
1938           appended to the the device tree bootargs property.
1939
1940 endchoice
1941
1942 config CMDLINE
1943         string "Default kernel command string"
1944         default ""
1945         help
1946           On some architectures (EBSA110 and CATS), there is currently no way
1947           for the boot loader to pass arguments to the kernel. For these
1948           architectures, you should supply some command-line options at build
1949           time by entering them here. As a minimum, you should specify the
1950           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1951
1952 choice
1953         prompt "Kernel command line type" if CMDLINE != ""
1954         default CMDLINE_FROM_BOOTLOADER
1955         depends on ATAGS
1956
1957 config CMDLINE_FROM_BOOTLOADER
1958         bool "Use bootloader kernel arguments if available"
1959         help
1960           Uses the command-line options passed by the boot loader. If
1961           the boot loader doesn't provide any, the default kernel command
1962           string provided in CMDLINE will be used.
1963
1964 config CMDLINE_EXTEND
1965         bool "Extend bootloader kernel arguments"
1966         help
1967           The command-line arguments provided by the boot loader will be
1968           appended to the default kernel command string.
1969
1970 config CMDLINE_FORCE
1971         bool "Always use the default kernel command string"
1972         help
1973           Always use the default kernel command string, even if the boot
1974           loader passes other arguments to the kernel.
1975           This is useful if you cannot or don't want to change the
1976           command-line options your boot loader passes to the kernel.
1977 endchoice
1978
1979 config XIP_KERNEL
1980         bool "Kernel Execute-In-Place from ROM"
1981         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1982         help
1983           Execute-In-Place allows the kernel to run from non-volatile storage
1984           directly addressable by the CPU, such as NOR flash. This saves RAM
1985           space since the text section of the kernel is not loaded from flash
1986           to RAM.  Read-write sections, such as the data section and stack,
1987           are still copied to RAM.  The XIP kernel is not compressed since
1988           it has to run directly from flash, so it will take more space to
1989           store it.  The flash address used to link the kernel object files,
1990           and for storing it, is configuration dependent. Therefore, if you
1991           say Y here, you must know the proper physical address where to
1992           store the kernel image depending on your own flash memory usage.
1993
1994           Also note that the make target becomes "make xipImage" rather than
1995           "make zImage" or "make Image".  The final kernel binary to put in
1996           ROM memory will be arch/arm/boot/xipImage.
1997
1998           If unsure, say N.
1999
2000 config XIP_PHYS_ADDR
2001         hex "XIP Kernel Physical Location"
2002         depends on XIP_KERNEL
2003         default "0x00080000"
2004         help
2005           This is the physical address in your flash memory the kernel will
2006           be linked for and stored to.  This address is dependent on your
2007           own flash usage.
2008
2009 config KEXEC
2010         bool "Kexec system call (EXPERIMENTAL)"
2011         depends on (!SMP || HOTPLUG_CPU)
2012         help
2013           kexec is a system call that implements the ability to shutdown your
2014           current kernel, and to start another kernel.  It is like a reboot
2015           but it is independent of the system firmware.   And like a reboot
2016           you can start any kernel with it, not just Linux.
2017
2018           It is an ongoing process to be certain the hardware in a machine
2019           is properly shutdown, so do not be surprised if this code does not
2020           initially work for you.  It may help to enable device hotplugging
2021           support.
2022
2023 config ATAGS_PROC
2024         bool "Export atags in procfs"
2025         depends on ATAGS && KEXEC
2026         default y
2027         help
2028           Should the atags used to boot the kernel be exported in an "atags"
2029           file in procfs. Useful with kexec.
2030
2031 config CRASH_DUMP
2032         bool "Build kdump crash kernel (EXPERIMENTAL)"
2033         help
2034           Generate crash dump after being started by kexec. This should
2035           be normally only set in special crash dump kernels which are
2036           loaded in the main kernel with kexec-tools into a specially
2037           reserved region and then later executed after a crash by
2038           kdump/kexec. The crash dump kernel must be compiled to a
2039           memory address not used by the main kernel
2040
2041           For more details see Documentation/kdump/kdump.txt
2042
2043 config AUTO_ZRELADDR
2044         bool "Auto calculation of the decompressed kernel image address"
2045         depends on !ZBOOT_ROM && !ARCH_U300
2046         help
2047           ZRELADDR is the physical address where the decompressed kernel
2048           image will be placed. If AUTO_ZRELADDR is selected, the address
2049           will be determined at run-time by masking the current IP with
2050           0xf8000000. This assumes the zImage being placed in the first 128MB
2051           from start of memory.
2052
2053 endmenu
2054
2055 menu "CPU Power Management"
2056
2057 if ARCH_HAS_CPUFREQ
2058 source "drivers/cpufreq/Kconfig"
2059
2060 config CPU_FREQ_S3C
2061         bool
2062         help
2063           Internal configuration node for common cpufreq on Samsung SoC
2064
2065 config CPU_FREQ_S3C24XX
2066         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2067         depends on ARCH_S3C24XX && CPU_FREQ
2068         select CPU_FREQ_S3C
2069         help
2070           This enables the CPUfreq driver for the Samsung S3C24XX family
2071           of CPUs.
2072
2073           For details, take a look at <file:Documentation/cpu-freq>.
2074
2075           If in doubt, say N.
2076
2077 config CPU_FREQ_S3C24XX_PLL
2078         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2079         depends on CPU_FREQ_S3C24XX
2080         help
2081           Compile in support for changing the PLL frequency from the
2082           S3C24XX series CPUfreq driver. The PLL takes time to settle
2083           after a frequency change, so by default it is not enabled.
2084
2085           This also means that the PLL tables for the selected CPU(s) will
2086           be built which may increase the size of the kernel image.
2087
2088 config CPU_FREQ_S3C24XX_DEBUG
2089         bool "Debug CPUfreq Samsung driver core"
2090         depends on CPU_FREQ_S3C24XX
2091         help
2092           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2093
2094 config CPU_FREQ_S3C24XX_IODEBUG
2095         bool "Debug CPUfreq Samsung driver IO timing"
2096         depends on CPU_FREQ_S3C24XX
2097         help
2098           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2099
2100 config CPU_FREQ_S3C24XX_DEBUGFS
2101         bool "Export debugfs for CPUFreq"
2102         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2103         help
2104           Export status information via debugfs.
2105
2106 endif
2107
2108 source "drivers/cpuidle/Kconfig"
2109
2110 endmenu
2111
2112 menu "Floating point emulation"
2113
2114 comment "At least one emulation must be selected"
2115
2116 config FPE_NWFPE
2117         bool "NWFPE math emulation"
2118         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2119         ---help---
2120           Say Y to include the NWFPE floating point emulator in the kernel.
2121           This is necessary to run most binaries. Linux does not currently
2122           support floating point hardware so you need to say Y here even if
2123           your machine has an FPA or floating point co-processor podule.
2124
2125           You may say N here if you are going to load the Acorn FPEmulator
2126           early in the bootup.
2127
2128 config FPE_NWFPE_XP
2129         bool "Support extended precision"
2130         depends on FPE_NWFPE
2131         help
2132           Say Y to include 80-bit support in the kernel floating-point
2133           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2134           Note that gcc does not generate 80-bit operations by default,
2135           so in most cases this option only enlarges the size of the
2136           floating point emulator without any good reason.
2137
2138           You almost surely want to say N here.
2139
2140 config FPE_FASTFPE
2141         bool "FastFPE math emulation (EXPERIMENTAL)"
2142         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2143         ---help---
2144           Say Y here to include the FAST floating point emulator in the kernel.
2145           This is an experimental much faster emulator which now also has full
2146           precision for the mantissa.  It does not support any exceptions.
2147           It is very simple, and approximately 3-6 times faster than NWFPE.
2148
2149           It should be sufficient for most programs.  It may be not suitable
2150           for scientific calculations, but you have to check this for yourself.
2151           If you do not feel you need a faster FP emulation you should better
2152           choose NWFPE.
2153
2154 config VFP
2155         bool "VFP-format floating point maths"
2156         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2157         help
2158           Say Y to include VFP support code in the kernel. This is needed
2159           if your hardware includes a VFP unit.
2160
2161           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2162           release notes and additional status information.
2163
2164           Say N if your target does not have VFP hardware.
2165
2166 config VFPv3
2167         bool
2168         depends on VFP
2169         default y if CPU_V7
2170
2171 config NEON
2172         bool "Advanced SIMD (NEON) Extension support"
2173         depends on VFPv3 && CPU_V7
2174         help
2175           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2176           Extension.
2177
2178 endmenu
2179
2180 menu "Userspace binary formats"
2181
2182 source "fs/Kconfig.binfmt"
2183
2184 config ARTHUR
2185         tristate "RISC OS personality"
2186         depends on !AEABI
2187         help
2188           Say Y here to include the kernel code necessary if you want to run
2189           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2190           experimental; if this sounds frightening, say N and sleep in peace.
2191           You can also say M here to compile this support as a module (which
2192           will be called arthur).
2193
2194 endmenu
2195
2196 menu "Power management options"
2197
2198 source "kernel/power/Kconfig"
2199
2200 config ARCH_SUSPEND_POSSIBLE
2201         depends on !ARCH_S5PC100
2202         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2203                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2204         def_bool y
2205
2206 config ARM_CPU_SUSPEND
2207         def_bool PM_SLEEP
2208
2209 endmenu
2210
2211 source "net/Kconfig"
2212
2213 source "drivers/Kconfig"
2214
2215 source "fs/Kconfig"
2216
2217 source "arch/arm/Kconfig.debug"
2218
2219 source "security/Kconfig"
2220
2221 source "crypto/Kconfig"
2222
2223 source "lib/Kconfig"
2224
2225 source "arch/arm/kvm/Kconfig"