arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_WANT_IPC_PARSE_VERSION
   8         select BUILDTIME_EXTABLE_SORT if MMU
   9         select CPU_PM if (SUSPEND || CPU_IDLE)
  10         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  11         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  12         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  13         select GENERIC_IRQ_PROBE
  14         select GENERIC_IRQ_SHOW
  15         select GENERIC_PCI_IOMAP
  16         select GENERIC_SMP_IDLE_THREAD
  17         select GENERIC_STRNCPY_FROM_USER
  18         select GENERIC_STRNLEN_USER
  19         select HARDIRQS_SW_RESEND
  20         select HAVE_AOUT
  21         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  22         select HAVE_ARCH_KGDB
  23         select HAVE_ARCH_SECCOMP_FILTER
  24         select HAVE_ARCH_TRACEHOOK
  25         select HAVE_BPF_JIT
  26         select HAVE_C_RECORDMCOUNT
  27         select HAVE_DEBUG_KMEMLEAK
  28         select HAVE_DMA_API_DEBUG
  29         select HAVE_DMA_ATTRS
  30         select HAVE_DMA_CONTIGUOUS if MMU
  31         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  32         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  33         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  34         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  35         select HAVE_GENERIC_DMA_COHERENT
  36         select HAVE_GENERIC_HARDIRQS
  37         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  38         select HAVE_IDE if PCI || ISA || PCMCIA
  39         select HAVE_IRQ_WORK
  40         select HAVE_KERNEL_GZIP
  41         select HAVE_KERNEL_LZMA
  42         select HAVE_KERNEL_LZO
  43         select HAVE_KERNEL_XZ
  44         select HAVE_KPROBES if !XIP_KERNEL
  45         select HAVE_KRETPROBES if (HAVE_KPROBES)
  46         select HAVE_MEMBLOCK
  47         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  48         select HAVE_PERF_EVENTS
  49         select HAVE_REGS_AND_STACK_ACCESS_API
  50         select HAVE_SYSCALL_TRACEPOINTS
  51         select HAVE_UID16
  52         select KTIME_SCALAR
  53         select PERF_USE_VMALLOC
  54         select RTC_LIB
  55         select SYS_SUPPORTS_APM_EMULATION
  56         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  57         select MODULES_USE_ELF_REL
  58         select CLONE_BACKWARDS
  59         help
  60           The ARM series is a line of low-power-consumption RISC chip designs
  61           licensed by ARM Ltd and targeted at embedded applications and
  62           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  63           manufactured, but legacy ARM-based PC hardware remains popular in
  64           Europe.  There is an ARM Linux project with a web page at
  65           <http://www.arm.linux.org.uk/>.
  66
  67 config ARM_HAS_SG_CHAIN
  68         bool
  69
  70 config NEED_SG_DMA_LENGTH
  71         bool
  72
  73 config ARM_DMA_USE_IOMMU
  74         bool
  75         select ARM_HAS_SG_CHAIN
  76         select NEED_SG_DMA_LENGTH
  77
  78 config HAVE_PWM
  79         bool
  80
  81 config MIGHT_HAVE_PCI
  82         bool
  83
  84 config SYS_SUPPORTS_APM_EMULATION
  85         bool
  86
  87 config GENERIC_GPIO
  88         bool
  89
  90 config HAVE_TCM
  91         bool
  92         select GENERIC_ALLOCATOR
  93
  94 config HAVE_PROC_CPU
  95         bool
  96
  97 config NO_IOPORT
  98         bool
  99
 100 config EISA
 101         bool
 102         ---help---
 103           The Extended Industry Standard Architecture (EISA) bus was
 104           developed as an open alternative to the IBM MicroChannel bus.
 105
 106           The EISA bus provided some of the features of the IBM MicroChannel
 107           bus while maintaining backward compatibility with cards made for
 108           the older ISA bus.  The EISA bus saw limited use between 1988 and
 109           1995 when it was made obsolete by the PCI bus.
 110
 111           Say Y here if you are building a kernel for an EISA-based machine.
 112
 113           Otherwise, say N.
 114
 115 config SBUS
 116         bool
 117
 118 config STACKTRACE_SUPPORT
 119         bool
 120         default y
 121
 122 config HAVE_LATENCYTOP_SUPPORT
 123         bool
 124         depends on !SMP
 125         default y
 126
 127 config LOCKDEP_SUPPORT
 128         bool
 129         default y
 130
 131 config TRACE_IRQFLAGS_SUPPORT
 132         bool
 133         default y
 134
 135 config RWSEM_GENERIC_SPINLOCK
 136         bool
 137         default y
 138
 139 config RWSEM_XCHGADD_ALGORITHM
 140         bool
 141
 142 config ARCH_HAS_ILOG2_U32
 143         bool
 144
 145 config ARCH_HAS_ILOG2_U64
 146         bool
 147
 148 config ARCH_HAS_CPUFREQ
 149         bool
 150         help
 151           Internal node to signify that the ARCH has CPUFREQ support
 152           and that the relevant menu configurations are displayed for
 153           it.
 154
 155 config GENERIC_HWEIGHT
 156         bool
 157         default y
 158
 159 config GENERIC_CALIBRATE_DELAY
 160         bool
 161         default y
 162
 163 config ARCH_MAY_HAVE_PC_FDC
 164         bool
 165
 166 config ZONE_DMA
 167         bool
 168
 169 config NEED_DMA_MAP_STATE
 170        def_bool y
 171
 172 config ARCH_HAS_DMA_SET_COHERENT_MASK
 173         bool
 174
 175 config GENERIC_ISA_DMA
 176         bool
 177
 178 config FIQ
 179         bool
 180
 181 config NEED_RET_TO_USER
 182         bool
 183
 184 config ARCH_MTD_XIP
 185         bool
 186
 187 config VECTORS_BASE
 188         hex
 189         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 190         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 191         default 0x00000000
 192         help
 193           The base address of exception vectors.
 194
 195 config ARM_PATCH_PHYS_VIRT
 196         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 197         default y
 198         depends on !XIP_KERNEL && MMU
 199         depends on !ARCH_REALVIEW || !SPARSEMEM
 200         help
 201           Patch phys-to-virt and virt-to-phys translation functions at
 202           boot and module load time according to the position of the
 203           kernel in system memory.
 204
 205           This can only be used with non-XIP MMU kernels where the base
 206           of physical memory is at a 16MB boundary.
 207
 208           Only disable this option if you know that you do not require
 209           this feature (eg, building a kernel for a single machine) and
 210           you need to shrink the kernel to the minimal size.
 211
 212 config NEED_MACH_GPIO_H
 213         bool
 214         help
 215           Select this when mach/gpio.h is required to provide special
 216           definitions for this platform. The need for mach/gpio.h should
 217           be avoided when possible.
 218
 219 config NEED_MACH_IO_H
 220         bool
 221         help
 222           Select this when mach/io.h is required to provide special
 223           definitions for this platform.  The need for mach/io.h should
 224           be avoided when possible.
 225
 226 config NEED_MACH_MEMORY_H
 227         bool
 228         help
 229           Select this when mach/memory.h is required to provide special
 230           definitions for this platform.  The need for mach/memory.h should
 231           be avoided when possible.
 232
 233 config PHYS_OFFSET
 234         hex "Physical address of main memory" if MMU
 235         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 236         default DRAM_BASE if !MMU
 237         help
 238           Please provide the physical address corresponding to the
 239           location of main memory in your system.
 240
 241 config GENERIC_BUG
 242         def_bool y
 243         depends on BUG
 244
 245 source "init/Kconfig"
 246
 247 source "kernel/Kconfig.freezer"
 248
 249 menu "System Type"
 250
 251 config MMU
 252         bool "MMU-based Paged Memory Management Support"
 253         default y
 254         help
 255           Select if you want MMU-based virtualised addressing space
 256           support by paged memory management. If unsure, say 'Y'.
 257
 258 #
 259 # The "ARM system type" choice list is ordered alphabetically by option
 260 # text.  Please add new entries in the option alphabetic order.
 261 #
 262 choice
 263         prompt "ARM system type"
 264         default ARCH_MULTIPLATFORM
 265
 266 config ARCH_MULTIPLATFORM
 267         bool "Allow multiple platforms to be selected"
 268         depends on MMU
 269         select ARM_PATCH_PHYS_VIRT
 270         select AUTO_ZRELADDR
 271         select COMMON_CLK
 272         select MULTI_IRQ_HANDLER
 273         select SPARSE_IRQ
 274         select USE_OF
 275
 276 config ARCH_INTEGRATOR
 277         bool "ARM Ltd. Integrator family"
 278         select ARCH_HAS_CPUFREQ
 279         select ARM_AMBA
 280         select COMMON_CLK
 281         select COMMON_CLK_VERSATILE
 282         select GENERIC_CLOCKEVENTS
 283         select HAVE_TCM
 284         select ICST
 285         select MULTI_IRQ_HANDLER
 286         select NEED_MACH_MEMORY_H
 287         select PLAT_VERSATILE
 288         select SPARSE_IRQ
 289         select VERSATILE_FPGA_IRQ
 290         help
 291           Support for ARM's Integrator platform.
 292
 293 config ARCH_REALVIEW
 294         bool "ARM Ltd. RealView family"
 295         select ARCH_WANT_OPTIONAL_GPIOLIB
 296         select ARM_AMBA
 297         select ARM_TIMER_SP804
 298         select COMMON_CLK
 299         select COMMON_CLK_VERSATILE
 300         select GENERIC_CLOCKEVENTS
 301         select GPIO_PL061 if GPIOLIB
 302         select ICST
 303         select NEED_MACH_MEMORY_H
 304         select PLAT_VERSATILE
 305         select PLAT_VERSATILE_CLCD
 306         help
 307           This enables support for ARM Ltd RealView boards.
 308
 309 config ARCH_VERSATILE
 310         bool "ARM Ltd. Versatile family"
 311         select ARCH_WANT_OPTIONAL_GPIOLIB
 312         select ARM_AMBA
 313         select ARM_TIMER_SP804
 314         select ARM_VIC
 315         select CLKDEV_LOOKUP
 316         select GENERIC_CLOCKEVENTS
 317         select HAVE_MACH_CLKDEV
 318         select ICST
 319         select PLAT_VERSATILE
 320         select PLAT_VERSATILE_CLCD
 321         select PLAT_VERSATILE_CLOCK
 322         select VERSATILE_FPGA_IRQ
 323         help
 324           This enables support for ARM Ltd Versatile board.
 325
 326 config ARCH_AT91
 327         bool "Atmel AT91"
 328         select ARCH_REQUIRE_GPIOLIB
 329         select CLKDEV_LOOKUP
 330         select HAVE_CLK
 331         select IRQ_DOMAIN
 332         select NEED_MACH_GPIO_H
 333         select NEED_MACH_IO_H if PCCARD
 334         select PINCTRL
 335         select PINCTRL_AT91 if USE_OF
 336         help
 337           This enables support for systems based on Atmel
 338           AT91RM9200 and AT91SAM9* processors.
 339
 340 config ARCH_BCM2835
 341         bool "Broadcom BCM2835 family"
 342         select ARCH_REQUIRE_GPIOLIB
 343         select ARM_AMBA
 344         select ARM_ERRATA_411920
 345         select ARM_TIMER_SP804
 346         select CLKDEV_LOOKUP
 347         select CLKSRC_OF
 348         select COMMON_CLK
 349         select CPU_V6
 350         select GENERIC_CLOCKEVENTS
 351         select MULTI_IRQ_HANDLER
 352         select PINCTRL
 353         select PINCTRL_BCM2835
 354         select SPARSE_IRQ
 355         select USE_OF
 356         help
 357           This enables support for the Broadcom BCM2835 SoC. This SoC is
 358           use in the Raspberry Pi, and Roku 2 devices.
 359
 360 config ARCH_CNS3XXX
 361         bool "Cavium Networks CNS3XXX family"
 362         select ARM_GIC
 363         select CPU_V6K
 364         select GENERIC_CLOCKEVENTS
 365         select MIGHT_HAVE_CACHE_L2X0
 366         select MIGHT_HAVE_PCI
 367         select PCI_DOMAINS if PCI
 368         help
 369           Support for Cavium Networks CNS3XXX platform.
 370
 371 config ARCH_CLPS711X
 372         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 373         select ARCH_REQUIRE_GPIOLIB
 374         select AUTO_ZRELADDR
 375         select CLKDEV_LOOKUP
 376         select COMMON_CLK
 377         select CPU_ARM720T
 378         select GENERIC_CLOCKEVENTS
 379         select MULTI_IRQ_HANDLER
 380         select NEED_MACH_MEMORY_H
 381         select SPARSE_IRQ
 382         help
 383           Support for Cirrus Logic 711x/721x/731x based boards.
 384
 385 config ARCH_GEMINI
 386         bool "Cortina Systems Gemini"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select ARCH_USES_GETTIMEOFFSET
 389         select CPU_FA526
 390         help
 391           Support for the Cortina Systems Gemini family SoCs
 392
 393 config ARCH_SIRF
 394         bool "CSR SiRF"
 395         select ARCH_REQUIRE_GPIOLIB
 396         select COMMON_CLK
 397         select GENERIC_CLOCKEVENTS
 398         select GENERIC_IRQ_CHIP
 399         select MIGHT_HAVE_CACHE_L2X0
 400         select NO_IOPORT
 401         select PINCTRL
 402         select PINCTRL_SIRF
 403         select USE_OF
 404         help
 405           Support for CSR SiRFprimaII/Marco/Polo platforms
 406
 407 config ARCH_EBSA110
 408         bool "EBSA-110"
 409         select ARCH_USES_GETTIMEOFFSET
 410         select CPU_SA110
 411         select ISA
 412         select NEED_MACH_IO_H
 413         select NEED_MACH_MEMORY_H
 414         select NO_IOPORT
 415         help
 416           This is an evaluation board for the StrongARM processor available
 417           from Digital. It has limited hardware on-board, including an
 418           Ethernet interface, two PCMCIA sockets, two serial ports and a
 419           parallel port.
 420
 421 config ARCH_EP93XX
 422         bool "EP93xx-based"
 423         select ARCH_HAS_HOLES_MEMORYMODEL
 424         select ARCH_REQUIRE_GPIOLIB
 425         select ARCH_USES_GETTIMEOFFSET
 426         select ARM_AMBA
 427         select ARM_VIC
 428         select CLKDEV_LOOKUP
 429         select CPU_ARM920T
 430         select NEED_MACH_MEMORY_H
 431         help
 432           This enables support for the Cirrus EP93xx series of CPUs.
 433
 434 config ARCH_FOOTBRIDGE
 435         bool "FootBridge"
 436         select CPU_SA110
 437         select FOOTBRIDGE
 438         select GENERIC_CLOCKEVENTS
 439         select HAVE_IDE
 440         select NEED_MACH_IO_H if !MMU
 441         select NEED_MACH_MEMORY_H
 442         help
 443           Support for systems based on the DC21285 companion chip
 444           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 445
 446 config ARCH_MXS
 447         bool "Freescale MXS-based"
 448         select ARCH_REQUIRE_GPIOLIB
 449         select CLKDEV_LOOKUP
 450         select CLKSRC_MMIO
 451         select COMMON_CLK
 452         select GENERIC_CLOCKEVENTS
 453         select HAVE_CLK_PREPARE
 454         select MULTI_IRQ_HANDLER
 455         select PINCTRL
 456         select SPARSE_IRQ
 457         select USE_OF
 458         help
 459           Support for Freescale MXS-based family of processors
 460
 461 config ARCH_NETX
 462         bool "Hilscher NetX based"
 463         select ARM_VIC
 464         select CLKSRC_MMIO
 465         select CPU_ARM926T
 466         select GENERIC_CLOCKEVENTS
 467         help
 468           This enables support for systems based on the Hilscher NetX Soc
 469
 470 config ARCH_H720X
 471         bool "Hynix HMS720x-based"
 472         select ARCH_USES_GETTIMEOFFSET
 473         select CPU_ARM720T
 474         select ISA_DMA_API
 475         help
 476           This enables support for systems based on the Hynix HMS720x
 477
 478 config ARCH_IOP13XX
 479         bool "IOP13xx-based"
 480         depends on MMU
 481         select ARCH_SUPPORTS_MSI
 482         select CPU_XSC3
 483         select NEED_MACH_MEMORY_H
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         select VMSPLIT_1G
 488         help
 489           Support for Intel's IOP13XX (XScale) family of processors.
 490
 491 config ARCH_IOP32X
 492         bool "IOP32x-based"
 493         depends on MMU
 494         select ARCH_REQUIRE_GPIOLIB
 495         select CPU_XSCALE
 496         select NEED_MACH_GPIO_H
 497         select NEED_RET_TO_USER
 498         select PCI
 499         select PLAT_IOP
 500         help
 501           Support for Intel's 80219 and IOP32X (XScale) family of
 502           processors.
 503
 504 config ARCH_IOP33X
 505         bool "IOP33x-based"
 506         depends on MMU
 507         select ARCH_REQUIRE_GPIOLIB
 508         select CPU_XSCALE
 509         select NEED_MACH_GPIO_H
 510         select NEED_RET_TO_USER
 511         select PCI
 512         select PLAT_IOP
 513         help
 514           Support for Intel's IOP33X (XScale) family of processors.
 515
 516 config ARCH_IXP4XX
 517         bool "IXP4xx-based"
 518         depends on MMU
 519         select ARCH_HAS_DMA_SET_COHERENT_MASK
 520         select ARCH_REQUIRE_GPIOLIB
 521         select CLKSRC_MMIO
 522         select CPU_XSCALE
 523         select DMABOUNCE if PCI
 524         select GENERIC_CLOCKEVENTS
 525         select MIGHT_HAVE_PCI
 526         select NEED_MACH_IO_H
 527         help
 528           Support for Intel's IXP4XX (XScale) family of processors.
 529
 530 config ARCH_DOVE
 531         bool "Marvell Dove"
 532         select ARCH_REQUIRE_GPIOLIB
 533         select COMMON_CLK_DOVE
 534         select CPU_V7
 535         select GENERIC_CLOCKEVENTS
 536         select MIGHT_HAVE_PCI
 537         select PINCTRL
 538         select PINCTRL_DOVE
 539         select PLAT_ORION_LEGACY
 540         select USB_ARCH_HAS_EHCI
 541         help
 542           Support for the Marvell Dove SoC 88AP510
 543
 544 config ARCH_KIRKWOOD
 545         bool "Marvell Kirkwood"
 546         select ARCH_REQUIRE_GPIOLIB
 547         select CPU_FEROCEON
 548         select GENERIC_CLOCKEVENTS
 549         select PCI
 550         select PCI_QUIRKS
 551         select PINCTRL
 552         select PINCTRL_KIRKWOOD
 553         select PLAT_ORION_LEGACY
 554         help
 555           Support for the following Marvell Kirkwood series SoCs:
 556           88F6180, 88F6192 and 88F6281.
 557
 558 config ARCH_MV78XX0
 559         bool "Marvell MV78xx0"
 560         select ARCH_REQUIRE_GPIOLIB
 561         select CPU_FEROCEON
 562         select GENERIC_CLOCKEVENTS
 563         select PCI
 564         select PLAT_ORION_LEGACY
 565         help
 566           Support for the following Marvell MV78xx0 series SoCs:
 567           MV781x0, MV782x0.
 568
 569 config ARCH_ORION5X
 570         bool "Marvell Orion"
 571         depends on MMU
 572         select ARCH_REQUIRE_GPIOLIB
 573         select CPU_FEROCEON
 574         select GENERIC_CLOCKEVENTS
 575         select PCI
 576         select PLAT_ORION_LEGACY
 577         help
 578           Support for the following Marvell Orion 5x series SoCs:
 579           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 580           Orion-2 (5281), Orion-1-90 (6183).
 581
 582 config ARCH_MMP
 583         bool "Marvell PXA168/910/MMP2"
 584         depends on MMU
 585         select ARCH_REQUIRE_GPIOLIB
 586         select CLKDEV_LOOKUP
 587         select GENERIC_ALLOCATOR
 588         select GENERIC_CLOCKEVENTS
 589         select GPIO_PXA
 590         select IRQ_DOMAIN
 591         select NEED_MACH_GPIO_H
 592         select PINCTRL
 593         select PLAT_PXA
 594         select SPARSE_IRQ
 595         help
 596           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 597
 598 config ARCH_KS8695
 599         bool "Micrel/Kendin KS8695"
 600         select ARCH_REQUIRE_GPIOLIB
 601         select CLKSRC_MMIO
 602         select CPU_ARM922T
 603         select GENERIC_CLOCKEVENTS
 604         select NEED_MACH_MEMORY_H
 605         help
 606           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 607           System-on-Chip devices.
 608
 609 config ARCH_W90X900
 610         bool "Nuvoton W90X900 CPU"
 611         select ARCH_REQUIRE_GPIOLIB
 612         select CLKDEV_LOOKUP
 613         select CLKSRC_MMIO
 614         select CPU_ARM926T
 615         select GENERIC_CLOCKEVENTS
 616         help
 617           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 618           At present, the w90x900 has been renamed nuc900, regarding
 619           the ARM series product line, you can login the following
 620           link address to know more.
 621
 622           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 623                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 624
 625 config ARCH_LPC32XX
 626         bool "NXP LPC32XX"
 627         select ARCH_REQUIRE_GPIOLIB
 628         select ARM_AMBA
 629         select CLKDEV_LOOKUP
 630         select CLKSRC_MMIO
 631         select CPU_ARM926T
 632         select GENERIC_CLOCKEVENTS
 633         select HAVE_IDE
 634         select HAVE_PWM
 635         select USB_ARCH_HAS_OHCI
 636         select USE_OF
 637         help
 638           Support for the NXP LPC32XX family of processors
 639
 640 config ARCH_TEGRA
 641         bool "NVIDIA Tegra"
 642         select ARCH_HAS_CPUFREQ
 643         select CLKDEV_LOOKUP
 644         select CLKSRC_MMIO
 645         select CLKSRC_OF
 646         select COMMON_CLK
 647         select GENERIC_CLOCKEVENTS
 648         select HAVE_CLK
 649         select HAVE_SMP
 650         select MIGHT_HAVE_CACHE_L2X0
 651         select SPARSE_IRQ
 652         select USE_OF
 653         help
 654           This enables support for NVIDIA Tegra based systems (Tegra APX,
 655           Tegra 6xx and Tegra 2 series).
 656
 657 config ARCH_PXA
 658         bool "PXA2xx/PXA3xx-based"
 659         depends on MMU
 660         select ARCH_HAS_CPUFREQ
 661         select ARCH_MTD_XIP
 662         select ARCH_REQUIRE_GPIOLIB
 663         select ARM_CPU_SUSPEND if PM
 664         select AUTO_ZRELADDR
 665         select CLKDEV_LOOKUP
 666         select CLKSRC_MMIO
 667         select GENERIC_CLOCKEVENTS
 668         select GPIO_PXA
 669         select HAVE_IDE
 670         select MULTI_IRQ_HANDLER
 671         select NEED_MACH_GPIO_H
 672         select PLAT_PXA
 673         select SPARSE_IRQ
 674         help
 675           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 676
 677 config ARCH_MSM
 678         bool "Qualcomm MSM"
 679         select ARCH_REQUIRE_GPIOLIB
 680         select CLKDEV_LOOKUP
 681         select GENERIC_CLOCKEVENTS
 682         select HAVE_CLK
 683         help
 684           Support for Qualcomm MSM/QSD based systems.  This runs on the
 685           apps processor of the MSM/QSD and depends on a shared memory
 686           interface to the modem processor which runs the baseband
 687           stack and controls some vital subsystems
 688           (clock and power control, etc).
 689
 690 config ARCH_SHMOBILE
 691         bool "Renesas SH-Mobile / R-Mobile"
 692         select CLKDEV_LOOKUP
 693         select GENERIC_CLOCKEVENTS
 694         select HAVE_CLK
 695         select HAVE_MACH_CLKDEV
 696         select HAVE_SMP
 697         select MIGHT_HAVE_CACHE_L2X0
 698         select MULTI_IRQ_HANDLER
 699         select NEED_MACH_MEMORY_H
 700         select NO_IOPORT
 701         select PM_GENERIC_DOMAINS if PM
 702         select SPARSE_IRQ
 703         help
 704           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 705
 706 config ARCH_RPC
 707         bool "RiscPC"
 708         select ARCH_ACORN
 709         select ARCH_MAY_HAVE_PC_FDC
 710         select ARCH_SPARSEMEM_ENABLE
 711         select ARCH_USES_GETTIMEOFFSET
 712         select FIQ
 713         select HAVE_IDE
 714         select HAVE_PATA_PLATFORM
 715         select ISA_DMA_API
 716         select NEED_MACH_IO_H
 717         select NEED_MACH_MEMORY_H
 718         select NO_IOPORT
 719         help
 720           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 721           CD-ROM interface, serial and parallel port, and the floppy drive.
 722
 723 config ARCH_SA1100
 724         bool "SA1100-based"
 725         select ARCH_HAS_CPUFREQ
 726         select ARCH_MTD_XIP
 727         select ARCH_REQUIRE_GPIOLIB
 728         select ARCH_SPARSEMEM_ENABLE
 729         select CLKDEV_LOOKUP
 730         select CLKSRC_MMIO
 731         select CPU_FREQ
 732         select CPU_SA1100
 733         select GENERIC_CLOCKEVENTS
 734         select HAVE_IDE
 735         select ISA
 736         select NEED_MACH_GPIO_H
 737         select NEED_MACH_MEMORY_H
 738         select SPARSE_IRQ
 739         help
 740           Support for StrongARM 11x0 based boards.
 741
 742 config ARCH_S3C24XX
 743         bool "Samsung S3C24XX SoCs"
 744         select ARCH_HAS_CPUFREQ
 745         select ARCH_USES_GETTIMEOFFSET
 746         select CLKDEV_LOOKUP
 747         select HAVE_CLK
 748         select HAVE_S3C2410_I2C if I2C
 749         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 750         select HAVE_S3C_RTC if RTC_CLASS
 751         select NEED_MACH_GPIO_H
 752         select NEED_MACH_IO_H
 753         help
 754           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 755           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 756           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 757           Samsung SMDK2410 development board (and derivatives).
 758
 759 config ARCH_S3C64XX
 760         bool "Samsung S3C64XX"
 761         select ARCH_HAS_CPUFREQ
 762         select ARCH_REQUIRE_GPIOLIB
 763         select ARCH_USES_GETTIMEOFFSET
 764         select ARM_VIC
 765         select CLKDEV_LOOKUP
 766         select CPU_V6
 767         select HAVE_CLK
 768         select HAVE_S3C2410_I2C if I2C
 769         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 770         select HAVE_TCM
 771         select NEED_MACH_GPIO_H
 772         select NO_IOPORT
 773         select PLAT_SAMSUNG
 774         select S3C_DEV_NAND
 775         select S3C_GPIO_TRACK
 776         select SAMSUNG_CLKSRC
 777         select SAMSUNG_GPIOLIB_4BIT
 778         select SAMSUNG_IRQ_VIC_TIMER
 779         select USB_ARCH_HAS_OHCI
 780         help
 781           Samsung S3C64XX series based systems
 782
 783 config ARCH_S5P64X0
 784         bool "Samsung S5P6440 S5P6450"
 785         select CLKDEV_LOOKUP
 786         select CLKSRC_MMIO
 787         select CPU_V6
 788         select GENERIC_CLOCKEVENTS
 789         select HAVE_CLK
 790         select HAVE_S3C2410_I2C if I2C
 791         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 792         select HAVE_S3C_RTC if RTC_CLASS
 793         select NEED_MACH_GPIO_H
 794         help
 795           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 796           SMDK6450.
 797
 798 config ARCH_S5PC100
 799         bool "Samsung S5PC100"
 800         select ARCH_USES_GETTIMEOFFSET
 801         select CLKDEV_LOOKUP
 802         select CPU_V7
 803         select HAVE_CLK
 804         select HAVE_S3C2410_I2C if I2C
 805         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 806         select HAVE_S3C_RTC if RTC_CLASS
 807         select NEED_MACH_GPIO_H
 808         help
 809           Samsung S5PC100 series based systems
 810
 811 config ARCH_S5PV210
 812         bool "Samsung S5PV210/S5PC110"
 813         select ARCH_HAS_CPUFREQ
 814         select ARCH_HAS_HOLES_MEMORYMODEL
 815         select ARCH_SPARSEMEM_ENABLE
 816         select CLKDEV_LOOKUP
 817         select CLKSRC_MMIO
 818         select CPU_V7
 819         select GENERIC_CLOCKEVENTS
 820         select HAVE_CLK
 821         select HAVE_S3C2410_I2C if I2C
 822         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 823         select HAVE_S3C_RTC if RTC_CLASS
 824         select NEED_MACH_GPIO_H
 825         select NEED_MACH_MEMORY_H
 826         help
 827           Samsung S5PV210/S5PC110 series based systems
 828
 829 config ARCH_EXYNOS
 830         bool "Samsung EXYNOS"
 831         select ARCH_HAS_CPUFREQ
 832         select ARCH_HAS_HOLES_MEMORYMODEL
 833         select ARCH_SPARSEMEM_ENABLE
 834         select CLKDEV_LOOKUP
 835         select CPU_V7
 836         select GENERIC_CLOCKEVENTS
 837         select HAVE_CLK
 838         select HAVE_S3C2410_I2C if I2C
 839         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 840         select HAVE_S3C_RTC if RTC_CLASS
 841         select NEED_MACH_GPIO_H
 842         select NEED_MACH_MEMORY_H
 843         help
 844           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 845
 846 config ARCH_SHARK
 847         bool "Shark"
 848         select ARCH_USES_GETTIMEOFFSET
 849         select CPU_SA110
 850         select ISA
 851         select ISA_DMA
 852         select NEED_MACH_MEMORY_H
 853         select PCI
 854         select ZONE_DMA
 855         help
 856           Support for the StrongARM based Digital DNARD machine, also known
 857           as "Shark" (<http://www.shark-linux.de/shark.html>).
 858
 859 config ARCH_U300
 860         bool "ST-Ericsson U300 Series"
 861         depends on MMU
 862         select ARCH_REQUIRE_GPIOLIB
 863         select ARM_AMBA
 864         select ARM_PATCH_PHYS_VIRT
 865         select ARM_VIC
 866         select CLKDEV_LOOKUP
 867         select CLKSRC_MMIO
 868         select COMMON_CLK
 869         select CPU_ARM926T
 870         select GENERIC_CLOCKEVENTS
 871         select HAVE_TCM
 872         select SPARSE_IRQ
 873         help
 874           Support for ST-Ericsson U300 series mobile platforms.
 875
 876 config ARCH_U8500
 877         bool "ST-Ericsson U8500 Series"
 878         depends on MMU
 879         select ARCH_HAS_CPUFREQ
 880         select ARCH_REQUIRE_GPIOLIB
 881         select ARM_AMBA
 882         select CLKDEV_LOOKUP
 883         select CPU_V7
 884         select GENERIC_CLOCKEVENTS
 885         select HAVE_SMP
 886         select MIGHT_HAVE_CACHE_L2X0
 887         select SPARSE_IRQ
 888         help
 889           Support for ST-Ericsson's Ux500 architecture
 890
 891 config ARCH_NOMADIK
 892         bool "STMicroelectronics Nomadik"
 893         select ARCH_REQUIRE_GPIOLIB
 894         select ARM_AMBA
 895         select ARM_VIC
 896         select COMMON_CLK
 897         select CPU_ARM926T
 898         select GENERIC_CLOCKEVENTS
 899         select MIGHT_HAVE_CACHE_L2X0
 900         select PINCTRL
 901         select PINCTRL_STN8815
 902         select SPARSE_IRQ
 903         help
 904           Support for the Nomadik platform by ST-Ericsson
 905
 906 config PLAT_SPEAR
 907         bool "ST SPEAr"
 908         select ARCH_HAS_CPUFREQ
 909         select ARCH_REQUIRE_GPIOLIB
 910         select ARM_AMBA
 911         select CLKDEV_LOOKUP
 912         select CLKSRC_MMIO
 913         select COMMON_CLK
 914         select GENERIC_CLOCKEVENTS
 915         select HAVE_CLK
 916         help
 917           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 918
 919 config ARCH_DAVINCI
 920         bool "TI DaVinci"
 921         select ARCH_HAS_HOLES_MEMORYMODEL
 922         select ARCH_REQUIRE_GPIOLIB
 923         select CLKDEV_LOOKUP
 924         select GENERIC_ALLOCATOR
 925         select GENERIC_CLOCKEVENTS
 926         select GENERIC_IRQ_CHIP
 927         select HAVE_IDE
 928         select NEED_MACH_GPIO_H
 929         select USE_OF
 930         select ZONE_DMA
 931         help
 932           Support for TI's DaVinci platform.
 933
 934 config ARCH_OMAP
 935         bool "TI OMAP"
 936         depends on MMU
 937         select ARCH_HAS_CPUFREQ
 938         select ARCH_HAS_HOLES_MEMORYMODEL
 939         select ARCH_REQUIRE_GPIOLIB
 940         select CLKSRC_MMIO
 941         select GENERIC_CLOCKEVENTS
 942         select HAVE_CLK
 943         help
 944           Support for TI's OMAP platform (OMAP1/2/3/4).
 945
 946 config ARCH_VT8500_SINGLE
 947         bool "VIA/WonderMedia 85xx"
 948         select ARCH_HAS_CPUFREQ
 949         select ARCH_REQUIRE_GPIOLIB
 950         select CLKDEV_LOOKUP
 951         select COMMON_CLK
 952         select CPU_ARM926T
 953         select GENERIC_CLOCKEVENTS
 954         select HAVE_CLK
 955         select MULTI_IRQ_HANDLER
 956         select SPARSE_IRQ
 957         select USE_OF
 958         help
 959           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 960
 961 endchoice
 962
 963 menu "Multiple platform selection"
 964         depends on ARCH_MULTIPLATFORM
 965
 966 comment "CPU Core family selection"
 967
 968 config ARCH_MULTI_V4
 969         bool "ARMv4 based platforms (FA526, StrongARM)"
 970         depends on !ARCH_MULTI_V6_V7
 971         select ARCH_MULTI_V4_V5
 972
 973 config ARCH_MULTI_V4T
 974         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 975         depends on !ARCH_MULTI_V6_V7
 976         select ARCH_MULTI_V4_V5
 977
 978 config ARCH_MULTI_V5
 979         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 980         depends on !ARCH_MULTI_V6_V7
 981         select ARCH_MULTI_V4_V5
 982
 983 config ARCH_MULTI_V4_V5
 984         bool
 985
 986 config ARCH_MULTI_V6
 987         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 988         select ARCH_MULTI_V6_V7
 989         select CPU_V6
 990
 991 config ARCH_MULTI_V7
 992         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 993         default y
 994         select ARCH_MULTI_V6_V7
 995         select ARCH_VEXPRESS
 996         select CPU_V7
 997
 998 config ARCH_MULTI_V6_V7
 999         bool
1000
1001 config ARCH_MULTI_CPU_AUTO
1002         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1003         select ARCH_MULTI_V5
1004
1005 endmenu
1006
1007 #
1008 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1009 # Kconfigs may be included either alphabetically (according to the
1010 # plat- suffix) or along side the corresponding mach-* source.
1011 #
1012 source "arch/arm/mach-mvebu/Kconfig"
1013
1014 source "arch/arm/mach-at91/Kconfig"
1015
1016 source "arch/arm/mach-bcm/Kconfig"
1017
1018 source "arch/arm/mach-clps711x/Kconfig"
1019
1020 source "arch/arm/mach-cns3xxx/Kconfig"
1021
1022 source "arch/arm/mach-davinci/Kconfig"
1023
1024 source "arch/arm/mach-dove/Kconfig"
1025
1026 source "arch/arm/mach-ep93xx/Kconfig"
1027
1028 source "arch/arm/mach-footbridge/Kconfig"
1029
1030 source "arch/arm/mach-gemini/Kconfig"
1031
1032 source "arch/arm/mach-h720x/Kconfig"
1033
1034 source "arch/arm/mach-highbank/Kconfig"
1035
1036 source "arch/arm/mach-integrator/Kconfig"
1037
1038 source "arch/arm/mach-iop32x/Kconfig"
1039
1040 source "arch/arm/mach-iop33x/Kconfig"
1041
1042 source "arch/arm/mach-iop13xx/Kconfig"
1043
1044 source "arch/arm/mach-ixp4xx/Kconfig"
1045
1046 source "arch/arm/mach-kirkwood/Kconfig"
1047
1048 source "arch/arm/mach-ks8695/Kconfig"
1049
1050 source "arch/arm/mach-msm/Kconfig"
1051
1052 source "arch/arm/mach-mv78xx0/Kconfig"
1053
1054 source "arch/arm/mach-imx/Kconfig"
1055
1056 source "arch/arm/mach-mxs/Kconfig"
1057
1058 source "arch/arm/mach-netx/Kconfig"
1059
1060 source "arch/arm/mach-nomadik/Kconfig"
1061
1062 source "arch/arm/plat-omap/Kconfig"
1063
1064 source "arch/arm/mach-omap1/Kconfig"
1065
1066 source "arch/arm/mach-omap2/Kconfig"
1067
1068 source "arch/arm/mach-orion5x/Kconfig"
1069
1070 source "arch/arm/mach-picoxcell/Kconfig"
1071
1072 source "arch/arm/mach-pxa/Kconfig"
1073 source "arch/arm/plat-pxa/Kconfig"
1074
1075 source "arch/arm/mach-mmp/Kconfig"
1076
1077 source "arch/arm/mach-realview/Kconfig"
1078
1079 source "arch/arm/mach-sa1100/Kconfig"
1080
1081 source "arch/arm/plat-samsung/Kconfig"
1082 source "arch/arm/plat-s3c24xx/Kconfig"
1083
1084 source "arch/arm/mach-socfpga/Kconfig"
1085
1086 source "arch/arm/plat-spear/Kconfig"
1087
1088 source "arch/arm/mach-s3c24xx/Kconfig"
1089 if ARCH_S3C24XX
1090 source "arch/arm/mach-s3c2412/Kconfig"
1091 source "arch/arm/mach-s3c2440/Kconfig"
1092 endif
1093
1094 if ARCH_S3C64XX
1095 source "arch/arm/mach-s3c64xx/Kconfig"
1096 endif
1097
1098 source "arch/arm/mach-s5p64x0/Kconfig"
1099
1100 source "arch/arm/mach-s5pc100/Kconfig"
1101
1102 source "arch/arm/mach-s5pv210/Kconfig"
1103
1104 source "arch/arm/mach-exynos/Kconfig"
1105
1106 source "arch/arm/mach-shmobile/Kconfig"
1107
1108 source "arch/arm/mach-sunxi/Kconfig"
1109
1110 source "arch/arm/mach-prima2/Kconfig"
1111
1112 source "arch/arm/mach-tegra/Kconfig"
1113
1114 source "arch/arm/mach-u300/Kconfig"
1115
1116 source "arch/arm/mach-ux500/Kconfig"
1117
1118 source "arch/arm/mach-versatile/Kconfig"
1119
1120 source "arch/arm/mach-vexpress/Kconfig"
1121 source "arch/arm/plat-versatile/Kconfig"
1122
1123 source "arch/arm/mach-vt8500/Kconfig"
1124
1125 source "arch/arm/mach-w90x900/Kconfig"
1126
1127 source "arch/arm/mach-zynq/Kconfig"
1128
1129 # Definitions to make life easier
1130 config ARCH_ACORN
1131         bool
1132
1133 config PLAT_IOP
1134         bool
1135         select GENERIC_CLOCKEVENTS
1136
1137 config PLAT_ORION
1138         bool
1139         select CLKSRC_MMIO
1140         select COMMON_CLK
1141         select GENERIC_IRQ_CHIP
1142         select IRQ_DOMAIN
1143
1144 config PLAT_ORION_LEGACY
1145         bool
1146         select PLAT_ORION
1147
1148 config PLAT_PXA
1149         bool
1150
1151 config PLAT_VERSATILE
1152         bool
1153
1154 config ARM_TIMER_SP804
1155         bool
1156         select CLKSRC_MMIO
1157         select HAVE_SCHED_CLOCK
1158
1159 source arch/arm/mm/Kconfig
1160
1161 config ARM_NR_BANKS
1162         int
1163         default 16 if ARCH_EP93XX
1164         default 8
1165
1166 config IWMMXT
1167         bool "Enable iWMMXt support"
1168         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1169         default y if PXA27x || PXA3xx || ARCH_MMP
1170         help
1171           Enable support for iWMMXt context switching at run time if
1172           running on a CPU that supports it.
1173
1174 config XSCALE_PMU
1175         bool
1176         depends on CPU_XSCALE
1177         default y
1178
1179 config MULTI_IRQ_HANDLER
1180         bool
1181         help
1182           Allow each machine to specify it's own IRQ handler at run time.
1183
1184 if !MMU
1185 source "arch/arm/Kconfig-nommu"
1186 endif
1187
1188 config ARM_ERRATA_326103
1189         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1190         depends on CPU_V6
1191         help
1192           Executing a SWP instruction to read-only memory does not set bit 11
1193           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1194           treat the access as a read, preventing a COW from occurring and
1195           causing the faulting task to livelock.
1196
1197 config ARM_ERRATA_411920
1198         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1199         depends on CPU_V6 || CPU_V6K
1200         help
1201           Invalidation of the Instruction Cache operation can
1202           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1203           It does not affect the MPCore. This option enables the ARM Ltd.
1204           recommended workaround.
1205
1206 config ARM_ERRATA_430973
1207         bool "ARM errata: Stale prediction on replaced interworking branch"
1208         depends on CPU_V7
1209         help
1210           This option enables the workaround for the 430973 Cortex-A8
1211           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1212           interworking branch is replaced with another code sequence at the
1213           same virtual address, whether due to self-modifying code or virtual
1214           to physical address re-mapping, Cortex-A8 does not recover from the
1215           stale interworking branch prediction. This results in Cortex-A8
1216           executing the new code sequence in the incorrect ARM or Thumb state.
1217           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1218           and also flushes the branch target cache at every context switch.
1219           Note that setting specific bits in the ACTLR register may not be
1220           available in non-secure mode.
1221
1222 config ARM_ERRATA_458693
1223         bool "ARM errata: Processor deadlock when a false hazard is created"
1224         depends on CPU_V7
1225         depends on !ARCH_MULTIPLATFORM
1226         help
1227           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1228           erratum. For very specific sequences of memory operations, it is
1229           possible for a hazard condition intended for a cache line to instead
1230           be incorrectly associated with a different cache line. This false
1231           hazard might then cause a processor deadlock. The workaround enables
1232           the L1 caching of the NEON accesses and disables the PLD instruction
1233           in the ACTLR register. Note that setting specific bits in the ACTLR
1234           register may not be available in non-secure mode.
1235
1236 config ARM_ERRATA_460075
1237         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1238         depends on CPU_V7
1239         depends on !ARCH_MULTIPLATFORM
1240         help
1241           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1242           erratum. Any asynchronous access to the L2 cache may encounter a
1243           situation in which recent store transactions to the L2 cache are lost
1244           and overwritten with stale memory contents from external memory. The
1245           workaround disables the write-allocate mode for the L2 cache via the
1246           ACTLR register. Note that setting specific bits in the ACTLR register
1247           may not be available in non-secure mode.
1248
1249 config ARM_ERRATA_742230
1250         bool "ARM errata: DMB operation may be faulty"
1251         depends on CPU_V7 && SMP
1252         depends on !ARCH_MULTIPLATFORM
1253         help
1254           This option enables the workaround for the 742230 Cortex-A9
1255           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1256           between two write operations may not ensure the correct visibility
1257           ordering of the two writes. This workaround sets a specific bit in
1258           the diagnostic register of the Cortex-A9 which causes the DMB
1259           instruction to behave as a DSB, ensuring the correct behaviour of
1260           the two writes.
1261
1262 config ARM_ERRATA_742231
1263         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1264         depends on CPU_V7 && SMP
1265         depends on !ARCH_MULTIPLATFORM
1266         help
1267           This option enables the workaround for the 742231 Cortex-A9
1268           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1269           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1270           accessing some data located in the same cache line, may get corrupted
1271           data due to bad handling of the address hazard when the line gets
1272           replaced from one of the CPUs at the same time as another CPU is
1273           accessing it. This workaround sets specific bits in the diagnostic
1274           register of the Cortex-A9 which reduces the linefill issuing
1275           capabilities of the processor.
1276
1277 config PL310_ERRATA_588369
1278         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1279         depends on CACHE_L2X0
1280         help
1281            The PL310 L2 cache controller implements three types of Clean &
1282            Invalidate maintenance operations: by Physical Address
1283            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1284            They are architecturally defined to behave as the execution of a
1285            clean operation followed immediately by an invalidate operation,
1286            both performing to the same memory location. This functionality
1287            is not correctly implemented in PL310 as clean lines are not
1288            invalidated as a result of these operations.
1289
1290 config ARM_ERRATA_720789
1291         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1292         depends on CPU_V7
1293         help
1294           This option enables the workaround for the 720789 Cortex-A9 (prior to
1295           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1296           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1297           As a consequence of this erratum, some TLB entries which should be
1298           invalidated are not, resulting in an incoherency in the system page
1299           tables. The workaround changes the TLB flushing routines to invalidate
1300           entries regardless of the ASID.
1301
1302 config PL310_ERRATA_727915
1303         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1304         depends on CACHE_L2X0
1305         help
1306           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1307           operation (offset 0x7FC). This operation runs in background so that
1308           PL310 can handle normal accesses while it is in progress. Under very
1309           rare circumstances, due to this erratum, write data can be lost when
1310           PL310 treats a cacheable write transaction during a Clean &
1311           Invalidate by Way operation.
1312
1313 config ARM_ERRATA_743622
1314         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1315         depends on CPU_V7
1316         depends on !ARCH_MULTIPLATFORM
1317         help
1318           This option enables the workaround for the 743622 Cortex-A9
1319           (r2p*) erratum. Under very rare conditions, a faulty
1320           optimisation in the Cortex-A9 Store Buffer may lead to data
1321           corruption. This workaround sets a specific bit in the diagnostic
1322           register of the Cortex-A9 which disables the Store Buffer
1323           optimisation, preventing the defect from occurring. This has no
1324           visible impact on the overall performance or power consumption of the
1325           processor.
1326
1327 config ARM_ERRATA_751472
1328         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1329         depends on CPU_V7
1330         depends on !ARCH_MULTIPLATFORM
1331         help
1332           This option enables the workaround for the 751472 Cortex-A9 (prior
1333           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1334           completion of a following broadcasted operation if the second
1335           operation is received by a CPU before the ICIALLUIS has completed,
1336           potentially leading to corrupted entries in the cache or TLB.
1337
1338 config PL310_ERRATA_753970
1339         bool "PL310 errata: cache sync operation may be faulty"
1340         depends on CACHE_PL310
1341         help
1342           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1343
1344           Under some condition the effect of cache sync operation on
1345           the store buffer still remains when the operation completes.
1346           This means that the store buffer is always asked to drain and
1347           this prevents it from merging any further writes. The workaround
1348           is to replace the normal offset of cache sync operation (0x730)
1349           by another offset targeting an unmapped PL310 register 0x740.
1350           This has the same effect as the cache sync operation: store buffer
1351           drain and waiting for all buffers empty.
1352
1353 config ARM_ERRATA_754322
1354         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1355         depends on CPU_V7
1356         help
1357           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1358           r3p*) erratum. A speculative memory access may cause a page table walk
1359           which starts prior to an ASID switch but completes afterwards. This
1360           can populate the micro-TLB with a stale entry which may be hit with
1361           the new ASID. This workaround places two dsb instructions in the mm
1362           switching code so that no page table walks can cross the ASID switch.
1363
1364 config ARM_ERRATA_754327
1365         bool "ARM errata: no automatic Store Buffer drain"
1366         depends on CPU_V7 && SMP
1367         help
1368           This option enables the workaround for the 754327 Cortex-A9 (prior to
1369           r2p0) erratum. The Store Buffer does not have any automatic draining
1370           mechanism and therefore a livelock may occur if an external agent
1371           continuously polls a memory location waiting to observe an update.
1372           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1373           written polling loops from denying visibility of updates to memory.
1374
1375 config ARM_ERRATA_364296
1376         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1377         depends on CPU_V6 && !SMP
1378         help
1379           This options enables the workaround for the 364296 ARM1136
1380           r0p2 erratum (possible cache data corruption with
1381           hit-under-miss enabled). It sets the undocumented bit 31 in
1382           the auxiliary control register and the FI bit in the control
1383           register, thus disabling hit-under-miss without putting the
1384           processor into full low interrupt latency mode. ARM11MPCore
1385           is not affected.
1386
1387 config ARM_ERRATA_764369
1388         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1389         depends on CPU_V7 && SMP
1390         help
1391           This option enables the workaround for erratum 764369
1392           affecting Cortex-A9 MPCore with two or more processors (all
1393           current revisions). Under certain timing circumstances, a data
1394           cache line maintenance operation by MVA targeting an Inner
1395           Shareable memory region may fail to proceed up to either the
1396           Point of Coherency or to the Point of Unification of the
1397           system. This workaround adds a DSB instruction before the
1398           relevant cache maintenance functions and sets a specific bit
1399           in the diagnostic control register of the SCU.
1400
1401 config PL310_ERRATA_769419
1402         bool "PL310 errata: no automatic Store Buffer drain"
1403         depends on CACHE_L2X0
1404         help
1405           On revisions of the PL310 prior to r3p2, the Store Buffer does
1406           not automatically drain. This can cause normal, non-cacheable
1407           writes to be retained when the memory system is idle, leading
1408           to suboptimal I/O performance for drivers using coherent DMA.
1409           This option adds a write barrier to the cpu_idle loop so that,
1410           on systems with an outer cache, the store buffer is drained
1411           explicitly.
1412
1413 config ARM_ERRATA_775420
1414        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1415        depends on CPU_V7
1416        help
1417          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1418          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1419          operation aborts with MMU exception, it might cause the processor
1420          to deadlock. This workaround puts DSB before executing ISB if
1421          an abort may occur on cache maintenance.
1422
1423 endmenu
1424
1425 source "arch/arm/common/Kconfig"
1426
1427 menu "Bus support"
1428
1429 config ARM_AMBA
1430         bool
1431
1432 config ISA
1433         bool
1434         help
1435           Find out whether you have ISA slots on your motherboard.  ISA is the
1436           name of a bus system, i.e. the way the CPU talks to the other stuff
1437           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1438           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1439           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1440
1441 # Select ISA DMA controller support
1442 config ISA_DMA
1443         bool
1444         select ISA_DMA_API
1445
1446 # Select ISA DMA interface
1447 config ISA_DMA_API
1448         bool
1449
1450 config PCI
1451         bool "PCI support" if MIGHT_HAVE_PCI
1452         help
1453           Find out whether you have a PCI motherboard. PCI is the name of a
1454           bus system, i.e. the way the CPU talks to the other stuff inside
1455           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1456           VESA. If you have PCI, say Y, otherwise N.
1457
1458 config PCI_DOMAINS
1459         bool
1460         depends on PCI
1461
1462 config PCI_NANOENGINE
1463         bool "BSE nanoEngine PCI support"
1464         depends on SA1100_NANOENGINE
1465         help
1466           Enable PCI on the BSE nanoEngine board.
1467
1468 config PCI_SYSCALL
1469         def_bool PCI
1470
1471 # Select the host bridge type
1472 config PCI_HOST_VIA82C505
1473         bool
1474         depends on PCI && ARCH_SHARK
1475         default y
1476
1477 config PCI_HOST_ITE8152
1478         bool
1479         depends on PCI && MACH_ARMCORE
1480         default y
1481         select DMABOUNCE
1482
1483 source "drivers/pci/Kconfig"
1484
1485 source "drivers/pcmcia/Kconfig"
1486
1487 endmenu
1488
1489 menu "Kernel Features"
1490
1491 config HAVE_SMP
1492         bool
1493         help
1494           This option should be selected by machines which have an SMP-
1495           capable CPU.
1496
1497           The only effect of this option is to make the SMP-related
1498           options available to the user for configuration.
1499
1500 config SMP
1501         bool "Symmetric Multi-Processing"
1502         depends on CPU_V6K || CPU_V7
1503         depends on GENERIC_CLOCKEVENTS
1504         depends on HAVE_SMP
1505         depends on MMU
1506         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1507         select USE_GENERIC_SMP_HELPERS
1508         help
1509           This enables support for systems with more than one CPU. If you have
1510           a system with only one CPU, like most personal computers, say N. If
1511           you have a system with more than one CPU, say Y.
1512
1513           If you say N here, the kernel will run on single and multiprocessor
1514           machines, but will use only one CPU of a multiprocessor machine. If
1515           you say Y here, the kernel will run on many, but not all, single
1516           processor machines. On a single processor machine, the kernel will
1517           run faster if you say N here.
1518
1519           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1520           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1521           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1522
1523           If you don't know what to do here, say N.
1524
1525 config SMP_ON_UP
1526         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1527         depends on EXPERIMENTAL
1528         depends on SMP && !XIP_KERNEL
1529         default y
1530         help
1531           SMP kernels contain instructions which fail on non-SMP processors.
1532           Enabling this option allows the kernel to modify itself to make
1533           these instructions safe.  Disabling it allows about 1K of space
1534           savings.
1535
1536           If you don't know what to do here, say Y.
1537
1538 config ARM_CPU_TOPOLOGY
1539         bool "Support cpu topology definition"
1540         depends on SMP && CPU_V7
1541         default y
1542         help
1543           Support ARM cpu topology definition. The MPIDR register defines
1544           affinity between processors which is then used to describe the cpu
1545           topology of an ARM System.
1546
1547 config SCHED_MC
1548         bool "Multi-core scheduler support"
1549         depends on ARM_CPU_TOPOLOGY
1550         help
1551           Multi-core scheduler support improves the CPU scheduler's decision
1552           making when dealing with multi-core CPU chips at a cost of slightly
1553           increased overhead in some places. If unsure say N here.
1554
1555 config SCHED_SMT
1556         bool "SMT scheduler support"
1557         depends on ARM_CPU_TOPOLOGY
1558         help
1559           Improves the CPU scheduler's decision making when dealing with
1560           MultiThreading at a cost of slightly increased overhead in some
1561           places. If unsure say N here.
1562
1563 config HAVE_ARM_SCU
1564         bool
1565         help
1566           This option enables support for the ARM system coherency unit
1567
1568 config ARM_ARCH_TIMER
1569         bool "Architected timer support"
1570         depends on CPU_V7
1571         help
1572           This option enables support for the ARM architected timer
1573
1574 config HAVE_ARM_TWD
1575         bool
1576         depends on SMP
1577         help
1578           This options enables support for the ARM timer and watchdog unit
1579
1580 choice
1581         prompt "Memory split"
1582         default VMSPLIT_3G
1583         help
1584           Select the desired split between kernel and user memory.
1585
1586           If you are not absolutely sure what you are doing, leave this
1587           option alone!
1588
1589         config VMSPLIT_3G
1590                 bool "3G/1G user/kernel split"
1591         config VMSPLIT_2G
1592                 bool "2G/2G user/kernel split"
1593         config VMSPLIT_1G
1594                 bool "1G/3G user/kernel split"
1595 endchoice
1596
1597 config PAGE_OFFSET
1598         hex
1599         default 0x40000000 if VMSPLIT_1G
1600         default 0x80000000 if VMSPLIT_2G
1601         default 0xC0000000
1602
1603 config NR_CPUS
1604         int "Maximum number of CPUs (2-32)"
1605         range 2 32
1606         depends on SMP
1607         default "4"
1608
1609 config HOTPLUG_CPU
1610         bool "Support for hot-pluggable CPUs"
1611         depends on SMP && HOTPLUG
1612         help
1613           Say Y here to experiment with turning CPUs off and on.  CPUs
1614           can be controlled through /sys/devices/system/cpu.
1615
1616 config LOCAL_TIMERS
1617         bool "Use local timer interrupts"
1618         depends on SMP
1619         default y
1620         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1621         help
1622           Enable support for local timers on SMP platforms, rather then the
1623           legacy IPI broadcast method.  Local timers allows the system
1624           accounting to be spread across the timer interval, preventing a
1625           "thundering herd" at every timer tick.
1626
1627 config ARCH_NR_GPIO
1628         int
1629         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1630         default 355 if ARCH_U8500
1631         default 264 if MACH_H4700
1632         default 512 if SOC_OMAP5
1633         default 288 if ARCH_VT8500
1634         default 0
1635         help
1636           Maximum number of GPIOs in the system.
1637
1638           If unsure, leave the default value.
1639
1640 source kernel/Kconfig.preempt
1641
1642 config HZ
1643         int
1644         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1645                 ARCH_S5PV210 || ARCH_EXYNOS4
1646         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1647         default AT91_TIMER_HZ if ARCH_AT91
1648         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1649         default 100
1650
1651 config THUMB2_KERNEL
1652         bool "Compile the kernel in Thumb-2 mode"
1653         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1654         select AEABI
1655         select ARM_ASM_UNIFIED
1656         select ARM_UNWIND
1657         help
1658           By enabling this option, the kernel will be compiled in
1659           Thumb-2 mode. A compiler/assembler that understand the unified
1660           ARM-Thumb syntax is needed.
1661
1662           If unsure, say N.
1663
1664 config THUMB2_AVOID_R_ARM_THM_JUMP11
1665         bool "Work around buggy Thumb-2 short branch relocations in gas"
1666         depends on THUMB2_KERNEL && MODULES
1667         default y
1668         help
1669           Various binutils versions can resolve Thumb-2 branches to
1670           locally-defined, preemptible global symbols as short-range "b.n"
1671           branch instructions.
1672
1673           This is a problem, because there's no guarantee the final
1674           destination of the symbol, or any candidate locations for a
1675           trampoline, are within range of the branch.  For this reason, the
1676           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1677           relocation in modules at all, and it makes little sense to add
1678           support.
1679
1680           The symptom is that the kernel fails with an "unsupported
1681           relocation" error when loading some modules.
1682
1683           Until fixed tools are available, passing
1684           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1685           code which hits this problem, at the cost of a bit of extra runtime
1686           stack usage in some cases.
1687
1688           The problem is described in more detail at:
1689               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1690
1691           Only Thumb-2 kernels are affected.
1692
1693           Unless you are sure your tools don't have this problem, say Y.
1694
1695 config ARM_ASM_UNIFIED
1696         bool
1697
1698 config AEABI
1699         bool "Use the ARM EABI to compile the kernel"
1700         help
1701           This option allows for the kernel to be compiled using the latest
1702           ARM ABI (aka EABI).  This is only useful if you are using a user
1703           space environment that is also compiled with EABI.
1704
1705           Since there are major incompatibilities between the legacy ABI and
1706           EABI, especially with regard to structure member alignment, this
1707           option also changes the kernel syscall calling convention to
1708           disambiguate both ABIs and allow for backward compatibility support
1709           (selected with CONFIG_OABI_COMPAT).
1710
1711           To use this you need GCC version 4.0.0 or later.
1712
1713 config OABI_COMPAT
1714         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1715         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1716         default y
1717         help
1718           This option preserves the old syscall interface along with the
1719           new (ARM EABI) one. It also provides a compatibility layer to
1720           intercept syscalls that have structure arguments which layout
1721           in memory differs between the legacy ABI and the new ARM EABI
1722           (only for non "thumb" binaries). This option adds a tiny
1723           overhead to all syscalls and produces a slightly larger kernel.
1724           If you know you'll be using only pure EABI user space then you
1725           can say N here. If this option is not selected and you attempt
1726           to execute a legacy ABI binary then the result will be
1727           UNPREDICTABLE (in fact it can be predicted that it won't work
1728           at all). If in doubt say Y.
1729
1730 config ARCH_HAS_HOLES_MEMORYMODEL
1731         bool
1732
1733 config ARCH_SPARSEMEM_ENABLE
1734         bool
1735
1736 config ARCH_SPARSEMEM_DEFAULT
1737         def_bool ARCH_SPARSEMEM_ENABLE
1738
1739 config ARCH_SELECT_MEMORY_MODEL
1740         def_bool ARCH_SPARSEMEM_ENABLE
1741
1742 config HAVE_ARCH_PFN_VALID
1743         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1744
1745 config HIGHMEM
1746         bool "High Memory Support"
1747         depends on MMU
1748         help
1749           The address space of ARM processors is only 4 Gigabytes large
1750           and it has to accommodate user address space, kernel address
1751           space as well as some memory mapped IO. That means that, if you
1752           have a large amount of physical memory and/or IO, not all of the
1753           memory can be "permanently mapped" by the kernel. The physical
1754           memory that is not permanently mapped is called "high memory".
1755
1756           Depending on the selected kernel/user memory split, minimum
1757           vmalloc space and actual amount of RAM, you may not need this
1758           option which should result in a slightly faster kernel.
1759
1760           If unsure, say n.
1761
1762 config HIGHPTE
1763         bool "Allocate 2nd-level pagetables from highmem"
1764         depends on HIGHMEM
1765
1766 config HW_PERF_EVENTS
1767         bool "Enable hardware performance counter support for perf events"
1768         depends on PERF_EVENTS
1769         default y
1770         help
1771           Enable hardware performance counter support for perf events. If
1772           disabled, perf events will use software events only.
1773
1774 source "mm/Kconfig"
1775
1776 config FORCE_MAX_ZONEORDER
1777         int "Maximum zone order" if ARCH_SHMOBILE
1778         range 11 64 if ARCH_SHMOBILE
1779         default "12" if SOC_AM33XX
1780         default "9" if SA1111
1781         default "11"
1782         help
1783           The kernel memory allocator divides physically contiguous memory
1784           blocks into "zones", where each zone is a power of two number of
1785           pages.  This option selects the largest power of two that the kernel
1786           keeps in the memory allocator.  If you need to allocate very large
1787           blocks of physically contiguous memory, then you may need to
1788           increase this value.
1789
1790           This config option is actually maximum order plus one. For example,
1791           a value of 11 means that the largest free memory block is 2^10 pages.
1792
1793 config ALIGNMENT_TRAP
1794         bool
1795         depends on CPU_CP15_MMU
1796         default y if !ARCH_EBSA110
1797         select HAVE_PROC_CPU if PROC_FS
1798         help
1799           ARM processors cannot fetch/store information which is not
1800           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1801           address divisible by 4. On 32-bit ARM processors, these non-aligned
1802           fetch/store instructions will be emulated in software if you say
1803           here, which has a severe performance impact. This is necessary for
1804           correct operation of some network protocols. With an IP-only
1805           configuration it is safe to say N, otherwise say Y.
1806
1807 config UACCESS_WITH_MEMCPY
1808         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1809         depends on MMU
1810         default y if CPU_FEROCEON
1811         help
1812           Implement faster copy_to_user and clear_user methods for CPU
1813           cores where a 8-word STM instruction give significantly higher
1814           memory write throughput than a sequence of individual 32bit stores.
1815
1816           A possible side effect is a slight increase in scheduling latency
1817           between threads sharing the same address space if they invoke
1818           such copy operations with large buffers.
1819
1820           However, if the CPU data cache is using a write-allocate mode,
1821           this option is unlikely to provide any performance gain.
1822
1823 config SECCOMP
1824         bool
1825         prompt "Enable seccomp to safely compute untrusted bytecode"
1826         ---help---
1827           This kernel feature is useful for number crunching applications
1828           that may need to compute untrusted bytecode during their
1829           execution. By using pipes or other transports made available to
1830           the process as file descriptors supporting the read/write
1831           syscalls, it's possible to isolate those applications in
1832           their own address space using seccomp. Once seccomp is
1833           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1834           and the task is only allowed to execute a few safe syscalls
1835           defined by each seccomp mode.
1836
1837 config CC_STACKPROTECTOR
1838         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1839         depends on EXPERIMENTAL
1840         help
1841           This option turns on the -fstack-protector GCC feature. This
1842           feature puts, at the beginning of functions, a canary value on
1843           the stack just before the return address, and validates
1844           the value just before actually returning.  Stack based buffer
1845           overflows (that need to overwrite this return address) now also
1846           overwrite the canary, which gets detected and the attack is then
1847           neutralized via a kernel panic.
1848           This feature requires gcc version 4.2 or above.
1849
1850 config XEN_DOM0
1851         def_bool y
1852         depends on XEN
1853
1854 config XEN
1855         bool "Xen guest support on ARM (EXPERIMENTAL)"
1856         depends on EXPERIMENTAL && ARM && OF
1857         depends on CPU_V7 && !CPU_V6
1858         help
1859           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1860
1861 endmenu
1862
1863 menu "Boot options"
1864
1865 config USE_OF
1866         bool "Flattened Device Tree support"
1867         select IRQ_DOMAIN
1868         select OF
1869         select OF_EARLY_FLATTREE
1870         help
1871           Include support for flattened device tree machine descriptions.
1872
1873 config ATAGS
1874         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1875         default y
1876         help
1877           This is the traditional way of passing data to the kernel at boot
1878           time. If you are solely relying on the flattened device tree (or
1879           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1880           to remove ATAGS support from your kernel binary.  If unsure,
1881           leave this to y.
1882
1883 config DEPRECATED_PARAM_STRUCT
1884         bool "Provide old way to pass kernel parameters"
1885         depends on ATAGS
1886         help
1887           This was deprecated in 2001 and announced to live on for 5 years.
1888           Some old boot loaders still use this way.
1889
1890 # Compressed boot loader in ROM.  Yes, we really want to ask about
1891 # TEXT and BSS so we preserve their values in the config files.
1892 config ZBOOT_ROM_TEXT
1893         hex "Compressed ROM boot loader base address"
1894         default "0"
1895         help
1896           The physical address at which the ROM-able zImage is to be
1897           placed in the target.  Platforms which normally make use of
1898           ROM-able zImage formats normally set this to a suitable
1899           value in their defconfig file.
1900
1901           If ZBOOT_ROM is not enabled, this has no effect.
1902
1903 config ZBOOT_ROM_BSS
1904         hex "Compressed ROM boot loader BSS address"
1905         default "0"
1906         help
1907           The base address of an area of read/write memory in the target
1908           for the ROM-able zImage which must be available while the
1909           decompressor is running. It must be large enough to hold the
1910           entire decompressed kernel plus an additional 128 KiB.
1911           Platforms which normally make use of ROM-able zImage formats
1912           normally set this to a suitable value in their defconfig file.
1913
1914           If ZBOOT_ROM is not enabled, this has no effect.
1915
1916 config ZBOOT_ROM
1917         bool "Compressed boot loader in ROM/flash"
1918         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1919         help
1920           Say Y here if you intend to execute your compressed kernel image
1921           (zImage) directly from ROM or flash.  If unsure, say N.
1922
1923 choice
1924         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1925         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1926         default ZBOOT_ROM_NONE
1927         help
1928           Include experimental SD/MMC loading code in the ROM-able zImage.
1929           With this enabled it is possible to write the ROM-able zImage
1930           kernel image to an MMC or SD card and boot the kernel straight
1931           from the reset vector. At reset the processor Mask ROM will load
1932           the first part of the ROM-able zImage which in turn loads the
1933           rest the kernel image to RAM.
1934
1935 config ZBOOT_ROM_NONE
1936         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1937         help
1938           Do not load image from SD or MMC
1939
1940 config ZBOOT_ROM_MMCIF
1941         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1942         help
1943           Load image from MMCIF hardware block.
1944
1945 config ZBOOT_ROM_SH_MOBILE_SDHI
1946         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1947         help
1948           Load image from SDHI hardware block
1949
1950 endchoice
1951
1952 config ARM_APPENDED_DTB
1953         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1954         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1955         help
1956           With this option, the boot code will look for a device tree binary
1957           (DTB) appended to zImage
1958           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1959
1960           This is meant as a backward compatibility convenience for those
1961           systems with a bootloader that can't be upgraded to accommodate
1962           the documented boot protocol using a device tree.
1963
1964           Beware that there is very little in terms of protection against
1965           this option being confused by leftover garbage in memory that might
1966           look like a DTB header after a reboot if no actual DTB is appended
1967           to zImage.  Do not leave this option active in a production kernel
1968           if you don't intend to always append a DTB.  Proper passing of the
1969           location into r2 of a bootloader provided DTB is always preferable
1970           to this option.
1971
1972 config ARM_ATAG_DTB_COMPAT
1973         bool "Supplement the appended DTB with traditional ATAG information"
1974         depends on ARM_APPENDED_DTB
1975         help
1976           Some old bootloaders can't be updated to a DTB capable one, yet
1977           they provide ATAGs with memory configuration, the ramdisk address,
1978           the kernel cmdline string, etc.  Such information is dynamically
1979           provided by the bootloader and can't always be stored in a static
1980           DTB.  To allow a device tree enabled kernel to be used with such
1981           bootloaders, this option allows zImage to extract the information
1982           from the ATAG list and store it at run time into the appended DTB.
1983
1984 choice
1985         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1986         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1987
1988 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1989         bool "Use bootloader kernel arguments if available"
1990         help
1991           Uses the command-line options passed by the boot loader instead of
1992           the device tree bootargs property. If the boot loader doesn't provide
1993           any, the device tree bootargs property will be used.
1994
1995 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1996         bool "Extend with bootloader kernel arguments"
1997         help
1998           The command-line arguments provided by the boot loader will be
1999           appended to the the device tree bootargs property.
2000
2001 endchoice
2002
2003 config CMDLINE
2004         string "Default kernel command string"
2005         default ""
2006         help
2007           On some architectures (EBSA110 and CATS), there is currently no way
2008           for the boot loader to pass arguments to the kernel. For these
2009           architectures, you should supply some command-line options at build
2010           time by entering them here. As a minimum, you should specify the
2011           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2012
2013 choice
2014         prompt "Kernel command line type" if CMDLINE != ""
2015         default CMDLINE_FROM_BOOTLOADER
2016         depends on ATAGS
2017
2018 config CMDLINE_FROM_BOOTLOADER
2019         bool "Use bootloader kernel arguments if available"
2020         help
2021           Uses the command-line options passed by the boot loader. If
2022           the boot loader doesn't provide any, the default kernel command
2023           string provided in CMDLINE will be used.
2024
2025 config CMDLINE_EXTEND
2026         bool "Extend bootloader kernel arguments"
2027         help
2028           The command-line arguments provided by the boot loader will be
2029           appended to the default kernel command string.
2030
2031 config CMDLINE_FORCE
2032         bool "Always use the default kernel command string"
2033         help
2034           Always use the default kernel command string, even if the boot
2035           loader passes other arguments to the kernel.
2036           This is useful if you cannot or don't want to change the
2037           command-line options your boot loader passes to the kernel.
2038 endchoice
2039
2040 config XIP_KERNEL
2041         bool "Kernel Execute-In-Place from ROM"
2042         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2043         help
2044           Execute-In-Place allows the kernel to run from non-volatile storage
2045           directly addressable by the CPU, such as NOR flash. This saves RAM
2046           space since the text section of the kernel is not loaded from flash
2047           to RAM.  Read-write sections, such as the data section and stack,
2048           are still copied to RAM.  The XIP kernel is not compressed since
2049           it has to run directly from flash, so it will take more space to
2050           store it.  The flash address used to link the kernel object files,
2051           and for storing it, is configuration dependent. Therefore, if you
2052           say Y here, you must know the proper physical address where to
2053           store the kernel image depending on your own flash memory usage.
2054
2055           Also note that the make target becomes "make xipImage" rather than
2056           "make zImage" or "make Image".  The final kernel binary to put in
2057           ROM memory will be arch/arm/boot/xipImage.
2058
2059           If unsure, say N.
2060
2061 config XIP_PHYS_ADDR
2062         hex "XIP Kernel Physical Location"
2063         depends on XIP_KERNEL
2064         default "0x00080000"
2065         help
2066           This is the physical address in your flash memory the kernel will
2067           be linked for and stored to.  This address is dependent on your
2068           own flash usage.
2069
2070 config KEXEC
2071         bool "Kexec system call (EXPERIMENTAL)"
2072         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2073         help
2074           kexec is a system call that implements the ability to shutdown your
2075           current kernel, and to start another kernel.  It is like a reboot
2076           but it is independent of the system firmware.   And like a reboot
2077           you can start any kernel with it, not just Linux.
2078
2079           It is an ongoing process to be certain the hardware in a machine
2080           is properly shutdown, so do not be surprised if this code does not
2081           initially work for you.  It may help to enable device hotplugging
2082           support.
2083
2084 config ATAGS_PROC
2085         bool "Export atags in procfs"
2086         depends on ATAGS && KEXEC
2087         default y
2088         help
2089           Should the atags used to boot the kernel be exported in an "atags"
2090           file in procfs. Useful with kexec.
2091
2092 config CRASH_DUMP
2093         bool "Build kdump crash kernel (EXPERIMENTAL)"
2094         depends on EXPERIMENTAL
2095         help
2096           Generate crash dump after being started by kexec. This should
2097           be normally only set in special crash dump kernels which are
2098           loaded in the main kernel with kexec-tools into a specially
2099           reserved region and then later executed after a crash by
2100           kdump/kexec. The crash dump kernel must be compiled to a
2101           memory address not used by the main kernel
2102
2103           For more details see Documentation/kdump/kdump.txt
2104
2105 config AUTO_ZRELADDR
2106         bool "Auto calculation of the decompressed kernel image address"
2107         depends on !ZBOOT_ROM && !ARCH_U300
2108         help
2109           ZRELADDR is the physical address where the decompressed kernel
2110           image will be placed. If AUTO_ZRELADDR is selected, the address
2111           will be determined at run-time by masking the current IP with
2112           0xf8000000. This assumes the zImage being placed in the first 128MB
2113           from start of memory.
2114
2115 endmenu
2116
2117 menu "CPU Power Management"
2118
2119 if ARCH_HAS_CPUFREQ
2120
2121 source "drivers/cpufreq/Kconfig"
2122
2123 config CPU_FREQ_IMX
2124         tristate "CPUfreq driver for i.MX CPUs"
2125         depends on ARCH_MXC && CPU_FREQ
2126         select CPU_FREQ_TABLE
2127         help
2128           This enables the CPUfreq driver for i.MX CPUs.
2129
2130 config CPU_FREQ_SA1100
2131         bool
2132
2133 config CPU_FREQ_SA1110
2134         bool
2135
2136 config CPU_FREQ_INTEGRATOR
2137         tristate "CPUfreq driver for ARM Integrator CPUs"
2138         depends on ARCH_INTEGRATOR && CPU_FREQ
2139         default y
2140         help
2141           This enables the CPUfreq driver for ARM Integrator CPUs.
2142
2143           For details, take a look at <file:Documentation/cpu-freq>.
2144
2145           If in doubt, say Y.
2146
2147 config CPU_FREQ_PXA
2148         bool
2149         depends on CPU_FREQ && ARCH_PXA && PXA25x
2150         default y
2151         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2152         select CPU_FREQ_TABLE
2153
2154 config CPU_FREQ_S3C
2155         bool
2156         help
2157           Internal configuration node for common cpufreq on Samsung SoC
2158
2159 config CPU_FREQ_S3C24XX
2160         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2161         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2162         select CPU_FREQ_S3C
2163         help
2164           This enables the CPUfreq driver for the Samsung S3C24XX family
2165           of CPUs.
2166
2167           For details, take a look at <file:Documentation/cpu-freq>.
2168
2169           If in doubt, say N.
2170
2171 config CPU_FREQ_S3C24XX_PLL
2172         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2173         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2174         help
2175           Compile in support for changing the PLL frequency from the
2176           S3C24XX series CPUfreq driver. The PLL takes time to settle
2177           after a frequency change, so by default it is not enabled.
2178
2179           This also means that the PLL tables for the selected CPU(s) will
2180           be built which may increase the size of the kernel image.
2181
2182 config CPU_FREQ_S3C24XX_DEBUG
2183         bool "Debug CPUfreq Samsung driver core"
2184         depends on CPU_FREQ_S3C24XX
2185         help
2186           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2187
2188 config CPU_FREQ_S3C24XX_IODEBUG
2189         bool "Debug CPUfreq Samsung driver IO timing"
2190         depends on CPU_FREQ_S3C24XX
2191         help
2192           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2193
2194 config CPU_FREQ_S3C24XX_DEBUGFS
2195         bool "Export debugfs for CPUFreq"
2196         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2197         help
2198           Export status information via debugfs.
2199
2200 endif
2201
2202 source "drivers/cpuidle/Kconfig"
2203
2204 endmenu
2205
2206 menu "Floating point emulation"
2207
2208 comment "At least one emulation must be selected"
2209
2210 config FPE_NWFPE
2211         bool "NWFPE math emulation"
2212         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2213         ---help---
2214           Say Y to include the NWFPE floating point emulator in the kernel.
2215           This is necessary to run most binaries. Linux does not currently
2216           support floating point hardware so you need to say Y here even if
2217           your machine has an FPA or floating point co-processor podule.
2218
2219           You may say N here if you are going to load the Acorn FPEmulator
2220           early in the bootup.
2221
2222 config FPE_NWFPE_XP
2223         bool "Support extended precision"
2224         depends on FPE_NWFPE
2225         help
2226           Say Y to include 80-bit support in the kernel floating-point
2227           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2228           Note that gcc does not generate 80-bit operations by default,
2229           so in most cases this option only enlarges the size of the
2230           floating point emulator without any good reason.
2231
2232           You almost surely want to say N here.
2233
2234 config FPE_FASTFPE
2235         bool "FastFPE math emulation (EXPERIMENTAL)"
2236         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2237         ---help---
2238           Say Y here to include the FAST floating point emulator in the kernel.
2239           This is an experimental much faster emulator which now also has full
2240           precision for the mantissa.  It does not support any exceptions.
2241           It is very simple, and approximately 3-6 times faster than NWFPE.
2242
2243           It should be sufficient for most programs.  It may be not suitable
2244           for scientific calculations, but you have to check this for yourself.
2245           If you do not feel you need a faster FP emulation you should better
2246           choose NWFPE.
2247
2248 config VFP
2249         bool "VFP-format floating point maths"
2250         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2251         help
2252           Say Y to include VFP support code in the kernel. This is needed
2253           if your hardware includes a VFP unit.
2254
2255           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2256           release notes and additional status information.
2257
2258           Say N if your target does not have VFP hardware.
2259
2260 config VFPv3
2261         bool
2262         depends on VFP
2263         default y if CPU_V7
2264
2265 config NEON
2266         bool "Advanced SIMD (NEON) Extension support"
2267         depends on VFPv3 && CPU_V7
2268         help
2269           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2270           Extension.
2271
2272 endmenu
2273
2274 menu "Userspace binary formats"
2275
2276 source "fs/Kconfig.binfmt"
2277
2278 config ARTHUR
2279         tristate "RISC OS personality"
2280         depends on !AEABI
2281         help
2282           Say Y here to include the kernel code necessary if you want to run
2283           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2284           experimental; if this sounds frightening, say N and sleep in peace.
2285           You can also say M here to compile this support as a module (which
2286           will be called arthur).
2287
2288 endmenu
2289
2290 menu "Power management options"
2291
2292 source "kernel/power/Kconfig"
2293
2294 config ARCH_SUSPEND_POSSIBLE
2295         depends on !ARCH_S5PC100
2296         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2297                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2298         def_bool y
2299
2300 config ARM_CPU_SUSPEND
2301         def_bool PM_SLEEP
2302
2303 endmenu
2304
2305 source "net/Kconfig"
2306
2307 source "drivers/Kconfig"
2308
2309 source "fs/Kconfig"
2310
2311 source "arch/arm/Kconfig.debug"
2312
2313 source "security/Kconfig"
2314
2315 source "crypto/Kconfig"
2316
2317 source "lib/Kconfig"