4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
86 config SYS_SUPPORTS_APM_EMULATION
94 select GENERIC_ALLOCATOR
105 The Extended Industry Standard Architecture (EISA) bus was
106 developed as an open alternative to the IBM MicroChannel bus.
108 The EISA bus provided some of the features of the IBM MicroChannel
109 bus while maintaining backward compatibility with cards made for
110 the older ISA bus. The EISA bus saw limited use between 1988 and
111 1995 when it was made obsolete by the PCI bus.
113 Say Y here if you are building a kernel for an EISA-based machine.
120 config STACKTRACE_SUPPORT
124 config HAVE_LATENCYTOP_SUPPORT
129 config LOCKDEP_SUPPORT
133 config TRACE_IRQFLAGS_SUPPORT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config GENERIC_HWEIGHT
161 config GENERIC_CALIBRATE_DELAY
165 config ARCH_MAY_HAVE_PC_FDC
171 config NEED_DMA_MAP_STATE
174 config ARCH_HAS_DMA_SET_COHERENT_MASK
177 config GENERIC_ISA_DMA
183 config NEED_RET_TO_USER
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_GPIO_H
217 Select this when mach/gpio.h is required to provide special
218 definitions for this platform. The need for mach/gpio.h should
219 be avoided when possible.
221 config NEED_MACH_IO_H
224 Select this when mach/io.h is required to provide special
225 definitions for this platform. The need for mach/io.h should
226 be avoided when possible.
228 config NEED_MACH_MEMORY_H
231 Select this when mach/memory.h is required to provide special
232 definitions for this platform. The need for mach/memory.h should
233 be avoided when possible.
236 hex "Physical address of main memory" if MMU
237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
238 default DRAM_BASE if !MMU
240 Please provide the physical address corresponding to the
241 location of main memory in your system.
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
254 bool "MMU-based Paged Memory Management Support"
257 Select if you want MMU-based virtualised addressing space
258 support by paged memory management. If unsure, say 'Y'.
261 # The "ARM system type" choice list is ordered alphabetically by option
262 # text. Please add new entries in the option alphabetic order.
265 prompt "ARM system type"
266 default ARCH_VERSATILE if !MMU
267 default ARCH_MULTIPLATFORM if MMU
269 config ARCH_MULTIPLATFORM
270 bool "Allow multiple platforms to be selected"
272 select ARM_PATCH_PHYS_VIRT
275 select MULTI_IRQ_HANDLER
279 config ARCH_INTEGRATOR
280 bool "ARM Ltd. Integrator family"
281 select ARCH_HAS_CPUFREQ
284 select COMMON_CLK_VERSATILE
285 select GENERIC_CLOCKEVENTS
288 select MULTI_IRQ_HANDLER
289 select NEED_MACH_MEMORY_H
290 select PLAT_VERSATILE
292 select VERSATILE_FPGA_IRQ
294 Support for ARM's Integrator platform.
297 bool "ARM Ltd. RealView family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select COMMON_CLK_VERSATILE
303 select GENERIC_CLOCKEVENTS
304 select GPIO_PL061 if GPIOLIB
306 select NEED_MACH_MEMORY_H
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for ARM Ltd RealView boards.
312 config ARCH_VERSATILE
313 bool "ARM Ltd. Versatile family"
314 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select ARM_TIMER_SP804
319 select GENERIC_CLOCKEVENTS
320 select HAVE_MACH_CLKDEV
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLCD
324 select PLAT_VERSATILE_CLOCK
325 select VERSATILE_FPGA_IRQ
327 This enables support for ARM Ltd Versatile board.
331 select ARCH_REQUIRE_GPIOLIB
335 select NEED_MACH_GPIO_H
336 select NEED_MACH_IO_H if PCCARD
338 select PINCTRL_AT91 if USE_OF
340 This enables support for systems based on Atmel
341 AT91RM9200 and AT91SAM9* processors.
344 bool "Broadcom BCM2835 family"
345 select ARCH_REQUIRE_GPIOLIB
347 select ARM_ERRATA_411920
348 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select MULTI_IRQ_HANDLER
356 select PINCTRL_BCM2835
360 This enables support for the Broadcom BCM2835 SoC. This SoC is
361 use in the Raspberry Pi, and Roku 2 devices.
364 bool "Cavium Networks CNS3XXX family"
367 select GENERIC_CLOCKEVENTS
368 select MIGHT_HAVE_CACHE_L2X0
369 select MIGHT_HAVE_PCI
370 select PCI_DOMAINS if PCI
372 Support for Cavium Networks CNS3XXX platform.
375 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
376 select ARCH_REQUIRE_GPIOLIB
381 select GENERIC_CLOCKEVENTS
382 select MULTI_IRQ_HANDLER
383 select NEED_MACH_MEMORY_H
386 Support for Cirrus Logic 711x/721x/731x based boards.
389 bool "Cortina Systems Gemini"
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_USES_GETTIMEOFFSET
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
402 select GENERIC_IRQ_CHIP
403 select MIGHT_HAVE_CACHE_L2X0
409 Support for CSR SiRFprimaII/Marco/Polo platforms
413 select ARCH_USES_GETTIMEOFFSET
416 select NEED_MACH_IO_H
417 select NEED_MACH_MEMORY_H
420 This is an evaluation board for the StrongARM processor available
421 from Digital. It has limited hardware on-board, including an
422 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 select ARCH_HAS_HOLES_MEMORYMODEL
428 select ARCH_REQUIRE_GPIOLIB
429 select ARCH_USES_GETTIMEOFFSET
434 select NEED_MACH_MEMORY_H
436 This enables support for the Cirrus EP93xx series of CPUs.
438 config ARCH_FOOTBRIDGE
442 select GENERIC_CLOCKEVENTS
444 select NEED_MACH_IO_H if !MMU
445 select NEED_MACH_MEMORY_H
447 Support for systems based on the DC21285 companion chip
448 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
451 bool "Freescale MXS-based"
452 select ARCH_REQUIRE_GPIOLIB
456 select GENERIC_CLOCKEVENTS
457 select HAVE_CLK_PREPARE
458 select MULTI_IRQ_HANDLER
463 Support for Freescale MXS-based family of processors
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
475 bool "Hynix HMS720x-based"
476 select ARCH_USES_GETTIMEOFFSET
480 This enables support for systems based on the Hynix HMS720x
485 select ARCH_SUPPORTS_MSI
487 select NEED_MACH_MEMORY_H
488 select NEED_RET_TO_USER
493 Support for Intel's IOP13XX (XScale) family of processors.
498 select ARCH_REQUIRE_GPIOLIB
500 select NEED_MACH_GPIO_H
501 select NEED_RET_TO_USER
505 Support for Intel's 80219 and IOP32X (XScale) family of
511 select ARCH_REQUIRE_GPIOLIB
513 select NEED_MACH_GPIO_H
514 select NEED_RET_TO_USER
518 Support for Intel's IOP33X (XScale) family of processors.
523 select ARCH_HAS_DMA_SET_COHERENT_MASK
524 select ARCH_REQUIRE_GPIOLIB
527 select DMABOUNCE if PCI
528 select GENERIC_CLOCKEVENTS
529 select MIGHT_HAVE_PCI
530 select NEED_MACH_IO_H
532 Support for Intel's IXP4XX (XScale) family of processors.
536 select ARCH_REQUIRE_GPIOLIB
537 select COMMON_CLK_DOVE
539 select GENERIC_CLOCKEVENTS
540 select MIGHT_HAVE_PCI
543 select PLAT_ORION_LEGACY
544 select USB_ARCH_HAS_EHCI
546 Support for the Marvell Dove SoC 88AP510
549 bool "Marvell Kirkwood"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
556 select PINCTRL_KIRKWOOD
557 select PLAT_ORION_LEGACY
559 Support for the following Marvell Kirkwood series SoCs:
560 88F6180, 88F6192 and 88F6281.
563 bool "Marvell MV78xx0"
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
568 select PLAT_ORION_LEGACY
570 Support for the following Marvell MV78xx0 series SoCs:
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION_LEGACY
582 Support for the following Marvell Orion 5x series SoCs:
583 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
584 Orion-2 (5281), Orion-1-90 (6183).
587 bool "Marvell PXA168/910/MMP2"
589 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_ALLOCATOR
592 select GENERIC_CLOCKEVENTS
595 select NEED_MACH_GPIO_H
600 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
603 bool "Micrel/Kendin KS8695"
604 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
615 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
639 select USB_ARCH_HAS_OHCI
642 Support for the NXP LPC32XX family of processors
646 select ARCH_HAS_CPUFREQ
647 select ARCH_REQUIRE_GPIOLIB
652 select GENERIC_CLOCKEVENTS
655 select MIGHT_HAVE_CACHE_L2X0
659 This enables support for NVIDIA Tegra based systems (Tegra APX,
660 Tegra 6xx and Tegra 2 series).
663 bool "PXA2xx/PXA3xx-based"
665 select ARCH_HAS_CPUFREQ
667 select ARCH_REQUIRE_GPIOLIB
668 select ARM_CPU_SUSPEND if PM
672 select GENERIC_CLOCKEVENTS
675 select MULTI_IRQ_HANDLER
676 select NEED_MACH_GPIO_H
680 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
684 select ARCH_REQUIRE_GPIOLIB
686 select GENERIC_CLOCKEVENTS
689 Support for Qualcomm MSM/QSD based systems. This runs on the
690 apps processor of the MSM/QSD and depends on a shared memory
691 interface to the modem processor which runs the baseband
692 stack and controls some vital subsystems
693 (clock and power control, etc).
696 bool "Renesas SH-Mobile / R-Mobile"
698 select GENERIC_CLOCKEVENTS
700 select HAVE_MACH_CLKDEV
702 select MIGHT_HAVE_CACHE_L2X0
703 select MULTI_IRQ_HANDLER
704 select NEED_MACH_MEMORY_H
707 select PM_GENERIC_DOMAINS if PM
710 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
715 select ARCH_MAY_HAVE_PC_FDC
716 select ARCH_SPARSEMEM_ENABLE
717 select ARCH_USES_GETTIMEOFFSET
720 select HAVE_PATA_PLATFORM
722 select NEED_MACH_IO_H
723 select NEED_MACH_MEMORY_H
726 On the Acorn Risc-PC, Linux can support the internal IDE disk and
727 CD-ROM interface, serial and parallel port, and the floppy drive.
731 select ARCH_HAS_CPUFREQ
733 select ARCH_REQUIRE_GPIOLIB
734 select ARCH_SPARSEMEM_ENABLE
739 select GENERIC_CLOCKEVENTS
742 select NEED_MACH_GPIO_H
743 select NEED_MACH_MEMORY_H
746 Support for StrongARM 11x0 based boards.
749 bool "Samsung S3C24XX SoCs"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_USES_GETTIMEOFFSET
754 select HAVE_S3C2410_I2C if I2C
755 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 select HAVE_S3C_RTC if RTC_CLASS
757 select NEED_MACH_GPIO_H
758 select NEED_MACH_IO_H
760 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
761 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
762 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
763 Samsung SMDK2410 development board (and derivatives).
766 bool "Samsung S3C64XX"
767 select ARCH_HAS_CPUFREQ
768 select ARCH_REQUIRE_GPIOLIB
769 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select NEED_MACH_GPIO_H
781 select S3C_GPIO_TRACK
782 select SAMSUNG_CLKSRC
783 select SAMSUNG_GPIOLIB_4BIT
784 select SAMSUNG_IRQ_VIC_TIMER
785 select USB_ARCH_HAS_OHCI
787 Samsung S3C64XX series based systems
790 bool "Samsung S5P6440 S5P6450"
794 select GENERIC_CLOCKEVENTS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select HAVE_S3C_RTC if RTC_CLASS
799 select NEED_MACH_GPIO_H
801 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
805 bool "Samsung S5PC100"
806 select ARCH_USES_GETTIMEOFFSET
810 select HAVE_S3C2410_I2C if I2C
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select HAVE_S3C_RTC if RTC_CLASS
813 select NEED_MACH_GPIO_H
815 Samsung S5PC100 series based systems
818 bool "Samsung S5PV210/S5PC110"
819 select ARCH_HAS_CPUFREQ
820 select ARCH_HAS_HOLES_MEMORYMODEL
821 select ARCH_SPARSEMEM_ENABLE
825 select GENERIC_CLOCKEVENTS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select HAVE_S3C_RTC if RTC_CLASS
830 select NEED_MACH_GPIO_H
831 select NEED_MACH_MEMORY_H
833 Samsung S5PV210/S5PC110 series based systems
836 bool "Samsung EXYNOS"
837 select ARCH_HAS_CPUFREQ
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_SPARSEMEM_ENABLE
842 select GENERIC_CLOCKEVENTS
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C2410_WATCHDOG if WATCHDOG
846 select HAVE_S3C_RTC if RTC_CLASS
847 select NEED_MACH_GPIO_H
848 select NEED_MACH_MEMORY_H
850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
854 select ARCH_USES_GETTIMEOFFSET
858 select NEED_MACH_MEMORY_H
862 Support for the StrongARM based Digital DNARD machine, also known
863 as "Shark" (<http://www.shark-linux.de/shark.html>).
866 bool "ST-Ericsson U300 Series"
868 select ARCH_REQUIRE_GPIOLIB
870 select ARM_PATCH_PHYS_VIRT
876 select GENERIC_CLOCKEVENTS
880 Support for ST-Ericsson U300 series mobile platforms.
883 bool "ST-Ericsson U8500 Series"
885 select ARCH_HAS_CPUFREQ
886 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_CLOCKEVENTS
892 select MIGHT_HAVE_CACHE_L2X0
895 Support for ST-Ericsson's Ux500 architecture
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
902 select CLKSRC_NOMADIK_MTU
905 select GENERIC_CLOCKEVENTS
906 select MIGHT_HAVE_CACHE_L2X0
909 select PINCTRL_STN8815
912 Support for the Nomadik platform by ST-Ericsson
916 select ARCH_HAS_CPUFREQ
917 select ARCH_REQUIRE_GPIOLIB
922 select GENERIC_CLOCKEVENTS
925 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
929 select ARCH_HAS_HOLES_MEMORYMODEL
930 select ARCH_REQUIRE_GPIOLIB
932 select GENERIC_ALLOCATOR
933 select GENERIC_CLOCKEVENTS
934 select GENERIC_IRQ_CHIP
936 select NEED_MACH_GPIO_H
940 Support for TI's DaVinci platform.
945 select ARCH_HAS_CPUFREQ
946 select ARCH_HAS_HOLES_MEMORYMODEL
948 select ARCH_REQUIRE_GPIOLIB
951 select GENERIC_CLOCKEVENTS
952 select GENERIC_IRQ_CHIP
956 select NEED_MACH_IO_H if PCCARD
957 select NEED_MACH_MEMORY_H
959 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
963 menu "Multiple platform selection"
964 depends on ARCH_MULTIPLATFORM
966 comment "CPU Core family selection"
969 bool "ARMv4 based platforms (FA526, StrongARM)"
970 depends on !ARCH_MULTI_V6_V7
971 select ARCH_MULTI_V4_V5
973 config ARCH_MULTI_V4T
974 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
975 depends on !ARCH_MULTI_V6_V7
976 select ARCH_MULTI_V4_V5
979 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
980 depends on !ARCH_MULTI_V6_V7
981 select ARCH_MULTI_V4_V5
983 config ARCH_MULTI_V4_V5
987 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
988 select ARCH_MULTI_V6_V7
992 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
994 select ARCH_MULTI_V6_V7
998 config ARCH_MULTI_V6_V7
1001 config ARCH_MULTI_CPU_AUTO
1002 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1003 select ARCH_MULTI_V5
1008 # This is sorted alphabetically by mach-* pathname. However, plat-*
1009 # Kconfigs may be included either alphabetically (according to the
1010 # plat- suffix) or along side the corresponding mach-* source.
1012 source "arch/arm/mach-mvebu/Kconfig"
1014 source "arch/arm/mach-at91/Kconfig"
1016 source "arch/arm/mach-bcm/Kconfig"
1018 source "arch/arm/mach-clps711x/Kconfig"
1020 source "arch/arm/mach-cns3xxx/Kconfig"
1022 source "arch/arm/mach-davinci/Kconfig"
1024 source "arch/arm/mach-dove/Kconfig"
1026 source "arch/arm/mach-ep93xx/Kconfig"
1028 source "arch/arm/mach-footbridge/Kconfig"
1030 source "arch/arm/mach-gemini/Kconfig"
1032 source "arch/arm/mach-h720x/Kconfig"
1034 source "arch/arm/mach-highbank/Kconfig"
1036 source "arch/arm/mach-integrator/Kconfig"
1038 source "arch/arm/mach-iop32x/Kconfig"
1040 source "arch/arm/mach-iop33x/Kconfig"
1042 source "arch/arm/mach-iop13xx/Kconfig"
1044 source "arch/arm/mach-ixp4xx/Kconfig"
1046 source "arch/arm/mach-kirkwood/Kconfig"
1048 source "arch/arm/mach-ks8695/Kconfig"
1050 source "arch/arm/mach-msm/Kconfig"
1052 source "arch/arm/mach-mv78xx0/Kconfig"
1054 source "arch/arm/mach-imx/Kconfig"
1056 source "arch/arm/mach-mxs/Kconfig"
1058 source "arch/arm/mach-netx/Kconfig"
1060 source "arch/arm/mach-nomadik/Kconfig"
1062 source "arch/arm/plat-omap/Kconfig"
1064 source "arch/arm/mach-omap1/Kconfig"
1066 source "arch/arm/mach-omap2/Kconfig"
1068 source "arch/arm/mach-orion5x/Kconfig"
1070 source "arch/arm/mach-picoxcell/Kconfig"
1072 source "arch/arm/mach-pxa/Kconfig"
1073 source "arch/arm/plat-pxa/Kconfig"
1075 source "arch/arm/mach-mmp/Kconfig"
1077 source "arch/arm/mach-realview/Kconfig"
1079 source "arch/arm/mach-sa1100/Kconfig"
1081 source "arch/arm/plat-samsung/Kconfig"
1083 source "arch/arm/mach-socfpga/Kconfig"
1085 source "arch/arm/plat-spear/Kconfig"
1087 source "arch/arm/mach-s3c24xx/Kconfig"
1090 source "arch/arm/mach-s3c64xx/Kconfig"
1093 source "arch/arm/mach-s5p64x0/Kconfig"
1095 source "arch/arm/mach-s5pc100/Kconfig"
1097 source "arch/arm/mach-s5pv210/Kconfig"
1099 source "arch/arm/mach-exynos/Kconfig"
1101 source "arch/arm/mach-shmobile/Kconfig"
1103 source "arch/arm/mach-sunxi/Kconfig"
1105 source "arch/arm/mach-prima2/Kconfig"
1107 source "arch/arm/mach-tegra/Kconfig"
1109 source "arch/arm/mach-u300/Kconfig"
1111 source "arch/arm/mach-ux500/Kconfig"
1113 source "arch/arm/mach-versatile/Kconfig"
1115 source "arch/arm/mach-vexpress/Kconfig"
1116 source "arch/arm/plat-versatile/Kconfig"
1118 source "arch/arm/mach-virt/Kconfig"
1120 source "arch/arm/mach-vt8500/Kconfig"
1122 source "arch/arm/mach-w90x900/Kconfig"
1124 source "arch/arm/mach-zynq/Kconfig"
1126 # Definitions to make life easier
1132 select GENERIC_CLOCKEVENTS
1138 select GENERIC_IRQ_CHIP
1141 config PLAT_ORION_LEGACY
1148 config PLAT_VERSATILE
1151 config ARM_TIMER_SP804
1154 select HAVE_SCHED_CLOCK
1156 source arch/arm/mm/Kconfig
1160 default 16 if ARCH_EP93XX
1164 bool "Enable iWMMXt support"
1165 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1166 default y if PXA27x || PXA3xx || ARCH_MMP
1168 Enable support for iWMMXt context switching at run time if
1169 running on a CPU that supports it.
1173 depends on CPU_XSCALE
1176 config MULTI_IRQ_HANDLER
1179 Allow each machine to specify it's own IRQ handler at run time.
1182 source "arch/arm/Kconfig-nommu"
1185 config ARM_ERRATA_326103
1186 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1189 Executing a SWP instruction to read-only memory does not set bit 11
1190 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1191 treat the access as a read, preventing a COW from occurring and
1192 causing the faulting task to livelock.
1194 config ARM_ERRATA_411920
1195 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1196 depends on CPU_V6 || CPU_V6K
1198 Invalidation of the Instruction Cache operation can
1199 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1200 It does not affect the MPCore. This option enables the ARM Ltd.
1201 recommended workaround.
1203 config ARM_ERRATA_430973
1204 bool "ARM errata: Stale prediction on replaced interworking branch"
1207 This option enables the workaround for the 430973 Cortex-A8
1208 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1209 interworking branch is replaced with another code sequence at the
1210 same virtual address, whether due to self-modifying code or virtual
1211 to physical address re-mapping, Cortex-A8 does not recover from the
1212 stale interworking branch prediction. This results in Cortex-A8
1213 executing the new code sequence in the incorrect ARM or Thumb state.
1214 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1215 and also flushes the branch target cache at every context switch.
1216 Note that setting specific bits in the ACTLR register may not be
1217 available in non-secure mode.
1219 config ARM_ERRATA_458693
1220 bool "ARM errata: Processor deadlock when a false hazard is created"
1222 depends on !ARCH_MULTIPLATFORM
1224 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1225 erratum. For very specific sequences of memory operations, it is
1226 possible for a hazard condition intended for a cache line to instead
1227 be incorrectly associated with a different cache line. This false
1228 hazard might then cause a processor deadlock. The workaround enables
1229 the L1 caching of the NEON accesses and disables the PLD instruction
1230 in the ACTLR register. Note that setting specific bits in the ACTLR
1231 register may not be available in non-secure mode.
1233 config ARM_ERRATA_460075
1234 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1236 depends on !ARCH_MULTIPLATFORM
1238 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1239 erratum. Any asynchronous access to the L2 cache may encounter a
1240 situation in which recent store transactions to the L2 cache are lost
1241 and overwritten with stale memory contents from external memory. The
1242 workaround disables the write-allocate mode for the L2 cache via the
1243 ACTLR register. Note that setting specific bits in the ACTLR register
1244 may not be available in non-secure mode.
1246 config ARM_ERRATA_742230
1247 bool "ARM errata: DMB operation may be faulty"
1248 depends on CPU_V7 && SMP
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 742230 Cortex-A9
1252 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1253 between two write operations may not ensure the correct visibility
1254 ordering of the two writes. This workaround sets a specific bit in
1255 the diagnostic register of the Cortex-A9 which causes the DMB
1256 instruction to behave as a DSB, ensuring the correct behaviour of
1259 config ARM_ERRATA_742231
1260 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1261 depends on CPU_V7 && SMP
1262 depends on !ARCH_MULTIPLATFORM
1264 This option enables the workaround for the 742231 Cortex-A9
1265 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1266 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1267 accessing some data located in the same cache line, may get corrupted
1268 data due to bad handling of the address hazard when the line gets
1269 replaced from one of the CPUs at the same time as another CPU is
1270 accessing it. This workaround sets specific bits in the diagnostic
1271 register of the Cortex-A9 which reduces the linefill issuing
1272 capabilities of the processor.
1274 config PL310_ERRATA_588369
1275 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1276 depends on CACHE_L2X0
1278 The PL310 L2 cache controller implements three types of Clean &
1279 Invalidate maintenance operations: by Physical Address
1280 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1281 They are architecturally defined to behave as the execution of a
1282 clean operation followed immediately by an invalidate operation,
1283 both performing to the same memory location. This functionality
1284 is not correctly implemented in PL310 as clean lines are not
1285 invalidated as a result of these operations.
1287 config ARM_ERRATA_720789
1288 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1291 This option enables the workaround for the 720789 Cortex-A9 (prior to
1292 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1293 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1294 As a consequence of this erratum, some TLB entries which should be
1295 invalidated are not, resulting in an incoherency in the system page
1296 tables. The workaround changes the TLB flushing routines to invalidate
1297 entries regardless of the ASID.
1299 config PL310_ERRATA_727915
1300 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1301 depends on CACHE_L2X0
1303 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1304 operation (offset 0x7FC). This operation runs in background so that
1305 PL310 can handle normal accesses while it is in progress. Under very
1306 rare circumstances, due to this erratum, write data can be lost when
1307 PL310 treats a cacheable write transaction during a Clean &
1308 Invalidate by Way operation.
1310 config ARM_ERRATA_743622
1311 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1313 depends on !ARCH_MULTIPLATFORM
1315 This option enables the workaround for the 743622 Cortex-A9
1316 (r2p*) erratum. Under very rare conditions, a faulty
1317 optimisation in the Cortex-A9 Store Buffer may lead to data
1318 corruption. This workaround sets a specific bit in the diagnostic
1319 register of the Cortex-A9 which disables the Store Buffer
1320 optimisation, preventing the defect from occurring. This has no
1321 visible impact on the overall performance or power consumption of the
1324 config ARM_ERRATA_751472
1325 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1327 depends on !ARCH_MULTIPLATFORM
1329 This option enables the workaround for the 751472 Cortex-A9 (prior
1330 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1331 completion of a following broadcasted operation if the second
1332 operation is received by a CPU before the ICIALLUIS has completed,
1333 potentially leading to corrupted entries in the cache or TLB.
1335 config PL310_ERRATA_753970
1336 bool "PL310 errata: cache sync operation may be faulty"
1337 depends on CACHE_PL310
1339 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1341 Under some condition the effect of cache sync operation on
1342 the store buffer still remains when the operation completes.
1343 This means that the store buffer is always asked to drain and
1344 this prevents it from merging any further writes. The workaround
1345 is to replace the normal offset of cache sync operation (0x730)
1346 by another offset targeting an unmapped PL310 register 0x740.
1347 This has the same effect as the cache sync operation: store buffer
1348 drain and waiting for all buffers empty.
1350 config ARM_ERRATA_754322
1351 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1354 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1355 r3p*) erratum. A speculative memory access may cause a page table walk
1356 which starts prior to an ASID switch but completes afterwards. This
1357 can populate the micro-TLB with a stale entry which may be hit with
1358 the new ASID. This workaround places two dsb instructions in the mm
1359 switching code so that no page table walks can cross the ASID switch.
1361 config ARM_ERRATA_754327
1362 bool "ARM errata: no automatic Store Buffer drain"
1363 depends on CPU_V7 && SMP
1365 This option enables the workaround for the 754327 Cortex-A9 (prior to
1366 r2p0) erratum. The Store Buffer does not have any automatic draining
1367 mechanism and therefore a livelock may occur if an external agent
1368 continuously polls a memory location waiting to observe an update.
1369 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1370 written polling loops from denying visibility of updates to memory.
1372 config ARM_ERRATA_364296
1373 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1374 depends on CPU_V6 && !SMP
1376 This options enables the workaround for the 364296 ARM1136
1377 r0p2 erratum (possible cache data corruption with
1378 hit-under-miss enabled). It sets the undocumented bit 31 in
1379 the auxiliary control register and the FI bit in the control
1380 register, thus disabling hit-under-miss without putting the
1381 processor into full low interrupt latency mode. ARM11MPCore
1384 config ARM_ERRATA_764369
1385 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1386 depends on CPU_V7 && SMP
1388 This option enables the workaround for erratum 764369
1389 affecting Cortex-A9 MPCore with two or more processors (all
1390 current revisions). Under certain timing circumstances, a data
1391 cache line maintenance operation by MVA targeting an Inner
1392 Shareable memory region may fail to proceed up to either the
1393 Point of Coherency or to the Point of Unification of the
1394 system. This workaround adds a DSB instruction before the
1395 relevant cache maintenance functions and sets a specific bit
1396 in the diagnostic control register of the SCU.
1398 config PL310_ERRATA_769419
1399 bool "PL310 errata: no automatic Store Buffer drain"
1400 depends on CACHE_L2X0
1402 On revisions of the PL310 prior to r3p2, the Store Buffer does
1403 not automatically drain. This can cause normal, non-cacheable
1404 writes to be retained when the memory system is idle, leading
1405 to suboptimal I/O performance for drivers using coherent DMA.
1406 This option adds a write barrier to the cpu_idle loop so that,
1407 on systems with an outer cache, the store buffer is drained
1410 config ARM_ERRATA_775420
1411 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1414 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1415 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1416 operation aborts with MMU exception, it might cause the processor
1417 to deadlock. This workaround puts DSB before executing ISB if
1418 an abort may occur on cache maintenance.
1422 source "arch/arm/common/Kconfig"
1432 Find out whether you have ISA slots on your motherboard. ISA is the
1433 name of a bus system, i.e. the way the CPU talks to the other stuff
1434 inside your box. Other bus systems are PCI, EISA, MicroChannel
1435 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1436 newer boards don't support it. If you have ISA, say Y, otherwise N.
1438 # Select ISA DMA controller support
1443 config ARCH_NO_VIRT_TO_BUS
1445 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1447 # Select ISA DMA interface
1452 bool "PCI support" if MIGHT_HAVE_PCI
1454 Find out whether you have a PCI motherboard. PCI is the name of a
1455 bus system, i.e. the way the CPU talks to the other stuff inside
1456 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1457 VESA. If you have PCI, say Y, otherwise N.
1463 config PCI_NANOENGINE
1464 bool "BSE nanoEngine PCI support"
1465 depends on SA1100_NANOENGINE
1467 Enable PCI on the BSE nanoEngine board.
1472 # Select the host bridge type
1473 config PCI_HOST_VIA82C505
1475 depends on PCI && ARCH_SHARK
1478 config PCI_HOST_ITE8152
1480 depends on PCI && MACH_ARMCORE
1484 source "drivers/pci/Kconfig"
1486 source "drivers/pcmcia/Kconfig"
1490 menu "Kernel Features"
1495 This option should be selected by machines which have an SMP-
1498 The only effect of this option is to make the SMP-related
1499 options available to the user for configuration.
1502 bool "Symmetric Multi-Processing"
1503 depends on CPU_V6K || CPU_V7
1504 depends on GENERIC_CLOCKEVENTS
1507 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1508 select USE_GENERIC_SMP_HELPERS
1510 This enables support for systems with more than one CPU. If you have
1511 a system with only one CPU, like most personal computers, say N. If
1512 you have a system with more than one CPU, say Y.
1514 If you say N here, the kernel will run on single and multiprocessor
1515 machines, but will use only one CPU of a multiprocessor machine. If
1516 you say Y here, the kernel will run on many, but not all, single
1517 processor machines. On a single processor machine, the kernel will
1518 run faster if you say N here.
1520 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1521 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1522 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1524 If you don't know what to do here, say N.
1527 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1528 depends on SMP && !XIP_KERNEL
1531 SMP kernels contain instructions which fail on non-SMP processors.
1532 Enabling this option allows the kernel to modify itself to make
1533 these instructions safe. Disabling it allows about 1K of space
1536 If you don't know what to do here, say Y.
1538 config ARM_CPU_TOPOLOGY
1539 bool "Support cpu topology definition"
1540 depends on SMP && CPU_V7
1543 Support ARM cpu topology definition. The MPIDR register defines
1544 affinity between processors which is then used to describe the cpu
1545 topology of an ARM System.
1548 bool "Multi-core scheduler support"
1549 depends on ARM_CPU_TOPOLOGY
1551 Multi-core scheduler support improves the CPU scheduler's decision
1552 making when dealing with multi-core CPU chips at a cost of slightly
1553 increased overhead in some places. If unsure say N here.
1556 bool "SMT scheduler support"
1557 depends on ARM_CPU_TOPOLOGY
1559 Improves the CPU scheduler's decision making when dealing with
1560 MultiThreading at a cost of slightly increased overhead in some
1561 places. If unsure say N here.
1566 This option enables support for the ARM system coherency unit
1568 config HAVE_ARM_ARCH_TIMER
1569 bool "Architected timer support"
1571 select ARM_ARCH_TIMER
1573 This option enables support for the ARM architected timer
1579 This options enables support for the ARM timer and watchdog unit
1582 prompt "Memory split"
1585 Select the desired split between kernel and user memory.
1587 If you are not absolutely sure what you are doing, leave this
1591 bool "3G/1G user/kernel split"
1593 bool "2G/2G user/kernel split"
1595 bool "1G/3G user/kernel split"
1600 default 0x40000000 if VMSPLIT_1G
1601 default 0x80000000 if VMSPLIT_2G
1605 int "Maximum number of CPUs (2-32)"
1611 bool "Support for hot-pluggable CPUs"
1612 depends on SMP && HOTPLUG
1614 Say Y here to experiment with turning CPUs off and on. CPUs
1615 can be controlled through /sys/devices/system/cpu.
1618 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1621 Say Y here if you want Linux to communicate with system firmware
1622 implementing the PSCI specification for CPU-centric power
1623 management operations described in ARM document number ARM DEN
1624 0022A ("Power State Coordination Interface System Software on
1628 bool "Use local timer interrupts"
1631 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1633 Enable support for local timers on SMP platforms, rather then the
1634 legacy IPI broadcast method. Local timers allows the system
1635 accounting to be spread across the timer interval, preventing a
1636 "thundering herd" at every timer tick.
1640 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1641 default 355 if ARCH_U8500
1642 default 264 if MACH_H4700
1643 default 512 if SOC_OMAP5
1644 default 288 if ARCH_VT8500 || ARCH_SUNXI
1647 Maximum number of GPIOs in the system.
1649 If unsure, leave the default value.
1651 source kernel/Kconfig.preempt
1655 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1656 ARCH_S5PV210 || ARCH_EXYNOS4
1657 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1658 default AT91_TIMER_HZ if ARCH_AT91
1659 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1663 def_bool HIGH_RES_TIMERS
1665 config THUMB2_KERNEL
1666 bool "Compile the kernel in Thumb-2 mode"
1667 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1669 select ARM_ASM_UNIFIED
1672 By enabling this option, the kernel will be compiled in
1673 Thumb-2 mode. A compiler/assembler that understand the unified
1674 ARM-Thumb syntax is needed.
1678 config THUMB2_AVOID_R_ARM_THM_JUMP11
1679 bool "Work around buggy Thumb-2 short branch relocations in gas"
1680 depends on THUMB2_KERNEL && MODULES
1683 Various binutils versions can resolve Thumb-2 branches to
1684 locally-defined, preemptible global symbols as short-range "b.n"
1685 branch instructions.
1687 This is a problem, because there's no guarantee the final
1688 destination of the symbol, or any candidate locations for a
1689 trampoline, are within range of the branch. For this reason, the
1690 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1691 relocation in modules at all, and it makes little sense to add
1694 The symptom is that the kernel fails with an "unsupported
1695 relocation" error when loading some modules.
1697 Until fixed tools are available, passing
1698 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1699 code which hits this problem, at the cost of a bit of extra runtime
1700 stack usage in some cases.
1702 The problem is described in more detail at:
1703 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1705 Only Thumb-2 kernels are affected.
1707 Unless you are sure your tools don't have this problem, say Y.
1709 config ARM_ASM_UNIFIED
1713 bool "Use the ARM EABI to compile the kernel"
1715 This option allows for the kernel to be compiled using the latest
1716 ARM ABI (aka EABI). This is only useful if you are using a user
1717 space environment that is also compiled with EABI.
1719 Since there are major incompatibilities between the legacy ABI and
1720 EABI, especially with regard to structure member alignment, this
1721 option also changes the kernel syscall calling convention to
1722 disambiguate both ABIs and allow for backward compatibility support
1723 (selected with CONFIG_OABI_COMPAT).
1725 To use this you need GCC version 4.0.0 or later.
1728 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1729 depends on AEABI && !THUMB2_KERNEL
1732 This option preserves the old syscall interface along with the
1733 new (ARM EABI) one. It also provides a compatibility layer to
1734 intercept syscalls that have structure arguments which layout
1735 in memory differs between the legacy ABI and the new ARM EABI
1736 (only for non "thumb" binaries). This option adds a tiny
1737 overhead to all syscalls and produces a slightly larger kernel.
1738 If you know you'll be using only pure EABI user space then you
1739 can say N here. If this option is not selected and you attempt
1740 to execute a legacy ABI binary then the result will be
1741 UNPREDICTABLE (in fact it can be predicted that it won't work
1742 at all). If in doubt say Y.
1744 config ARCH_HAS_HOLES_MEMORYMODEL
1747 config ARCH_SPARSEMEM_ENABLE
1750 config ARCH_SPARSEMEM_DEFAULT
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config ARCH_SELECT_MEMORY_MODEL
1754 def_bool ARCH_SPARSEMEM_ENABLE
1756 config HAVE_ARCH_PFN_VALID
1757 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1760 bool "High Memory Support"
1763 The address space of ARM processors is only 4 Gigabytes large
1764 and it has to accommodate user address space, kernel address
1765 space as well as some memory mapped IO. That means that, if you
1766 have a large amount of physical memory and/or IO, not all of the
1767 memory can be "permanently mapped" by the kernel. The physical
1768 memory that is not permanently mapped is called "high memory".
1770 Depending on the selected kernel/user memory split, minimum
1771 vmalloc space and actual amount of RAM, you may not need this
1772 option which should result in a slightly faster kernel.
1777 bool "Allocate 2nd-level pagetables from highmem"
1780 config HW_PERF_EVENTS
1781 bool "Enable hardware performance counter support for perf events"
1782 depends on PERF_EVENTS
1785 Enable hardware performance counter support for perf events. If
1786 disabled, perf events will use software events only.
1790 config FORCE_MAX_ZONEORDER
1791 int "Maximum zone order" if ARCH_SHMOBILE
1792 range 11 64 if ARCH_SHMOBILE
1793 default "12" if SOC_AM33XX
1794 default "9" if SA1111
1797 The kernel memory allocator divides physically contiguous memory
1798 blocks into "zones", where each zone is a power of two number of
1799 pages. This option selects the largest power of two that the kernel
1800 keeps in the memory allocator. If you need to allocate very large
1801 blocks of physically contiguous memory, then you may need to
1802 increase this value.
1804 This config option is actually maximum order plus one. For example,
1805 a value of 11 means that the largest free memory block is 2^10 pages.
1807 config ALIGNMENT_TRAP
1809 depends on CPU_CP15_MMU
1810 default y if !ARCH_EBSA110
1811 select HAVE_PROC_CPU if PROC_FS
1813 ARM processors cannot fetch/store information which is not
1814 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1815 address divisible by 4. On 32-bit ARM processors, these non-aligned
1816 fetch/store instructions will be emulated in software if you say
1817 here, which has a severe performance impact. This is necessary for
1818 correct operation of some network protocols. With an IP-only
1819 configuration it is safe to say N, otherwise say Y.
1821 config UACCESS_WITH_MEMCPY
1822 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1824 default y if CPU_FEROCEON
1826 Implement faster copy_to_user and clear_user methods for CPU
1827 cores where a 8-word STM instruction give significantly higher
1828 memory write throughput than a sequence of individual 32bit stores.
1830 A possible side effect is a slight increase in scheduling latency
1831 between threads sharing the same address space if they invoke
1832 such copy operations with large buffers.
1834 However, if the CPU data cache is using a write-allocate mode,
1835 this option is unlikely to provide any performance gain.
1839 prompt "Enable seccomp to safely compute untrusted bytecode"
1841 This kernel feature is useful for number crunching applications
1842 that may need to compute untrusted bytecode during their
1843 execution. By using pipes or other transports made available to
1844 the process as file descriptors supporting the read/write
1845 syscalls, it's possible to isolate those applications in
1846 their own address space using seccomp. Once seccomp is
1847 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1848 and the task is only allowed to execute a few safe syscalls
1849 defined by each seccomp mode.
1851 config CC_STACKPROTECTOR
1852 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1854 This option turns on the -fstack-protector GCC feature. This
1855 feature puts, at the beginning of functions, a canary value on
1856 the stack just before the return address, and validates
1857 the value just before actually returning. Stack based buffer
1858 overflows (that need to overwrite this return address) now also
1859 overwrite the canary, which gets detected and the attack is then
1860 neutralized via a kernel panic.
1861 This feature requires gcc version 4.2 or above.
1868 bool "Xen guest support on ARM (EXPERIMENTAL)"
1869 depends on ARM && AEABI && OF
1870 depends on CPU_V7 && !CPU_V6
1871 depends on !GENERIC_ATOMIC64
1873 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1880 bool "Flattened Device Tree support"
1883 select OF_EARLY_FLATTREE
1885 Include support for flattened device tree machine descriptions.
1888 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1891 This is the traditional way of passing data to the kernel at boot
1892 time. If you are solely relying on the flattened device tree (or
1893 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1894 to remove ATAGS support from your kernel binary. If unsure,
1897 config DEPRECATED_PARAM_STRUCT
1898 bool "Provide old way to pass kernel parameters"
1901 This was deprecated in 2001 and announced to live on for 5 years.
1902 Some old boot loaders still use this way.
1904 # Compressed boot loader in ROM. Yes, we really want to ask about
1905 # TEXT and BSS so we preserve their values in the config files.
1906 config ZBOOT_ROM_TEXT
1907 hex "Compressed ROM boot loader base address"
1910 The physical address at which the ROM-able zImage is to be
1911 placed in the target. Platforms which normally make use of
1912 ROM-able zImage formats normally set this to a suitable
1913 value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1917 config ZBOOT_ROM_BSS
1918 hex "Compressed ROM boot loader BSS address"
1921 The base address of an area of read/write memory in the target
1922 for the ROM-able zImage which must be available while the
1923 decompressor is running. It must be large enough to hold the
1924 entire decompressed kernel plus an additional 128 KiB.
1925 Platforms which normally make use of ROM-able zImage formats
1926 normally set this to a suitable value in their defconfig file.
1928 If ZBOOT_ROM is not enabled, this has no effect.
1931 bool "Compressed boot loader in ROM/flash"
1932 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1934 Say Y here if you intend to execute your compressed kernel image
1935 (zImage) directly from ROM or flash. If unsure, say N.
1938 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1939 depends on ZBOOT_ROM && ARCH_SH7372
1940 default ZBOOT_ROM_NONE
1942 Include experimental SD/MMC loading code in the ROM-able zImage.
1943 With this enabled it is possible to write the ROM-able zImage
1944 kernel image to an MMC or SD card and boot the kernel straight
1945 from the reset vector. At reset the processor Mask ROM will load
1946 the first part of the ROM-able zImage which in turn loads the
1947 rest the kernel image to RAM.
1949 config ZBOOT_ROM_NONE
1950 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1952 Do not load image from SD or MMC
1954 config ZBOOT_ROM_MMCIF
1955 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1957 Load image from MMCIF hardware block.
1959 config ZBOOT_ROM_SH_MOBILE_SDHI
1960 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1962 Load image from SDHI hardware block
1966 config ARM_APPENDED_DTB
1967 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968 depends on OF && !ZBOOT_ROM
1970 With this option, the boot code will look for a device tree binary
1971 (DTB) appended to zImage
1972 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1974 This is meant as a backward compatibility convenience for those
1975 systems with a bootloader that can't be upgraded to accommodate
1976 the documented boot protocol using a device tree.
1978 Beware that there is very little in terms of protection against
1979 this option being confused by leftover garbage in memory that might
1980 look like a DTB header after a reboot if no actual DTB is appended
1981 to zImage. Do not leave this option active in a production kernel
1982 if you don't intend to always append a DTB. Proper passing of the
1983 location into r2 of a bootloader provided DTB is always preferable
1986 config ARM_ATAG_DTB_COMPAT
1987 bool "Supplement the appended DTB with traditional ATAG information"
1988 depends on ARM_APPENDED_DTB
1990 Some old bootloaders can't be updated to a DTB capable one, yet
1991 they provide ATAGs with memory configuration, the ramdisk address,
1992 the kernel cmdline string, etc. Such information is dynamically
1993 provided by the bootloader and can't always be stored in a static
1994 DTB. To allow a device tree enabled kernel to be used with such
1995 bootloaders, this option allows zImage to extract the information
1996 from the ATAG list and store it at run time into the appended DTB.
1999 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2000 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2002 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2003 bool "Use bootloader kernel arguments if available"
2005 Uses the command-line options passed by the boot loader instead of
2006 the device tree bootargs property. If the boot loader doesn't provide
2007 any, the device tree bootargs property will be used.
2009 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2010 bool "Extend with bootloader kernel arguments"
2012 The command-line arguments provided by the boot loader will be
2013 appended to the the device tree bootargs property.
2018 string "Default kernel command string"
2021 On some architectures (EBSA110 and CATS), there is currently no way
2022 for the boot loader to pass arguments to the kernel. For these
2023 architectures, you should supply some command-line options at build
2024 time by entering them here. As a minimum, you should specify the
2025 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2028 prompt "Kernel command line type" if CMDLINE != ""
2029 default CMDLINE_FROM_BOOTLOADER
2032 config CMDLINE_FROM_BOOTLOADER
2033 bool "Use bootloader kernel arguments if available"
2035 Uses the command-line options passed by the boot loader. If
2036 the boot loader doesn't provide any, the default kernel command
2037 string provided in CMDLINE will be used.
2039 config CMDLINE_EXTEND
2040 bool "Extend bootloader kernel arguments"
2042 The command-line arguments provided by the boot loader will be
2043 appended to the default kernel command string.
2045 config CMDLINE_FORCE
2046 bool "Always use the default kernel command string"
2048 Always use the default kernel command string, even if the boot
2049 loader passes other arguments to the kernel.
2050 This is useful if you cannot or don't want to change the
2051 command-line options your boot loader passes to the kernel.
2055 bool "Kernel Execute-In-Place from ROM"
2056 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2058 Execute-In-Place allows the kernel to run from non-volatile storage
2059 directly addressable by the CPU, such as NOR flash. This saves RAM
2060 space since the text section of the kernel is not loaded from flash
2061 to RAM. Read-write sections, such as the data section and stack,
2062 are still copied to RAM. The XIP kernel is not compressed since
2063 it has to run directly from flash, so it will take more space to
2064 store it. The flash address used to link the kernel object files,
2065 and for storing it, is configuration dependent. Therefore, if you
2066 say Y here, you must know the proper physical address where to
2067 store the kernel image depending on your own flash memory usage.
2069 Also note that the make target becomes "make xipImage" rather than
2070 "make zImage" or "make Image". The final kernel binary to put in
2071 ROM memory will be arch/arm/boot/xipImage.
2075 config XIP_PHYS_ADDR
2076 hex "XIP Kernel Physical Location"
2077 depends on XIP_KERNEL
2078 default "0x00080000"
2080 This is the physical address in your flash memory the kernel will
2081 be linked for and stored to. This address is dependent on your
2085 bool "Kexec system call (EXPERIMENTAL)"
2086 depends on (!SMP || HOTPLUG_CPU)
2088 kexec is a system call that implements the ability to shutdown your
2089 current kernel, and to start another kernel. It is like a reboot
2090 but it is independent of the system firmware. And like a reboot
2091 you can start any kernel with it, not just Linux.
2093 It is an ongoing process to be certain the hardware in a machine
2094 is properly shutdown, so do not be surprised if this code does not
2095 initially work for you. It may help to enable device hotplugging
2099 bool "Export atags in procfs"
2100 depends on ATAGS && KEXEC
2103 Should the atags used to boot the kernel be exported in an "atags"
2104 file in procfs. Useful with kexec.
2107 bool "Build kdump crash kernel (EXPERIMENTAL)"
2109 Generate crash dump after being started by kexec. This should
2110 be normally only set in special crash dump kernels which are
2111 loaded in the main kernel with kexec-tools into a specially
2112 reserved region and then later executed after a crash by
2113 kdump/kexec. The crash dump kernel must be compiled to a
2114 memory address not used by the main kernel
2116 For more details see Documentation/kdump/kdump.txt
2118 config AUTO_ZRELADDR
2119 bool "Auto calculation of the decompressed kernel image address"
2120 depends on !ZBOOT_ROM && !ARCH_U300
2122 ZRELADDR is the physical address where the decompressed kernel
2123 image will be placed. If AUTO_ZRELADDR is selected, the address
2124 will be determined at run-time by masking the current IP with
2125 0xf8000000. This assumes the zImage being placed in the first 128MB
2126 from start of memory.
2130 menu "CPU Power Management"
2134 source "drivers/cpufreq/Kconfig"
2137 tristate "CPUfreq driver for i.MX CPUs"
2138 depends on ARCH_MXC && CPU_FREQ
2139 select CPU_FREQ_TABLE
2141 This enables the CPUfreq driver for i.MX CPUs.
2143 config CPU_FREQ_SA1100
2146 config CPU_FREQ_SA1110
2149 config CPU_FREQ_INTEGRATOR
2150 tristate "CPUfreq driver for ARM Integrator CPUs"
2151 depends on ARCH_INTEGRATOR && CPU_FREQ
2154 This enables the CPUfreq driver for ARM Integrator CPUs.
2156 For details, take a look at <file:Documentation/cpu-freq>.
2162 depends on CPU_FREQ && ARCH_PXA && PXA25x
2164 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2165 select CPU_FREQ_TABLE
2170 Internal configuration node for common cpufreq on Samsung SoC
2172 config CPU_FREQ_S3C24XX
2173 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2174 depends on ARCH_S3C24XX && CPU_FREQ
2177 This enables the CPUfreq driver for the Samsung S3C24XX family
2180 For details, take a look at <file:Documentation/cpu-freq>.
2184 config CPU_FREQ_S3C24XX_PLL
2185 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2186 depends on CPU_FREQ_S3C24XX
2188 Compile in support for changing the PLL frequency from the
2189 S3C24XX series CPUfreq driver. The PLL takes time to settle
2190 after a frequency change, so by default it is not enabled.
2192 This also means that the PLL tables for the selected CPU(s) will
2193 be built which may increase the size of the kernel image.
2195 config CPU_FREQ_S3C24XX_DEBUG
2196 bool "Debug CPUfreq Samsung driver core"
2197 depends on CPU_FREQ_S3C24XX
2199 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2201 config CPU_FREQ_S3C24XX_IODEBUG
2202 bool "Debug CPUfreq Samsung driver IO timing"
2203 depends on CPU_FREQ_S3C24XX
2205 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2207 config CPU_FREQ_S3C24XX_DEBUGFS
2208 bool "Export debugfs for CPUFreq"
2209 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2211 Export status information via debugfs.
2215 source "drivers/cpuidle/Kconfig"
2219 menu "Floating point emulation"
2221 comment "At least one emulation must be selected"
2224 bool "NWFPE math emulation"
2225 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2227 Say Y to include the NWFPE floating point emulator in the kernel.
2228 This is necessary to run most binaries. Linux does not currently
2229 support floating point hardware so you need to say Y here even if
2230 your machine has an FPA or floating point co-processor podule.
2232 You may say N here if you are going to load the Acorn FPEmulator
2233 early in the bootup.
2236 bool "Support extended precision"
2237 depends on FPE_NWFPE
2239 Say Y to include 80-bit support in the kernel floating-point
2240 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2241 Note that gcc does not generate 80-bit operations by default,
2242 so in most cases this option only enlarges the size of the
2243 floating point emulator without any good reason.
2245 You almost surely want to say N here.
2248 bool "FastFPE math emulation (EXPERIMENTAL)"
2249 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2251 Say Y here to include the FAST floating point emulator in the kernel.
2252 This is an experimental much faster emulator which now also has full
2253 precision for the mantissa. It does not support any exceptions.
2254 It is very simple, and approximately 3-6 times faster than NWFPE.
2256 It should be sufficient for most programs. It may be not suitable
2257 for scientific calculations, but you have to check this for yourself.
2258 If you do not feel you need a faster FP emulation you should better
2262 bool "VFP-format floating point maths"
2263 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2265 Say Y to include VFP support code in the kernel. This is needed
2266 if your hardware includes a VFP unit.
2268 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2269 release notes and additional status information.
2271 Say N if your target does not have VFP hardware.
2279 bool "Advanced SIMD (NEON) Extension support"
2280 depends on VFPv3 && CPU_V7
2282 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2287 menu "Userspace binary formats"
2289 source "fs/Kconfig.binfmt"
2292 tristate "RISC OS personality"
2295 Say Y here to include the kernel code necessary if you want to run
2296 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2297 experimental; if this sounds frightening, say N and sleep in peace.
2298 You can also say M here to compile this support as a module (which
2299 will be called arthur).
2303 menu "Power management options"
2305 source "kernel/power/Kconfig"
2307 config ARCH_SUSPEND_POSSIBLE
2308 depends on !ARCH_S5PC100
2309 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2310 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2313 config ARM_CPU_SUSPEND
2318 source "net/Kconfig"
2320 source "drivers/Kconfig"
2324 source "arch/arm/Kconfig.debug"
2326 source "security/Kconfig"
2328 source "crypto/Kconfig"
2330 source "lib/Kconfig"
2332 source "arch/arm/kvm/Kconfig"