4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MIGHT_HAVE_PCI
318 select MULTI_IRQ_HANDLER
322 config ARCH_INTEGRATOR
323 bool "ARM Ltd. Integrator family"
324 select ARCH_HAS_CPUFREQ
326 select ARM_PATCH_PHYS_VIRT
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
333 select MULTI_IRQ_HANDLER
334 select NEED_MACH_MEMORY_H
335 select PLAT_VERSATILE
338 select VERSATILE_FPGA_IRQ
340 Support for ARM's Integrator platform.
343 bool "ARM Ltd. RealView family"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select ARM_TIMER_SP804
348 select COMMON_CLK_VERSATILE
349 select GENERIC_CLOCKEVENTS
350 select GPIO_PL061 if GPIOLIB
352 select NEED_MACH_MEMORY_H
353 select PLAT_VERSATILE
354 select PLAT_VERSATILE_CLCD
356 This enables support for ARM Ltd RealView boards.
358 config ARCH_VERSATILE
359 bool "ARM Ltd. Versatile family"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
362 select ARM_TIMER_SP804
365 select GENERIC_CLOCKEVENTS
366 select HAVE_MACH_CLKDEV
368 select PLAT_VERSATILE
369 select PLAT_VERSATILE_CLCD
370 select PLAT_VERSATILE_CLOCK
371 select VERSATILE_FPGA_IRQ
373 This enables support for ARM Ltd Versatile board.
377 select ARCH_REQUIRE_GPIOLIB
380 select NEED_MACH_IO_H if PCCARD
382 select PINCTRL_AT91 if USE_OF
384 This enables support for systems based on Atmel
385 AT91RM9200 and AT91SAM9* processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
397 Support for Cirrus Logic 711x/721x/731x based boards.
400 bool "Cortina Systems Gemini"
401 select ARCH_REQUIRE_GPIOLIB
404 select GENERIC_CLOCKEVENTS
406 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
417 This is an evaluation board for the StrongARM processor available
418 from Digital. It has limited hardware on-board, including an
419 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 bool "Energy Micro efm32"
425 select ARCH_REQUIRE_GPIOLIB
431 select GENERIC_CLOCKEVENTS
437 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
485 Support for Intel's IOP13XX (XScale) family of processors.
490 select ARCH_REQUIRE_GPIOLIB
493 select NEED_RET_TO_USER
497 Support for Intel's 80219 and IOP32X (XScale) family of
503 select ARCH_REQUIRE_GPIOLIB
506 select NEED_RET_TO_USER
510 Support for Intel's IOP33X (XScale) family of processors.
515 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select ARCH_REQUIRE_GPIOLIB
517 select ARCH_SUPPORTS_BIG_ENDIAN
520 select DMABOUNCE if PCI
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
523 select NEED_MACH_IO_H
524 select USB_EHCI_BIG_ENDIAN_DESC
525 select USB_EHCI_BIG_ENDIAN_MMIO
527 Support for Intel's IXP4XX (XScale) family of processors.
531 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
538 select PLAT_ORION_LEGACY
540 Support for the Marvell Dove SoC 88AP510
543 bool "Marvell Kirkwood"
544 select ARCH_HAS_CPUFREQ
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 select PLAT_ORION_LEGACY
567 Support for the following Marvell MV78xx0 series SoCs:
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select MULTI_IRQ_HANDLER
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
638 Support for the NXP LPC32XX family of processors
641 bool "PXA2xx/PXA3xx-based"
643 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_CPU_SUSPEND if PM
650 select GENERIC_CLOCKEVENTS
653 select MULTI_IRQ_HANDLER
657 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
660 bool "Qualcomm MSM (non-multiplatform)"
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas ARM SoCs (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas ARM SoC platforms using a non-multiplatform
689 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
701 select HAVE_PATA_PLATFORM
703 select NEED_MACH_IO_H
704 select NEED_MACH_MEMORY_H
708 On the Acorn Risc-PC, Linux can support the internal IDE disk and
709 CD-ROM interface, serial and parallel port, and the floppy drive.
713 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
716 select ARCH_SPARSEMEM_ENABLE
721 select GENERIC_CLOCKEVENTS
724 select NEED_MACH_MEMORY_H
727 Support for StrongARM 11x0 based boards.
730 bool "Samsung S3C24XX SoCs"
731 select ARCH_HAS_CPUFREQ
732 select ARCH_REQUIRE_GPIOLIB
735 select CLKSRC_SAMSUNG_PWM
736 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select HAVE_S3C_RTC if RTC_CLASS
741 select MULTI_IRQ_HANDLER
742 select NEED_MACH_IO_H
745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
748 Samsung SMDK2410 development board (and derivatives).
751 bool "Samsung S3C64XX"
752 select ARCH_HAS_CPUFREQ
753 select ARCH_REQUIRE_GPIOLIB
758 select CLKSRC_SAMSUNG_PWM
759 select COMMON_CLK_SAMSUNG
761 select GENERIC_CLOCKEVENTS
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select PM_GENERIC_DOMAINS if PM
770 select S3C_GPIO_TRACK
772 select SAMSUNG_WAKEMASK
773 select SAMSUNG_WDT_RESET
775 Samsung S3C64XX series based systems
778 bool "Samsung S5P6440 S5P6450"
781 select CLKSRC_SAMSUNG_PWM
783 select GENERIC_CLOCKEVENTS
785 select HAVE_S3C2410_I2C if I2C
786 select HAVE_S3C2410_WATCHDOG if WATCHDOG
787 select HAVE_S3C_RTC if RTC_CLASS
788 select NEED_MACH_GPIO_H
790 select SAMSUNG_WDT_RESET
792 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
796 bool "Samsung S5PC100"
797 select ARCH_REQUIRE_GPIOLIB
800 select CLKSRC_SAMSUNG_PWM
802 select GENERIC_CLOCKEVENTS
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
809 select SAMSUNG_WDT_RESET
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
820 select CLKSRC_SAMSUNG_PWM
822 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select HAVE_S3C_RTC if RTC_CLASS
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
838 select GENERIC_ALLOCATOR
839 select GENERIC_CLOCKEVENTS
840 select GENERIC_IRQ_CHIP
846 Support for TI's DaVinci platform.
851 select ARCH_HAS_CPUFREQ
852 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
861 select NEED_MACH_IO_H if PCCARD
862 select NEED_MACH_MEMORY_H
864 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
868 menu "Multiple platform selection"
869 depends on ARCH_MULTIPLATFORM
871 comment "CPU Core family selection"
874 bool "ARMv4 based platforms (FA526)"
875 depends on !ARCH_MULTI_V6_V7
876 select ARCH_MULTI_V4_V5
879 config ARCH_MULTI_V4T
880 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
881 depends on !ARCH_MULTI_V6_V7
882 select ARCH_MULTI_V4_V5
883 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
884 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
885 CPU_ARM925T || CPU_ARM940T)
888 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
891 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
892 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
893 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
895 config ARCH_MULTI_V4_V5
899 bool "ARMv6 based platforms (ARM11)"
900 select ARCH_MULTI_V6_V7
904 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
906 select ARCH_MULTI_V6_V7
910 config ARCH_MULTI_V6_V7
912 select MIGHT_HAVE_CACHE_L2X0
914 config ARCH_MULTI_CPU_AUTO
915 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
921 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
925 select HAVE_ARM_ARCH_TIMER
928 # This is sorted alphabetically by mach-* pathname. However, plat-*
929 # Kconfigs may be included either alphabetically (according to the
930 # plat- suffix) or along side the corresponding mach-* source.
932 source "arch/arm/mach-mvebu/Kconfig"
934 source "arch/arm/mach-at91/Kconfig"
936 source "arch/arm/mach-axxia/Kconfig"
938 source "arch/arm/mach-bcm/Kconfig"
940 source "arch/arm/mach-berlin/Kconfig"
942 source "arch/arm/mach-clps711x/Kconfig"
944 source "arch/arm/mach-cns3xxx/Kconfig"
946 source "arch/arm/mach-davinci/Kconfig"
948 source "arch/arm/mach-dove/Kconfig"
950 source "arch/arm/mach-ep93xx/Kconfig"
952 source "arch/arm/mach-footbridge/Kconfig"
954 source "arch/arm/mach-gemini/Kconfig"
956 source "arch/arm/mach-highbank/Kconfig"
958 source "arch/arm/mach-hisi/Kconfig"
960 source "arch/arm/mach-integrator/Kconfig"
962 source "arch/arm/mach-iop32x/Kconfig"
964 source "arch/arm/mach-iop33x/Kconfig"
966 source "arch/arm/mach-iop13xx/Kconfig"
968 source "arch/arm/mach-ixp4xx/Kconfig"
970 source "arch/arm/mach-keystone/Kconfig"
972 source "arch/arm/mach-kirkwood/Kconfig"
974 source "arch/arm/mach-ks8695/Kconfig"
976 source "arch/arm/mach-msm/Kconfig"
978 source "arch/arm/mach-moxart/Kconfig"
980 source "arch/arm/mach-mv78xx0/Kconfig"
982 source "arch/arm/mach-imx/Kconfig"
984 source "arch/arm/mach-mxs/Kconfig"
986 source "arch/arm/mach-netx/Kconfig"
988 source "arch/arm/mach-nomadik/Kconfig"
990 source "arch/arm/mach-nspire/Kconfig"
992 source "arch/arm/plat-omap/Kconfig"
994 source "arch/arm/mach-omap1/Kconfig"
996 source "arch/arm/mach-omap2/Kconfig"
998 source "arch/arm/mach-orion5x/Kconfig"
1000 source "arch/arm/mach-picoxcell/Kconfig"
1002 source "arch/arm/mach-pxa/Kconfig"
1003 source "arch/arm/plat-pxa/Kconfig"
1005 source "arch/arm/mach-mmp/Kconfig"
1007 source "arch/arm/mach-qcom/Kconfig"
1009 source "arch/arm/mach-realview/Kconfig"
1011 source "arch/arm/mach-rockchip/Kconfig"
1013 source "arch/arm/mach-sa1100/Kconfig"
1015 source "arch/arm/plat-samsung/Kconfig"
1017 source "arch/arm/mach-socfpga/Kconfig"
1019 source "arch/arm/mach-spear/Kconfig"
1021 source "arch/arm/mach-sti/Kconfig"
1023 source "arch/arm/mach-s3c24xx/Kconfig"
1025 source "arch/arm/mach-s3c64xx/Kconfig"
1027 source "arch/arm/mach-s5p64x0/Kconfig"
1029 source "arch/arm/mach-s5pc100/Kconfig"
1031 source "arch/arm/mach-s5pv210/Kconfig"
1033 source "arch/arm/mach-exynos/Kconfig"
1035 source "arch/arm/mach-shmobile/Kconfig"
1037 source "arch/arm/mach-sunxi/Kconfig"
1039 source "arch/arm/mach-prima2/Kconfig"
1041 source "arch/arm/mach-tegra/Kconfig"
1043 source "arch/arm/mach-u300/Kconfig"
1045 source "arch/arm/mach-ux500/Kconfig"
1047 source "arch/arm/mach-versatile/Kconfig"
1049 source "arch/arm/mach-vexpress/Kconfig"
1050 source "arch/arm/plat-versatile/Kconfig"
1052 source "arch/arm/mach-vt8500/Kconfig"
1054 source "arch/arm/mach-w90x900/Kconfig"
1056 source "arch/arm/mach-zynq/Kconfig"
1058 # Definitions to make life easier
1064 select GENERIC_CLOCKEVENTS
1070 select GENERIC_IRQ_CHIP
1073 config PLAT_ORION_LEGACY
1080 config PLAT_VERSATILE
1083 config ARM_TIMER_SP804
1086 select CLKSRC_OF if OF
1088 source "arch/arm/firmware/Kconfig"
1090 source arch/arm/mm/Kconfig
1094 default 16 if ARCH_EP93XX
1098 bool "Enable iWMMXt support"
1099 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1100 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1102 Enable support for iWMMXt context switching at run time if
1103 running on a CPU that supports it.
1105 config MULTI_IRQ_HANDLER
1108 Allow each machine to specify it's own IRQ handler at run time.
1111 source "arch/arm/Kconfig-nommu"
1114 config PJ4B_ERRATA_4742
1115 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1116 depends on CPU_PJ4B && MACH_ARMADA_370
1119 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1120 Event (WFE) IDLE states, a specific timing sensitivity exists between
1121 the retiring WFI/WFE instructions and the newly issued subsequent
1122 instructions. This sensitivity can result in a CPU hang scenario.
1124 The software must insert either a Data Synchronization Barrier (DSB)
1125 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1128 config ARM_ERRATA_326103
1129 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1132 Executing a SWP instruction to read-only memory does not set bit 11
1133 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1134 treat the access as a read, preventing a COW from occurring and
1135 causing the faulting task to livelock.
1137 config ARM_ERRATA_411920
1138 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1139 depends on CPU_V6 || CPU_V6K
1141 Invalidation of the Instruction Cache operation can
1142 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1143 It does not affect the MPCore. This option enables the ARM Ltd.
1144 recommended workaround.
1146 config ARM_ERRATA_430973
1147 bool "ARM errata: Stale prediction on replaced interworking branch"
1150 This option enables the workaround for the 430973 Cortex-A8
1151 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1152 interworking branch is replaced with another code sequence at the
1153 same virtual address, whether due to self-modifying code or virtual
1154 to physical address re-mapping, Cortex-A8 does not recover from the
1155 stale interworking branch prediction. This results in Cortex-A8
1156 executing the new code sequence in the incorrect ARM or Thumb state.
1157 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1158 and also flushes the branch target cache at every context switch.
1159 Note that setting specific bits in the ACTLR register may not be
1160 available in non-secure mode.
1162 config ARM_ERRATA_458693
1163 bool "ARM errata: Processor deadlock when a false hazard is created"
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1168 erratum. For very specific sequences of memory operations, it is
1169 possible for a hazard condition intended for a cache line to instead
1170 be incorrectly associated with a different cache line. This false
1171 hazard might then cause a processor deadlock. The workaround enables
1172 the L1 caching of the NEON accesses and disables the PLD instruction
1173 in the ACTLR register. Note that setting specific bits in the ACTLR
1174 register may not be available in non-secure mode.
1176 config ARM_ERRATA_460075
1177 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1179 depends on !ARCH_MULTIPLATFORM
1181 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1182 erratum. Any asynchronous access to the L2 cache may encounter a
1183 situation in which recent store transactions to the L2 cache are lost
1184 and overwritten with stale memory contents from external memory. The
1185 workaround disables the write-allocate mode for the L2 cache via the
1186 ACTLR register. Note that setting specific bits in the ACTLR register
1187 may not be available in non-secure mode.
1189 config ARM_ERRATA_742230
1190 bool "ARM errata: DMB operation may be faulty"
1191 depends on CPU_V7 && SMP
1192 depends on !ARCH_MULTIPLATFORM
1194 This option enables the workaround for the 742230 Cortex-A9
1195 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1196 between two write operations may not ensure the correct visibility
1197 ordering of the two writes. This workaround sets a specific bit in
1198 the diagnostic register of the Cortex-A9 which causes the DMB
1199 instruction to behave as a DSB, ensuring the correct behaviour of
1202 config ARM_ERRATA_742231
1203 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1204 depends on CPU_V7 && SMP
1205 depends on !ARCH_MULTIPLATFORM
1207 This option enables the workaround for the 742231 Cortex-A9
1208 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1209 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1210 accessing some data located in the same cache line, may get corrupted
1211 data due to bad handling of the address hazard when the line gets
1212 replaced from one of the CPUs at the same time as another CPU is
1213 accessing it. This workaround sets specific bits in the diagnostic
1214 register of the Cortex-A9 which reduces the linefill issuing
1215 capabilities of the processor.
1217 config PL310_ERRATA_588369
1218 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1219 depends on CACHE_L2X0
1221 The PL310 L2 cache controller implements three types of Clean &
1222 Invalidate maintenance operations: by Physical Address
1223 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1224 They are architecturally defined to behave as the execution of a
1225 clean operation followed immediately by an invalidate operation,
1226 both performing to the same memory location. This functionality
1227 is not correctly implemented in PL310 as clean lines are not
1228 invalidated as a result of these operations.
1230 config ARM_ERRATA_643719
1231 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1232 depends on CPU_V7 && SMP
1234 This option enables the workaround for the 643719 Cortex-A9 (prior to
1235 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1236 register returns zero when it should return one. The workaround
1237 corrects this value, ensuring cache maintenance operations which use
1238 it behave as intended and avoiding data corruption.
1240 config ARM_ERRATA_720789
1241 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1244 This option enables the workaround for the 720789 Cortex-A9 (prior to
1245 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1246 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1247 As a consequence of this erratum, some TLB entries which should be
1248 invalidated are not, resulting in an incoherency in the system page
1249 tables. The workaround changes the TLB flushing routines to invalidate
1250 entries regardless of the ASID.
1252 config PL310_ERRATA_727915
1253 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1254 depends on CACHE_L2X0
1256 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1257 operation (offset 0x7FC). This operation runs in background so that
1258 PL310 can handle normal accesses while it is in progress. Under very
1259 rare circumstances, due to this erratum, write data can be lost when
1260 PL310 treats a cacheable write transaction during a Clean &
1261 Invalidate by Way operation.
1263 config ARM_ERRATA_743622
1264 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1266 depends on !ARCH_MULTIPLATFORM
1268 This option enables the workaround for the 743622 Cortex-A9
1269 (r2p*) erratum. Under very rare conditions, a faulty
1270 optimisation in the Cortex-A9 Store Buffer may lead to data
1271 corruption. This workaround sets a specific bit in the diagnostic
1272 register of the Cortex-A9 which disables the Store Buffer
1273 optimisation, preventing the defect from occurring. This has no
1274 visible impact on the overall performance or power consumption of the
1277 config ARM_ERRATA_751472
1278 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1280 depends on !ARCH_MULTIPLATFORM
1282 This option enables the workaround for the 751472 Cortex-A9 (prior
1283 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1284 completion of a following broadcasted operation if the second
1285 operation is received by a CPU before the ICIALLUIS has completed,
1286 potentially leading to corrupted entries in the cache or TLB.
1288 config PL310_ERRATA_753970
1289 bool "PL310 errata: cache sync operation may be faulty"
1290 depends on CACHE_PL310
1292 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1294 Under some condition the effect of cache sync operation on
1295 the store buffer still remains when the operation completes.
1296 This means that the store buffer is always asked to drain and
1297 this prevents it from merging any further writes. The workaround
1298 is to replace the normal offset of cache sync operation (0x730)
1299 by another offset targeting an unmapped PL310 register 0x740.
1300 This has the same effect as the cache sync operation: store buffer
1301 drain and waiting for all buffers empty.
1303 config ARM_ERRATA_754322
1304 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1307 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1308 r3p*) erratum. A speculative memory access may cause a page table walk
1309 which starts prior to an ASID switch but completes afterwards. This
1310 can populate the micro-TLB with a stale entry which may be hit with
1311 the new ASID. This workaround places two dsb instructions in the mm
1312 switching code so that no page table walks can cross the ASID switch.
1314 config ARM_ERRATA_754327
1315 bool "ARM errata: no automatic Store Buffer drain"
1316 depends on CPU_V7 && SMP
1318 This option enables the workaround for the 754327 Cortex-A9 (prior to
1319 r2p0) erratum. The Store Buffer does not have any automatic draining
1320 mechanism and therefore a livelock may occur if an external agent
1321 continuously polls a memory location waiting to observe an update.
1322 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1323 written polling loops from denying visibility of updates to memory.
1325 config ARM_ERRATA_364296
1326 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1329 This options enables the workaround for the 364296 ARM1136
1330 r0p2 erratum (possible cache data corruption with
1331 hit-under-miss enabled). It sets the undocumented bit 31 in
1332 the auxiliary control register and the FI bit in the control
1333 register, thus disabling hit-under-miss without putting the
1334 processor into full low interrupt latency mode. ARM11MPCore
1337 config ARM_ERRATA_764369
1338 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1339 depends on CPU_V7 && SMP
1341 This option enables the workaround for erratum 764369
1342 affecting Cortex-A9 MPCore with two or more processors (all
1343 current revisions). Under certain timing circumstances, a data
1344 cache line maintenance operation by MVA targeting an Inner
1345 Shareable memory region may fail to proceed up to either the
1346 Point of Coherency or to the Point of Unification of the
1347 system. This workaround adds a DSB instruction before the
1348 relevant cache maintenance functions and sets a specific bit
1349 in the diagnostic control register of the SCU.
1351 config PL310_ERRATA_769419
1352 bool "PL310 errata: no automatic Store Buffer drain"
1353 depends on CACHE_L2X0
1355 On revisions of the PL310 prior to r3p2, the Store Buffer does
1356 not automatically drain. This can cause normal, non-cacheable
1357 writes to be retained when the memory system is idle, leading
1358 to suboptimal I/O performance for drivers using coherent DMA.
1359 This option adds a write barrier to the cpu_idle loop so that,
1360 on systems with an outer cache, the store buffer is drained
1363 config ARM_ERRATA_775420
1364 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1367 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1368 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1369 operation aborts with MMU exception, it might cause the processor
1370 to deadlock. This workaround puts DSB before executing ISB if
1371 an abort may occur on cache maintenance.
1373 config ARM_ERRATA_798181
1374 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1375 depends on CPU_V7 && SMP
1377 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1378 adequately shooting down all use of the old entries. This
1379 option enables the Linux kernel workaround for this erratum
1380 which sends an IPI to the CPUs that are running the same ASID
1381 as the one being invalidated.
1383 config ARM_ERRATA_773022
1384 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1387 This option enables the workaround for the 773022 Cortex-A15
1388 (up to r0p4) erratum. In certain rare sequences of code, the
1389 loop buffer may deliver incorrect instructions. This
1390 workaround disables the loop buffer to avoid the erratum.
1394 source "arch/arm/common/Kconfig"
1404 Find out whether you have ISA slots on your motherboard. ISA is the
1405 name of a bus system, i.e. the way the CPU talks to the other stuff
1406 inside your box. Other bus systems are PCI, EISA, MicroChannel
1407 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1408 newer boards don't support it. If you have ISA, say Y, otherwise N.
1410 # Select ISA DMA controller support
1415 # Select ISA DMA interface
1420 bool "PCI support" if MIGHT_HAVE_PCI
1422 Find out whether you have a PCI motherboard. PCI is the name of a
1423 bus system, i.e. the way the CPU talks to the other stuff inside
1424 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1425 VESA. If you have PCI, say Y, otherwise N.
1431 config PCI_NANOENGINE
1432 bool "BSE nanoEngine PCI support"
1433 depends on SA1100_NANOENGINE
1435 Enable PCI on the BSE nanoEngine board.
1440 config PCI_HOST_ITE8152
1442 depends on PCI && MACH_ARMCORE
1446 source "drivers/pci/Kconfig"
1447 source "drivers/pci/pcie/Kconfig"
1449 source "drivers/pcmcia/Kconfig"
1453 menu "Kernel Features"
1458 This option should be selected by machines which have an SMP-
1461 The only effect of this option is to make the SMP-related
1462 options available to the user for configuration.
1465 bool "Symmetric Multi-Processing"
1466 depends on CPU_V6K || CPU_V7
1467 depends on GENERIC_CLOCKEVENTS
1469 depends on MMU || ARM_MPU
1471 This enables support for systems with more than one CPU. If you have
1472 a system with only one CPU, say N. If you have a system with more
1473 than one CPU, say Y.
1475 If you say N here, the kernel will run on uni- and multiprocessor
1476 machines, but will use only one CPU of a multiprocessor machine. If
1477 you say Y here, the kernel will run on many, but not all,
1478 uniprocessor machines. On a uniprocessor machine, the kernel
1479 will run faster if you say N here.
1481 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1482 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1483 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1485 If you don't know what to do here, say N.
1488 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1489 depends on SMP && !XIP_KERNEL && MMU
1492 SMP kernels contain instructions which fail on non-SMP processors.
1493 Enabling this option allows the kernel to modify itself to make
1494 these instructions safe. Disabling it allows about 1K of space
1497 If you don't know what to do here, say Y.
1499 config ARM_CPU_TOPOLOGY
1500 bool "Support cpu topology definition"
1501 depends on SMP && CPU_V7
1504 Support ARM cpu topology definition. The MPIDR register defines
1505 affinity between processors which is then used to describe the cpu
1506 topology of an ARM System.
1509 bool "Multi-core scheduler support"
1510 depends on ARM_CPU_TOPOLOGY
1512 Multi-core scheduler support improves the CPU scheduler's decision
1513 making when dealing with multi-core CPU chips at a cost of slightly
1514 increased overhead in some places. If unsure say N here.
1517 bool "SMT scheduler support"
1518 depends on ARM_CPU_TOPOLOGY
1520 Improves the CPU scheduler's decision making when dealing with
1521 MultiThreading at a cost of slightly increased overhead in some
1522 places. If unsure say N here.
1527 This option enables support for the ARM system coherency unit
1529 config HAVE_ARM_ARCH_TIMER
1530 bool "Architected timer support"
1532 select ARM_ARCH_TIMER
1533 select GENERIC_CLOCKEVENTS
1535 This option enables support for the ARM architected timer
1540 select CLKSRC_OF if OF
1542 This options enables support for the ARM timer and watchdog unit
1545 bool "Multi-Cluster Power Management"
1546 depends on CPU_V7 && SMP
1548 This option provides the common power management infrastructure
1549 for (multi-)cluster based systems, such as big.LITTLE based
1553 bool "big.LITTLE support (Experimental)"
1554 depends on CPU_V7 && SMP
1557 This option enables support selections for the big.LITTLE
1558 system architecture.
1561 bool "big.LITTLE switcher support"
1562 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1563 select ARM_CPU_SUSPEND
1566 The big.LITTLE "switcher" provides the core functionality to
1567 transparently handle transition between a cluster of A15's
1568 and a cluster of A7's in a big.LITTLE system.
1570 config BL_SWITCHER_DUMMY_IF
1571 tristate "Simple big.LITTLE switcher user interface"
1572 depends on BL_SWITCHER && DEBUG_KERNEL
1574 This is a simple and dummy char dev interface to control
1575 the big.LITTLE switcher core code. It is meant for
1576 debugging purposes only.
1579 prompt "Memory split"
1583 Select the desired split between kernel and user memory.
1585 If you are not absolutely sure what you are doing, leave this
1589 bool "3G/1G user/kernel split"
1591 bool "2G/2G user/kernel split"
1593 bool "1G/3G user/kernel split"
1598 default PHYS_OFFSET if !MMU
1599 default 0x40000000 if VMSPLIT_1G
1600 default 0x80000000 if VMSPLIT_2G
1604 int "Maximum number of CPUs (2-32)"
1610 bool "Support for hot-pluggable CPUs"
1613 Say Y here to experiment with turning CPUs off and on. CPUs
1614 can be controlled through /sys/devices/system/cpu.
1617 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1620 Say Y here if you want Linux to communicate with system firmware
1621 implementing the PSCI specification for CPU-centric power
1622 management operations described in ARM document number ARM DEN
1623 0022A ("Power State Coordination Interface System Software on
1626 # The GPIO number here must be sorted by descending number. In case of
1627 # a multiplatform kernel, we just want the highest value required by the
1628 # selected platforms.
1631 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1632 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1633 default 416 if ARCH_SUNXI
1634 default 392 if ARCH_U8500
1635 default 352 if ARCH_VT8500
1636 default 264 if MACH_H4700
1639 Maximum number of GPIOs in the system.
1641 If unsure, leave the default value.
1643 source kernel/Kconfig.preempt
1647 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1648 ARCH_S5PV210 || ARCH_EXYNOS4
1649 default AT91_TIMER_HZ if ARCH_AT91
1650 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1654 depends on HZ_FIXED = 0
1655 prompt "Timer frequency"
1679 default HZ_FIXED if HZ_FIXED != 0
1680 default 100 if HZ_100
1681 default 200 if HZ_200
1682 default 250 if HZ_250
1683 default 300 if HZ_300
1684 default 500 if HZ_500
1688 def_bool HIGH_RES_TIMERS
1690 config THUMB2_KERNEL
1691 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1692 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1693 default y if CPU_THUMBONLY
1695 select ARM_ASM_UNIFIED
1698 By enabling this option, the kernel will be compiled in
1699 Thumb-2 mode. A compiler/assembler that understand the unified
1700 ARM-Thumb syntax is needed.
1704 config THUMB2_AVOID_R_ARM_THM_JUMP11
1705 bool "Work around buggy Thumb-2 short branch relocations in gas"
1706 depends on THUMB2_KERNEL && MODULES
1709 Various binutils versions can resolve Thumb-2 branches to
1710 locally-defined, preemptible global symbols as short-range "b.n"
1711 branch instructions.
1713 This is a problem, because there's no guarantee the final
1714 destination of the symbol, or any candidate locations for a
1715 trampoline, are within range of the branch. For this reason, the
1716 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1717 relocation in modules at all, and it makes little sense to add
1720 The symptom is that the kernel fails with an "unsupported
1721 relocation" error when loading some modules.
1723 Until fixed tools are available, passing
1724 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1725 code which hits this problem, at the cost of a bit of extra runtime
1726 stack usage in some cases.
1728 The problem is described in more detail at:
1729 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1731 Only Thumb-2 kernels are affected.
1733 Unless you are sure your tools don't have this problem, say Y.
1735 config ARM_ASM_UNIFIED
1739 bool "Use the ARM EABI to compile the kernel"
1741 This option allows for the kernel to be compiled using the latest
1742 ARM ABI (aka EABI). This is only useful if you are using a user
1743 space environment that is also compiled with EABI.
1745 Since there are major incompatibilities between the legacy ABI and
1746 EABI, especially with regard to structure member alignment, this
1747 option also changes the kernel syscall calling convention to
1748 disambiguate both ABIs and allow for backward compatibility support
1749 (selected with CONFIG_OABI_COMPAT).
1751 To use this you need GCC version 4.0.0 or later.
1754 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1755 depends on AEABI && !THUMB2_KERNEL
1757 This option preserves the old syscall interface along with the
1758 new (ARM EABI) one. It also provides a compatibility layer to
1759 intercept syscalls that have structure arguments which layout
1760 in memory differs between the legacy ABI and the new ARM EABI
1761 (only for non "thumb" binaries). This option adds a tiny
1762 overhead to all syscalls and produces a slightly larger kernel.
1764 The seccomp filter system will not be available when this is
1765 selected, since there is no way yet to sensibly distinguish
1766 between calling conventions during filtering.
1768 If you know you'll be using only pure EABI user space then you
1769 can say N here. If this option is not selected and you attempt
1770 to execute a legacy ABI binary then the result will be
1771 UNPREDICTABLE (in fact it can be predicted that it won't work
1772 at all). If in doubt say N.
1774 config ARCH_HAS_HOLES_MEMORYMODEL
1777 config ARCH_SPARSEMEM_ENABLE
1780 config ARCH_SPARSEMEM_DEFAULT
1781 def_bool ARCH_SPARSEMEM_ENABLE
1783 config ARCH_SELECT_MEMORY_MODEL
1784 def_bool ARCH_SPARSEMEM_ENABLE
1786 config HAVE_ARCH_PFN_VALID
1787 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1790 bool "High Memory Support"
1793 The address space of ARM processors is only 4 Gigabytes large
1794 and it has to accommodate user address space, kernel address
1795 space as well as some memory mapped IO. That means that, if you
1796 have a large amount of physical memory and/or IO, not all of the
1797 memory can be "permanently mapped" by the kernel. The physical
1798 memory that is not permanently mapped is called "high memory".
1800 Depending on the selected kernel/user memory split, minimum
1801 vmalloc space and actual amount of RAM, you may not need this
1802 option which should result in a slightly faster kernel.
1807 bool "Allocate 2nd-level pagetables from highmem"
1810 config HW_PERF_EVENTS
1811 bool "Enable hardware performance counter support for perf events"
1812 depends on PERF_EVENTS
1815 Enable hardware performance counter support for perf events. If
1816 disabled, perf events will use software events only.
1818 config SYS_SUPPORTS_HUGETLBFS
1822 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1826 config ARCH_WANT_GENERAL_HUGETLB
1831 config FORCE_MAX_ZONEORDER
1832 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1833 range 11 64 if ARCH_SHMOBILE_LEGACY
1834 default "12" if SOC_AM33XX
1835 default "9" if SA1111 || ARCH_EFM32
1838 The kernel memory allocator divides physically contiguous memory
1839 blocks into "zones", where each zone is a power of two number of
1840 pages. This option selects the largest power of two that the kernel
1841 keeps in the memory allocator. If you need to allocate very large
1842 blocks of physically contiguous memory, then you may need to
1843 increase this value.
1845 This config option is actually maximum order plus one. For example,
1846 a value of 11 means that the largest free memory block is 2^10 pages.
1848 config ALIGNMENT_TRAP
1850 depends on CPU_CP15_MMU
1851 default y if !ARCH_EBSA110
1852 select HAVE_PROC_CPU if PROC_FS
1854 ARM processors cannot fetch/store information which is not
1855 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1856 address divisible by 4. On 32-bit ARM processors, these non-aligned
1857 fetch/store instructions will be emulated in software if you say
1858 here, which has a severe performance impact. This is necessary for
1859 correct operation of some network protocols. With an IP-only
1860 configuration it is safe to say N, otherwise say Y.
1862 config UACCESS_WITH_MEMCPY
1863 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1865 default y if CPU_FEROCEON
1867 Implement faster copy_to_user and clear_user methods for CPU
1868 cores where a 8-word STM instruction give significantly higher
1869 memory write throughput than a sequence of individual 32bit stores.
1871 A possible side effect is a slight increase in scheduling latency
1872 between threads sharing the same address space if they invoke
1873 such copy operations with large buffers.
1875 However, if the CPU data cache is using a write-allocate mode,
1876 this option is unlikely to provide any performance gain.
1880 prompt "Enable seccomp to safely compute untrusted bytecode"
1882 This kernel feature is useful for number crunching applications
1883 that may need to compute untrusted bytecode during their
1884 execution. By using pipes or other transports made available to
1885 the process as file descriptors supporting the read/write
1886 syscalls, it's possible to isolate those applications in
1887 their own address space using seccomp. Once seccomp is
1888 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1889 and the task is only allowed to execute a few safe syscalls
1890 defined by each seccomp mode.
1903 bool "Xen guest support on ARM (EXPERIMENTAL)"
1904 depends on ARM && AEABI && OF
1905 depends on CPU_V7 && !CPU_V6
1906 depends on !GENERIC_ATOMIC64
1908 select ARCH_DMA_ADDR_T_64BIT
1912 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1919 bool "Flattened Device Tree support"
1922 select OF_EARLY_FLATTREE
1923 select OF_RESERVED_MEM
1925 Include support for flattened device tree machine descriptions.
1928 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1931 This is the traditional way of passing data to the kernel at boot
1932 time. If you are solely relying on the flattened device tree (or
1933 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1934 to remove ATAGS support from your kernel binary. If unsure,
1937 config DEPRECATED_PARAM_STRUCT
1938 bool "Provide old way to pass kernel parameters"
1941 This was deprecated in 2001 and announced to live on for 5 years.
1942 Some old boot loaders still use this way.
1944 # Compressed boot loader in ROM. Yes, we really want to ask about
1945 # TEXT and BSS so we preserve their values in the config files.
1946 config ZBOOT_ROM_TEXT
1947 hex "Compressed ROM boot loader base address"
1950 The physical address at which the ROM-able zImage is to be
1951 placed in the target. Platforms which normally make use of
1952 ROM-able zImage formats normally set this to a suitable
1953 value in their defconfig file.
1955 If ZBOOT_ROM is not enabled, this has no effect.
1957 config ZBOOT_ROM_BSS
1958 hex "Compressed ROM boot loader BSS address"
1961 The base address of an area of read/write memory in the target
1962 for the ROM-able zImage which must be available while the
1963 decompressor is running. It must be large enough to hold the
1964 entire decompressed kernel plus an additional 128 KiB.
1965 Platforms which normally make use of ROM-able zImage formats
1966 normally set this to a suitable value in their defconfig file.
1968 If ZBOOT_ROM is not enabled, this has no effect.
1971 bool "Compressed boot loader in ROM/flash"
1972 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1973 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1975 Say Y here if you intend to execute your compressed kernel image
1976 (zImage) directly from ROM or flash. If unsure, say N.
1979 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1980 depends on ZBOOT_ROM && ARCH_SH7372
1981 default ZBOOT_ROM_NONE
1983 Include experimental SD/MMC loading code in the ROM-able zImage.
1984 With this enabled it is possible to write the ROM-able zImage
1985 kernel image to an MMC or SD card and boot the kernel straight
1986 from the reset vector. At reset the processor Mask ROM will load
1987 the first part of the ROM-able zImage which in turn loads the
1988 rest the kernel image to RAM.
1990 config ZBOOT_ROM_NONE
1991 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1993 Do not load image from SD or MMC
1995 config ZBOOT_ROM_MMCIF
1996 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1998 Load image from MMCIF hardware block.
2000 config ZBOOT_ROM_SH_MOBILE_SDHI
2001 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2003 Load image from SDHI hardware block
2007 config ARM_APPENDED_DTB
2008 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2011 With this option, the boot code will look for a device tree binary
2012 (DTB) appended to zImage
2013 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2015 This is meant as a backward compatibility convenience for those
2016 systems with a bootloader that can't be upgraded to accommodate
2017 the documented boot protocol using a device tree.
2019 Beware that there is very little in terms of protection against
2020 this option being confused by leftover garbage in memory that might
2021 look like a DTB header after a reboot if no actual DTB is appended
2022 to zImage. Do not leave this option active in a production kernel
2023 if you don't intend to always append a DTB. Proper passing of the
2024 location into r2 of a bootloader provided DTB is always preferable
2027 config ARM_ATAG_DTB_COMPAT
2028 bool "Supplement the appended DTB with traditional ATAG information"
2029 depends on ARM_APPENDED_DTB
2031 Some old bootloaders can't be updated to a DTB capable one, yet
2032 they provide ATAGs with memory configuration, the ramdisk address,
2033 the kernel cmdline string, etc. Such information is dynamically
2034 provided by the bootloader and can't always be stored in a static
2035 DTB. To allow a device tree enabled kernel to be used with such
2036 bootloaders, this option allows zImage to extract the information
2037 from the ATAG list and store it at run time into the appended DTB.
2040 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2041 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2043 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2044 bool "Use bootloader kernel arguments if available"
2046 Uses the command-line options passed by the boot loader instead of
2047 the device tree bootargs property. If the boot loader doesn't provide
2048 any, the device tree bootargs property will be used.
2050 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2051 bool "Extend with bootloader kernel arguments"
2053 The command-line arguments provided by the boot loader will be
2054 appended to the the device tree bootargs property.
2059 string "Default kernel command string"
2062 On some architectures (EBSA110 and CATS), there is currently no way
2063 for the boot loader to pass arguments to the kernel. For these
2064 architectures, you should supply some command-line options at build
2065 time by entering them here. As a minimum, you should specify the
2066 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2069 prompt "Kernel command line type" if CMDLINE != ""
2070 default CMDLINE_FROM_BOOTLOADER
2073 config CMDLINE_FROM_BOOTLOADER
2074 bool "Use bootloader kernel arguments if available"
2076 Uses the command-line options passed by the boot loader. If
2077 the boot loader doesn't provide any, the default kernel command
2078 string provided in CMDLINE will be used.
2080 config CMDLINE_EXTEND
2081 bool "Extend bootloader kernel arguments"
2083 The command-line arguments provided by the boot loader will be
2084 appended to the default kernel command string.
2086 config CMDLINE_FORCE
2087 bool "Always use the default kernel command string"
2089 Always use the default kernel command string, even if the boot
2090 loader passes other arguments to the kernel.
2091 This is useful if you cannot or don't want to change the
2092 command-line options your boot loader passes to the kernel.
2096 bool "Kernel Execute-In-Place from ROM"
2097 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2099 Execute-In-Place allows the kernel to run from non-volatile storage
2100 directly addressable by the CPU, such as NOR flash. This saves RAM
2101 space since the text section of the kernel is not loaded from flash
2102 to RAM. Read-write sections, such as the data section and stack,
2103 are still copied to RAM. The XIP kernel is not compressed since
2104 it has to run directly from flash, so it will take more space to
2105 store it. The flash address used to link the kernel object files,
2106 and for storing it, is configuration dependent. Therefore, if you
2107 say Y here, you must know the proper physical address where to
2108 store the kernel image depending on your own flash memory usage.
2110 Also note that the make target becomes "make xipImage" rather than
2111 "make zImage" or "make Image". The final kernel binary to put in
2112 ROM memory will be arch/arm/boot/xipImage.
2116 config XIP_PHYS_ADDR
2117 hex "XIP Kernel Physical Location"
2118 depends on XIP_KERNEL
2119 default "0x00080000"
2121 This is the physical address in your flash memory the kernel will
2122 be linked for and stored to. This address is dependent on your
2126 bool "Kexec system call (EXPERIMENTAL)"
2127 depends on (!SMP || PM_SLEEP_SMP)
2129 kexec is a system call that implements the ability to shutdown your
2130 current kernel, and to start another kernel. It is like a reboot
2131 but it is independent of the system firmware. And like a reboot
2132 you can start any kernel with it, not just Linux.
2134 It is an ongoing process to be certain the hardware in a machine
2135 is properly shutdown, so do not be surprised if this code does not
2136 initially work for you.
2139 bool "Export atags in procfs"
2140 depends on ATAGS && KEXEC
2143 Should the atags used to boot the kernel be exported in an "atags"
2144 file in procfs. Useful with kexec.
2147 bool "Build kdump crash kernel (EXPERIMENTAL)"
2149 Generate crash dump after being started by kexec. This should
2150 be normally only set in special crash dump kernels which are
2151 loaded in the main kernel with kexec-tools into a specially
2152 reserved region and then later executed after a crash by
2153 kdump/kexec. The crash dump kernel must be compiled to a
2154 memory address not used by the main kernel
2156 For more details see Documentation/kdump/kdump.txt
2158 config AUTO_ZRELADDR
2159 bool "Auto calculation of the decompressed kernel image address"
2161 ZRELADDR is the physical address where the decompressed kernel
2162 image will be placed. If AUTO_ZRELADDR is selected, the address
2163 will be determined at run-time by masking the current IP with
2164 0xf8000000. This assumes the zImage being placed in the first 128MB
2165 from start of memory.
2169 menu "CPU Power Management"
2172 source "drivers/cpufreq/Kconfig"
2175 source "drivers/cpuidle/Kconfig"
2179 menu "Floating point emulation"
2181 comment "At least one emulation must be selected"
2184 bool "NWFPE math emulation"
2185 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2187 Say Y to include the NWFPE floating point emulator in the kernel.
2188 This is necessary to run most binaries. Linux does not currently
2189 support floating point hardware so you need to say Y here even if
2190 your machine has an FPA or floating point co-processor podule.
2192 You may say N here if you are going to load the Acorn FPEmulator
2193 early in the bootup.
2196 bool "Support extended precision"
2197 depends on FPE_NWFPE
2199 Say Y to include 80-bit support in the kernel floating-point
2200 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2201 Note that gcc does not generate 80-bit operations by default,
2202 so in most cases this option only enlarges the size of the
2203 floating point emulator without any good reason.
2205 You almost surely want to say N here.
2208 bool "FastFPE math emulation (EXPERIMENTAL)"
2209 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2211 Say Y here to include the FAST floating point emulator in the kernel.
2212 This is an experimental much faster emulator which now also has full
2213 precision for the mantissa. It does not support any exceptions.
2214 It is very simple, and approximately 3-6 times faster than NWFPE.
2216 It should be sufficient for most programs. It may be not suitable
2217 for scientific calculations, but you have to check this for yourself.
2218 If you do not feel you need a faster FP emulation you should better
2222 bool "VFP-format floating point maths"
2223 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2225 Say Y to include VFP support code in the kernel. This is needed
2226 if your hardware includes a VFP unit.
2228 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2229 release notes and additional status information.
2231 Say N if your target does not have VFP hardware.
2239 bool "Advanced SIMD (NEON) Extension support"
2240 depends on VFPv3 && CPU_V7
2242 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2245 config KERNEL_MODE_NEON
2246 bool "Support for NEON in kernel mode"
2247 depends on NEON && AEABI
2249 Say Y to include support for NEON in kernel mode.
2253 menu "Userspace binary formats"
2255 source "fs/Kconfig.binfmt"
2258 tristate "RISC OS personality"
2261 Say Y here to include the kernel code necessary if you want to run
2262 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2263 experimental; if this sounds frightening, say N and sleep in peace.
2264 You can also say M here to compile this support as a module (which
2265 will be called arthur).
2269 menu "Power management options"
2271 source "kernel/power/Kconfig"
2273 config ARCH_SUSPEND_POSSIBLE
2274 depends on !ARCH_S5PC100
2275 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2276 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2279 config ARM_CPU_SUSPEND
2284 source "net/Kconfig"
2286 source "drivers/Kconfig"
2290 source "arch/arm/Kconfig.debug"
2292 source "security/Kconfig"
2294 source "crypto/Kconfig"
2296 source "lib/Kconfig"
2298 source "arch/arm/kvm/Kconfig"