arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_IRQ_SHOW_LEVEL
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARCH_REALVIEW
 333         bool "ARM Ltd. RealView family"
 334         select ARCH_WANT_OPTIONAL_GPIOLIB
 335         select ARM_AMBA
 336         select ARM_TIMER_SP804
 337         select COMMON_CLK
 338         select COMMON_CLK_VERSATILE
 339         select GENERIC_CLOCKEVENTS
 340         select GPIO_PL061 if GPIOLIB
 341         select ICST
 342         select NEED_MACH_MEMORY_H
 343         select PLAT_VERSATILE
 344         select PLAT_VERSATILE_SCHED_CLOCK
 345         help
 346           This enables support for ARM Ltd RealView boards.
 347
 348 config ARCH_VERSATILE
 349         bool "ARM Ltd. Versatile family"
 350         select ARCH_WANT_OPTIONAL_GPIOLIB
 351         select ARM_AMBA
 352         select ARM_TIMER_SP804
 353         select ARM_VIC
 354         select CLKDEV_LOOKUP
 355         select GENERIC_CLOCKEVENTS
 356         select HAVE_MACH_CLKDEV
 357         select ICST
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_CLOCK
 360         select PLAT_VERSATILE_SCHED_CLOCK
 361         select VERSATILE_FPGA_IRQ
 362         help
 363           This enables support for ARM Ltd Versatile board.
 364
 365 config ARCH_CLPS711X
 366         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 367         select ARCH_REQUIRE_GPIOLIB
 368         select AUTO_ZRELADDR
 369         select CLKSRC_MMIO
 370         select COMMON_CLK
 371         select CPU_ARM720T
 372         select GENERIC_CLOCKEVENTS
 373         select MFD_SYSCON
 374         select SOC_BUS
 375         help
 376           Support for Cirrus Logic 711x/721x/731x based boards.
 377
 378 config ARCH_GEMINI
 379         bool "Cortina Systems Gemini"
 380         select ARCH_REQUIRE_GPIOLIB
 381         select CLKSRC_MMIO
 382         select CPU_FA526
 383         select GENERIC_CLOCKEVENTS
 384         help
 385           Support for the Cortina Systems Gemini family SoCs
 386
 387 config ARCH_EBSA110
 388         bool "EBSA-110"
 389         select ARCH_USES_GETTIMEOFFSET
 390         select CPU_SA110
 391         select ISA
 392         select NEED_MACH_IO_H
 393         select NEED_MACH_MEMORY_H
 394         select NO_IOPORT_MAP
 395         help
 396           This is an evaluation board for the StrongARM processor available
 397           from Digital. It has limited hardware on-board, including an
 398           Ethernet interface, two PCMCIA sockets, two serial ports and a
 399           parallel port.
 400
 401 config ARCH_EFM32
 402         bool "Energy Micro efm32"
 403         depends on !MMU
 404         select ARCH_REQUIRE_GPIOLIB
 405         select ARM_NVIC
 406         select AUTO_ZRELADDR
 407         select CLKSRC_OF
 408         select COMMON_CLK
 409         select CPU_V7M
 410         select GENERIC_CLOCKEVENTS
 411         select NO_DMA
 412         select NO_IOPORT_MAP
 413         select SPARSE_IRQ
 414         select USE_OF
 415         help
 416           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 417           processors.
 418
 419 config ARCH_EP93XX
 420         bool "EP93xx-based"
 421         select ARCH_HAS_HOLES_MEMORYMODEL
 422         select ARCH_REQUIRE_GPIOLIB
 423         select ARCH_USES_GETTIMEOFFSET
 424         select ARM_AMBA
 425         select ARM_VIC
 426         select CLKDEV_LOOKUP
 427         select CPU_ARM920T
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         help
 542           Support for the following Marvell Orion 5x series SoCs:
 543           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 544           Orion-2 (5281), Orion-1-90 (6183).
 545
 546 config ARCH_MMP
 547         bool "Marvell PXA168/910/MMP2"
 548         depends on MMU
 549         select ARCH_REQUIRE_GPIOLIB
 550         select CLKDEV_LOOKUP
 551         select GENERIC_ALLOCATOR
 552         select GENERIC_CLOCKEVENTS
 553         select GPIO_PXA
 554         select IRQ_DOMAIN
 555         select MULTI_IRQ_HANDLER
 556         select PINCTRL
 557         select PLAT_PXA
 558         select SPARSE_IRQ
 559         help
 560           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 561
 562 config ARCH_KS8695
 563         bool "Micrel/Kendin KS8695"
 564         select ARCH_REQUIRE_GPIOLIB
 565         select CLKSRC_MMIO
 566         select CPU_ARM922T
 567         select GENERIC_CLOCKEVENTS
 568         select NEED_MACH_MEMORY_H
 569         help
 570           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 571           System-on-Chip devices.
 572
 573 config ARCH_W90X900
 574         bool "Nuvoton W90X900 CPU"
 575         select ARCH_REQUIRE_GPIOLIB
 576         select CLKDEV_LOOKUP
 577         select CLKSRC_MMIO
 578         select CPU_ARM926T
 579         select GENERIC_CLOCKEVENTS
 580         help
 581           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 582           At present, the w90x900 has been renamed nuc900, regarding
 583           the ARM series product line, you can login the following
 584           link address to know more.
 585
 586           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 587                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 588
 589 config ARCH_LPC32XX
 590         bool "NXP LPC32XX"
 591         select ARCH_REQUIRE_GPIOLIB
 592         select ARM_AMBA
 593         select CLKDEV_LOOKUP
 594         select CLKSRC_MMIO
 595         select CPU_ARM926T
 596         select GENERIC_CLOCKEVENTS
 597         select HAVE_IDE
 598         select USE_OF
 599         help
 600           Support for the NXP LPC32XX family of processors
 601
 602 config ARCH_PXA
 603         bool "PXA2xx/PXA3xx-based"
 604         depends on MMU
 605         select ARCH_MTD_XIP
 606         select ARCH_REQUIRE_GPIOLIB
 607         select ARM_CPU_SUSPEND if PM
 608         select AUTO_ZRELADDR
 609         select CLKDEV_LOOKUP
 610         select CLKSRC_MMIO
 611         select CLKSRC_OF
 612         select GENERIC_CLOCKEVENTS
 613         select GPIO_PXA
 614         select HAVE_IDE
 615         select IRQ_DOMAIN
 616         select MULTI_IRQ_HANDLER
 617         select PLAT_PXA
 618         select SPARSE_IRQ
 619         help
 620           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 621
 622 config ARCH_SHMOBILE_LEGACY
 623         bool "Renesas ARM SoCs (non-multiplatform)"
 624         select ARCH_SHMOBILE
 625         select ARM_PATCH_PHYS_VIRT if MMU
 626         select CLKDEV_LOOKUP
 627         select CPU_V7
 628         select GENERIC_CLOCKEVENTS
 629         select HAVE_ARM_SCU if SMP
 630         select HAVE_ARM_TWD if SMP
 631         select HAVE_SMP
 632         select MIGHT_HAVE_CACHE_L2X0
 633         select MULTI_IRQ_HANDLER
 634         select NO_IOPORT_MAP
 635         select PINCTRL
 636         select PM_GENERIC_DOMAINS if PM
 637         select SH_CLK_CPG
 638         select SPARSE_IRQ
 639         help
 640           Support for Renesas ARM SoC platforms using a non-multiplatform
 641           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 642           and RZ families.
 643
 644 config ARCH_RPC
 645         bool "RiscPC"
 646         select ARCH_ACORN
 647         select ARCH_MAY_HAVE_PC_FDC
 648         select ARCH_SPARSEMEM_ENABLE
 649         select ARCH_USES_GETTIMEOFFSET
 650         select CPU_SA110
 651         select FIQ
 652         select HAVE_IDE
 653         select HAVE_PATA_PLATFORM
 654         select ISA_DMA_API
 655         select NEED_MACH_IO_H
 656         select NEED_MACH_MEMORY_H
 657         select NO_IOPORT_MAP
 658         select VIRT_TO_BUS
 659         help
 660           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 661           CD-ROM interface, serial and parallel port, and the floppy drive.
 662
 663 config ARCH_SA1100
 664         bool "SA1100-based"
 665         select ARCH_MTD_XIP
 666         select ARCH_REQUIRE_GPIOLIB
 667         select ARCH_SPARSEMEM_ENABLE
 668         select CLKDEV_LOOKUP
 669         select CLKSRC_MMIO
 670         select CPU_FREQ
 671         select CPU_SA1100
 672         select GENERIC_CLOCKEVENTS
 673         select HAVE_IDE
 674         select IRQ_DOMAIN
 675         select ISA
 676         select MULTI_IRQ_HANDLER
 677         select NEED_MACH_MEMORY_H
 678         select SPARSE_IRQ
 679         help
 680           Support for StrongARM 11x0 based boards.
 681
 682 config ARCH_S3C24XX
 683         bool "Samsung S3C24XX SoCs"
 684         select ARCH_REQUIRE_GPIOLIB
 685         select ATAGS
 686         select CLKDEV_LOOKUP
 687         select CLKSRC_SAMSUNG_PWM
 688         select GENERIC_CLOCKEVENTS
 689         select GPIO_SAMSUNG
 690         select HAVE_S3C2410_I2C if I2C
 691         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 692         select HAVE_S3C_RTC if RTC_CLASS
 693         select MULTI_IRQ_HANDLER
 694         select NEED_MACH_IO_H
 695         select SAMSUNG_ATAGS
 696         help
 697           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 698           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 699           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 700           Samsung SMDK2410 development board (and derivatives).
 701
 702 config ARCH_S3C64XX
 703         bool "Samsung S3C64XX"
 704         select ARCH_REQUIRE_GPIOLIB
 705         select ARM_AMBA
 706         select ARM_VIC
 707         select ATAGS
 708         select CLKDEV_LOOKUP
 709         select CLKSRC_SAMSUNG_PWM
 710         select COMMON_CLK_SAMSUNG
 711         select CPU_V6K
 712         select GENERIC_CLOCKEVENTS
 713         select GPIO_SAMSUNG
 714         select HAVE_S3C2410_I2C if I2C
 715         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 716         select HAVE_TCM
 717         select NO_IOPORT_MAP
 718         select PLAT_SAMSUNG
 719         select PM_GENERIC_DOMAINS if PM
 720         select S3C_DEV_NAND
 721         select S3C_GPIO_TRACK
 722         select SAMSUNG_ATAGS
 723         select SAMSUNG_WAKEMASK
 724         select SAMSUNG_WDT_RESET
 725         help
 726           Samsung S3C64XX series based systems
 727
 728 config ARCH_DAVINCI
 729         bool "TI DaVinci"
 730         select ARCH_HAS_HOLES_MEMORYMODEL
 731         select ARCH_REQUIRE_GPIOLIB
 732         select CLKDEV_LOOKUP
 733         select GENERIC_ALLOCATOR
 734         select GENERIC_CLOCKEVENTS
 735         select GENERIC_IRQ_CHIP
 736         select HAVE_IDE
 737         select TI_PRIV_EDMA
 738         select USE_OF
 739         select ZONE_DMA
 740         help
 741           Support for TI's DaVinci platform.
 742
 743 config ARCH_OMAP1
 744         bool "TI OMAP1"
 745         depends on MMU
 746         select ARCH_HAS_HOLES_MEMORYMODEL
 747         select ARCH_OMAP
 748         select ARCH_REQUIRE_GPIOLIB
 749         select CLKDEV_LOOKUP
 750         select CLKSRC_MMIO
 751         select GENERIC_CLOCKEVENTS
 752         select GENERIC_IRQ_CHIP
 753         select HAVE_IDE
 754         select IRQ_DOMAIN
 755         select NEED_MACH_IO_H if PCCARD
 756         select NEED_MACH_MEMORY_H
 757         help
 758           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 759
 760 endchoice
 761
 762 menu "Multiple platform selection"
 763         depends on ARCH_MULTIPLATFORM
 764
 765 comment "CPU Core family selection"
 766
 767 config ARCH_MULTI_V4
 768         bool "ARMv4 based platforms (FA526)"
 769         depends on !ARCH_MULTI_V6_V7
 770         select ARCH_MULTI_V4_V5
 771         select CPU_FA526
 772
 773 config ARCH_MULTI_V4T
 774         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 775         depends on !ARCH_MULTI_V6_V7
 776         select ARCH_MULTI_V4_V5
 777         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 778                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 779                 CPU_ARM925T || CPU_ARM940T)
 780
 781 config ARCH_MULTI_V5
 782         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 783         depends on !ARCH_MULTI_V6_V7
 784         select ARCH_MULTI_V4_V5
 785         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 786                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 787                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 788
 789 config ARCH_MULTI_V4_V5
 790         bool
 791
 792 config ARCH_MULTI_V6
 793         bool "ARMv6 based platforms (ARM11)"
 794         select ARCH_MULTI_V6_V7
 795         select CPU_V6K
 796
 797 config ARCH_MULTI_V7
 798         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 799         default y
 800         select ARCH_MULTI_V6_V7
 801         select CPU_V7
 802         select HAVE_SMP
 803
 804 config ARCH_MULTI_V6_V7
 805         bool
 806         select MIGHT_HAVE_CACHE_L2X0
 807
 808 config ARCH_MULTI_CPU_AUTO
 809         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 810         select ARCH_MULTI_V5
 811
 812 endmenu
 813
 814 config ARCH_VIRT
 815         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 816         select ARM_AMBA
 817         select ARM_GIC
 818         select ARM_PSCI
 819         select HAVE_ARM_ARCH_TIMER
 820
 821 #
 822 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 823 # Kconfigs may be included either alphabetically (according to the
 824 # plat- suffix) or along side the corresponding mach-* source.
 825 #
 826 source "arch/arm/mach-mvebu/Kconfig"
 827
 828 source "arch/arm/mach-alpine/Kconfig"
 829
 830 source "arch/arm/mach-asm9260/Kconfig"
 831
 832 source "arch/arm/mach-at91/Kconfig"
 833
 834 source "arch/arm/mach-axxia/Kconfig"
 835
 836 source "arch/arm/mach-bcm/Kconfig"
 837
 838 source "arch/arm/mach-berlin/Kconfig"
 839
 840 source "arch/arm/mach-clps711x/Kconfig"
 841
 842 source "arch/arm/mach-cns3xxx/Kconfig"
 843
 844 source "arch/arm/mach-davinci/Kconfig"
 845
 846 source "arch/arm/mach-digicolor/Kconfig"
 847
 848 source "arch/arm/mach-dove/Kconfig"
 849
 850 source "arch/arm/mach-ep93xx/Kconfig"
 851
 852 source "arch/arm/mach-footbridge/Kconfig"
 853
 854 source "arch/arm/mach-gemini/Kconfig"
 855
 856 source "arch/arm/mach-highbank/Kconfig"
 857
 858 source "arch/arm/mach-hisi/Kconfig"
 859
 860 source "arch/arm/mach-integrator/Kconfig"
 861
 862 source "arch/arm/mach-iop32x/Kconfig"
 863
 864 source "arch/arm/mach-iop33x/Kconfig"
 865
 866 source "arch/arm/mach-iop13xx/Kconfig"
 867
 868 source "arch/arm/mach-ixp4xx/Kconfig"
 869
 870 source "arch/arm/mach-keystone/Kconfig"
 871
 872 source "arch/arm/mach-ks8695/Kconfig"
 873
 874 source "arch/arm/mach-meson/Kconfig"
 875
 876 source "arch/arm/mach-moxart/Kconfig"
 877
 878 source "arch/arm/mach-mv78xx0/Kconfig"
 879
 880 source "arch/arm/mach-imx/Kconfig"
 881
 882 source "arch/arm/mach-mediatek/Kconfig"
 883
 884 source "arch/arm/mach-mxs/Kconfig"
 885
 886 source "arch/arm/mach-netx/Kconfig"
 887
 888 source "arch/arm/mach-nomadik/Kconfig"
 889
 890 source "arch/arm/mach-nspire/Kconfig"
 891
 892 source "arch/arm/plat-omap/Kconfig"
 893
 894 source "arch/arm/mach-omap1/Kconfig"
 895
 896 source "arch/arm/mach-omap2/Kconfig"
 897
 898 source "arch/arm/mach-orion5x/Kconfig"
 899
 900 source "arch/arm/mach-picoxcell/Kconfig"
 901
 902 source "arch/arm/mach-pxa/Kconfig"
 903 source "arch/arm/plat-pxa/Kconfig"
 904
 905 source "arch/arm/mach-mmp/Kconfig"
 906
 907 source "arch/arm/mach-qcom/Kconfig"
 908
 909 source "arch/arm/mach-realview/Kconfig"
 910
 911 source "arch/arm/mach-rockchip/Kconfig"
 912
 913 source "arch/arm/mach-sa1100/Kconfig"
 914
 915 source "arch/arm/mach-socfpga/Kconfig"
 916
 917 source "arch/arm/mach-spear/Kconfig"
 918
 919 source "arch/arm/mach-sti/Kconfig"
 920
 921 source "arch/arm/mach-s3c24xx/Kconfig"
 922
 923 source "arch/arm/mach-s3c64xx/Kconfig"
 924
 925 source "arch/arm/mach-s5pv210/Kconfig"
 926
 927 source "arch/arm/mach-exynos/Kconfig"
 928 source "arch/arm/plat-samsung/Kconfig"
 929
 930 source "arch/arm/mach-shmobile/Kconfig"
 931
 932 source "arch/arm/mach-sunxi/Kconfig"
 933
 934 source "arch/arm/mach-prima2/Kconfig"
 935
 936 source "arch/arm/mach-tegra/Kconfig"
 937
 938 source "arch/arm/mach-u300/Kconfig"
 939
 940 source "arch/arm/mach-ux500/Kconfig"
 941
 942 source "arch/arm/mach-versatile/Kconfig"
 943
 944 source "arch/arm/mach-vexpress/Kconfig"
 945 source "arch/arm/plat-versatile/Kconfig"
 946
 947 source "arch/arm/mach-vt8500/Kconfig"
 948
 949 source "arch/arm/mach-w90x900/Kconfig"
 950
 951 source "arch/arm/mach-zynq/Kconfig"
 952
 953 # Definitions to make life easier
 954 config ARCH_ACORN
 955         bool
 956
 957 config PLAT_IOP
 958         bool
 959         select GENERIC_CLOCKEVENTS
 960
 961 config PLAT_ORION
 962         bool
 963         select CLKSRC_MMIO
 964         select COMMON_CLK
 965         select GENERIC_IRQ_CHIP
 966         select IRQ_DOMAIN
 967
 968 config PLAT_ORION_LEGACY
 969         bool
 970         select PLAT_ORION
 971
 972 config PLAT_PXA
 973         bool
 974
 975 config PLAT_VERSATILE
 976         bool
 977
 978 source "arch/arm/firmware/Kconfig"
 979
 980 source arch/arm/mm/Kconfig
 981
 982 config IWMMXT
 983         bool "Enable iWMMXt support"
 984         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 985         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 986         help
 987           Enable support for iWMMXt context switching at run time if
 988           running on a CPU that supports it.
 989
 990 config MULTI_IRQ_HANDLER
 991         bool
 992         help
 993           Allow each machine to specify it's own IRQ handler at run time.
 994
 995 if !MMU
 996 source "arch/arm/Kconfig-nommu"
 997 endif
 998
 999 config PJ4B_ERRATA_4742
1000         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1001         depends on CPU_PJ4B && MACH_ARMADA_370
1002         default y
1003         help
1004           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1005           Event (WFE) IDLE states, a specific timing sensitivity exists between
1006           the retiring WFI/WFE instructions and the newly issued subsequent
1007           instructions.  This sensitivity can result in a CPU hang scenario.
1008           Workaround:
1009           The software must insert either a Data Synchronization Barrier (DSB)
1010           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1011           instruction
1012
1013 config ARM_ERRATA_326103
1014         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1015         depends on CPU_V6
1016         help
1017           Executing a SWP instruction to read-only memory does not set bit 11
1018           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1019           treat the access as a read, preventing a COW from occurring and
1020           causing the faulting task to livelock.
1021
1022 config ARM_ERRATA_411920
1023         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1024         depends on CPU_V6 || CPU_V6K
1025         help
1026           Invalidation of the Instruction Cache operation can
1027           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1028           It does not affect the MPCore. This option enables the ARM Ltd.
1029           recommended workaround.
1030
1031 config ARM_ERRATA_430973
1032         bool "ARM errata: Stale prediction on replaced interworking branch"
1033         depends on CPU_V7
1034         help
1035           This option enables the workaround for the 430973 Cortex-A8
1036           r1p* erratum. If a code sequence containing an ARM/Thumb
1037           interworking branch is replaced with another code sequence at the
1038           same virtual address, whether due to self-modifying code or virtual
1039           to physical address re-mapping, Cortex-A8 does not recover from the
1040           stale interworking branch prediction. This results in Cortex-A8
1041           executing the new code sequence in the incorrect ARM or Thumb state.
1042           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1043           and also flushes the branch target cache at every context switch.
1044           Note that setting specific bits in the ACTLR register may not be
1045           available in non-secure mode.
1046
1047 config ARM_ERRATA_458693
1048         bool "ARM errata: Processor deadlock when a false hazard is created"
1049         depends on CPU_V7
1050         depends on !ARCH_MULTIPLATFORM
1051         help
1052           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1053           erratum. For very specific sequences of memory operations, it is
1054           possible for a hazard condition intended for a cache line to instead
1055           be incorrectly associated with a different cache line. This false
1056           hazard might then cause a processor deadlock. The workaround enables
1057           the L1 caching of the NEON accesses and disables the PLD instruction
1058           in the ACTLR register. Note that setting specific bits in the ACTLR
1059           register may not be available in non-secure mode.
1060
1061 config ARM_ERRATA_460075
1062         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1063         depends on CPU_V7
1064         depends on !ARCH_MULTIPLATFORM
1065         help
1066           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1067           erratum. Any asynchronous access to the L2 cache may encounter a
1068           situation in which recent store transactions to the L2 cache are lost
1069           and overwritten with stale memory contents from external memory. The
1070           workaround disables the write-allocate mode for the L2 cache via the
1071           ACTLR register. Note that setting specific bits in the ACTLR register
1072           may not be available in non-secure mode.
1073
1074 config ARM_ERRATA_742230
1075         bool "ARM errata: DMB operation may be faulty"
1076         depends on CPU_V7 && SMP
1077         depends on !ARCH_MULTIPLATFORM
1078         help
1079           This option enables the workaround for the 742230 Cortex-A9
1080           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1081           between two write operations may not ensure the correct visibility
1082           ordering of the two writes. This workaround sets a specific bit in
1083           the diagnostic register of the Cortex-A9 which causes the DMB
1084           instruction to behave as a DSB, ensuring the correct behaviour of
1085           the two writes.
1086
1087 config ARM_ERRATA_742231
1088         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1089         depends on CPU_V7 && SMP
1090         depends on !ARCH_MULTIPLATFORM
1091         help
1092           This option enables the workaround for the 742231 Cortex-A9
1093           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1094           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1095           accessing some data located in the same cache line, may get corrupted
1096           data due to bad handling of the address hazard when the line gets
1097           replaced from one of the CPUs at the same time as another CPU is
1098           accessing it. This workaround sets specific bits in the diagnostic
1099           register of the Cortex-A9 which reduces the linefill issuing
1100           capabilities of the processor.
1101
1102 config ARM_ERRATA_643719
1103         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1104         depends on CPU_V7 && SMP
1105         default y
1106         help
1107           This option enables the workaround for the 643719 Cortex-A9 (prior to
1108           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1109           register returns zero when it should return one. The workaround
1110           corrects this value, ensuring cache maintenance operations which use
1111           it behave as intended and avoiding data corruption.
1112
1113 config ARM_ERRATA_720789
1114         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1115         depends on CPU_V7
1116         help
1117           This option enables the workaround for the 720789 Cortex-A9 (prior to
1118           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1119           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1120           As a consequence of this erratum, some TLB entries which should be
1121           invalidated are not, resulting in an incoherency in the system page
1122           tables. The workaround changes the TLB flushing routines to invalidate
1123           entries regardless of the ASID.
1124
1125 config ARM_ERRATA_743622
1126         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1127         depends on CPU_V7
1128         depends on !ARCH_MULTIPLATFORM
1129         help
1130           This option enables the workaround for the 743622 Cortex-A9
1131           (r2p*) erratum. Under very rare conditions, a faulty
1132           optimisation in the Cortex-A9 Store Buffer may lead to data
1133           corruption. This workaround sets a specific bit in the diagnostic
1134           register of the Cortex-A9 which disables the Store Buffer
1135           optimisation, preventing the defect from occurring. This has no
1136           visible impact on the overall performance or power consumption of the
1137           processor.
1138
1139 config ARM_ERRATA_751472
1140         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1141         depends on CPU_V7
1142         depends on !ARCH_MULTIPLATFORM
1143         help
1144           This option enables the workaround for the 751472 Cortex-A9 (prior
1145           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1146           completion of a following broadcasted operation if the second
1147           operation is received by a CPU before the ICIALLUIS has completed,
1148           potentially leading to corrupted entries in the cache or TLB.
1149
1150 config ARM_ERRATA_754322
1151         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1152         depends on CPU_V7
1153         help
1154           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1155           r3p*) erratum. A speculative memory access may cause a page table walk
1156           which starts prior to an ASID switch but completes afterwards. This
1157           can populate the micro-TLB with a stale entry which may be hit with
1158           the new ASID. This workaround places two dsb instructions in the mm
1159           switching code so that no page table walks can cross the ASID switch.
1160
1161 config ARM_ERRATA_754327
1162         bool "ARM errata: no automatic Store Buffer drain"
1163         depends on CPU_V7 && SMP
1164         help
1165           This option enables the workaround for the 754327 Cortex-A9 (prior to
1166           r2p0) erratum. The Store Buffer does not have any automatic draining
1167           mechanism and therefore a livelock may occur if an external agent
1168           continuously polls a memory location waiting to observe an update.
1169           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1170           written polling loops from denying visibility of updates to memory.
1171
1172 config ARM_ERRATA_364296
1173         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1174         depends on CPU_V6
1175         help
1176           This options enables the workaround for the 364296 ARM1136
1177           r0p2 erratum (possible cache data corruption with
1178           hit-under-miss enabled). It sets the undocumented bit 31 in
1179           the auxiliary control register and the FI bit in the control
1180           register, thus disabling hit-under-miss without putting the
1181           processor into full low interrupt latency mode. ARM11MPCore
1182           is not affected.
1183
1184 config ARM_ERRATA_764369
1185         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1186         depends on CPU_V7 && SMP
1187         help
1188           This option enables the workaround for erratum 764369
1189           affecting Cortex-A9 MPCore with two or more processors (all
1190           current revisions). Under certain timing circumstances, a data
1191           cache line maintenance operation by MVA targeting an Inner
1192           Shareable memory region may fail to proceed up to either the
1193           Point of Coherency or to the Point of Unification of the
1194           system. This workaround adds a DSB instruction before the
1195           relevant cache maintenance functions and sets a specific bit
1196           in the diagnostic control register of the SCU.
1197
1198 config ARM_ERRATA_775420
1199        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1200        depends on CPU_V7
1201        help
1202          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1203          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1204          operation aborts with MMU exception, it might cause the processor
1205          to deadlock. This workaround puts DSB before executing ISB if
1206          an abort may occur on cache maintenance.
1207
1208 config ARM_ERRATA_798181
1209         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1210         depends on CPU_V7 && SMP
1211         help
1212           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1213           adequately shooting down all use of the old entries. This
1214           option enables the Linux kernel workaround for this erratum
1215           which sends an IPI to the CPUs that are running the same ASID
1216           as the one being invalidated.
1217
1218 config ARM_ERRATA_773022
1219         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1220         depends on CPU_V7
1221         help
1222           This option enables the workaround for the 773022 Cortex-A15
1223           (up to r0p4) erratum. In certain rare sequences of code, the
1224           loop buffer may deliver incorrect instructions. This
1225           workaround disables the loop buffer to avoid the erratum.
1226
1227 endmenu
1228
1229 source "arch/arm/common/Kconfig"
1230
1231 menu "Bus support"
1232
1233 config ISA
1234         bool
1235         help
1236           Find out whether you have ISA slots on your motherboard.  ISA is the
1237           name of a bus system, i.e. the way the CPU talks to the other stuff
1238           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1239           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1240           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1241
1242 # Select ISA DMA controller support
1243 config ISA_DMA
1244         bool
1245         select ISA_DMA_API
1246
1247 # Select ISA DMA interface
1248 config ISA_DMA_API
1249         bool
1250
1251 config PCI
1252         bool "PCI support" if MIGHT_HAVE_PCI
1253         help
1254           Find out whether you have a PCI motherboard. PCI is the name of a
1255           bus system, i.e. the way the CPU talks to the other stuff inside
1256           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1257           VESA. If you have PCI, say Y, otherwise N.
1258
1259 config PCI_DOMAINS
1260         bool
1261         depends on PCI
1262
1263 config PCI_DOMAINS_GENERIC
1264         def_bool PCI_DOMAINS
1265
1266 config PCI_NANOENGINE
1267         bool "BSE nanoEngine PCI support"
1268         depends on SA1100_NANOENGINE
1269         help
1270           Enable PCI on the BSE nanoEngine board.
1271
1272 config PCI_SYSCALL
1273         def_bool PCI
1274
1275 config PCI_HOST_ITE8152
1276         bool
1277         depends on PCI && MACH_ARMCORE
1278         default y
1279         select DMABOUNCE
1280
1281 source "drivers/pci/Kconfig"
1282 source "drivers/pci/pcie/Kconfig"
1283
1284 source "drivers/pcmcia/Kconfig"
1285
1286 endmenu
1287
1288 menu "Kernel Features"
1289
1290 config HAVE_SMP
1291         bool
1292         help
1293           This option should be selected by machines which have an SMP-
1294           capable CPU.
1295
1296           The only effect of this option is to make the SMP-related
1297           options available to the user for configuration.
1298
1299 config SMP
1300         bool "Symmetric Multi-Processing"
1301         depends on CPU_V6K || CPU_V7
1302         depends on GENERIC_CLOCKEVENTS
1303         depends on HAVE_SMP
1304         depends on MMU || ARM_MPU
1305         help
1306           This enables support for systems with more than one CPU. If you have
1307           a system with only one CPU, say N. If you have a system with more
1308           than one CPU, say Y.
1309
1310           If you say N here, the kernel will run on uni- and multiprocessor
1311           machines, but will use only one CPU of a multiprocessor machine. If
1312           you say Y here, the kernel will run on many, but not all,
1313           uniprocessor machines. On a uniprocessor machine, the kernel
1314           will run faster if you say N here.
1315
1316           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1317           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1318           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1319
1320           If you don't know what to do here, say N.
1321
1322 config SMP_ON_UP
1323         bool "Allow booting SMP kernel on uniprocessor systems"
1324         depends on SMP && !XIP_KERNEL && MMU
1325         default y
1326         help
1327           SMP kernels contain instructions which fail on non-SMP processors.
1328           Enabling this option allows the kernel to modify itself to make
1329           these instructions safe.  Disabling it allows about 1K of space
1330           savings.
1331
1332           If you don't know what to do here, say Y.
1333
1334 config ARM_CPU_TOPOLOGY
1335         bool "Support cpu topology definition"
1336         depends on SMP && CPU_V7
1337         default y
1338         help
1339           Support ARM cpu topology definition. The MPIDR register defines
1340           affinity between processors which is then used to describe the cpu
1341           topology of an ARM System.
1342
1343 config SCHED_MC
1344         bool "Multi-core scheduler support"
1345         depends on ARM_CPU_TOPOLOGY
1346         help
1347           Multi-core scheduler support improves the CPU scheduler's decision
1348           making when dealing with multi-core CPU chips at a cost of slightly
1349           increased overhead in some places. If unsure say N here.
1350
1351 config SCHED_SMT
1352         bool "SMT scheduler support"
1353         depends on ARM_CPU_TOPOLOGY
1354         help
1355           Improves the CPU scheduler's decision making when dealing with
1356           MultiThreading at a cost of slightly increased overhead in some
1357           places. If unsure say N here.
1358
1359 config HAVE_ARM_SCU
1360         bool
1361         help
1362           This option enables support for the ARM system coherency unit
1363
1364 config HAVE_ARM_ARCH_TIMER
1365         bool "Architected timer support"
1366         depends on CPU_V7
1367         select ARM_ARCH_TIMER
1368         select GENERIC_CLOCKEVENTS
1369         help
1370           This option enables support for the ARM architected timer
1371
1372 config HAVE_ARM_TWD
1373         bool
1374         depends on SMP
1375         select CLKSRC_OF if OF
1376         help
1377           This options enables support for the ARM timer and watchdog unit
1378
1379 config MCPM
1380         bool "Multi-Cluster Power Management"
1381         depends on CPU_V7 && SMP
1382         help
1383           This option provides the common power management infrastructure
1384           for (multi-)cluster based systems, such as big.LITTLE based
1385           systems.
1386
1387 config MCPM_QUAD_CLUSTER
1388         bool
1389         depends on MCPM
1390         help
1391           To avoid wasting resources unnecessarily, MCPM only supports up
1392           to 2 clusters by default.
1393           Platforms with 3 or 4 clusters that use MCPM must select this
1394           option to allow the additional clusters to be managed.
1395
1396 config BIG_LITTLE
1397         bool "big.LITTLE support (Experimental)"
1398         depends on CPU_V7 && SMP
1399         select MCPM
1400         help
1401           This option enables support selections for the big.LITTLE
1402           system architecture.
1403
1404 config BL_SWITCHER
1405         bool "big.LITTLE switcher support"
1406         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1407         select ARM_CPU_SUSPEND
1408         select CPU_PM
1409         help
1410           The big.LITTLE "switcher" provides the core functionality to
1411           transparently handle transition between a cluster of A15's
1412           and a cluster of A7's in a big.LITTLE system.
1413
1414 config BL_SWITCHER_DUMMY_IF
1415         tristate "Simple big.LITTLE switcher user interface"
1416         depends on BL_SWITCHER && DEBUG_KERNEL
1417         help
1418           This is a simple and dummy char dev interface to control
1419           the big.LITTLE switcher core code.  It is meant for
1420           debugging purposes only.
1421
1422 choice
1423         prompt "Memory split"
1424         depends on MMU
1425         default VMSPLIT_3G
1426         help
1427           Select the desired split between kernel and user memory.
1428
1429           If you are not absolutely sure what you are doing, leave this
1430           option alone!
1431
1432         config VMSPLIT_3G
1433                 bool "3G/1G user/kernel split"
1434         config VMSPLIT_2G
1435                 bool "2G/2G user/kernel split"
1436         config VMSPLIT_1G
1437                 bool "1G/3G user/kernel split"
1438 endchoice
1439
1440 config PAGE_OFFSET
1441         hex
1442         default PHYS_OFFSET if !MMU
1443         default 0x40000000 if VMSPLIT_1G
1444         default 0x80000000 if VMSPLIT_2G
1445         default 0xC0000000
1446
1447 config NR_CPUS
1448         int "Maximum number of CPUs (2-32)"
1449         range 2 32
1450         depends on SMP
1451         default "4"
1452
1453 config HOTPLUG_CPU
1454         bool "Support for hot-pluggable CPUs"
1455         depends on SMP
1456         help
1457           Say Y here to experiment with turning CPUs off and on.  CPUs
1458           can be controlled through /sys/devices/system/cpu.
1459
1460 config ARM_PSCI
1461         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1462         depends on CPU_V7
1463         help
1464           Say Y here if you want Linux to communicate with system firmware
1465           implementing the PSCI specification for CPU-centric power
1466           management operations described in ARM document number ARM DEN
1467           0022A ("Power State Coordination Interface System Software on
1468           ARM processors").
1469
1470 # The GPIO number here must be sorted by descending number. In case of
1471 # a multiplatform kernel, we just want the highest value required by the
1472 # selected platforms.
1473 config ARCH_NR_GPIO
1474         int
1475         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1476         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1477                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1478         default 416 if ARCH_SUNXI
1479         default 392 if ARCH_U8500
1480         default 352 if ARCH_VT8500
1481         default 288 if ARCH_ROCKCHIP
1482         default 264 if MACH_H4700
1483         default 0
1484         help
1485           Maximum number of GPIOs in the system.
1486
1487           If unsure, leave the default value.
1488
1489 source kernel/Kconfig.preempt
1490
1491 config HZ_FIXED
1492         int
1493         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1494                 ARCH_S5PV210 || ARCH_EXYNOS4
1495         default 128 if SOC_AT91RM9200
1496         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1497         default 0
1498
1499 choice
1500         depends on HZ_FIXED = 0
1501         prompt "Timer frequency"
1502
1503 config HZ_100
1504         bool "100 Hz"
1505
1506 config HZ_200
1507         bool "200 Hz"
1508
1509 config HZ_250
1510         bool "250 Hz"
1511
1512 config HZ_300
1513         bool "300 Hz"
1514
1515 config HZ_500
1516         bool "500 Hz"
1517
1518 config HZ_1000
1519         bool "1000 Hz"
1520
1521 endchoice
1522
1523 config HZ
1524         int
1525         default HZ_FIXED if HZ_FIXED != 0
1526         default 100 if HZ_100
1527         default 200 if HZ_200
1528         default 250 if HZ_250
1529         default 300 if HZ_300
1530         default 500 if HZ_500
1531         default 1000
1532
1533 config SCHED_HRTICK
1534         def_bool HIGH_RES_TIMERS
1535
1536 config THUMB2_KERNEL
1537         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1538         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1539         default y if CPU_THUMBONLY
1540         select AEABI
1541         select ARM_ASM_UNIFIED
1542         select ARM_UNWIND
1543         help
1544           By enabling this option, the kernel will be compiled in
1545           Thumb-2 mode. A compiler/assembler that understand the unified
1546           ARM-Thumb syntax is needed.
1547
1548           If unsure, say N.
1549
1550 config THUMB2_AVOID_R_ARM_THM_JUMP11
1551         bool "Work around buggy Thumb-2 short branch relocations in gas"
1552         depends on THUMB2_KERNEL && MODULES
1553         default y
1554         help
1555           Various binutils versions can resolve Thumb-2 branches to
1556           locally-defined, preemptible global symbols as short-range "b.n"
1557           branch instructions.
1558
1559           This is a problem, because there's no guarantee the final
1560           destination of the symbol, or any candidate locations for a
1561           trampoline, are within range of the branch.  For this reason, the
1562           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1563           relocation in modules at all, and it makes little sense to add
1564           support.
1565
1566           The symptom is that the kernel fails with an "unsupported
1567           relocation" error when loading some modules.
1568
1569           Until fixed tools are available, passing
1570           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1571           code which hits this problem, at the cost of a bit of extra runtime
1572           stack usage in some cases.
1573
1574           The problem is described in more detail at:
1575               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1576
1577           Only Thumb-2 kernels are affected.
1578
1579           Unless you are sure your tools don't have this problem, say Y.
1580
1581 config ARM_ASM_UNIFIED
1582         bool
1583
1584 config AEABI
1585         bool "Use the ARM EABI to compile the kernel"
1586         help
1587           This option allows for the kernel to be compiled using the latest
1588           ARM ABI (aka EABI).  This is only useful if you are using a user
1589           space environment that is also compiled with EABI.
1590
1591           Since there are major incompatibilities between the legacy ABI and
1592           EABI, especially with regard to structure member alignment, this
1593           option also changes the kernel syscall calling convention to
1594           disambiguate both ABIs and allow for backward compatibility support
1595           (selected with CONFIG_OABI_COMPAT).
1596
1597           To use this you need GCC version 4.0.0 or later.
1598
1599 config OABI_COMPAT
1600         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1601         depends on AEABI && !THUMB2_KERNEL
1602         help
1603           This option preserves the old syscall interface along with the
1604           new (ARM EABI) one. It also provides a compatibility layer to
1605           intercept syscalls that have structure arguments which layout
1606           in memory differs between the legacy ABI and the new ARM EABI
1607           (only for non "thumb" binaries). This option adds a tiny
1608           overhead to all syscalls and produces a slightly larger kernel.
1609
1610           The seccomp filter system will not be available when this is
1611           selected, since there is no way yet to sensibly distinguish
1612           between calling conventions during filtering.
1613
1614           If you know you'll be using only pure EABI user space then you
1615           can say N here. If this option is not selected and you attempt
1616           to execute a legacy ABI binary then the result will be
1617           UNPREDICTABLE (in fact it can be predicted that it won't work
1618           at all). If in doubt say N.
1619
1620 config ARCH_HAS_HOLES_MEMORYMODEL
1621         bool
1622
1623 config ARCH_SPARSEMEM_ENABLE
1624         bool
1625
1626 config ARCH_SPARSEMEM_DEFAULT
1627         def_bool ARCH_SPARSEMEM_ENABLE
1628
1629 config ARCH_SELECT_MEMORY_MODEL
1630         def_bool ARCH_SPARSEMEM_ENABLE
1631
1632 config HAVE_ARCH_PFN_VALID
1633         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1634
1635 config HAVE_GENERIC_RCU_GUP
1636         def_bool y
1637         depends on ARM_LPAE
1638
1639 config HIGHMEM
1640         bool "High Memory Support"
1641         depends on MMU
1642         help
1643           The address space of ARM processors is only 4 Gigabytes large
1644           and it has to accommodate user address space, kernel address
1645           space as well as some memory mapped IO. That means that, if you
1646           have a large amount of physical memory and/or IO, not all of the
1647           memory can be "permanently mapped" by the kernel. The physical
1648           memory that is not permanently mapped is called "high memory".
1649
1650           Depending on the selected kernel/user memory split, minimum
1651           vmalloc space and actual amount of RAM, you may not need this
1652           option which should result in a slightly faster kernel.
1653
1654           If unsure, say n.
1655
1656 config HIGHPTE
1657         bool "Allocate 2nd-level pagetables from highmem"
1658         depends on HIGHMEM
1659
1660 config HW_PERF_EVENTS
1661         bool "Enable hardware performance counter support for perf events"
1662         depends on PERF_EVENTS
1663         default y
1664         help
1665           Enable hardware performance counter support for perf events. If
1666           disabled, perf events will use software events only.
1667
1668 config SYS_SUPPORTS_HUGETLBFS
1669        def_bool y
1670        depends on ARM_LPAE
1671
1672 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1673        def_bool y
1674        depends on ARM_LPAE
1675
1676 config ARCH_WANT_GENERAL_HUGETLB
1677         def_bool y
1678
1679 config ARM_MODULE_PLTS
1680         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1681         depends on MODULES
1682         help
1683           Allocate PLTs when loading modules so that jumps and calls whose
1684           targets are too far away for their relative offsets to be encoded
1685           in the instructions themselves can be bounced via veneers in the
1686           module's PLT. This allows modules to be allocated in the generic
1687           vmalloc area after the dedicated module memory area has been
1688           exhausted. The modules will use slightly more memory, but after
1689           rounding up to page size, the actual memory footprint is usually
1690           the same.
1691
1692           Say y if you are getting out of memory errors while loading modules
1693
1694 source "mm/Kconfig"
1695
1696 config FORCE_MAX_ZONEORDER
1697         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1698         range 11 64 if ARCH_SHMOBILE_LEGACY
1699         default "12" if SOC_AM33XX
1700         default "9" if SA1111 || ARCH_EFM32
1701         default "11"
1702         help
1703           The kernel memory allocator divides physically contiguous memory
1704           blocks into "zones", where each zone is a power of two number of
1705           pages.  This option selects the largest power of two that the kernel
1706           keeps in the memory allocator.  If you need to allocate very large
1707           blocks of physically contiguous memory, then you may need to
1708           increase this value.
1709
1710           This config option is actually maximum order plus one. For example,
1711           a value of 11 means that the largest free memory block is 2^10 pages.
1712
1713 config ALIGNMENT_TRAP
1714         bool
1715         depends on CPU_CP15_MMU
1716         default y if !ARCH_EBSA110
1717         select HAVE_PROC_CPU if PROC_FS
1718         help
1719           ARM processors cannot fetch/store information which is not
1720           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1721           address divisible by 4. On 32-bit ARM processors, these non-aligned
1722           fetch/store instructions will be emulated in software if you say
1723           here, which has a severe performance impact. This is necessary for
1724           correct operation of some network protocols. With an IP-only
1725           configuration it is safe to say N, otherwise say Y.
1726
1727 config UACCESS_WITH_MEMCPY
1728         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1729         depends on MMU
1730         default y if CPU_FEROCEON
1731         help
1732           Implement faster copy_to_user and clear_user methods for CPU
1733           cores where a 8-word STM instruction give significantly higher
1734           memory write throughput than a sequence of individual 32bit stores.
1735
1736           A possible side effect is a slight increase in scheduling latency
1737           between threads sharing the same address space if they invoke
1738           such copy operations with large buffers.
1739
1740           However, if the CPU data cache is using a write-allocate mode,
1741           this option is unlikely to provide any performance gain.
1742
1743 config SECCOMP
1744         bool
1745         prompt "Enable seccomp to safely compute untrusted bytecode"
1746         ---help---
1747           This kernel feature is useful for number crunching applications
1748           that may need to compute untrusted bytecode during their
1749           execution. By using pipes or other transports made available to
1750           the process as file descriptors supporting the read/write
1751           syscalls, it's possible to isolate those applications in
1752           their own address space using seccomp. Once seccomp is
1753           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1754           and the task is only allowed to execute a few safe syscalls
1755           defined by each seccomp mode.
1756
1757 config SWIOTLB
1758         def_bool y
1759
1760 config IOMMU_HELPER
1761         def_bool SWIOTLB
1762
1763 config XEN_DOM0
1764         def_bool y
1765         depends on XEN
1766
1767 config XEN
1768         bool "Xen guest support on ARM"
1769         depends on ARM && AEABI && OF
1770         depends on CPU_V7 && !CPU_V6
1771         depends on !GENERIC_ATOMIC64
1772         depends on MMU
1773         select ARCH_DMA_ADDR_T_64BIT
1774         select ARM_PSCI
1775         select SWIOTLB_XEN
1776         help
1777           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1778
1779 endmenu
1780
1781 menu "Boot options"
1782
1783 config USE_OF
1784         bool "Flattened Device Tree support"
1785         select IRQ_DOMAIN
1786         select OF
1787         select OF_EARLY_FLATTREE
1788         select OF_RESERVED_MEM
1789         help
1790           Include support for flattened device tree machine descriptions.
1791
1792 config ATAGS
1793         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1794         default y
1795         help
1796           This is the traditional way of passing data to the kernel at boot
1797           time. If you are solely relying on the flattened device tree (or
1798           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1799           to remove ATAGS support from your kernel binary.  If unsure,
1800           leave this to y.
1801
1802 config DEPRECATED_PARAM_STRUCT
1803         bool "Provide old way to pass kernel parameters"
1804         depends on ATAGS
1805         help
1806           This was deprecated in 2001 and announced to live on for 5 years.
1807           Some old boot loaders still use this way.
1808
1809 # Compressed boot loader in ROM.  Yes, we really want to ask about
1810 # TEXT and BSS so we preserve their values in the config files.
1811 config ZBOOT_ROM_TEXT
1812         hex "Compressed ROM boot loader base address"
1813         default "0"
1814         help
1815           The physical address at which the ROM-able zImage is to be
1816           placed in the target.  Platforms which normally make use of
1817           ROM-able zImage formats normally set this to a suitable
1818           value in their defconfig file.
1819
1820           If ZBOOT_ROM is not enabled, this has no effect.
1821
1822 config ZBOOT_ROM_BSS
1823         hex "Compressed ROM boot loader BSS address"
1824         default "0"
1825         help
1826           The base address of an area of read/write memory in the target
1827           for the ROM-able zImage which must be available while the
1828           decompressor is running. It must be large enough to hold the
1829           entire decompressed kernel plus an additional 128 KiB.
1830           Platforms which normally make use of ROM-able zImage formats
1831           normally set this to a suitable value in their defconfig file.
1832
1833           If ZBOOT_ROM is not enabled, this has no effect.
1834
1835 config ZBOOT_ROM
1836         bool "Compressed boot loader in ROM/flash"
1837         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1838         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1839         help
1840           Say Y here if you intend to execute your compressed kernel image
1841           (zImage) directly from ROM or flash.  If unsure, say N.
1842
1843 config ARM_APPENDED_DTB
1844         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1845         depends on OF
1846         help
1847           With this option, the boot code will look for a device tree binary
1848           (DTB) appended to zImage
1849           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1850
1851           This is meant as a backward compatibility convenience for those
1852           systems with a bootloader that can't be upgraded to accommodate
1853           the documented boot protocol using a device tree.
1854
1855           Beware that there is very little in terms of protection against
1856           this option being confused by leftover garbage in memory that might
1857           look like a DTB header after a reboot if no actual DTB is appended
1858           to zImage.  Do not leave this option active in a production kernel
1859           if you don't intend to always append a DTB.  Proper passing of the
1860           location into r2 of a bootloader provided DTB is always preferable
1861           to this option.
1862
1863 config ARM_ATAG_DTB_COMPAT
1864         bool "Supplement the appended DTB with traditional ATAG information"
1865         depends on ARM_APPENDED_DTB
1866         help
1867           Some old bootloaders can't be updated to a DTB capable one, yet
1868           they provide ATAGs with memory configuration, the ramdisk address,
1869           the kernel cmdline string, etc.  Such information is dynamically
1870           provided by the bootloader and can't always be stored in a static
1871           DTB.  To allow a device tree enabled kernel to be used with such
1872           bootloaders, this option allows zImage to extract the information
1873           from the ATAG list and store it at run time into the appended DTB.
1874
1875 choice
1876         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1877         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1878
1879 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1880         bool "Use bootloader kernel arguments if available"
1881         help
1882           Uses the command-line options passed by the boot loader instead of
1883           the device tree bootargs property. If the boot loader doesn't provide
1884           any, the device tree bootargs property will be used.
1885
1886 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1887         bool "Extend with bootloader kernel arguments"
1888         help
1889           The command-line arguments provided by the boot loader will be
1890           appended to the the device tree bootargs property.
1891
1892 endchoice
1893
1894 config CMDLINE
1895         string "Default kernel command string"
1896         default ""
1897         help
1898           On some architectures (EBSA110 and CATS), there is currently no way
1899           for the boot loader to pass arguments to the kernel. For these
1900           architectures, you should supply some command-line options at build
1901           time by entering them here. As a minimum, you should specify the
1902           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1903
1904 choice
1905         prompt "Kernel command line type" if CMDLINE != ""
1906         default CMDLINE_FROM_BOOTLOADER
1907         depends on ATAGS
1908
1909 config CMDLINE_FROM_BOOTLOADER
1910         bool "Use bootloader kernel arguments if available"
1911         help
1912           Uses the command-line options passed by the boot loader. If
1913           the boot loader doesn't provide any, the default kernel command
1914           string provided in CMDLINE will be used.
1915
1916 config CMDLINE_EXTEND
1917         bool "Extend bootloader kernel arguments"
1918         help
1919           The command-line arguments provided by the boot loader will be
1920           appended to the default kernel command string.
1921
1922 config CMDLINE_FORCE
1923         bool "Always use the default kernel command string"
1924         help
1925           Always use the default kernel command string, even if the boot
1926           loader passes other arguments to the kernel.
1927           This is useful if you cannot or don't want to change the
1928           command-line options your boot loader passes to the kernel.
1929 endchoice
1930
1931 config XIP_KERNEL
1932         bool "Kernel Execute-In-Place from ROM"
1933         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1934         help
1935           Execute-In-Place allows the kernel to run from non-volatile storage
1936           directly addressable by the CPU, such as NOR flash. This saves RAM
1937           space since the text section of the kernel is not loaded from flash
1938           to RAM.  Read-write sections, such as the data section and stack,
1939           are still copied to RAM.  The XIP kernel is not compressed since
1940           it has to run directly from flash, so it will take more space to
1941           store it.  The flash address used to link the kernel object files,
1942           and for storing it, is configuration dependent. Therefore, if you
1943           say Y here, you must know the proper physical address where to
1944           store the kernel image depending on your own flash memory usage.
1945
1946           Also note that the make target becomes "make xipImage" rather than
1947           "make zImage" or "make Image".  The final kernel binary to put in
1948           ROM memory will be arch/arm/boot/xipImage.
1949
1950           If unsure, say N.
1951
1952 config XIP_PHYS_ADDR
1953         hex "XIP Kernel Physical Location"
1954         depends on XIP_KERNEL
1955         default "0x00080000"
1956         help
1957           This is the physical address in your flash memory the kernel will
1958           be linked for and stored to.  This address is dependent on your
1959           own flash usage.
1960
1961 config KEXEC
1962         bool "Kexec system call (EXPERIMENTAL)"
1963         depends on (!SMP || PM_SLEEP_SMP)
1964         help
1965           kexec is a system call that implements the ability to shutdown your
1966           current kernel, and to start another kernel.  It is like a reboot
1967           but it is independent of the system firmware.   And like a reboot
1968           you can start any kernel with it, not just Linux.
1969
1970           It is an ongoing process to be certain the hardware in a machine
1971           is properly shutdown, so do not be surprised if this code does not
1972           initially work for you.
1973
1974 config ATAGS_PROC
1975         bool "Export atags in procfs"
1976         depends on ATAGS && KEXEC
1977         default y
1978         help
1979           Should the atags used to boot the kernel be exported in an "atags"
1980           file in procfs. Useful with kexec.
1981
1982 config CRASH_DUMP
1983         bool "Build kdump crash kernel (EXPERIMENTAL)"
1984         help
1985           Generate crash dump after being started by kexec. This should
1986           be normally only set in special crash dump kernels which are
1987           loaded in the main kernel with kexec-tools into a specially
1988           reserved region and then later executed after a crash by
1989           kdump/kexec. The crash dump kernel must be compiled to a
1990           memory address not used by the main kernel
1991
1992           For more details see Documentation/kdump/kdump.txt
1993
1994 config AUTO_ZRELADDR
1995         bool "Auto calculation of the decompressed kernel image address"
1996         help
1997           ZRELADDR is the physical address where the decompressed kernel
1998           image will be placed. If AUTO_ZRELADDR is selected, the address
1999           will be determined at run-time by masking the current IP with
2000           0xf8000000. This assumes the zImage being placed in the first 128MB
2001           from start of memory.
2002
2003 endmenu
2004
2005 menu "CPU Power Management"
2006
2007 source "drivers/cpufreq/Kconfig"
2008
2009 source "drivers/cpuidle/Kconfig"
2010
2011 endmenu
2012
2013 menu "Floating point emulation"
2014
2015 comment "At least one emulation must be selected"
2016
2017 config FPE_NWFPE
2018         bool "NWFPE math emulation"
2019         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2020         ---help---
2021           Say Y to include the NWFPE floating point emulator in the kernel.
2022           This is necessary to run most binaries. Linux does not currently
2023           support floating point hardware so you need to say Y here even if
2024           your machine has an FPA or floating point co-processor podule.
2025
2026           You may say N here if you are going to load the Acorn FPEmulator
2027           early in the bootup.
2028
2029 config FPE_NWFPE_XP
2030         bool "Support extended precision"
2031         depends on FPE_NWFPE
2032         help
2033           Say Y to include 80-bit support in the kernel floating-point
2034           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2035           Note that gcc does not generate 80-bit operations by default,
2036           so in most cases this option only enlarges the size of the
2037           floating point emulator without any good reason.
2038
2039           You almost surely want to say N here.
2040
2041 config FPE_FASTFPE
2042         bool "FastFPE math emulation (EXPERIMENTAL)"
2043         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2044         ---help---
2045           Say Y here to include the FAST floating point emulator in the kernel.
2046           This is an experimental much faster emulator which now also has full
2047           precision for the mantissa.  It does not support any exceptions.
2048           It is very simple, and approximately 3-6 times faster than NWFPE.
2049
2050           It should be sufficient for most programs.  It may be not suitable
2051           for scientific calculations, but you have to check this for yourself.
2052           If you do not feel you need a faster FP emulation you should better
2053           choose NWFPE.
2054
2055 config VFP
2056         bool "VFP-format floating point maths"
2057         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2058         help
2059           Say Y to include VFP support code in the kernel. This is needed
2060           if your hardware includes a VFP unit.
2061
2062           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2063           release notes and additional status information.
2064
2065           Say N if your target does not have VFP hardware.
2066
2067 config VFPv3
2068         bool
2069         depends on VFP
2070         default y if CPU_V7
2071
2072 config NEON
2073         bool "Advanced SIMD (NEON) Extension support"
2074         depends on VFPv3 && CPU_V7
2075         help
2076           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2077           Extension.
2078
2079 config KERNEL_MODE_NEON
2080         bool "Support for NEON in kernel mode"
2081         depends on NEON && AEABI
2082         help
2083           Say Y to include support for NEON in kernel mode.
2084
2085 endmenu
2086
2087 menu "Userspace binary formats"
2088
2089 source "fs/Kconfig.binfmt"
2090
2091 endmenu
2092
2093 menu "Power management options"
2094
2095 source "kernel/power/Kconfig"
2096
2097 config ARCH_SUSPEND_POSSIBLE
2098         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2099                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2100         def_bool y
2101
2102 config ARM_CPU_SUSPEND
2103         def_bool PM_SLEEP
2104
2105 config ARCH_HIBERNATION_POSSIBLE
2106         bool
2107         depends on MMU
2108         default y if ARCH_SUSPEND_POSSIBLE
2109
2110 endmenu
2111
2112 source "net/Kconfig"
2113
2114 source "drivers/Kconfig"
2115
2116 source "drivers/firmware/Kconfig"
2117
2118 source "fs/Kconfig"
2119
2120 source "arch/arm/Kconfig.debug"
2121
2122 source "security/Kconfig"
2123
2124 source "crypto/Kconfig"
2125 if CRYPTO
2126 source "arch/arm/crypto/Kconfig"
2127 endif
2128
2129 source "lib/Kconfig"
2130
2131 source "arch/arm/kvm/Kconfig"