4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
63 select HAVE_CONTEXT_TRACKING
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
75 config NEED_SG_DMA_LENGTH
78 config ARM_DMA_USE_IOMMU
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
107 config MIGHT_HAVE_PCI
110 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_HAS_DMA_SET_COHERENT_MASK
201 config GENERIC_ISA_DMA
207 config NEED_RET_TO_USER
215 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
216 default DRAM_BASE if REMAP_VECTORS_TO_RAM
219 The base address of exception vectors.
221 config ARM_PATCH_PHYS_VIRT
222 bool "Patch physical to virtual translations at runtime" if EMBEDDED
224 depends on !XIP_KERNEL && MMU
225 depends on !ARCH_REALVIEW || !SPARSEMEM
227 Patch phys-to-virt and virt-to-phys translation functions at
228 boot and module load time according to the position of the
229 kernel in system memory.
231 This can only be used with non-XIP MMU kernels where the base
232 of physical memory is at a 16MB boundary.
234 Only disable this option if you know that you do not require
235 this feature (eg, building a kernel for a single machine) and
236 you need to shrink the kernel to the minimal size.
238 config NEED_MACH_GPIO_H
241 Select this when mach/gpio.h is required to provide special
242 definitions for this platform. The need for mach/gpio.h should
243 be avoided when possible.
245 config NEED_MACH_IO_H
248 Select this when mach/io.h is required to provide special
249 definitions for this platform. The need for mach/io.h should
250 be avoided when possible.
252 config NEED_MACH_MEMORY_H
255 Select this when mach/memory.h is required to provide special
256 definitions for this platform. The need for mach/memory.h should
257 be avoided when possible.
260 hex "Physical address of main memory" if MMU
261 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
262 default DRAM_BASE if !MMU
264 Please provide the physical address corresponding to the
265 location of main memory in your system.
271 source "init/Kconfig"
273 source "kernel/Kconfig.freezer"
278 bool "MMU-based Paged Memory Management Support"
281 Select if you want MMU-based virtualised addressing space
282 support by paged memory management. If unsure, say 'Y'.
285 # The "ARM system type" choice list is ordered alphabetically by option
286 # text. Please add new entries in the option alphabetic order.
289 prompt "ARM system type"
290 default ARCH_VERSATILE if !MMU
291 default ARCH_MULTIPLATFORM if MMU
293 config ARCH_MULTIPLATFORM
294 bool "Allow multiple platforms to be selected"
296 select ARM_PATCH_PHYS_VIRT
299 select MULTI_IRQ_HANDLER
303 config ARCH_INTEGRATOR
304 bool "ARM Ltd. Integrator family"
305 select ARCH_HAS_CPUFREQ
308 select COMMON_CLK_VERSATILE
309 select GENERIC_CLOCKEVENTS
312 select MULTI_IRQ_HANDLER
313 select NEED_MACH_MEMORY_H
314 select PLAT_VERSATILE
316 select VERSATILE_FPGA_IRQ
318 Support for ARM's Integrator platform.
321 bool "ARM Ltd. RealView family"
322 select ARCH_WANT_OPTIONAL_GPIOLIB
324 select ARM_TIMER_SP804
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
328 select GPIO_PL061 if GPIOLIB
330 select NEED_MACH_MEMORY_H
331 select PLAT_VERSATILE
332 select PLAT_VERSATILE_CLCD
334 This enables support for ARM Ltd RealView boards.
336 config ARCH_VERSATILE
337 bool "ARM Ltd. Versatile family"
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_TIMER_SP804
343 select GENERIC_CLOCKEVENTS
344 select HAVE_MACH_CLKDEV
346 select PLAT_VERSATILE
347 select PLAT_VERSATILE_CLCD
348 select PLAT_VERSATILE_CLOCK
349 select VERSATILE_FPGA_IRQ
351 This enables support for ARM Ltd Versatile board.
355 select ARCH_REQUIRE_GPIOLIB
359 select NEED_MACH_GPIO_H
360 select NEED_MACH_IO_H if PCCARD
362 select PINCTRL_AT91 if USE_OF
364 This enables support for systems based on Atmel
365 AT91RM9200 and AT91SAM9* processors.
368 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
369 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
377 select MULTI_IRQ_HANDLER
380 Support for Cirrus Logic 711x/721x/731x based boards.
383 bool "Cortina Systems Gemini"
384 select ARCH_REQUIRE_GPIOLIB
385 select ARCH_USES_GETTIMEOFFSET
386 select NEED_MACH_GPIO_H
389 Support for the Cortina Systems Gemini family SoCs
393 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_IO_H
397 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
407 select ARCH_HAS_HOLES_MEMORYMODEL
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_MEMORY_H
416 This enables support for the Cirrus EP93xx series of CPUs.
418 config ARCH_FOOTBRIDGE
422 select GENERIC_CLOCKEVENTS
424 select NEED_MACH_IO_H if !MMU
425 select NEED_MACH_MEMORY_H
427 Support for systems based on the DC21285 companion chip
428 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
431 bool "Hilscher NetX based"
435 select GENERIC_CLOCKEVENTS
437 This enables support for systems based on the Hilscher NetX Soc
442 select ARCH_SUPPORTS_MSI
444 select NEED_MACH_MEMORY_H
445 select NEED_RET_TO_USER
450 Support for Intel's IOP13XX (XScale) family of processors.
455 select ARCH_REQUIRE_GPIOLIB
457 select NEED_MACH_GPIO_H
458 select NEED_RET_TO_USER
462 Support for Intel's 80219 and IOP32X (XScale) family of
468 select ARCH_REQUIRE_GPIOLIB
470 select NEED_MACH_GPIO_H
471 select NEED_RET_TO_USER
475 Support for Intel's IOP33X (XScale) family of processors.
480 select ARCH_HAS_DMA_SET_COHERENT_MASK
481 select ARCH_REQUIRE_GPIOLIB
484 select DMABOUNCE if PCI
485 select GENERIC_CLOCKEVENTS
486 select MIGHT_HAVE_PCI
487 select NEED_MACH_IO_H
488 select USB_EHCI_BIG_ENDIAN_MMIO
489 select USB_EHCI_BIG_ENDIAN_DESC
491 Support for Intel's IXP4XX (XScale) family of processors.
495 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
498 select MIGHT_HAVE_PCI
501 select PLAT_ORION_LEGACY
502 select USB_ARCH_HAS_EHCI
505 Support for the Marvell Dove SoC 88AP510
508 bool "Marvell Kirkwood"
509 select ARCH_HAS_CPUFREQ
510 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
516 select PINCTRL_KIRKWOOD
517 select PLAT_ORION_LEGACY
520 Support for the following Marvell Kirkwood series SoCs:
521 88F6180, 88F6192 and 88F6281.
524 bool "Marvell MV78xx0"
525 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
529 select PLAT_ORION_LEGACY
532 Support for the following Marvell MV78xx0 series SoCs:
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
542 select PLAT_ORION_LEGACY
545 Support for the following Marvell Orion 5x series SoCs:
546 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
547 Orion-2 (5281), Orion-1-90 (6183).
550 bool "Marvell PXA168/910/MMP2"
552 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_ALLOCATOR
555 select GENERIC_CLOCKEVENTS
558 select NEED_MACH_GPIO_H
563 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
566 bool "Micrel/Kendin KS8695"
567 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
571 select NEED_MACH_MEMORY_H
573 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
574 System-on-Chip devices.
577 bool "Nuvoton W90X900 CPU"
578 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
584 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
585 At present, the w90x900 has been renamed nuc900, regarding
586 the ARM series product line, you can login the following
587 link address to know more.
589 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
590 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
594 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
602 select USB_ARCH_HAS_OHCI
605 Support for the NXP LPC32XX family of processors
608 bool "PXA2xx/PXA3xx-based"
610 select ARCH_HAS_CPUFREQ
612 select ARCH_REQUIRE_GPIOLIB
613 select ARM_CPU_SUSPEND if PM
617 select GENERIC_CLOCKEVENTS
620 select MULTI_IRQ_HANDLER
621 select NEED_MACH_GPIO_H
625 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
629 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
634 Support for Qualcomm MSM/QSD based systems. This runs on the
635 apps processor of the MSM/QSD and depends on a shared memory
636 interface to the modem processor which runs the baseband
637 stack and controls some vital subsystems
638 (clock and power control, etc).
641 bool "Renesas SH-Mobile / R-Mobile"
642 select ARM_PATCH_PHYS_VIRT
644 select GENERIC_CLOCKEVENTS
645 select HAVE_ARM_SCU if SMP
646 select HAVE_ARM_TWD if LOCAL_TIMERS
648 select HAVE_MACH_CLKDEV
650 select MIGHT_HAVE_CACHE_L2X0
651 select MULTI_IRQ_HANDLER
654 select PM_GENERIC_DOMAINS if PM
657 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
662 select ARCH_MAY_HAVE_PC_FDC
663 select ARCH_SPARSEMEM_ENABLE
664 select ARCH_USES_GETTIMEOFFSET
667 select HAVE_PATA_PLATFORM
669 select NEED_MACH_IO_H
670 select NEED_MACH_MEMORY_H
674 On the Acorn Risc-PC, Linux can support the internal IDE disk and
675 CD-ROM interface, serial and parallel port, and the floppy drive.
679 select ARCH_HAS_CPUFREQ
681 select ARCH_REQUIRE_GPIOLIB
682 select ARCH_SPARSEMEM_ENABLE
687 select GENERIC_CLOCKEVENTS
690 select NEED_MACH_GPIO_H
691 select NEED_MACH_MEMORY_H
694 Support for StrongARM 11x0 based boards.
697 bool "Samsung S3C24XX SoCs"
698 select ARCH_HAS_CPUFREQ
699 select ARCH_REQUIRE_GPIOLIB
702 select GENERIC_CLOCKEVENTS
705 select HAVE_S3C2410_I2C if I2C
706 select HAVE_S3C2410_WATCHDOG if WATCHDOG
707 select HAVE_S3C_RTC if RTC_CLASS
708 select MULTI_IRQ_HANDLER
709 select NEED_MACH_GPIO_H
710 select NEED_MACH_IO_H
713 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
714 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
715 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
716 Samsung SMDK2410 development board (and derivatives).
719 bool "Samsung S3C64XX"
720 select ARCH_HAS_CPUFREQ
721 select ARCH_REQUIRE_GPIOLIB
726 select GENERIC_CLOCKEVENTS
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
732 select NEED_MACH_GPIO_H
736 select S3C_GPIO_TRACK
738 select SAMSUNG_CLKSRC
739 select SAMSUNG_GPIOLIB_4BIT
740 select SAMSUNG_IRQ_VIC_TIMER
741 select SAMSUNG_WDT_RESET
742 select USB_ARCH_HAS_OHCI
744 Samsung S3C64XX series based systems
747 bool "Samsung S5P6440 S5P6450"
751 select GENERIC_CLOCKEVENTS
754 select HAVE_S3C2410_I2C if I2C
755 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 select HAVE_S3C_RTC if RTC_CLASS
757 select NEED_MACH_GPIO_H
758 select SAMSUNG_WDT_RESET
761 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
765 bool "Samsung S5PC100"
766 select ARCH_REQUIRE_GPIOLIB
770 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select HAVE_S3C_RTC if RTC_CLASS
776 select NEED_MACH_GPIO_H
777 select SAMSUNG_WDT_RESET
780 Samsung S5PC100 series based systems
783 bool "Samsung S5PV210/S5PC110"
784 select ARCH_HAS_CPUFREQ
785 select ARCH_HAS_HOLES_MEMORYMODEL
786 select ARCH_SPARSEMEM_ENABLE
790 select GENERIC_CLOCKEVENTS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
797 select NEED_MACH_MEMORY_H
800 Samsung S5PV210/S5PC110 series based systems
803 bool "Samsung EXYNOS"
804 select ARCH_HAS_CPUFREQ
805 select ARCH_HAS_HOLES_MEMORYMODEL
806 select ARCH_REQUIRE_GPIOLIB
807 select ARCH_SPARSEMEM_ENABLE
812 select GENERIC_CLOCKEVENTS
814 select HAVE_S3C2410_I2C if I2C
815 select HAVE_S3C2410_WATCHDOG if WATCHDOG
816 select HAVE_S3C_RTC if RTC_CLASS
817 select NEED_MACH_MEMORY_H
821 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
825 select ARCH_USES_GETTIMEOFFSET
829 select NEED_MACH_MEMORY_H
834 Support for the StrongARM based Digital DNARD machine, also known
835 as "Shark" (<http://www.shark-linux.de/shark.html>).
839 select ARCH_HAS_HOLES_MEMORYMODEL
840 select ARCH_REQUIRE_GPIOLIB
842 select GENERIC_ALLOCATOR
843 select GENERIC_CLOCKEVENTS
844 select GENERIC_IRQ_CHIP
846 select NEED_MACH_GPIO_H
851 Support for TI's DaVinci platform.
856 select ARCH_HAS_CPUFREQ
857 select ARCH_HAS_HOLES_MEMORYMODEL
859 select ARCH_REQUIRE_GPIOLIB
862 select GENERIC_CLOCKEVENTS
863 select GENERIC_IRQ_CHIP
867 select NEED_MACH_IO_H if PCCARD
868 select NEED_MACH_MEMORY_H
870 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
874 menu "Multiple platform selection"
875 depends on ARCH_MULTIPLATFORM
877 comment "CPU Core family selection"
879 config ARCH_MULTI_V4T
880 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
881 depends on !ARCH_MULTI_V6_V7
882 select ARCH_MULTI_V4_V5
883 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
884 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
885 CPU_ARM925T || CPU_ARM940T)
888 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
891 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
892 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
893 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
895 config ARCH_MULTI_V4_V5
899 bool "ARMv6 based platforms (ARM11)"
900 select ARCH_MULTI_V6_V7
904 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
906 select ARCH_MULTI_V6_V7
909 config ARCH_MULTI_V6_V7
912 config ARCH_MULTI_CPU_AUTO
913 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
919 # This is sorted alphabetically by mach-* pathname. However, plat-*
920 # Kconfigs may be included either alphabetically (according to the
921 # plat- suffix) or along side the corresponding mach-* source.
923 source "arch/arm/mach-mvebu/Kconfig"
925 source "arch/arm/mach-at91/Kconfig"
927 source "arch/arm/mach-bcm/Kconfig"
929 source "arch/arm/mach-bcm2835/Kconfig"
931 source "arch/arm/mach-clps711x/Kconfig"
933 source "arch/arm/mach-cns3xxx/Kconfig"
935 source "arch/arm/mach-davinci/Kconfig"
937 source "arch/arm/mach-dove/Kconfig"
939 source "arch/arm/mach-ep93xx/Kconfig"
941 source "arch/arm/mach-footbridge/Kconfig"
943 source "arch/arm/mach-gemini/Kconfig"
945 source "arch/arm/mach-highbank/Kconfig"
947 source "arch/arm/mach-integrator/Kconfig"
949 source "arch/arm/mach-iop32x/Kconfig"
951 source "arch/arm/mach-iop33x/Kconfig"
953 source "arch/arm/mach-iop13xx/Kconfig"
955 source "arch/arm/mach-ixp4xx/Kconfig"
957 source "arch/arm/mach-keystone/Kconfig"
959 source "arch/arm/mach-kirkwood/Kconfig"
961 source "arch/arm/mach-ks8695/Kconfig"
963 source "arch/arm/mach-msm/Kconfig"
965 source "arch/arm/mach-mv78xx0/Kconfig"
967 source "arch/arm/mach-imx/Kconfig"
969 source "arch/arm/mach-mxs/Kconfig"
971 source "arch/arm/mach-netx/Kconfig"
973 source "arch/arm/mach-nomadik/Kconfig"
975 source "arch/arm/mach-nspire/Kconfig"
977 source "arch/arm/plat-omap/Kconfig"
979 source "arch/arm/mach-omap1/Kconfig"
981 source "arch/arm/mach-omap2/Kconfig"
983 source "arch/arm/mach-orion5x/Kconfig"
985 source "arch/arm/mach-picoxcell/Kconfig"
987 source "arch/arm/mach-pxa/Kconfig"
988 source "arch/arm/plat-pxa/Kconfig"
990 source "arch/arm/mach-mmp/Kconfig"
992 source "arch/arm/mach-realview/Kconfig"
994 source "arch/arm/mach-rockchip/Kconfig"
996 source "arch/arm/mach-sa1100/Kconfig"
998 source "arch/arm/plat-samsung/Kconfig"
1000 source "arch/arm/mach-socfpga/Kconfig"
1002 source "arch/arm/mach-spear/Kconfig"
1004 source "arch/arm/mach-sti/Kconfig"
1006 source "arch/arm/mach-s3c24xx/Kconfig"
1009 source "arch/arm/mach-s3c64xx/Kconfig"
1012 source "arch/arm/mach-s5p64x0/Kconfig"
1014 source "arch/arm/mach-s5pc100/Kconfig"
1016 source "arch/arm/mach-s5pv210/Kconfig"
1018 source "arch/arm/mach-exynos/Kconfig"
1020 source "arch/arm/mach-shmobile/Kconfig"
1022 source "arch/arm/mach-sunxi/Kconfig"
1024 source "arch/arm/mach-prima2/Kconfig"
1026 source "arch/arm/mach-tegra/Kconfig"
1028 source "arch/arm/mach-u300/Kconfig"
1030 source "arch/arm/mach-ux500/Kconfig"
1032 source "arch/arm/mach-versatile/Kconfig"
1034 source "arch/arm/mach-vexpress/Kconfig"
1035 source "arch/arm/plat-versatile/Kconfig"
1037 source "arch/arm/mach-virt/Kconfig"
1039 source "arch/arm/mach-vt8500/Kconfig"
1041 source "arch/arm/mach-w90x900/Kconfig"
1043 source "arch/arm/mach-zynq/Kconfig"
1045 # Definitions to make life easier
1051 select GENERIC_CLOCKEVENTS
1057 select GENERIC_IRQ_CHIP
1060 config PLAT_ORION_LEGACY
1067 config PLAT_VERSATILE
1070 config ARM_TIMER_SP804
1073 select CLKSRC_OF if OF
1075 source arch/arm/mm/Kconfig
1079 default 16 if ARCH_EP93XX
1083 bool "Enable iWMMXt support" if !CPU_PJ4
1084 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1085 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1087 Enable support for iWMMXt context switching at run time if
1088 running on a CPU that supports it.
1092 depends on CPU_XSCALE
1095 config MULTI_IRQ_HANDLER
1098 Allow each machine to specify it's own IRQ handler at run time.
1101 source "arch/arm/Kconfig-nommu"
1104 config PJ4B_ERRATA_4742
1105 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1106 depends on CPU_PJ4B && MACH_ARMADA_370
1109 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1110 Event (WFE) IDLE states, a specific timing sensitivity exists between
1111 the retiring WFI/WFE instructions and the newly issued subsequent
1112 instructions. This sensitivity can result in a CPU hang scenario.
1114 The software must insert either a Data Synchronization Barrier (DSB)
1115 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1118 config ARM_ERRATA_326103
1119 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1122 Executing a SWP instruction to read-only memory does not set bit 11
1123 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1124 treat the access as a read, preventing a COW from occurring and
1125 causing the faulting task to livelock.
1127 config ARM_ERRATA_411920
1128 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1129 depends on CPU_V6 || CPU_V6K
1131 Invalidation of the Instruction Cache operation can
1132 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1133 It does not affect the MPCore. This option enables the ARM Ltd.
1134 recommended workaround.
1136 config ARM_ERRATA_430973
1137 bool "ARM errata: Stale prediction on replaced interworking branch"
1140 This option enables the workaround for the 430973 Cortex-A8
1141 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1142 interworking branch is replaced with another code sequence at the
1143 same virtual address, whether due to self-modifying code or virtual
1144 to physical address re-mapping, Cortex-A8 does not recover from the
1145 stale interworking branch prediction. This results in Cortex-A8
1146 executing the new code sequence in the incorrect ARM or Thumb state.
1147 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1148 and also flushes the branch target cache at every context switch.
1149 Note that setting specific bits in the ACTLR register may not be
1150 available in non-secure mode.
1152 config ARM_ERRATA_458693
1153 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742230 Cortex-A9
1185 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1186 between two write operations may not ensure the correct visibility
1187 ordering of the two writes. This workaround sets a specific bit in
1188 the diagnostic register of the Cortex-A9 which causes the DMB
1189 instruction to behave as a DSB, ensuring the correct behaviour of
1192 config ARM_ERRATA_742231
1193 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 742231 Cortex-A9
1198 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1199 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1200 accessing some data located in the same cache line, may get corrupted
1201 data due to bad handling of the address hazard when the line gets
1202 replaced from one of the CPUs at the same time as another CPU is
1203 accessing it. This workaround sets specific bits in the diagnostic
1204 register of the Cortex-A9 which reduces the linefill issuing
1205 capabilities of the processor.
1207 config PL310_ERRATA_588369
1208 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1209 depends on CACHE_L2X0
1211 The PL310 L2 cache controller implements three types of Clean &
1212 Invalidate maintenance operations: by Physical Address
1213 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1214 They are architecturally defined to behave as the execution of a
1215 clean operation followed immediately by an invalidate operation,
1216 both performing to the same memory location. This functionality
1217 is not correctly implemented in PL310 as clean lines are not
1218 invalidated as a result of these operations.
1220 config ARM_ERRATA_643719
1221 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1222 depends on CPU_V7 && SMP
1224 This option enables the workaround for the 643719 Cortex-A9 (prior to
1225 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1226 register returns zero when it should return one. The workaround
1227 corrects this value, ensuring cache maintenance operations which use
1228 it behave as intended and avoiding data corruption.
1230 config ARM_ERRATA_720789
1231 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1234 This option enables the workaround for the 720789 Cortex-A9 (prior to
1235 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1236 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1237 As a consequence of this erratum, some TLB entries which should be
1238 invalidated are not, resulting in an incoherency in the system page
1239 tables. The workaround changes the TLB flushing routines to invalidate
1240 entries regardless of the ASID.
1242 config PL310_ERRATA_727915
1243 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1244 depends on CACHE_L2X0
1246 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1247 operation (offset 0x7FC). This operation runs in background so that
1248 PL310 can handle normal accesses while it is in progress. Under very
1249 rare circumstances, due to this erratum, write data can be lost when
1250 PL310 treats a cacheable write transaction during a Clean &
1251 Invalidate by Way operation.
1253 config ARM_ERRATA_743622
1254 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1256 depends on !ARCH_MULTIPLATFORM
1258 This option enables the workaround for the 743622 Cortex-A9
1259 (r2p*) erratum. Under very rare conditions, a faulty
1260 optimisation in the Cortex-A9 Store Buffer may lead to data
1261 corruption. This workaround sets a specific bit in the diagnostic
1262 register of the Cortex-A9 which disables the Store Buffer
1263 optimisation, preventing the defect from occurring. This has no
1264 visible impact on the overall performance or power consumption of the
1267 config ARM_ERRATA_751472
1268 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1270 depends on !ARCH_MULTIPLATFORM
1272 This option enables the workaround for the 751472 Cortex-A9 (prior
1273 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1274 completion of a following broadcasted operation if the second
1275 operation is received by a CPU before the ICIALLUIS has completed,
1276 potentially leading to corrupted entries in the cache or TLB.
1278 config PL310_ERRATA_753970
1279 bool "PL310 errata: cache sync operation may be faulty"
1280 depends on CACHE_PL310
1282 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1284 Under some condition the effect of cache sync operation on
1285 the store buffer still remains when the operation completes.
1286 This means that the store buffer is always asked to drain and
1287 this prevents it from merging any further writes. The workaround
1288 is to replace the normal offset of cache sync operation (0x730)
1289 by another offset targeting an unmapped PL310 register 0x740.
1290 This has the same effect as the cache sync operation: store buffer
1291 drain and waiting for all buffers empty.
1293 config ARM_ERRATA_754322
1294 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1297 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1298 r3p*) erratum. A speculative memory access may cause a page table walk
1299 which starts prior to an ASID switch but completes afterwards. This
1300 can populate the micro-TLB with a stale entry which may be hit with
1301 the new ASID. This workaround places two dsb instructions in the mm
1302 switching code so that no page table walks can cross the ASID switch.
1304 config ARM_ERRATA_754327
1305 bool "ARM errata: no automatic Store Buffer drain"
1306 depends on CPU_V7 && SMP
1308 This option enables the workaround for the 754327 Cortex-A9 (prior to
1309 r2p0) erratum. The Store Buffer does not have any automatic draining
1310 mechanism and therefore a livelock may occur if an external agent
1311 continuously polls a memory location waiting to observe an update.
1312 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1313 written polling loops from denying visibility of updates to memory.
1315 config ARM_ERRATA_364296
1316 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1317 depends on CPU_V6 && !SMP
1319 This options enables the workaround for the 364296 ARM1136
1320 r0p2 erratum (possible cache data corruption with
1321 hit-under-miss enabled). It sets the undocumented bit 31 in
1322 the auxiliary control register and the FI bit in the control
1323 register, thus disabling hit-under-miss without putting the
1324 processor into full low interrupt latency mode. ARM11MPCore
1327 config ARM_ERRATA_764369
1328 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1329 depends on CPU_V7 && SMP
1331 This option enables the workaround for erratum 764369
1332 affecting Cortex-A9 MPCore with two or more processors (all
1333 current revisions). Under certain timing circumstances, a data
1334 cache line maintenance operation by MVA targeting an Inner
1335 Shareable memory region may fail to proceed up to either the
1336 Point of Coherency or to the Point of Unification of the
1337 system. This workaround adds a DSB instruction before the
1338 relevant cache maintenance functions and sets a specific bit
1339 in the diagnostic control register of the SCU.
1341 config PL310_ERRATA_769419
1342 bool "PL310 errata: no automatic Store Buffer drain"
1343 depends on CACHE_L2X0
1345 On revisions of the PL310 prior to r3p2, the Store Buffer does
1346 not automatically drain. This can cause normal, non-cacheable
1347 writes to be retained when the memory system is idle, leading
1348 to suboptimal I/O performance for drivers using coherent DMA.
1349 This option adds a write barrier to the cpu_idle loop so that,
1350 on systems with an outer cache, the store buffer is drained
1353 config ARM_ERRATA_775420
1354 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1357 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1358 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1359 operation aborts with MMU exception, it might cause the processor
1360 to deadlock. This workaround puts DSB before executing ISB if
1361 an abort may occur on cache maintenance.
1363 config ARM_ERRATA_798181
1364 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1365 depends on CPU_V7 && SMP
1367 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1368 adequately shooting down all use of the old entries. This
1369 option enables the Linux kernel workaround for this erratum
1370 which sends an IPI to the CPUs that are running the same ASID
1371 as the one being invalidated.
1375 source "arch/arm/common/Kconfig"
1385 Find out whether you have ISA slots on your motherboard. ISA is the
1386 name of a bus system, i.e. the way the CPU talks to the other stuff
1387 inside your box. Other bus systems are PCI, EISA, MicroChannel
1388 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1389 newer boards don't support it. If you have ISA, say Y, otherwise N.
1391 # Select ISA DMA controller support
1396 # Select ISA DMA interface
1401 bool "PCI support" if MIGHT_HAVE_PCI
1403 Find out whether you have a PCI motherboard. PCI is the name of a
1404 bus system, i.e. the way the CPU talks to the other stuff inside
1405 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1406 VESA. If you have PCI, say Y, otherwise N.
1412 config PCI_NANOENGINE
1413 bool "BSE nanoEngine PCI support"
1414 depends on SA1100_NANOENGINE
1416 Enable PCI on the BSE nanoEngine board.
1421 # Select the host bridge type
1422 config PCI_HOST_VIA82C505
1424 depends on PCI && ARCH_SHARK
1427 config PCI_HOST_ITE8152
1429 depends on PCI && MACH_ARMCORE
1433 source "drivers/pci/Kconfig"
1434 source "drivers/pci/pcie/Kconfig"
1436 source "drivers/pcmcia/Kconfig"
1440 menu "Kernel Features"
1445 This option should be selected by machines which have an SMP-
1448 The only effect of this option is to make the SMP-related
1449 options available to the user for configuration.
1452 bool "Symmetric Multi-Processing"
1453 depends on CPU_V6K || CPU_V7
1454 depends on GENERIC_CLOCKEVENTS
1456 depends on MMU || ARM_MPU
1457 select USE_GENERIC_SMP_HELPERS
1459 This enables support for systems with more than one CPU. If you have
1460 a system with only one CPU, like most personal computers, say N. If
1461 you have a system with more than one CPU, say Y.
1463 If you say N here, the kernel will run on single and multiprocessor
1464 machines, but will use only one CPU of a multiprocessor machine. If
1465 you say Y here, the kernel will run on many, but not all, single
1466 processor machines. On a single processor machine, the kernel will
1467 run faster if you say N here.
1469 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1470 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1471 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1473 If you don't know what to do here, say N.
1476 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1477 depends on SMP && !XIP_KERNEL && MMU
1480 SMP kernels contain instructions which fail on non-SMP processors.
1481 Enabling this option allows the kernel to modify itself to make
1482 these instructions safe. Disabling it allows about 1K of space
1485 If you don't know what to do here, say Y.
1487 config ARM_CPU_TOPOLOGY
1488 bool "Support cpu topology definition"
1489 depends on SMP && CPU_V7
1492 Support ARM cpu topology definition. The MPIDR register defines
1493 affinity between processors which is then used to describe the cpu
1494 topology of an ARM System.
1497 bool "Multi-core scheduler support"
1498 depends on ARM_CPU_TOPOLOGY
1500 Multi-core scheduler support improves the CPU scheduler's decision
1501 making when dealing with multi-core CPU chips at a cost of slightly
1502 increased overhead in some places. If unsure say N here.
1505 bool "SMT scheduler support"
1506 depends on ARM_CPU_TOPOLOGY
1508 Improves the CPU scheduler's decision making when dealing with
1509 MultiThreading at a cost of slightly increased overhead in some
1510 places. If unsure say N here.
1515 This option enables support for the ARM system coherency unit
1517 config HAVE_ARM_ARCH_TIMER
1518 bool "Architected timer support"
1520 select ARM_ARCH_TIMER
1522 This option enables support for the ARM architected timer
1527 select CLKSRC_OF if OF
1529 This options enables support for the ARM timer and watchdog unit
1532 bool "Multi-Cluster Power Management"
1533 depends on CPU_V7 && SMP
1535 This option provides the common power management infrastructure
1536 for (multi-)cluster based systems, such as big.LITTLE based
1540 prompt "Memory split"
1543 Select the desired split between kernel and user memory.
1545 If you are not absolutely sure what you are doing, leave this
1549 bool "3G/1G user/kernel split"
1551 bool "2G/2G user/kernel split"
1553 bool "1G/3G user/kernel split"
1558 default 0x40000000 if VMSPLIT_1G
1559 default 0x80000000 if VMSPLIT_2G
1563 int "Maximum number of CPUs (2-32)"
1569 bool "Support for hot-pluggable CPUs"
1572 Say Y here to experiment with turning CPUs off and on. CPUs
1573 can be controlled through /sys/devices/system/cpu.
1576 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1579 Say Y here if you want Linux to communicate with system firmware
1580 implementing the PSCI specification for CPU-centric power
1581 management operations described in ARM document number ARM DEN
1582 0022A ("Power State Coordination Interface System Software on
1586 bool "Use local timer interrupts"
1590 Enable support for local timers on SMP platforms, rather then the
1591 legacy IPI broadcast method. Local timers allows the system
1592 accounting to be spread across the timer interval, preventing a
1593 "thundering herd" at every timer tick.
1595 # The GPIO number here must be sorted by descending number. In case of
1596 # a multiplatform kernel, we just want the highest value required by the
1597 # selected platforms.
1600 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1601 default 512 if SOC_OMAP5
1602 default 512 if ARCH_KEYSTONE
1603 default 392 if ARCH_U8500
1604 default 352 if ARCH_VT8500
1605 default 288 if ARCH_SUNXI
1606 default 264 if MACH_H4700
1609 Maximum number of GPIOs in the system.
1611 If unsure, leave the default value.
1613 source kernel/Kconfig.preempt
1617 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1618 ARCH_S5PV210 || ARCH_EXYNOS4
1619 default AT91_TIMER_HZ if ARCH_AT91
1620 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1624 def_bool HIGH_RES_TIMERS
1626 config THUMB2_KERNEL
1627 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1628 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1629 default y if CPU_THUMBONLY
1631 select ARM_ASM_UNIFIED
1634 By enabling this option, the kernel will be compiled in
1635 Thumb-2 mode. A compiler/assembler that understand the unified
1636 ARM-Thumb syntax is needed.
1640 config THUMB2_AVOID_R_ARM_THM_JUMP11
1641 bool "Work around buggy Thumb-2 short branch relocations in gas"
1642 depends on THUMB2_KERNEL && MODULES
1645 Various binutils versions can resolve Thumb-2 branches to
1646 locally-defined, preemptible global symbols as short-range "b.n"
1647 branch instructions.
1649 This is a problem, because there's no guarantee the final
1650 destination of the symbol, or any candidate locations for a
1651 trampoline, are within range of the branch. For this reason, the
1652 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1653 relocation in modules at all, and it makes little sense to add
1656 The symptom is that the kernel fails with an "unsupported
1657 relocation" error when loading some modules.
1659 Until fixed tools are available, passing
1660 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1661 code which hits this problem, at the cost of a bit of extra runtime
1662 stack usage in some cases.
1664 The problem is described in more detail at:
1665 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1667 Only Thumb-2 kernels are affected.
1669 Unless you are sure your tools don't have this problem, say Y.
1671 config ARM_ASM_UNIFIED
1675 bool "Use the ARM EABI to compile the kernel"
1677 This option allows for the kernel to be compiled using the latest
1678 ARM ABI (aka EABI). This is only useful if you are using a user
1679 space environment that is also compiled with EABI.
1681 Since there are major incompatibilities between the legacy ABI and
1682 EABI, especially with regard to structure member alignment, this
1683 option also changes the kernel syscall calling convention to
1684 disambiguate both ABIs and allow for backward compatibility support
1685 (selected with CONFIG_OABI_COMPAT).
1687 To use this you need GCC version 4.0.0 or later.
1690 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1691 depends on AEABI && !THUMB2_KERNEL
1694 This option preserves the old syscall interface along with the
1695 new (ARM EABI) one. It also provides a compatibility layer to
1696 intercept syscalls that have structure arguments which layout
1697 in memory differs between the legacy ABI and the new ARM EABI
1698 (only for non "thumb" binaries). This option adds a tiny
1699 overhead to all syscalls and produces a slightly larger kernel.
1700 If you know you'll be using only pure EABI user space then you
1701 can say N here. If this option is not selected and you attempt
1702 to execute a legacy ABI binary then the result will be
1703 UNPREDICTABLE (in fact it can be predicted that it won't work
1704 at all). If in doubt say Y.
1706 config ARCH_HAS_HOLES_MEMORYMODEL
1709 config ARCH_SPARSEMEM_ENABLE
1712 config ARCH_SPARSEMEM_DEFAULT
1713 def_bool ARCH_SPARSEMEM_ENABLE
1715 config ARCH_SELECT_MEMORY_MODEL
1716 def_bool ARCH_SPARSEMEM_ENABLE
1718 config HAVE_ARCH_PFN_VALID
1719 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1722 bool "High Memory Support"
1725 The address space of ARM processors is only 4 Gigabytes large
1726 and it has to accommodate user address space, kernel address
1727 space as well as some memory mapped IO. That means that, if you
1728 have a large amount of physical memory and/or IO, not all of the
1729 memory can be "permanently mapped" by the kernel. The physical
1730 memory that is not permanently mapped is called "high memory".
1732 Depending on the selected kernel/user memory split, minimum
1733 vmalloc space and actual amount of RAM, you may not need this
1734 option which should result in a slightly faster kernel.
1739 bool "Allocate 2nd-level pagetables from highmem"
1742 config HW_PERF_EVENTS
1743 bool "Enable hardware performance counter support for perf events"
1744 depends on PERF_EVENTS
1747 Enable hardware performance counter support for perf events. If
1748 disabled, perf events will use software events only.
1750 config SYS_SUPPORTS_HUGETLBFS
1754 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1760 config FORCE_MAX_ZONEORDER
1761 int "Maximum zone order" if ARCH_SHMOBILE
1762 range 11 64 if ARCH_SHMOBILE
1763 default "12" if SOC_AM33XX
1764 default "9" if SA1111
1767 The kernel memory allocator divides physically contiguous memory
1768 blocks into "zones", where each zone is a power of two number of
1769 pages. This option selects the largest power of two that the kernel
1770 keeps in the memory allocator. If you need to allocate very large
1771 blocks of physically contiguous memory, then you may need to
1772 increase this value.
1774 This config option is actually maximum order plus one. For example,
1775 a value of 11 means that the largest free memory block is 2^10 pages.
1777 config ALIGNMENT_TRAP
1779 depends on CPU_CP15_MMU
1780 default y if !ARCH_EBSA110
1781 select HAVE_PROC_CPU if PROC_FS
1783 ARM processors cannot fetch/store information which is not
1784 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1785 address divisible by 4. On 32-bit ARM processors, these non-aligned
1786 fetch/store instructions will be emulated in software if you say
1787 here, which has a severe performance impact. This is necessary for
1788 correct operation of some network protocols. With an IP-only
1789 configuration it is safe to say N, otherwise say Y.
1791 config UACCESS_WITH_MEMCPY
1792 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1794 default y if CPU_FEROCEON
1796 Implement faster copy_to_user and clear_user methods for CPU
1797 cores where a 8-word STM instruction give significantly higher
1798 memory write throughput than a sequence of individual 32bit stores.
1800 A possible side effect is a slight increase in scheduling latency
1801 between threads sharing the same address space if they invoke
1802 such copy operations with large buffers.
1804 However, if the CPU data cache is using a write-allocate mode,
1805 this option is unlikely to provide any performance gain.
1809 prompt "Enable seccomp to safely compute untrusted bytecode"
1811 This kernel feature is useful for number crunching applications
1812 that may need to compute untrusted bytecode during their
1813 execution. By using pipes or other transports made available to
1814 the process as file descriptors supporting the read/write
1815 syscalls, it's possible to isolate those applications in
1816 their own address space using seccomp. Once seccomp is
1817 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1818 and the task is only allowed to execute a few safe syscalls
1819 defined by each seccomp mode.
1821 config CC_STACKPROTECTOR
1822 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1824 This option turns on the -fstack-protector GCC feature. This
1825 feature puts, at the beginning of functions, a canary value on
1826 the stack just before the return address, and validates
1827 the value just before actually returning. Stack based buffer
1828 overflows (that need to overwrite this return address) now also
1829 overwrite the canary, which gets detected and the attack is then
1830 neutralized via a kernel panic.
1831 This feature requires gcc version 4.2 or above.
1838 bool "Xen guest support on ARM (EXPERIMENTAL)"
1839 depends on ARM && AEABI && OF
1840 depends on CPU_V7 && !CPU_V6
1841 depends on !GENERIC_ATOMIC64
1844 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1851 bool "Flattened Device Tree support"
1854 select OF_EARLY_FLATTREE
1856 Include support for flattened device tree machine descriptions.
1859 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1862 This is the traditional way of passing data to the kernel at boot
1863 time. If you are solely relying on the flattened device tree (or
1864 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1865 to remove ATAGS support from your kernel binary. If unsure,
1868 config DEPRECATED_PARAM_STRUCT
1869 bool "Provide old way to pass kernel parameters"
1872 This was deprecated in 2001 and announced to live on for 5 years.
1873 Some old boot loaders still use this way.
1875 # Compressed boot loader in ROM. Yes, we really want to ask about
1876 # TEXT and BSS so we preserve their values in the config files.
1877 config ZBOOT_ROM_TEXT
1878 hex "Compressed ROM boot loader base address"
1881 The physical address at which the ROM-able zImage is to be
1882 placed in the target. Platforms which normally make use of
1883 ROM-able zImage formats normally set this to a suitable
1884 value in their defconfig file.
1886 If ZBOOT_ROM is not enabled, this has no effect.
1888 config ZBOOT_ROM_BSS
1889 hex "Compressed ROM boot loader BSS address"
1892 The base address of an area of read/write memory in the target
1893 for the ROM-able zImage which must be available while the
1894 decompressor is running. It must be large enough to hold the
1895 entire decompressed kernel plus an additional 128 KiB.
1896 Platforms which normally make use of ROM-able zImage formats
1897 normally set this to a suitable value in their defconfig file.
1899 If ZBOOT_ROM is not enabled, this has no effect.
1902 bool "Compressed boot loader in ROM/flash"
1903 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1905 Say Y here if you intend to execute your compressed kernel image
1906 (zImage) directly from ROM or flash. If unsure, say N.
1909 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1910 depends on ZBOOT_ROM && ARCH_SH7372
1911 default ZBOOT_ROM_NONE
1913 Include experimental SD/MMC loading code in the ROM-able zImage.
1914 With this enabled it is possible to write the ROM-able zImage
1915 kernel image to an MMC or SD card and boot the kernel straight
1916 from the reset vector. At reset the processor Mask ROM will load
1917 the first part of the ROM-able zImage which in turn loads the
1918 rest the kernel image to RAM.
1920 config ZBOOT_ROM_NONE
1921 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1923 Do not load image from SD or MMC
1925 config ZBOOT_ROM_MMCIF
1926 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1928 Load image from MMCIF hardware block.
1930 config ZBOOT_ROM_SH_MOBILE_SDHI
1931 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1933 Load image from SDHI hardware block
1937 config ARM_APPENDED_DTB
1938 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1939 depends on OF && !ZBOOT_ROM
1941 With this option, the boot code will look for a device tree binary
1942 (DTB) appended to zImage
1943 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1945 This is meant as a backward compatibility convenience for those
1946 systems with a bootloader that can't be upgraded to accommodate
1947 the documented boot protocol using a device tree.
1949 Beware that there is very little in terms of protection against
1950 this option being confused by leftover garbage in memory that might
1951 look like a DTB header after a reboot if no actual DTB is appended
1952 to zImage. Do not leave this option active in a production kernel
1953 if you don't intend to always append a DTB. Proper passing of the
1954 location into r2 of a bootloader provided DTB is always preferable
1957 config ARM_ATAG_DTB_COMPAT
1958 bool "Supplement the appended DTB with traditional ATAG information"
1959 depends on ARM_APPENDED_DTB
1961 Some old bootloaders can't be updated to a DTB capable one, yet
1962 they provide ATAGs with memory configuration, the ramdisk address,
1963 the kernel cmdline string, etc. Such information is dynamically
1964 provided by the bootloader and can't always be stored in a static
1965 DTB. To allow a device tree enabled kernel to be used with such
1966 bootloaders, this option allows zImage to extract the information
1967 from the ATAG list and store it at run time into the appended DTB.
1970 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1971 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1973 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1974 bool "Use bootloader kernel arguments if available"
1976 Uses the command-line options passed by the boot loader instead of
1977 the device tree bootargs property. If the boot loader doesn't provide
1978 any, the device tree bootargs property will be used.
1980 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1981 bool "Extend with bootloader kernel arguments"
1983 The command-line arguments provided by the boot loader will be
1984 appended to the the device tree bootargs property.
1989 string "Default kernel command string"
1992 On some architectures (EBSA110 and CATS), there is currently no way
1993 for the boot loader to pass arguments to the kernel. For these
1994 architectures, you should supply some command-line options at build
1995 time by entering them here. As a minimum, you should specify the
1996 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1999 prompt "Kernel command line type" if CMDLINE != ""
2000 default CMDLINE_FROM_BOOTLOADER
2003 config CMDLINE_FROM_BOOTLOADER
2004 bool "Use bootloader kernel arguments if available"
2006 Uses the command-line options passed by the boot loader. If
2007 the boot loader doesn't provide any, the default kernel command
2008 string provided in CMDLINE will be used.
2010 config CMDLINE_EXTEND
2011 bool "Extend bootloader kernel arguments"
2013 The command-line arguments provided by the boot loader will be
2014 appended to the default kernel command string.
2016 config CMDLINE_FORCE
2017 bool "Always use the default kernel command string"
2019 Always use the default kernel command string, even if the boot
2020 loader passes other arguments to the kernel.
2021 This is useful if you cannot or don't want to change the
2022 command-line options your boot loader passes to the kernel.
2026 bool "Kernel Execute-In-Place from ROM"
2027 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2029 Execute-In-Place allows the kernel to run from non-volatile storage
2030 directly addressable by the CPU, such as NOR flash. This saves RAM
2031 space since the text section of the kernel is not loaded from flash
2032 to RAM. Read-write sections, such as the data section and stack,
2033 are still copied to RAM. The XIP kernel is not compressed since
2034 it has to run directly from flash, so it will take more space to
2035 store it. The flash address used to link the kernel object files,
2036 and for storing it, is configuration dependent. Therefore, if you
2037 say Y here, you must know the proper physical address where to
2038 store the kernel image depending on your own flash memory usage.
2040 Also note that the make target becomes "make xipImage" rather than
2041 "make zImage" or "make Image". The final kernel binary to put in
2042 ROM memory will be arch/arm/boot/xipImage.
2046 config XIP_PHYS_ADDR
2047 hex "XIP Kernel Physical Location"
2048 depends on XIP_KERNEL
2049 default "0x00080000"
2051 This is the physical address in your flash memory the kernel will
2052 be linked for and stored to. This address is dependent on your
2056 bool "Kexec system call (EXPERIMENTAL)"
2057 depends on (!SMP || PM_SLEEP_SMP)
2059 kexec is a system call that implements the ability to shutdown your
2060 current kernel, and to start another kernel. It is like a reboot
2061 but it is independent of the system firmware. And like a reboot
2062 you can start any kernel with it, not just Linux.
2064 It is an ongoing process to be certain the hardware in a machine
2065 is properly shutdown, so do not be surprised if this code does not
2066 initially work for you. It may help to enable device hotplugging
2070 bool "Export atags in procfs"
2071 depends on ATAGS && KEXEC
2074 Should the atags used to boot the kernel be exported in an "atags"
2075 file in procfs. Useful with kexec.
2078 bool "Build kdump crash kernel (EXPERIMENTAL)"
2080 Generate crash dump after being started by kexec. This should
2081 be normally only set in special crash dump kernels which are
2082 loaded in the main kernel with kexec-tools into a specially
2083 reserved region and then later executed after a crash by
2084 kdump/kexec. The crash dump kernel must be compiled to a
2085 memory address not used by the main kernel
2087 For more details see Documentation/kdump/kdump.txt
2089 config AUTO_ZRELADDR
2090 bool "Auto calculation of the decompressed kernel image address"
2091 depends on !ZBOOT_ROM
2093 ZRELADDR is the physical address where the decompressed kernel
2094 image will be placed. If AUTO_ZRELADDR is selected, the address
2095 will be determined at run-time by masking the current IP with
2096 0xf8000000. This assumes the zImage being placed in the first 128MB
2097 from start of memory.
2101 menu "CPU Power Management"
2104 source "drivers/cpufreq/Kconfig"
2107 source "drivers/cpuidle/Kconfig"
2111 menu "Floating point emulation"
2113 comment "At least one emulation must be selected"
2116 bool "NWFPE math emulation"
2117 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2119 Say Y to include the NWFPE floating point emulator in the kernel.
2120 This is necessary to run most binaries. Linux does not currently
2121 support floating point hardware so you need to say Y here even if
2122 your machine has an FPA or floating point co-processor podule.
2124 You may say N here if you are going to load the Acorn FPEmulator
2125 early in the bootup.
2128 bool "Support extended precision"
2129 depends on FPE_NWFPE
2131 Say Y to include 80-bit support in the kernel floating-point
2132 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2133 Note that gcc does not generate 80-bit operations by default,
2134 so in most cases this option only enlarges the size of the
2135 floating point emulator without any good reason.
2137 You almost surely want to say N here.
2140 bool "FastFPE math emulation (EXPERIMENTAL)"
2141 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2143 Say Y here to include the FAST floating point emulator in the kernel.
2144 This is an experimental much faster emulator which now also has full
2145 precision for the mantissa. It does not support any exceptions.
2146 It is very simple, and approximately 3-6 times faster than NWFPE.
2148 It should be sufficient for most programs. It may be not suitable
2149 for scientific calculations, but you have to check this for yourself.
2150 If you do not feel you need a faster FP emulation you should better
2154 bool "VFP-format floating point maths"
2155 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2157 Say Y to include VFP support code in the kernel. This is needed
2158 if your hardware includes a VFP unit.
2160 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2161 release notes and additional status information.
2163 Say N if your target does not have VFP hardware.
2171 bool "Advanced SIMD (NEON) Extension support"
2172 depends on VFPv3 && CPU_V7
2174 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2179 menu "Userspace binary formats"
2181 source "fs/Kconfig.binfmt"
2184 tristate "RISC OS personality"
2187 Say Y here to include the kernel code necessary if you want to run
2188 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2189 experimental; if this sounds frightening, say N and sleep in peace.
2190 You can also say M here to compile this support as a module (which
2191 will be called arthur).
2195 menu "Power management options"
2197 source "kernel/power/Kconfig"
2199 config ARCH_SUSPEND_POSSIBLE
2200 depends on !ARCH_S5PC100
2201 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2202 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2205 config ARM_CPU_SUSPEND
2210 source "net/Kconfig"
2212 source "drivers/Kconfig"
2216 source "arch/arm/Kconfig.debug"
2218 source "security/Kconfig"
2220 source "crypto/Kconfig"
2222 source "lib/Kconfig"
2224 source "arch/arm/kvm/Kconfig"