arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_WANT_IPC_PARSE_VERSION
   8         select CPU_PM if (SUSPEND || CPU_IDLE)
   9         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  10         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  12         select GENERIC_IRQ_PROBE
  13         select GENERIC_IRQ_SHOW
  14         select GENERIC_KERNEL_THREAD
  15         select GENERIC_PCI_IOMAP
  16         select GENERIC_SMP_IDLE_THREAD
  17         select GENERIC_STRNCPY_FROM_USER
  18         select GENERIC_STRNLEN_USER
  19         select HARDIRQS_SW_RESEND
  20         select HAVE_AOUT
  21         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  22         select HAVE_ARCH_KGDB
  23         select HAVE_ARCH_TRACEHOOK
  24         select HAVE_BPF_JIT
  25         select HAVE_C_RECORDMCOUNT
  26         select HAVE_DEBUG_KMEMLEAK
  27         select HAVE_DMA_API_DEBUG
  28         select HAVE_DMA_ATTRS
  29         select HAVE_DMA_CONTIGUOUS if MMU
  30         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  31         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  32         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  33         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  34         select HAVE_GENERIC_DMA_COHERENT
  35         select HAVE_GENERIC_HARDIRQS
  36         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  37         select HAVE_IDE if PCI || ISA || PCMCIA
  38         select HAVE_IRQ_WORK
  39         select HAVE_KERNEL_GZIP
  40         select HAVE_KERNEL_LZMA
  41         select HAVE_KERNEL_LZO
  42         select HAVE_KERNEL_XZ
  43         select HAVE_KPROBES if !XIP_KERNEL
  44         select HAVE_KRETPROBES if (HAVE_KPROBES)
  45         select HAVE_MEMBLOCK
  46         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  47         select HAVE_PERF_EVENTS
  48         select HAVE_REGS_AND_STACK_ACCESS_API
  49         select HAVE_SYSCALL_TRACEPOINTS
  50         select HAVE_UID16
  51         select KTIME_SCALAR
  52         select PERF_USE_VMALLOC
  53         select RTC_LIB
  54         select SYS_SUPPORTS_APM_EMULATION
  55         help
  56           The ARM series is a line of low-power-consumption RISC chip designs
  57           licensed by ARM Ltd and targeted at embedded applications and
  58           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  59           manufactured, but legacy ARM-based PC hardware remains popular in
  60           Europe.  There is an ARM Linux project with a web page at
  61           <http://www.arm.linux.org.uk/>.
  62
  63 config ARM_HAS_SG_CHAIN
  64         bool
  65
  66 config NEED_SG_DMA_LENGTH
  67         bool
  68
  69 config ARM_DMA_USE_IOMMU
  70         bool
  71         select ARM_HAS_SG_CHAIN
  72         select NEED_SG_DMA_LENGTH
  73
  74 config HAVE_PWM
  75         bool
  76
  77 config MIGHT_HAVE_PCI
  78         bool
  79
  80 config SYS_SUPPORTS_APM_EMULATION
  81         bool
  82
  83 config GENERIC_GPIO
  84         bool
  85
  86 config HAVE_TCM
  87         bool
  88         select GENERIC_ALLOCATOR
  89
  90 config HAVE_PROC_CPU
  91         bool
  92
  93 config NO_IOPORT
  94         bool
  95
  96 config EISA
  97         bool
  98         ---help---
  99           The Extended Industry Standard Architecture (EISA) bus was
 100           developed as an open alternative to the IBM MicroChannel bus.
 101
 102           The EISA bus provided some of the features of the IBM MicroChannel
 103           bus while maintaining backward compatibility with cards made for
 104           the older ISA bus.  The EISA bus saw limited use between 1988 and
 105           1995 when it was made obsolete by the PCI bus.
 106
 107           Say Y here if you are building a kernel for an EISA-based machine.
 108
 109           Otherwise, say N.
 110
 111 config SBUS
 112         bool
 113
 114 config STACKTRACE_SUPPORT
 115         bool
 116         default y
 117
 118 config HAVE_LATENCYTOP_SUPPORT
 119         bool
 120         depends on !SMP
 121         default y
 122
 123 config LOCKDEP_SUPPORT
 124         bool
 125         default y
 126
 127 config TRACE_IRQFLAGS_SUPPORT
 128         bool
 129         default y
 130
 131 config RWSEM_GENERIC_SPINLOCK
 132         bool
 133         default y
 134
 135 config RWSEM_XCHGADD_ALGORITHM
 136         bool
 137
 138 config ARCH_HAS_ILOG2_U32
 139         bool
 140
 141 config ARCH_HAS_ILOG2_U64
 142         bool
 143
 144 config ARCH_HAS_CPUFREQ
 145         bool
 146         help
 147           Internal node to signify that the ARCH has CPUFREQ support
 148           and that the relevant menu configurations are displayed for
 149           it.
 150
 151 config GENERIC_HWEIGHT
 152         bool
 153         default y
 154
 155 config GENERIC_CALIBRATE_DELAY
 156         bool
 157         default y
 158
 159 config ARCH_MAY_HAVE_PC_FDC
 160         bool
 161
 162 config ZONE_DMA
 163         bool
 164
 165 config NEED_DMA_MAP_STATE
 166        def_bool y
 167
 168 config ARCH_HAS_DMA_SET_COHERENT_MASK
 169         bool
 170
 171 config GENERIC_ISA_DMA
 172         bool
 173
 174 config FIQ
 175         bool
 176
 177 config NEED_RET_TO_USER
 178         bool
 179
 180 config ARCH_MTD_XIP
 181         bool
 182
 183 config VECTORS_BASE
 184         hex
 185         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 186         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 187         default 0x00000000
 188         help
 189           The base address of exception vectors.
 190
 191 config ARM_PATCH_PHYS_VIRT
 192         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 193         default y
 194         depends on !XIP_KERNEL && MMU
 195         depends on !ARCH_REALVIEW || !SPARSEMEM
 196         help
 197           Patch phys-to-virt and virt-to-phys translation functions at
 198           boot and module load time according to the position of the
 199           kernel in system memory.
 200
 201           This can only be used with non-XIP MMU kernels where the base
 202           of physical memory is at a 16MB boundary.
 203
 204           Only disable this option if you know that you do not require
 205           this feature (eg, building a kernel for a single machine) and
 206           you need to shrink the kernel to the minimal size.
 207
 208 config NEED_MACH_GPIO_H
 209         bool
 210         help
 211           Select this when mach/gpio.h is required to provide special
 212           definitions for this platform. The need for mach/gpio.h should
 213           be avoided when possible.
 214
 215 config NEED_MACH_IO_H
 216         bool
 217         help
 218           Select this when mach/io.h is required to provide special
 219           definitions for this platform.  The need for mach/io.h should
 220           be avoided when possible.
 221
 222 config NEED_MACH_MEMORY_H
 223         bool
 224         help
 225           Select this when mach/memory.h is required to provide special
 226           definitions for this platform.  The need for mach/memory.h should
 227           be avoided when possible.
 228
 229 config PHYS_OFFSET
 230         hex "Physical address of main memory" if MMU
 231         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 232         default DRAM_BASE if !MMU
 233         help
 234           Please provide the physical address corresponding to the
 235           location of main memory in your system.
 236
 237 config GENERIC_BUG
 238         def_bool y
 239         depends on BUG
 240
 241 source "init/Kconfig"
 242
 243 source "kernel/Kconfig.freezer"
 244
 245 menu "System Type"
 246
 247 config MMU
 248         bool "MMU-based Paged Memory Management Support"
 249         default y
 250         help
 251           Select if you want MMU-based virtualised addressing space
 252           support by paged memory management. If unsure, say 'Y'.
 253
 254 #
 255 # The "ARM system type" choice list is ordered alphabetically by option
 256 # text.  Please add new entries in the option alphabetic order.
 257 #
 258 choice
 259         prompt "ARM system type"
 260         default ARCH_MULTIPLATFORM
 261
 262 config ARCH_MULTIPLATFORM
 263         bool "Allow multiple platforms to be selected"
 264         depends on MMU
 265         select ARM_PATCH_PHYS_VIRT
 266         select AUTO_ZRELADDR
 267         select COMMON_CLK
 268         select MULTI_IRQ_HANDLER
 269         select SPARSE_IRQ
 270         select USE_OF
 271
 272 config ARCH_INTEGRATOR
 273         bool "ARM Ltd. Integrator family"
 274         select ARCH_HAS_CPUFREQ
 275         select ARM_AMBA
 276         select COMMON_CLK
 277         select COMMON_CLK_VERSATILE
 278         select GENERIC_CLOCKEVENTS
 279         select HAVE_TCM
 280         select ICST
 281         select MULTI_IRQ_HANDLER
 282         select NEED_MACH_MEMORY_H
 283         select PLAT_VERSATILE
 284         select PLAT_VERSATILE_FPGA_IRQ
 285         select SPARSE_IRQ
 286         help
 287           Support for ARM's Integrator platform.
 288
 289 config ARCH_REALVIEW
 290         bool "ARM Ltd. RealView family"
 291         select ARCH_WANT_OPTIONAL_GPIOLIB
 292         select ARM_AMBA
 293         select ARM_TIMER_SP804
 294         select COMMON_CLK
 295         select COMMON_CLK_VERSATILE
 296         select GENERIC_CLOCKEVENTS
 297         select GPIO_PL061 if GPIOLIB
 298         select ICST
 299         select NEED_MACH_MEMORY_H
 300         select PLAT_VERSATILE
 301         select PLAT_VERSATILE_CLCD
 302         help
 303           This enables support for ARM Ltd RealView boards.
 304
 305 config ARCH_VERSATILE
 306         bool "ARM Ltd. Versatile family"
 307         select ARCH_WANT_OPTIONAL_GPIOLIB
 308         select ARM_AMBA
 309         select ARM_TIMER_SP804
 310         select ARM_VIC
 311         select CLKDEV_LOOKUP
 312         select GENERIC_CLOCKEVENTS
 313         select HAVE_MACH_CLKDEV
 314         select ICST
 315         select PLAT_VERSATILE
 316         select PLAT_VERSATILE_CLCD
 317         select PLAT_VERSATILE_CLOCK
 318         select PLAT_VERSATILE_FPGA_IRQ
 319         help
 320           This enables support for ARM Ltd Versatile board.
 321
 322 config ARCH_AT91
 323         bool "Atmel AT91"
 324         select ARCH_REQUIRE_GPIOLIB
 325         select CLKDEV_LOOKUP
 326         select HAVE_CLK
 327         select IRQ_DOMAIN
 328         select NEED_MACH_GPIO_H
 329         select NEED_MACH_IO_H if PCCARD
 330         help
 331           This enables support for systems based on Atmel
 332           AT91RM9200 and AT91SAM9* processors.
 333
 334 config ARCH_BCM2835
 335         bool "Broadcom BCM2835 family"
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_AMBA
 338         select ARM_ERRATA_411920
 339         select ARM_TIMER_SP804
 340         select CLKDEV_LOOKUP
 341         select COMMON_CLK
 342         select CPU_V6
 343         select GENERIC_CLOCKEVENTS
 344         select MULTI_IRQ_HANDLER
 345         select SPARSE_IRQ
 346         select USE_OF
 347         help
 348           This enables support for the Broadcom BCM2835 SoC. This SoC is
 349           use in the Raspberry Pi, and Roku 2 devices.
 350
 351 config ARCH_CNS3XXX
 352         bool "Cavium Networks CNS3XXX family"
 353         select ARM_GIC
 354         select CPU_V6K
 355         select GENERIC_CLOCKEVENTS
 356         select MIGHT_HAVE_CACHE_L2X0
 357         select MIGHT_HAVE_PCI
 358         select PCI_DOMAINS if PCI
 359         help
 360           Support for Cavium Networks CNS3XXX platform.
 361
 362 config ARCH_CLPS711X
 363         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 364         select ARCH_USES_GETTIMEOFFSET
 365         select CLKDEV_LOOKUP
 366         select COMMON_CLK
 367         select CPU_ARM720T
 368         select NEED_MACH_MEMORY_H
 369         help
 370           Support for Cirrus Logic 711x/721x/731x based boards.
 371
 372 config ARCH_GEMINI
 373         bool "Cortina Systems Gemini"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select ARCH_USES_GETTIMEOFFSET
 376         select CPU_FA526
 377         help
 378           Support for the Cortina Systems Gemini family SoCs
 379
 380 config ARCH_SIRF
 381         bool "CSR SiRF"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select COMMON_CLK
 384         select GENERIC_CLOCKEVENTS
 385         select GENERIC_IRQ_CHIP
 386         select MIGHT_HAVE_CACHE_L2X0
 387         select NO_IOPORT
 388         select PINCTRL
 389         select PINCTRL_SIRF
 390         select USE_OF
 391         help
 392           Support for CSR SiRFprimaII/Marco/Polo platforms
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select ARCH_USES_GETTIMEOFFSET
 397         select CPU_SA110
 398         select ISA
 399         select NEED_MACH_IO_H
 400         select NEED_MACH_MEMORY_H
 401         select NO_IOPORT
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EP93XX
 409         bool "EP93xx-based"
 410         select ARCH_HAS_HOLES_MEMORYMODEL
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARCH_USES_GETTIMEOFFSET
 413         select ARM_AMBA
 414         select ARM_VIC
 415         select CLKDEV_LOOKUP
 416         select CPU_ARM920T
 417         select NEED_MACH_MEMORY_H
 418         help
 419           This enables support for the Cirrus EP93xx series of CPUs.
 420
 421 config ARCH_FOOTBRIDGE
 422         bool "FootBridge"
 423         select CPU_SA110
 424         select FOOTBRIDGE
 425         select GENERIC_CLOCKEVENTS
 426         select HAVE_IDE
 427         select NEED_MACH_IO_H if !MMU
 428         select NEED_MACH_MEMORY_H
 429         help
 430           Support for systems based on the DC21285 companion chip
 431           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 432
 433 config ARCH_MXC
 434         bool "Freescale MXC/iMX-based"
 435         select ARCH_REQUIRE_GPIOLIB
 436         select CLKDEV_LOOKUP
 437         select CLKSRC_MMIO
 438         select GENERIC_CLOCKEVENTS
 439         select GENERIC_IRQ_CHIP
 440         select MULTI_IRQ_HANDLER
 441         select SPARSE_IRQ
 442         select USE_OF
 443         help
 444           Support for Freescale MXC/iMX-based family of processors
 445
 446 config ARCH_MXS
 447         bool "Freescale MXS-based"
 448         select ARCH_REQUIRE_GPIOLIB
 449         select CLKDEV_LOOKUP
 450         select CLKSRC_MMIO
 451         select COMMON_CLK
 452         select GENERIC_CLOCKEVENTS
 453         select HAVE_CLK_PREPARE
 454         select MULTI_IRQ_HANDLER
 455         select PINCTRL
 456         select SPARSE_IRQ
 457         select USE_OF
 458         help
 459           Support for Freescale MXS-based family of processors
 460
 461 config ARCH_NETX
 462         bool "Hilscher NetX based"
 463         select ARM_VIC
 464         select CLKSRC_MMIO
 465         select CPU_ARM926T
 466         select GENERIC_CLOCKEVENTS
 467         help
 468           This enables support for systems based on the Hilscher NetX Soc
 469
 470 config ARCH_H720X
 471         bool "Hynix HMS720x-based"
 472         select ARCH_USES_GETTIMEOFFSET
 473         select CPU_ARM720T
 474         select ISA_DMA_API
 475         help
 476           This enables support for systems based on the Hynix HMS720x
 477
 478 config ARCH_IOP13XX
 479         bool "IOP13xx-based"
 480         depends on MMU
 481         select ARCH_SUPPORTS_MSI
 482         select CPU_XSC3
 483         select NEED_MACH_MEMORY_H
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         select VMSPLIT_1G
 488         help
 489           Support for Intel's IOP13XX (XScale) family of processors.
 490
 491 config ARCH_IOP32X
 492         bool "IOP32x-based"
 493         depends on MMU
 494         select ARCH_REQUIRE_GPIOLIB
 495         select CPU_XSCALE
 496         select NEED_MACH_GPIO_H
 497         select NEED_RET_TO_USER
 498         select PCI
 499         select PLAT_IOP
 500         help
 501           Support for Intel's 80219 and IOP32X (XScale) family of
 502           processors.
 503
 504 config ARCH_IOP33X
 505         bool "IOP33x-based"
 506         depends on MMU
 507         select ARCH_REQUIRE_GPIOLIB
 508         select CPU_XSCALE
 509         select NEED_MACH_GPIO_H
 510         select NEED_RET_TO_USER
 511         select PCI
 512         select PLAT_IOP
 513         help
 514           Support for Intel's IOP33X (XScale) family of processors.
 515
 516 config ARCH_IXP4XX
 517         bool "IXP4xx-based"
 518         depends on MMU
 519         select ARCH_HAS_DMA_SET_COHERENT_MASK
 520         select ARCH_REQUIRE_GPIOLIB
 521         select CLKSRC_MMIO
 522         select CPU_XSCALE
 523         select DMABOUNCE if PCI
 524         select GENERIC_CLOCKEVENTS
 525         select MIGHT_HAVE_PCI
 526         select NEED_MACH_IO_H
 527         help
 528           Support for Intel's IXP4XX (XScale) family of processors.
 529
 530 config ARCH_DOVE
 531         bool "Marvell Dove"
 532         select ARCH_REQUIRE_GPIOLIB
 533         select CPU_V7
 534         select GENERIC_CLOCKEVENTS
 535         select MIGHT_HAVE_PCI
 536         select PLAT_ORION_LEGACY
 537         select USB_ARCH_HAS_EHCI
 538         help
 539           Support for the Marvell Dove SoC 88AP510
 540
 541 config ARCH_KIRKWOOD
 542         bool "Marvell Kirkwood"
 543         select ARCH_REQUIRE_GPIOLIB
 544         select CPU_FEROCEON
 545         select GENERIC_CLOCKEVENTS
 546         select PCI
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Kirkwood series SoCs:
 550           88F6180, 88F6192 and 88F6281.
 551
 552 config ARCH_MV78XX0
 553         bool "Marvell MV78xx0"
 554         select ARCH_REQUIRE_GPIOLIB
 555         select CPU_FEROCEON
 556         select GENERIC_CLOCKEVENTS
 557         select PCI
 558         select PLAT_ORION_LEGACY
 559         help
 560           Support for the following Marvell MV78xx0 series SoCs:
 561           MV781x0, MV782x0.
 562
 563 config ARCH_ORION5X
 564         bool "Marvell Orion"
 565         depends on MMU
 566         select ARCH_REQUIRE_GPIOLIB
 567         select CPU_FEROCEON
 568         select GENERIC_CLOCKEVENTS
 569         select PCI
 570         select PLAT_ORION_LEGACY
 571         help
 572           Support for the following Marvell Orion 5x series SoCs:
 573           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 574           Orion-2 (5281), Orion-1-90 (6183).
 575
 576 config ARCH_MMP
 577         bool "Marvell PXA168/910/MMP2"
 578         depends on MMU
 579         select ARCH_REQUIRE_GPIOLIB
 580         select CLKDEV_LOOKUP
 581         select GENERIC_ALLOCATOR
 582         select GENERIC_CLOCKEVENTS
 583         select GPIO_PXA
 584         select IRQ_DOMAIN
 585         select NEED_MACH_GPIO_H
 586         select PLAT_PXA
 587         select SPARSE_IRQ
 588         help
 589           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 590
 591 config ARCH_KS8695
 592         bool "Micrel/Kendin KS8695"
 593         select ARCH_REQUIRE_GPIOLIB
 594         select CLKSRC_MMIO
 595         select CPU_ARM922T
 596         select GENERIC_CLOCKEVENTS
 597         select NEED_MACH_MEMORY_H
 598         help
 599           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 600           System-on-Chip devices.
 601
 602 config ARCH_W90X900
 603         bool "Nuvoton W90X900 CPU"
 604         select ARCH_REQUIRE_GPIOLIB
 605         select CLKDEV_LOOKUP
 606         select CLKSRC_MMIO
 607         select CPU_ARM926T
 608         select GENERIC_CLOCKEVENTS
 609         help
 610           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 611           At present, the w90x900 has been renamed nuc900, regarding
 612           the ARM series product line, you can login the following
 613           link address to know more.
 614
 615           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 616                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 617
 618 config ARCH_LPC32XX
 619         bool "NXP LPC32XX"
 620         select ARCH_REQUIRE_GPIOLIB
 621         select ARM_AMBA
 622         select CLKDEV_LOOKUP
 623         select CLKSRC_MMIO
 624         select CPU_ARM926T
 625         select GENERIC_CLOCKEVENTS
 626         select HAVE_IDE
 627         select HAVE_PWM
 628         select USB_ARCH_HAS_OHCI
 629         select USE_OF
 630         help
 631           Support for the NXP LPC32XX family of processors
 632
 633 config ARCH_TEGRA
 634         bool "NVIDIA Tegra"
 635         select ARCH_HAS_CPUFREQ
 636         select CLKDEV_LOOKUP
 637         select CLKSRC_MMIO
 638         select COMMON_CLK
 639         select GENERIC_CLOCKEVENTS
 640         select GENERIC_GPIO
 641         select HAVE_CLK
 642         select HAVE_SMP
 643         select MIGHT_HAVE_CACHE_L2X0
 644         select USE_OF
 645         help
 646           This enables support for NVIDIA Tegra based systems (Tegra APX,
 647           Tegra 6xx and Tegra 2 series).
 648
 649 config ARCH_PXA
 650         bool "PXA2xx/PXA3xx-based"
 651         depends on MMU
 652         select ARCH_HAS_CPUFREQ
 653         select ARCH_MTD_XIP
 654         select ARCH_REQUIRE_GPIOLIB
 655         select ARM_CPU_SUSPEND if PM
 656         select AUTO_ZRELADDR
 657         select CLKDEV_LOOKUP
 658         select CLKSRC_MMIO
 659         select GENERIC_CLOCKEVENTS
 660         select GPIO_PXA
 661         select HAVE_IDE
 662         select MULTI_IRQ_HANDLER
 663         select NEED_MACH_GPIO_H
 664         select PLAT_PXA
 665         select SPARSE_IRQ
 666         help
 667           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 668
 669 config ARCH_MSM
 670         bool "Qualcomm MSM"
 671         select ARCH_REQUIRE_GPIOLIB
 672         select CLKDEV_LOOKUP
 673         select GENERIC_CLOCKEVENTS
 674         select HAVE_CLK
 675         help
 676           Support for Qualcomm MSM/QSD based systems.  This runs on the
 677           apps processor of the MSM/QSD and depends on a shared memory
 678           interface to the modem processor which runs the baseband
 679           stack and controls some vital subsystems
 680           (clock and power control, etc).
 681
 682 config ARCH_SHMOBILE
 683         bool "Renesas SH-Mobile / R-Mobile"
 684         select CLKDEV_LOOKUP
 685         select GENERIC_CLOCKEVENTS
 686         select HAVE_CLK
 687         select HAVE_MACH_CLKDEV
 688         select HAVE_SMP
 689         select MIGHT_HAVE_CACHE_L2X0
 690         select MULTI_IRQ_HANDLER
 691         select NEED_MACH_MEMORY_H
 692         select NO_IOPORT
 693         select PM_GENERIC_DOMAINS if PM
 694         select SPARSE_IRQ
 695         help
 696           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 697
 698 config ARCH_RPC
 699         bool "RiscPC"
 700         select ARCH_ACORN
 701         select ARCH_MAY_HAVE_PC_FDC
 702         select ARCH_SPARSEMEM_ENABLE
 703         select ARCH_USES_GETTIMEOFFSET
 704         select FIQ
 705         select HAVE_IDE
 706         select HAVE_PATA_PLATFORM
 707         select ISA_DMA_API
 708         select NEED_MACH_IO_H
 709         select NEED_MACH_MEMORY_H
 710         select NO_IOPORT
 711         help
 712           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 713           CD-ROM interface, serial and parallel port, and the floppy drive.
 714
 715 config ARCH_SA1100
 716         bool "SA1100-based"
 717         select ARCH_HAS_CPUFREQ
 718         select ARCH_MTD_XIP
 719         select ARCH_REQUIRE_GPIOLIB
 720         select ARCH_SPARSEMEM_ENABLE
 721         select CLKDEV_LOOKUP
 722         select CLKSRC_MMIO
 723         select CPU_FREQ
 724         select CPU_SA1100
 725         select GENERIC_CLOCKEVENTS
 726         select HAVE_IDE
 727         select ISA
 728         select NEED_MACH_GPIO_H
 729         select NEED_MACH_MEMORY_H
 730         select SPARSE_IRQ
 731         help
 732           Support for StrongARM 11x0 based boards.
 733
 734 config ARCH_S3C24XX
 735         bool "Samsung S3C24XX SoCs"
 736         select ARCH_HAS_CPUFREQ
 737         select ARCH_USES_GETTIMEOFFSET
 738         select CLKDEV_LOOKUP
 739         select GENERIC_GPIO
 740         select HAVE_CLK
 741         select HAVE_S3C2410_I2C if I2C
 742         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 743         select HAVE_S3C_RTC if RTC_CLASS
 744         select NEED_MACH_GPIO_H
 745         select NEED_MACH_IO_H
 746         help
 747           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 748           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 749           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 750           Samsung SMDK2410 development board (and derivatives).
 751
 752 config ARCH_S3C64XX
 753         bool "Samsung S3C64XX"
 754         select ARCH_HAS_CPUFREQ
 755         select ARCH_REQUIRE_GPIOLIB
 756         select ARCH_USES_GETTIMEOFFSET
 757         select ARM_VIC
 758         select CLKDEV_LOOKUP
 759         select CPU_V6
 760         select HAVE_CLK
 761         select HAVE_S3C2410_I2C if I2C
 762         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 763         select HAVE_TCM
 764         select NEED_MACH_GPIO_H
 765         select NO_IOPORT
 766         select PLAT_SAMSUNG
 767         select S3C_DEV_NAND
 768         select S3C_GPIO_TRACK
 769         select SAMSUNG_CLKSRC
 770         select SAMSUNG_GPIOLIB_4BIT
 771         select SAMSUNG_IRQ_VIC_TIMER
 772         select USB_ARCH_HAS_OHCI
 773         help
 774           Samsung S3C64XX series based systems
 775
 776 config ARCH_S5P64X0
 777         bool "Samsung S5P6440 S5P6450"
 778         select CLKDEV_LOOKUP
 779         select CLKSRC_MMIO
 780         select CPU_V6
 781         select GENERIC_CLOCKEVENTS
 782         select GENERIC_GPIO
 783         select HAVE_CLK
 784         select HAVE_S3C2410_I2C if I2C
 785         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 786         select HAVE_S3C_RTC if RTC_CLASS
 787         select NEED_MACH_GPIO_H
 788         help
 789           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 790           SMDK6450.
 791
 792 config ARCH_S5PC100
 793         bool "Samsung S5PC100"
 794         select ARCH_USES_GETTIMEOFFSET
 795         select CLKDEV_LOOKUP
 796         select CPU_V7
 797         select GENERIC_GPIO
 798         select HAVE_CLK
 799         select HAVE_S3C2410_I2C if I2C
 800         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 801         select HAVE_S3C_RTC if RTC_CLASS
 802         select NEED_MACH_GPIO_H
 803         help
 804           Samsung S5PC100 series based systems
 805
 806 config ARCH_S5PV210
 807         bool "Samsung S5PV210/S5PC110"
 808         select ARCH_HAS_CPUFREQ
 809         select ARCH_HAS_HOLES_MEMORYMODEL
 810         select ARCH_SPARSEMEM_ENABLE
 811         select CLKDEV_LOOKUP
 812         select CLKSRC_MMIO
 813         select CPU_V7
 814         select GENERIC_CLOCKEVENTS
 815         select GENERIC_GPIO
 816         select HAVE_CLK
 817         select HAVE_S3C2410_I2C if I2C
 818         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 819         select HAVE_S3C_RTC if RTC_CLASS
 820         select NEED_MACH_GPIO_H
 821         select NEED_MACH_MEMORY_H
 822         help
 823           Samsung S5PV210/S5PC110 series based systems
 824
 825 config ARCH_EXYNOS
 826         bool "Samsung EXYNOS"
 827         select ARCH_HAS_CPUFREQ
 828         select ARCH_HAS_HOLES_MEMORYMODEL
 829         select ARCH_SPARSEMEM_ENABLE
 830         select CLKDEV_LOOKUP
 831         select CPU_V7
 832         select GENERIC_CLOCKEVENTS
 833         select GENERIC_GPIO
 834         select HAVE_CLK
 835         select HAVE_S3C2410_I2C if I2C
 836         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 837         select HAVE_S3C_RTC if RTC_CLASS
 838         select NEED_MACH_GPIO_H
 839         select NEED_MACH_MEMORY_H
 840         help
 841           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 842
 843 config ARCH_SHARK
 844         bool "Shark"
 845         select ARCH_USES_GETTIMEOFFSET
 846         select CPU_SA110
 847         select ISA
 848         select ISA_DMA
 849         select NEED_MACH_MEMORY_H
 850         select PCI
 851         select ZONE_DMA
 852         help
 853           Support for the StrongARM based Digital DNARD machine, also known
 854           as "Shark" (<http://www.shark-linux.de/shark.html>).
 855
 856 config ARCH_U300
 857         bool "ST-Ericsson U300 Series"
 858         depends on MMU
 859         select ARCH_REQUIRE_GPIOLIB
 860         select ARM_AMBA
 861         select ARM_PATCH_PHYS_VIRT
 862         select ARM_VIC
 863         select CLKDEV_LOOKUP
 864         select CLKSRC_MMIO
 865         select COMMON_CLK
 866         select CPU_ARM926T
 867         select GENERIC_CLOCKEVENTS
 868         select GENERIC_GPIO
 869         select HAVE_TCM
 870         select SPARSE_IRQ
 871         help
 872           Support for ST-Ericsson U300 series mobile platforms.
 873
 874 config ARCH_U8500
 875         bool "ST-Ericsson U8500 Series"
 876         depends on MMU
 877         select ARCH_HAS_CPUFREQ
 878         select ARCH_REQUIRE_GPIOLIB
 879         select ARM_AMBA
 880         select CLKDEV_LOOKUP
 881         select CPU_V7
 882         select GENERIC_CLOCKEVENTS
 883         select HAVE_SMP
 884         select MIGHT_HAVE_CACHE_L2X0
 885         help
 886           Support for ST-Ericsson's Ux500 architecture
 887
 888 config ARCH_NOMADIK
 889         bool "STMicroelectronics Nomadik"
 890         select ARCH_REQUIRE_GPIOLIB
 891         select ARM_AMBA
 892         select ARM_VIC
 893         select COMMON_CLK
 894         select CPU_ARM926T
 895         select GENERIC_CLOCKEVENTS
 896         select MIGHT_HAVE_CACHE_L2X0
 897         select PINCTRL
 898         select PINCTRL_STN8815
 899         help
 900           Support for the Nomadik platform by ST-Ericsson
 901
 902 config PLAT_SPEAR
 903         bool "ST SPEAr"
 904         select ARCH_REQUIRE_GPIOLIB
 905         select ARM_AMBA
 906         select CLKDEV_LOOKUP
 907         select CLKSRC_MMIO
 908         select COMMON_CLK
 909         select GENERIC_CLOCKEVENTS
 910         select HAVE_CLK
 911         help
 912           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 913
 914 config ARCH_DAVINCI
 915         bool "TI DaVinci"
 916         select ARCH_HAS_HOLES_MEMORYMODEL
 917         select ARCH_REQUIRE_GPIOLIB
 918         select CLKDEV_LOOKUP
 919         select GENERIC_ALLOCATOR
 920         select GENERIC_CLOCKEVENTS
 921         select GENERIC_IRQ_CHIP
 922         select HAVE_IDE
 923         select NEED_MACH_GPIO_H
 924         select ZONE_DMA
 925         help
 926           Support for TI's DaVinci platform.
 927
 928 config ARCH_OMAP
 929         bool "TI OMAP"
 930         depends on MMU
 931         select ARCH_HAS_CPUFREQ
 932         select ARCH_HAS_HOLES_MEMORYMODEL
 933         select ARCH_REQUIRE_GPIOLIB
 934         select CLKSRC_MMIO
 935         select GENERIC_CLOCKEVENTS
 936         select HAVE_CLK
 937         select NEED_MACH_GPIO_H
 938         help
 939           Support for TI's OMAP platform (OMAP1/2/3/4).
 940
 941 config ARCH_VT8500
 942         bool "VIA/WonderMedia 85xx"
 943         select ARCH_HAS_CPUFREQ
 944         select ARCH_REQUIRE_GPIOLIB
 945         select CLKDEV_LOOKUP
 946         select COMMON_CLK
 947         select CPU_ARM926T
 948         select GENERIC_CLOCKEVENTS
 949         select GENERIC_GPIO
 950         select HAVE_CLK
 951         select USE_OF
 952         help
 953           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 954
 955 config ARCH_ZYNQ
 956         bool "Xilinx Zynq ARM Cortex A9 Platform"
 957         select ARM_AMBA
 958         select ARM_GIC
 959         select CLKDEV_LOOKUP
 960         select CPU_V7
 961         select GENERIC_CLOCKEVENTS
 962         select ICST
 963         select MIGHT_HAVE_CACHE_L2X0
 964         select USE_OF
 965         help
 966           Support for Xilinx Zynq ARM Cortex A9 Platform
 967 endchoice
 968
 969 menu "Multiple platform selection"
 970         depends on ARCH_MULTIPLATFORM
 971
 972 comment "CPU Core family selection"
 973
 974 config ARCH_MULTI_V4
 975         bool "ARMv4 based platforms (FA526, StrongARM)"
 976         depends on !ARCH_MULTI_V6_V7
 977         select ARCH_MULTI_V4_V5
 978
 979 config ARCH_MULTI_V4T
 980         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 981         depends on !ARCH_MULTI_V6_V7
 982         select ARCH_MULTI_V4_V5
 983
 984 config ARCH_MULTI_V5
 985         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 986         depends on !ARCH_MULTI_V6_V7
 987         select ARCH_MULTI_V4_V5
 988
 989 config ARCH_MULTI_V4_V5
 990         bool
 991
 992 config ARCH_MULTI_V6
 993         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 994         select ARCH_MULTI_V6_V7
 995         select CPU_V6
 996
 997 config ARCH_MULTI_V7
 998         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 999         default y
1000         select ARCH_MULTI_V6_V7
1001         select ARCH_VEXPRESS
1002         select CPU_V7
1003
1004 config ARCH_MULTI_V6_V7
1005         bool
1006
1007 config ARCH_MULTI_CPU_AUTO
1008         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1009         select ARCH_MULTI_V5
1010
1011 endmenu
1012
1013 #
1014 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1015 # Kconfigs may be included either alphabetically (according to the
1016 # plat- suffix) or along side the corresponding mach-* source.
1017 #
1018 source "arch/arm/mach-mvebu/Kconfig"
1019
1020 source "arch/arm/mach-at91/Kconfig"
1021
1022 source "arch/arm/mach-clps711x/Kconfig"
1023
1024 source "arch/arm/mach-cns3xxx/Kconfig"
1025
1026 source "arch/arm/mach-davinci/Kconfig"
1027
1028 source "arch/arm/mach-dove/Kconfig"
1029
1030 source "arch/arm/mach-ep93xx/Kconfig"
1031
1032 source "arch/arm/mach-footbridge/Kconfig"
1033
1034 source "arch/arm/mach-gemini/Kconfig"
1035
1036 source "arch/arm/mach-h720x/Kconfig"
1037
1038 source "arch/arm/mach-highbank/Kconfig"
1039
1040 source "arch/arm/mach-integrator/Kconfig"
1041
1042 source "arch/arm/mach-iop32x/Kconfig"
1043
1044 source "arch/arm/mach-iop33x/Kconfig"
1045
1046 source "arch/arm/mach-iop13xx/Kconfig"
1047
1048 source "arch/arm/mach-ixp4xx/Kconfig"
1049
1050 source "arch/arm/mach-kirkwood/Kconfig"
1051
1052 source "arch/arm/mach-ks8695/Kconfig"
1053
1054 source "arch/arm/mach-msm/Kconfig"
1055
1056 source "arch/arm/mach-mv78xx0/Kconfig"
1057
1058 source "arch/arm/plat-mxc/Kconfig"
1059
1060 source "arch/arm/mach-mxs/Kconfig"
1061
1062 source "arch/arm/mach-netx/Kconfig"
1063
1064 source "arch/arm/mach-nomadik/Kconfig"
1065 source "arch/arm/plat-nomadik/Kconfig"
1066
1067 source "arch/arm/plat-omap/Kconfig"
1068
1069 source "arch/arm/mach-omap1/Kconfig"
1070
1071 source "arch/arm/mach-omap2/Kconfig"
1072
1073 source "arch/arm/mach-orion5x/Kconfig"
1074
1075 source "arch/arm/mach-picoxcell/Kconfig"
1076
1077 source "arch/arm/mach-pxa/Kconfig"
1078 source "arch/arm/plat-pxa/Kconfig"
1079
1080 source "arch/arm/mach-mmp/Kconfig"
1081
1082 source "arch/arm/mach-realview/Kconfig"
1083
1084 source "arch/arm/mach-sa1100/Kconfig"
1085
1086 source "arch/arm/plat-samsung/Kconfig"
1087 source "arch/arm/plat-s3c24xx/Kconfig"
1088
1089 source "arch/arm/mach-socfpga/Kconfig"
1090
1091 source "arch/arm/plat-spear/Kconfig"
1092
1093 source "arch/arm/mach-s3c24xx/Kconfig"
1094 if ARCH_S3C24XX
1095 source "arch/arm/mach-s3c2412/Kconfig"
1096 source "arch/arm/mach-s3c2440/Kconfig"
1097 endif
1098
1099 if ARCH_S3C64XX
1100 source "arch/arm/mach-s3c64xx/Kconfig"
1101 endif
1102
1103 source "arch/arm/mach-s5p64x0/Kconfig"
1104
1105 source "arch/arm/mach-s5pc100/Kconfig"
1106
1107 source "arch/arm/mach-s5pv210/Kconfig"
1108
1109 source "arch/arm/mach-exynos/Kconfig"
1110
1111 source "arch/arm/mach-shmobile/Kconfig"
1112
1113 source "arch/arm/mach-prima2/Kconfig"
1114
1115 source "arch/arm/mach-tegra/Kconfig"
1116
1117 source "arch/arm/mach-u300/Kconfig"
1118
1119 source "arch/arm/mach-ux500/Kconfig"
1120
1121 source "arch/arm/mach-versatile/Kconfig"
1122
1123 source "arch/arm/mach-vexpress/Kconfig"
1124 source "arch/arm/plat-versatile/Kconfig"
1125
1126 source "arch/arm/mach-w90x900/Kconfig"
1127
1128 # Definitions to make life easier
1129 config ARCH_ACORN
1130         bool
1131
1132 config PLAT_IOP
1133         bool
1134         select GENERIC_CLOCKEVENTS
1135
1136 config PLAT_ORION
1137         bool
1138         select CLKSRC_MMIO
1139         select COMMON_CLK
1140         select GENERIC_IRQ_CHIP
1141         select IRQ_DOMAIN
1142
1143 config PLAT_ORION_LEGACY
1144         bool
1145         select PLAT_ORION
1146
1147 config PLAT_PXA
1148         bool
1149
1150 config PLAT_VERSATILE
1151         bool
1152
1153 config ARM_TIMER_SP804
1154         bool
1155         select CLKSRC_MMIO
1156         select HAVE_SCHED_CLOCK
1157
1158 source arch/arm/mm/Kconfig
1159
1160 config ARM_NR_BANKS
1161         int
1162         default 16 if ARCH_EP93XX
1163         default 8
1164
1165 config IWMMXT
1166         bool "Enable iWMMXt support"
1167         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1168         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1169         help
1170           Enable support for iWMMXt context switching at run time if
1171           running on a CPU that supports it.
1172
1173 config XSCALE_PMU
1174         bool
1175         depends on CPU_XSCALE
1176         default y
1177
1178 config MULTI_IRQ_HANDLER
1179         bool
1180         help
1181           Allow each machine to specify it's own IRQ handler at run time.
1182
1183 if !MMU
1184 source "arch/arm/Kconfig-nommu"
1185 endif
1186
1187 config ARM_ERRATA_326103
1188         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1189         depends on CPU_V6
1190         help
1191           Executing a SWP instruction to read-only memory does not set bit 11
1192           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1193           treat the access as a read, preventing a COW from occurring and
1194           causing the faulting task to livelock.
1195
1196 config ARM_ERRATA_411920
1197         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1198         depends on CPU_V6 || CPU_V6K
1199         help
1200           Invalidation of the Instruction Cache operation can
1201           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1202           It does not affect the MPCore. This option enables the ARM Ltd.
1203           recommended workaround.
1204
1205 config ARM_ERRATA_430973
1206         bool "ARM errata: Stale prediction on replaced interworking branch"
1207         depends on CPU_V7
1208         help
1209           This option enables the workaround for the 430973 Cortex-A8
1210           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1211           interworking branch is replaced with another code sequence at the
1212           same virtual address, whether due to self-modifying code or virtual
1213           to physical address re-mapping, Cortex-A8 does not recover from the
1214           stale interworking branch prediction. This results in Cortex-A8
1215           executing the new code sequence in the incorrect ARM or Thumb state.
1216           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1217           and also flushes the branch target cache at every context switch.
1218           Note that setting specific bits in the ACTLR register may not be
1219           available in non-secure mode.
1220
1221 config ARM_ERRATA_458693
1222         bool "ARM errata: Processor deadlock when a false hazard is created"
1223         depends on CPU_V7
1224         help
1225           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1226           erratum. For very specific sequences of memory operations, it is
1227           possible for a hazard condition intended for a cache line to instead
1228           be incorrectly associated with a different cache line. This false
1229           hazard might then cause a processor deadlock. The workaround enables
1230           the L1 caching of the NEON accesses and disables the PLD instruction
1231           in the ACTLR register. Note that setting specific bits in the ACTLR
1232           register may not be available in non-secure mode.
1233
1234 config ARM_ERRATA_460075
1235         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1236         depends on CPU_V7
1237         help
1238           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1239           erratum. Any asynchronous access to the L2 cache may encounter a
1240           situation in which recent store transactions to the L2 cache are lost
1241           and overwritten with stale memory contents from external memory. The
1242           workaround disables the write-allocate mode for the L2 cache via the
1243           ACTLR register. Note that setting specific bits in the ACTLR register
1244           may not be available in non-secure mode.
1245
1246 config ARM_ERRATA_742230
1247         bool "ARM errata: DMB operation may be faulty"
1248         depends on CPU_V7 && SMP
1249         help
1250           This option enables the workaround for the 742230 Cortex-A9
1251           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1252           between two write operations may not ensure the correct visibility
1253           ordering of the two writes. This workaround sets a specific bit in
1254           the diagnostic register of the Cortex-A9 which causes the DMB
1255           instruction to behave as a DSB, ensuring the correct behaviour of
1256           the two writes.
1257
1258 config ARM_ERRATA_742231
1259         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1260         depends on CPU_V7 && SMP
1261         help
1262           This option enables the workaround for the 742231 Cortex-A9
1263           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1264           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1265           accessing some data located in the same cache line, may get corrupted
1266           data due to bad handling of the address hazard when the line gets
1267           replaced from one of the CPUs at the same time as another CPU is
1268           accessing it. This workaround sets specific bits in the diagnostic
1269           register of the Cortex-A9 which reduces the linefill issuing
1270           capabilities of the processor.
1271
1272 config PL310_ERRATA_588369
1273         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1274         depends on CACHE_L2X0
1275         help
1276            The PL310 L2 cache controller implements three types of Clean &
1277            Invalidate maintenance operations: by Physical Address
1278            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1279            They are architecturally defined to behave as the execution of a
1280            clean operation followed immediately by an invalidate operation,
1281            both performing to the same memory location. This functionality
1282            is not correctly implemented in PL310 as clean lines are not
1283            invalidated as a result of these operations.
1284
1285 config ARM_ERRATA_720789
1286         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1287         depends on CPU_V7
1288         help
1289           This option enables the workaround for the 720789 Cortex-A9 (prior to
1290           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1291           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1292           As a consequence of this erratum, some TLB entries which should be
1293           invalidated are not, resulting in an incoherency in the system page
1294           tables. The workaround changes the TLB flushing routines to invalidate
1295           entries regardless of the ASID.
1296
1297 config PL310_ERRATA_727915
1298         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1299         depends on CACHE_L2X0
1300         help
1301           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1302           operation (offset 0x7FC). This operation runs in background so that
1303           PL310 can handle normal accesses while it is in progress. Under very
1304           rare circumstances, due to this erratum, write data can be lost when
1305           PL310 treats a cacheable write transaction during a Clean &
1306           Invalidate by Way operation.
1307
1308 config ARM_ERRATA_743622
1309         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1310         depends on CPU_V7
1311         help
1312           This option enables the workaround for the 743622 Cortex-A9
1313           (r2p*) erratum. Under very rare conditions, a faulty
1314           optimisation in the Cortex-A9 Store Buffer may lead to data
1315           corruption. This workaround sets a specific bit in the diagnostic
1316           register of the Cortex-A9 which disables the Store Buffer
1317           optimisation, preventing the defect from occurring. This has no
1318           visible impact on the overall performance or power consumption of the
1319           processor.
1320
1321 config ARM_ERRATA_751472
1322         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1323         depends on CPU_V7
1324         help
1325           This option enables the workaround for the 751472 Cortex-A9 (prior
1326           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1327           completion of a following broadcasted operation if the second
1328           operation is received by a CPU before the ICIALLUIS has completed,
1329           potentially leading to corrupted entries in the cache or TLB.
1330
1331 config PL310_ERRATA_753970
1332         bool "PL310 errata: cache sync operation may be faulty"
1333         depends on CACHE_PL310
1334         help
1335           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1336
1337           Under some condition the effect of cache sync operation on
1338           the store buffer still remains when the operation completes.
1339           This means that the store buffer is always asked to drain and
1340           this prevents it from merging any further writes. The workaround
1341           is to replace the normal offset of cache sync operation (0x730)
1342           by another offset targeting an unmapped PL310 register 0x740.
1343           This has the same effect as the cache sync operation: store buffer
1344           drain and waiting for all buffers empty.
1345
1346 config ARM_ERRATA_754322
1347         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1348         depends on CPU_V7
1349         help
1350           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1351           r3p*) erratum. A speculative memory access may cause a page table walk
1352           which starts prior to an ASID switch but completes afterwards. This
1353           can populate the micro-TLB with a stale entry which may be hit with
1354           the new ASID. This workaround places two dsb instructions in the mm
1355           switching code so that no page table walks can cross the ASID switch.
1356
1357 config ARM_ERRATA_754327
1358         bool "ARM errata: no automatic Store Buffer drain"
1359         depends on CPU_V7 && SMP
1360         help
1361           This option enables the workaround for the 754327 Cortex-A9 (prior to
1362           r2p0) erratum. The Store Buffer does not have any automatic draining
1363           mechanism and therefore a livelock may occur if an external agent
1364           continuously polls a memory location waiting to observe an update.
1365           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1366           written polling loops from denying visibility of updates to memory.
1367
1368 config ARM_ERRATA_364296
1369         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1370         depends on CPU_V6 && !SMP
1371         help
1372           This options enables the workaround for the 364296 ARM1136
1373           r0p2 erratum (possible cache data corruption with
1374           hit-under-miss enabled). It sets the undocumented bit 31 in
1375           the auxiliary control register and the FI bit in the control
1376           register, thus disabling hit-under-miss without putting the
1377           processor into full low interrupt latency mode. ARM11MPCore
1378           is not affected.
1379
1380 config ARM_ERRATA_764369
1381         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1382         depends on CPU_V7 && SMP
1383         help
1384           This option enables the workaround for erratum 764369
1385           affecting Cortex-A9 MPCore with two or more processors (all
1386           current revisions). Under certain timing circumstances, a data
1387           cache line maintenance operation by MVA targeting an Inner
1388           Shareable memory region may fail to proceed up to either the
1389           Point of Coherency or to the Point of Unification of the
1390           system. This workaround adds a DSB instruction before the
1391           relevant cache maintenance functions and sets a specific bit
1392           in the diagnostic control register of the SCU.
1393
1394 config PL310_ERRATA_769419
1395         bool "PL310 errata: no automatic Store Buffer drain"
1396         depends on CACHE_L2X0
1397         help
1398           On revisions of the PL310 prior to r3p2, the Store Buffer does
1399           not automatically drain. This can cause normal, non-cacheable
1400           writes to be retained when the memory system is idle, leading
1401           to suboptimal I/O performance for drivers using coherent DMA.
1402           This option adds a write barrier to the cpu_idle loop so that,
1403           on systems with an outer cache, the store buffer is drained
1404           explicitly.
1405
1406 config ARM_ERRATA_775420
1407        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1408        depends on CPU_V7
1409        help
1410          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1411          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1412          operation aborts with MMU exception, it might cause the processor
1413          to deadlock. This workaround puts DSB before executing ISB if
1414          an abort may occur on cache maintenance.
1415
1416 endmenu
1417
1418 source "arch/arm/common/Kconfig"
1419
1420 menu "Bus support"
1421
1422 config ARM_AMBA
1423         bool
1424
1425 config ISA
1426         bool
1427         help
1428           Find out whether you have ISA slots on your motherboard.  ISA is the
1429           name of a bus system, i.e. the way the CPU talks to the other stuff
1430           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1431           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1432           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1433
1434 # Select ISA DMA controller support
1435 config ISA_DMA
1436         bool
1437         select ISA_DMA_API
1438
1439 # Select ISA DMA interface
1440 config ISA_DMA_API
1441         bool
1442
1443 config PCI
1444         bool "PCI support" if MIGHT_HAVE_PCI
1445         help
1446           Find out whether you have a PCI motherboard. PCI is the name of a
1447           bus system, i.e. the way the CPU talks to the other stuff inside
1448           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1449           VESA. If you have PCI, say Y, otherwise N.
1450
1451 config PCI_DOMAINS
1452         bool
1453         depends on PCI
1454
1455 config PCI_NANOENGINE
1456         bool "BSE nanoEngine PCI support"
1457         depends on SA1100_NANOENGINE
1458         help
1459           Enable PCI on the BSE nanoEngine board.
1460
1461 config PCI_SYSCALL
1462         def_bool PCI
1463
1464 # Select the host bridge type
1465 config PCI_HOST_VIA82C505
1466         bool
1467         depends on PCI && ARCH_SHARK
1468         default y
1469
1470 config PCI_HOST_ITE8152
1471         bool
1472         depends on PCI && MACH_ARMCORE
1473         default y
1474         select DMABOUNCE
1475
1476 source "drivers/pci/Kconfig"
1477
1478 source "drivers/pcmcia/Kconfig"
1479
1480 endmenu
1481
1482 menu "Kernel Features"
1483
1484 config HAVE_SMP
1485         bool
1486         help
1487           This option should be selected by machines which have an SMP-
1488           capable CPU.
1489
1490           The only effect of this option is to make the SMP-related
1491           options available to the user for configuration.
1492
1493 config SMP
1494         bool "Symmetric Multi-Processing"
1495         depends on CPU_V6K || CPU_V7
1496         depends on GENERIC_CLOCKEVENTS
1497         depends on HAVE_SMP
1498         depends on MMU
1499         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1500         select USE_GENERIC_SMP_HELPERS
1501         help
1502           This enables support for systems with more than one CPU. If you have
1503           a system with only one CPU, like most personal computers, say N. If
1504           you have a system with more than one CPU, say Y.
1505
1506           If you say N here, the kernel will run on single and multiprocessor
1507           machines, but will use only one CPU of a multiprocessor machine. If
1508           you say Y here, the kernel will run on many, but not all, single
1509           processor machines. On a single processor machine, the kernel will
1510           run faster if you say N here.
1511
1512           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1513           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1514           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1515
1516           If you don't know what to do here, say N.
1517
1518 config SMP_ON_UP
1519         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1520         depends on EXPERIMENTAL
1521         depends on SMP && !XIP_KERNEL
1522         default y
1523         help
1524           SMP kernels contain instructions which fail on non-SMP processors.
1525           Enabling this option allows the kernel to modify itself to make
1526           these instructions safe.  Disabling it allows about 1K of space
1527           savings.
1528
1529           If you don't know what to do here, say Y.
1530
1531 config ARM_CPU_TOPOLOGY
1532         bool "Support cpu topology definition"
1533         depends on SMP && CPU_V7
1534         default y
1535         help
1536           Support ARM cpu topology definition. The MPIDR register defines
1537           affinity between processors which is then used to describe the cpu
1538           topology of an ARM System.
1539
1540 config SCHED_MC
1541         bool "Multi-core scheduler support"
1542         depends on ARM_CPU_TOPOLOGY
1543         help
1544           Multi-core scheduler support improves the CPU scheduler's decision
1545           making when dealing with multi-core CPU chips at a cost of slightly
1546           increased overhead in some places. If unsure say N here.
1547
1548 config SCHED_SMT
1549         bool "SMT scheduler support"
1550         depends on ARM_CPU_TOPOLOGY
1551         help
1552           Improves the CPU scheduler's decision making when dealing with
1553           MultiThreading at a cost of slightly increased overhead in some
1554           places. If unsure say N here.
1555
1556 config HAVE_ARM_SCU
1557         bool
1558         help
1559           This option enables support for the ARM system coherency unit
1560
1561 config ARM_ARCH_TIMER
1562         bool "Architected timer support"
1563         depends on CPU_V7
1564         help
1565           This option enables support for the ARM architected timer
1566
1567 config HAVE_ARM_TWD
1568         bool
1569         depends on SMP
1570         help
1571           This options enables support for the ARM timer and watchdog unit
1572
1573 choice
1574         prompt "Memory split"
1575         default VMSPLIT_3G
1576         help
1577           Select the desired split between kernel and user memory.
1578
1579           If you are not absolutely sure what you are doing, leave this
1580           option alone!
1581
1582         config VMSPLIT_3G
1583                 bool "3G/1G user/kernel split"
1584         config VMSPLIT_2G
1585                 bool "2G/2G user/kernel split"
1586         config VMSPLIT_1G
1587                 bool "1G/3G user/kernel split"
1588 endchoice
1589
1590 config PAGE_OFFSET
1591         hex
1592         default 0x40000000 if VMSPLIT_1G
1593         default 0x80000000 if VMSPLIT_2G
1594         default 0xC0000000
1595
1596 config NR_CPUS
1597         int "Maximum number of CPUs (2-32)"
1598         range 2 32
1599         depends on SMP
1600         default "4"
1601
1602 config HOTPLUG_CPU
1603         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1604         depends on SMP && HOTPLUG && EXPERIMENTAL
1605         help
1606           Say Y here to experiment with turning CPUs off and on.  CPUs
1607           can be controlled through /sys/devices/system/cpu.
1608
1609 config LOCAL_TIMERS
1610         bool "Use local timer interrupts"
1611         depends on SMP
1612         default y
1613         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1614         help
1615           Enable support for local timers on SMP platforms, rather then the
1616           legacy IPI broadcast method.  Local timers allows the system
1617           accounting to be spread across the timer interval, preventing a
1618           "thundering herd" at every timer tick.
1619
1620 config ARCH_NR_GPIO
1621         int
1622         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1623         default 355 if ARCH_U8500
1624         default 264 if MACH_H4700
1625         default 512 if SOC_OMAP5
1626         default 288 if ARCH_VT8500
1627         default 0
1628         help
1629           Maximum number of GPIOs in the system.
1630
1631           If unsure, leave the default value.
1632
1633 source kernel/Kconfig.preempt
1634
1635 config HZ
1636         int
1637         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1638                 ARCH_S5PV210 || ARCH_EXYNOS4
1639         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1640         default AT91_TIMER_HZ if ARCH_AT91
1641         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1642         default 100
1643
1644 config THUMB2_KERNEL
1645         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1646         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1647         select AEABI
1648         select ARM_ASM_UNIFIED
1649         select ARM_UNWIND
1650         help
1651           By enabling this option, the kernel will be compiled in
1652           Thumb-2 mode. A compiler/assembler that understand the unified
1653           ARM-Thumb syntax is needed.
1654
1655           If unsure, say N.
1656
1657 config THUMB2_AVOID_R_ARM_THM_JUMP11
1658         bool "Work around buggy Thumb-2 short branch relocations in gas"
1659         depends on THUMB2_KERNEL && MODULES
1660         default y
1661         help
1662           Various binutils versions can resolve Thumb-2 branches to
1663           locally-defined, preemptible global symbols as short-range "b.n"
1664           branch instructions.
1665
1666           This is a problem, because there's no guarantee the final
1667           destination of the symbol, or any candidate locations for a
1668           trampoline, are within range of the branch.  For this reason, the
1669           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1670           relocation in modules at all, and it makes little sense to add
1671           support.
1672
1673           The symptom is that the kernel fails with an "unsupported
1674           relocation" error when loading some modules.
1675
1676           Until fixed tools are available, passing
1677           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1678           code which hits this problem, at the cost of a bit of extra runtime
1679           stack usage in some cases.
1680
1681           The problem is described in more detail at:
1682               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1683
1684           Only Thumb-2 kernels are affected.
1685
1686           Unless you are sure your tools don't have this problem, say Y.
1687
1688 config ARM_ASM_UNIFIED
1689         bool
1690
1691 config AEABI
1692         bool "Use the ARM EABI to compile the kernel"
1693         help
1694           This option allows for the kernel to be compiled using the latest
1695           ARM ABI (aka EABI).  This is only useful if you are using a user
1696           space environment that is also compiled with EABI.
1697
1698           Since there are major incompatibilities between the legacy ABI and
1699           EABI, especially with regard to structure member alignment, this
1700           option also changes the kernel syscall calling convention to
1701           disambiguate both ABIs and allow for backward compatibility support
1702           (selected with CONFIG_OABI_COMPAT).
1703
1704           To use this you need GCC version 4.0.0 or later.
1705
1706 config OABI_COMPAT
1707         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1708         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1709         default y
1710         help
1711           This option preserves the old syscall interface along with the
1712           new (ARM EABI) one. It also provides a compatibility layer to
1713           intercept syscalls that have structure arguments which layout
1714           in memory differs between the legacy ABI and the new ARM EABI
1715           (only for non "thumb" binaries). This option adds a tiny
1716           overhead to all syscalls and produces a slightly larger kernel.
1717           If you know you'll be using only pure EABI user space then you
1718           can say N here. If this option is not selected and you attempt
1719           to execute a legacy ABI binary then the result will be
1720           UNPREDICTABLE (in fact it can be predicted that it won't work
1721           at all). If in doubt say Y.
1722
1723 config ARCH_HAS_HOLES_MEMORYMODEL
1724         bool
1725
1726 config ARCH_SPARSEMEM_ENABLE
1727         bool
1728
1729 config ARCH_SPARSEMEM_DEFAULT
1730         def_bool ARCH_SPARSEMEM_ENABLE
1731
1732 config ARCH_SELECT_MEMORY_MODEL
1733         def_bool ARCH_SPARSEMEM_ENABLE
1734
1735 config HAVE_ARCH_PFN_VALID
1736         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737
1738 config HIGHMEM
1739         bool "High Memory Support"
1740         depends on MMU
1741         help
1742           The address space of ARM processors is only 4 Gigabytes large
1743           and it has to accommodate user address space, kernel address
1744           space as well as some memory mapped IO. That means that, if you
1745           have a large amount of physical memory and/or IO, not all of the
1746           memory can be "permanently mapped" by the kernel. The physical
1747           memory that is not permanently mapped is called "high memory".
1748
1749           Depending on the selected kernel/user memory split, minimum
1750           vmalloc space and actual amount of RAM, you may not need this
1751           option which should result in a slightly faster kernel.
1752
1753           If unsure, say n.
1754
1755 config HIGHPTE
1756         bool "Allocate 2nd-level pagetables from highmem"
1757         depends on HIGHMEM
1758
1759 config HW_PERF_EVENTS
1760         bool "Enable hardware performance counter support for perf events"
1761         depends on PERF_EVENTS
1762         default y
1763         help
1764           Enable hardware performance counter support for perf events. If
1765           disabled, perf events will use software events only.
1766
1767 source "mm/Kconfig"
1768
1769 config FORCE_MAX_ZONEORDER
1770         int "Maximum zone order" if ARCH_SHMOBILE
1771         range 11 64 if ARCH_SHMOBILE
1772         default "12" if SOC_AM33XX
1773         default "9" if SA1111
1774         default "11"
1775         help
1776           The kernel memory allocator divides physically contiguous memory
1777           blocks into "zones", where each zone is a power of two number of
1778           pages.  This option selects the largest power of two that the kernel
1779           keeps in the memory allocator.  If you need to allocate very large
1780           blocks of physically contiguous memory, then you may need to
1781           increase this value.
1782
1783           This config option is actually maximum order plus one. For example,
1784           a value of 11 means that the largest free memory block is 2^10 pages.
1785
1786 config ALIGNMENT_TRAP
1787         bool
1788         depends on CPU_CP15_MMU
1789         default y if !ARCH_EBSA110
1790         select HAVE_PROC_CPU if PROC_FS
1791         help
1792           ARM processors cannot fetch/store information which is not
1793           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1794           address divisible by 4. On 32-bit ARM processors, these non-aligned
1795           fetch/store instructions will be emulated in software if you say
1796           here, which has a severe performance impact. This is necessary for
1797           correct operation of some network protocols. With an IP-only
1798           configuration it is safe to say N, otherwise say Y.
1799
1800 config UACCESS_WITH_MEMCPY
1801         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1802         depends on MMU
1803         default y if CPU_FEROCEON
1804         help
1805           Implement faster copy_to_user and clear_user methods for CPU
1806           cores where a 8-word STM instruction give significantly higher
1807           memory write throughput than a sequence of individual 32bit stores.
1808
1809           A possible side effect is a slight increase in scheduling latency
1810           between threads sharing the same address space if they invoke
1811           such copy operations with large buffers.
1812
1813           However, if the CPU data cache is using a write-allocate mode,
1814           this option is unlikely to provide any performance gain.
1815
1816 config SECCOMP
1817         bool
1818         prompt "Enable seccomp to safely compute untrusted bytecode"
1819         ---help---
1820           This kernel feature is useful for number crunching applications
1821           that may need to compute untrusted bytecode during their
1822           execution. By using pipes or other transports made available to
1823           the process as file descriptors supporting the read/write
1824           syscalls, it's possible to isolate those applications in
1825           their own address space using seccomp. Once seccomp is
1826           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1827           and the task is only allowed to execute a few safe syscalls
1828           defined by each seccomp mode.
1829
1830 config CC_STACKPROTECTOR
1831         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1832         depends on EXPERIMENTAL
1833         help
1834           This option turns on the -fstack-protector GCC feature. This
1835           feature puts, at the beginning of functions, a canary value on
1836           the stack just before the return address, and validates
1837           the value just before actually returning.  Stack based buffer
1838           overflows (that need to overwrite this return address) now also
1839           overwrite the canary, which gets detected and the attack is then
1840           neutralized via a kernel panic.
1841           This feature requires gcc version 4.2 or above.
1842
1843 config XEN_DOM0
1844         def_bool y
1845         depends on XEN
1846
1847 config XEN
1848         bool "Xen guest support on ARM (EXPERIMENTAL)"
1849         depends on EXPERIMENTAL && ARM && OF
1850         help
1851           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1852
1853 endmenu
1854
1855 menu "Boot options"
1856
1857 config USE_OF
1858         bool "Flattened Device Tree support"
1859         select IRQ_DOMAIN
1860         select OF
1861         select OF_EARLY_FLATTREE
1862         help
1863           Include support for flattened device tree machine descriptions.
1864
1865 config ATAGS
1866         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1867         default y
1868         help
1869           This is the traditional way of passing data to the kernel at boot
1870           time. If you are solely relying on the flattened device tree (or
1871           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1872           to remove ATAGS support from your kernel binary.  If unsure,
1873           leave this to y.
1874
1875 config DEPRECATED_PARAM_STRUCT
1876         bool "Provide old way to pass kernel parameters"
1877         depends on ATAGS
1878         help
1879           This was deprecated in 2001 and announced to live on for 5 years.
1880           Some old boot loaders still use this way.
1881
1882 # Compressed boot loader in ROM.  Yes, we really want to ask about
1883 # TEXT and BSS so we preserve their values in the config files.
1884 config ZBOOT_ROM_TEXT
1885         hex "Compressed ROM boot loader base address"
1886         default "0"
1887         help
1888           The physical address at which the ROM-able zImage is to be
1889           placed in the target.  Platforms which normally make use of
1890           ROM-able zImage formats normally set this to a suitable
1891           value in their defconfig file.
1892
1893           If ZBOOT_ROM is not enabled, this has no effect.
1894
1895 config ZBOOT_ROM_BSS
1896         hex "Compressed ROM boot loader BSS address"
1897         default "0"
1898         help
1899           The base address of an area of read/write memory in the target
1900           for the ROM-able zImage which must be available while the
1901           decompressor is running. It must be large enough to hold the
1902           entire decompressed kernel plus an additional 128 KiB.
1903           Platforms which normally make use of ROM-able zImage formats
1904           normally set this to a suitable value in their defconfig file.
1905
1906           If ZBOOT_ROM is not enabled, this has no effect.
1907
1908 config ZBOOT_ROM
1909         bool "Compressed boot loader in ROM/flash"
1910         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1911         help
1912           Say Y here if you intend to execute your compressed kernel image
1913           (zImage) directly from ROM or flash.  If unsure, say N.
1914
1915 choice
1916         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1917         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1918         default ZBOOT_ROM_NONE
1919         help
1920           Include experimental SD/MMC loading code in the ROM-able zImage.
1921           With this enabled it is possible to write the ROM-able zImage
1922           kernel image to an MMC or SD card and boot the kernel straight
1923           from the reset vector. At reset the processor Mask ROM will load
1924           the first part of the ROM-able zImage which in turn loads the
1925           rest the kernel image to RAM.
1926
1927 config ZBOOT_ROM_NONE
1928         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1929         help
1930           Do not load image from SD or MMC
1931
1932 config ZBOOT_ROM_MMCIF
1933         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1934         help
1935           Load image from MMCIF hardware block.
1936
1937 config ZBOOT_ROM_SH_MOBILE_SDHI
1938         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1939         help
1940           Load image from SDHI hardware block
1941
1942 endchoice
1943
1944 config ARM_APPENDED_DTB
1945         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1946         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1947         help
1948           With this option, the boot code will look for a device tree binary
1949           (DTB) appended to zImage
1950           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1951
1952           This is meant as a backward compatibility convenience for those
1953           systems with a bootloader that can't be upgraded to accommodate
1954           the documented boot protocol using a device tree.
1955
1956           Beware that there is very little in terms of protection against
1957           this option being confused by leftover garbage in memory that might
1958           look like a DTB header after a reboot if no actual DTB is appended
1959           to zImage.  Do not leave this option active in a production kernel
1960           if you don't intend to always append a DTB.  Proper passing of the
1961           location into r2 of a bootloader provided DTB is always preferable
1962           to this option.
1963
1964 config ARM_ATAG_DTB_COMPAT
1965         bool "Supplement the appended DTB with traditional ATAG information"
1966         depends on ARM_APPENDED_DTB
1967         help
1968           Some old bootloaders can't be updated to a DTB capable one, yet
1969           they provide ATAGs with memory configuration, the ramdisk address,
1970           the kernel cmdline string, etc.  Such information is dynamically
1971           provided by the bootloader and can't always be stored in a static
1972           DTB.  To allow a device tree enabled kernel to be used with such
1973           bootloaders, this option allows zImage to extract the information
1974           from the ATAG list and store it at run time into the appended DTB.
1975
1976 choice
1977         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1978         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1979
1980 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1981         bool "Use bootloader kernel arguments if available"
1982         help
1983           Uses the command-line options passed by the boot loader instead of
1984           the device tree bootargs property. If the boot loader doesn't provide
1985           any, the device tree bootargs property will be used.
1986
1987 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1988         bool "Extend with bootloader kernel arguments"
1989         help
1990           The command-line arguments provided by the boot loader will be
1991           appended to the the device tree bootargs property.
1992
1993 endchoice
1994
1995 config CMDLINE
1996         string "Default kernel command string"
1997         default ""
1998         help
1999           On some architectures (EBSA110 and CATS), there is currently no way
2000           for the boot loader to pass arguments to the kernel. For these
2001           architectures, you should supply some command-line options at build
2002           time by entering them here. As a minimum, you should specify the
2003           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2004
2005 choice
2006         prompt "Kernel command line type" if CMDLINE != ""
2007         default CMDLINE_FROM_BOOTLOADER
2008         depends on ATAGS
2009
2010 config CMDLINE_FROM_BOOTLOADER
2011         bool "Use bootloader kernel arguments if available"
2012         help
2013           Uses the command-line options passed by the boot loader. If
2014           the boot loader doesn't provide any, the default kernel command
2015           string provided in CMDLINE will be used.
2016
2017 config CMDLINE_EXTEND
2018         bool "Extend bootloader kernel arguments"
2019         help
2020           The command-line arguments provided by the boot loader will be
2021           appended to the default kernel command string.
2022
2023 config CMDLINE_FORCE
2024         bool "Always use the default kernel command string"
2025         help
2026           Always use the default kernel command string, even if the boot
2027           loader passes other arguments to the kernel.
2028           This is useful if you cannot or don't want to change the
2029           command-line options your boot loader passes to the kernel.
2030 endchoice
2031
2032 config XIP_KERNEL
2033         bool "Kernel Execute-In-Place from ROM"
2034         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2035         help
2036           Execute-In-Place allows the kernel to run from non-volatile storage
2037           directly addressable by the CPU, such as NOR flash. This saves RAM
2038           space since the text section of the kernel is not loaded from flash
2039           to RAM.  Read-write sections, such as the data section and stack,
2040           are still copied to RAM.  The XIP kernel is not compressed since
2041           it has to run directly from flash, so it will take more space to
2042           store it.  The flash address used to link the kernel object files,
2043           and for storing it, is configuration dependent. Therefore, if you
2044           say Y here, you must know the proper physical address where to
2045           store the kernel image depending on your own flash memory usage.
2046
2047           Also note that the make target becomes "make xipImage" rather than
2048           "make zImage" or "make Image".  The final kernel binary to put in
2049           ROM memory will be arch/arm/boot/xipImage.
2050
2051           If unsure, say N.
2052
2053 config XIP_PHYS_ADDR
2054         hex "XIP Kernel Physical Location"
2055         depends on XIP_KERNEL
2056         default "0x00080000"
2057         help
2058           This is the physical address in your flash memory the kernel will
2059           be linked for and stored to.  This address is dependent on your
2060           own flash usage.
2061
2062 config KEXEC
2063         bool "Kexec system call (EXPERIMENTAL)"
2064         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2065         help
2066           kexec is a system call that implements the ability to shutdown your
2067           current kernel, and to start another kernel.  It is like a reboot
2068           but it is independent of the system firmware.   And like a reboot
2069           you can start any kernel with it, not just Linux.
2070
2071           It is an ongoing process to be certain the hardware in a machine
2072           is properly shutdown, so do not be surprised if this code does not
2073           initially work for you.  It may help to enable device hotplugging
2074           support.
2075
2076 config ATAGS_PROC
2077         bool "Export atags in procfs"
2078         depends on ATAGS && KEXEC
2079         default y
2080         help
2081           Should the atags used to boot the kernel be exported in an "atags"
2082           file in procfs. Useful with kexec.
2083
2084 config CRASH_DUMP
2085         bool "Build kdump crash kernel (EXPERIMENTAL)"
2086         depends on EXPERIMENTAL
2087         help
2088           Generate crash dump after being started by kexec. This should
2089           be normally only set in special crash dump kernels which are
2090           loaded in the main kernel with kexec-tools into a specially
2091           reserved region and then later executed after a crash by
2092           kdump/kexec. The crash dump kernel must be compiled to a
2093           memory address not used by the main kernel
2094
2095           For more details see Documentation/kdump/kdump.txt
2096
2097 config AUTO_ZRELADDR
2098         bool "Auto calculation of the decompressed kernel image address"
2099         depends on !ZBOOT_ROM && !ARCH_U300
2100         help
2101           ZRELADDR is the physical address where the decompressed kernel
2102           image will be placed. If AUTO_ZRELADDR is selected, the address
2103           will be determined at run-time by masking the current IP with
2104           0xf8000000. This assumes the zImage being placed in the first 128MB
2105           from start of memory.
2106
2107 endmenu
2108
2109 menu "CPU Power Management"
2110
2111 if ARCH_HAS_CPUFREQ
2112
2113 source "drivers/cpufreq/Kconfig"
2114
2115 config CPU_FREQ_IMX
2116         tristate "CPUfreq driver for i.MX CPUs"
2117         depends on ARCH_MXC && CPU_FREQ
2118         select CPU_FREQ_TABLE
2119         help
2120           This enables the CPUfreq driver for i.MX CPUs.
2121
2122 config CPU_FREQ_SA1100
2123         bool
2124
2125 config CPU_FREQ_SA1110
2126         bool
2127
2128 config CPU_FREQ_INTEGRATOR
2129         tristate "CPUfreq driver for ARM Integrator CPUs"
2130         depends on ARCH_INTEGRATOR && CPU_FREQ
2131         default y
2132         help
2133           This enables the CPUfreq driver for ARM Integrator CPUs.
2134
2135           For details, take a look at <file:Documentation/cpu-freq>.
2136
2137           If in doubt, say Y.
2138
2139 config CPU_FREQ_PXA
2140         bool
2141         depends on CPU_FREQ && ARCH_PXA && PXA25x
2142         default y
2143         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2144         select CPU_FREQ_TABLE
2145
2146 config CPU_FREQ_S3C
2147         bool
2148         help
2149           Internal configuration node for common cpufreq on Samsung SoC
2150
2151 config CPU_FREQ_S3C24XX
2152         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2153         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2154         select CPU_FREQ_S3C
2155         help
2156           This enables the CPUfreq driver for the Samsung S3C24XX family
2157           of CPUs.
2158
2159           For details, take a look at <file:Documentation/cpu-freq>.
2160
2161           If in doubt, say N.
2162
2163 config CPU_FREQ_S3C24XX_PLL
2164         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2165         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2166         help
2167           Compile in support for changing the PLL frequency from the
2168           S3C24XX series CPUfreq driver. The PLL takes time to settle
2169           after a frequency change, so by default it is not enabled.
2170
2171           This also means that the PLL tables for the selected CPU(s) will
2172           be built which may increase the size of the kernel image.
2173
2174 config CPU_FREQ_S3C24XX_DEBUG
2175         bool "Debug CPUfreq Samsung driver core"
2176         depends on CPU_FREQ_S3C24XX
2177         help
2178           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2179
2180 config CPU_FREQ_S3C24XX_IODEBUG
2181         bool "Debug CPUfreq Samsung driver IO timing"
2182         depends on CPU_FREQ_S3C24XX
2183         help
2184           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2185
2186 config CPU_FREQ_S3C24XX_DEBUGFS
2187         bool "Export debugfs for CPUFreq"
2188         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2189         help
2190           Export status information via debugfs.
2191
2192 endif
2193
2194 source "drivers/cpuidle/Kconfig"
2195
2196 endmenu
2197
2198 menu "Floating point emulation"
2199
2200 comment "At least one emulation must be selected"
2201
2202 config FPE_NWFPE
2203         bool "NWFPE math emulation"
2204         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2205         ---help---
2206           Say Y to include the NWFPE floating point emulator in the kernel.
2207           This is necessary to run most binaries. Linux does not currently
2208           support floating point hardware so you need to say Y here even if
2209           your machine has an FPA or floating point co-processor podule.
2210
2211           You may say N here if you are going to load the Acorn FPEmulator
2212           early in the bootup.
2213
2214 config FPE_NWFPE_XP
2215         bool "Support extended precision"
2216         depends on FPE_NWFPE
2217         help
2218           Say Y to include 80-bit support in the kernel floating-point
2219           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2220           Note that gcc does not generate 80-bit operations by default,
2221           so in most cases this option only enlarges the size of the
2222           floating point emulator without any good reason.
2223
2224           You almost surely want to say N here.
2225
2226 config FPE_FASTFPE
2227         bool "FastFPE math emulation (EXPERIMENTAL)"
2228         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2229         ---help---
2230           Say Y here to include the FAST floating point emulator in the kernel.
2231           This is an experimental much faster emulator which now also has full
2232           precision for the mantissa.  It does not support any exceptions.
2233           It is very simple, and approximately 3-6 times faster than NWFPE.
2234
2235           It should be sufficient for most programs.  It may be not suitable
2236           for scientific calculations, but you have to check this for yourself.
2237           If you do not feel you need a faster FP emulation you should better
2238           choose NWFPE.
2239
2240 config VFP
2241         bool "VFP-format floating point maths"
2242         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2243         help
2244           Say Y to include VFP support code in the kernel. This is needed
2245           if your hardware includes a VFP unit.
2246
2247           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2248           release notes and additional status information.
2249
2250           Say N if your target does not have VFP hardware.
2251
2252 config VFPv3
2253         bool
2254         depends on VFP
2255         default y if CPU_V7
2256
2257 config NEON
2258         bool "Advanced SIMD (NEON) Extension support"
2259         depends on VFPv3 && CPU_V7
2260         help
2261           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2262           Extension.
2263
2264 endmenu
2265
2266 menu "Userspace binary formats"
2267
2268 source "fs/Kconfig.binfmt"
2269
2270 config ARTHUR
2271         tristate "RISC OS personality"
2272         depends on !AEABI
2273         help
2274           Say Y here to include the kernel code necessary if you want to run
2275           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2276           experimental; if this sounds frightening, say N and sleep in peace.
2277           You can also say M here to compile this support as a module (which
2278           will be called arthur).
2279
2280 endmenu
2281
2282 menu "Power management options"
2283
2284 source "kernel/power/Kconfig"
2285
2286 config ARCH_SUSPEND_POSSIBLE
2287         depends on !ARCH_S5PC100
2288         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2289                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2290         def_bool y
2291
2292 config ARM_CPU_SUSPEND
2293         def_bool PM_SLEEP
2294
2295 endmenu
2296
2297 source "net/Kconfig"
2298
2299 source "drivers/Kconfig"
2300
2301 source "fs/Kconfig"
2302
2303 source "arch/arm/Kconfig.debug"
2304
2305 source "security/Kconfig"
2306
2307 source "crypto/Kconfig"
2308
2309 source "lib/Kconfig"