arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_IRQ_SHOW_LEVEL
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARM_SINGLE_ARMV7M
 333         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 334         depends on !MMU
 335         select ARCH_WANT_OPTIONAL_GPIOLIB
 336         select ARM_NVIC
 337         select AUTO_ZRELADDR
 338         select CLKSRC_OF
 339         select COMMON_CLK
 340         select CPU_V7M
 341         select GENERIC_CLOCKEVENTS
 342         select NO_IOPORT_MAP
 343         select SPARSE_IRQ
 344         select USE_OF
 345
 346 config ARCH_REALVIEW
 347         bool "ARM Ltd. RealView family"
 348         select ARCH_WANT_OPTIONAL_GPIOLIB
 349         select ARM_AMBA
 350         select ARM_TIMER_SP804
 351         select COMMON_CLK
 352         select COMMON_CLK_VERSATILE
 353         select GENERIC_CLOCKEVENTS
 354         select GPIO_PL061 if GPIOLIB
 355         select ICST
 356         select NEED_MACH_MEMORY_H
 357         select PLAT_VERSATILE
 358         select PLAT_VERSATILE_SCHED_CLOCK
 359         help
 360           This enables support for ARM Ltd RealView boards.
 361
 362 config ARCH_VERSATILE
 363         bool "ARM Ltd. Versatile family"
 364         select ARCH_WANT_OPTIONAL_GPIOLIB
 365         select ARM_AMBA
 366         select ARM_TIMER_SP804
 367         select ARM_VIC
 368         select CLKDEV_LOOKUP
 369         select GENERIC_CLOCKEVENTS
 370         select HAVE_MACH_CLKDEV
 371         select ICST
 372         select PLAT_VERSATILE
 373         select PLAT_VERSATILE_CLOCK
 374         select PLAT_VERSATILE_SCHED_CLOCK
 375         select VERSATILE_FPGA_IRQ
 376         help
 377           This enables support for ARM Ltd Versatile board.
 378
 379 config ARCH_CLPS711X
 380         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 381         select ARCH_REQUIRE_GPIOLIB
 382         select AUTO_ZRELADDR
 383         select CLKSRC_MMIO
 384         select COMMON_CLK
 385         select CPU_ARM720T
 386         select GENERIC_CLOCKEVENTS
 387         select MFD_SYSCON
 388         select SOC_BUS
 389         help
 390           Support for Cirrus Logic 711x/721x/731x based boards.
 391
 392 config ARCH_GEMINI
 393         bool "Cortina Systems Gemini"
 394         select ARCH_REQUIRE_GPIOLIB
 395         select CLKSRC_MMIO
 396         select CPU_FA526
 397         select GENERIC_CLOCKEVENTS
 398         help
 399           Support for the Cortina Systems Gemini family SoCs
 400
 401 config ARCH_EBSA110
 402         bool "EBSA-110"
 403         select ARCH_USES_GETTIMEOFFSET
 404         select CPU_SA110
 405         select ISA
 406         select NEED_MACH_IO_H
 407         select NEED_MACH_MEMORY_H
 408         select NO_IOPORT_MAP
 409         help
 410           This is an evaluation board for the StrongARM processor available
 411           from Digital. It has limited hardware on-board, including an
 412           Ethernet interface, two PCMCIA sockets, two serial ports and a
 413           parallel port.
 414
 415 config ARCH_EP93XX
 416         bool "EP93xx-based"
 417         select ARCH_HAS_HOLES_MEMORYMODEL
 418         select ARCH_REQUIRE_GPIOLIB
 419         select ARCH_USES_GETTIMEOFFSET
 420         select ARM_AMBA
 421         select ARM_VIC
 422         select CLKDEV_LOOKUP
 423         select CPU_ARM920T
 424         help
 425           This enables support for the Cirrus EP93xx series of CPUs.
 426
 427 config ARCH_FOOTBRIDGE
 428         bool "FootBridge"
 429         select CPU_SA110
 430         select FOOTBRIDGE
 431         select GENERIC_CLOCKEVENTS
 432         select HAVE_IDE
 433         select NEED_MACH_IO_H if !MMU
 434         select NEED_MACH_MEMORY_H
 435         help
 436           Support for systems based on the DC21285 companion chip
 437           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 438
 439 config ARCH_NETX
 440         bool "Hilscher NetX based"
 441         select ARM_VIC
 442         select CLKSRC_MMIO
 443         select CPU_ARM926T
 444         select GENERIC_CLOCKEVENTS
 445         help
 446           This enables support for systems based on the Hilscher NetX Soc
 447
 448 config ARCH_IOP13XX
 449         bool "IOP13xx-based"
 450         depends on MMU
 451         select CPU_XSC3
 452         select NEED_MACH_MEMORY_H
 453         select NEED_RET_TO_USER
 454         select PCI
 455         select PLAT_IOP
 456         select VMSPLIT_1G
 457         select SPARSE_IRQ
 458         help
 459           Support for Intel's IOP13XX (XScale) family of processors.
 460
 461 config ARCH_IOP32X
 462         bool "IOP32x-based"
 463         depends on MMU
 464         select ARCH_REQUIRE_GPIOLIB
 465         select CPU_XSCALE
 466         select GPIO_IOP
 467         select NEED_RET_TO_USER
 468         select PCI
 469         select PLAT_IOP
 470         help
 471           Support for Intel's 80219 and IOP32X (XScale) family of
 472           processors.
 473
 474 config ARCH_IOP33X
 475         bool "IOP33x-based"
 476         depends on MMU
 477         select ARCH_REQUIRE_GPIOLIB
 478         select CPU_XSCALE
 479         select GPIO_IOP
 480         select NEED_RET_TO_USER
 481         select PCI
 482         select PLAT_IOP
 483         help
 484           Support for Intel's IOP33X (XScale) family of processors.
 485
 486 config ARCH_IXP4XX
 487         bool "IXP4xx-based"
 488         depends on MMU
 489         select ARCH_HAS_DMA_SET_COHERENT_MASK
 490         select ARCH_REQUIRE_GPIOLIB
 491         select ARCH_SUPPORTS_BIG_ENDIAN
 492         select CLKSRC_MMIO
 493         select CPU_XSCALE
 494         select DMABOUNCE if PCI
 495         select GENERIC_CLOCKEVENTS
 496         select MIGHT_HAVE_PCI
 497         select NEED_MACH_IO_H
 498         select USB_EHCI_BIG_ENDIAN_DESC
 499         select USB_EHCI_BIG_ENDIAN_MMIO
 500         help
 501           Support for Intel's IXP4XX (XScale) family of processors.
 502
 503 config ARCH_DOVE
 504         bool "Marvell Dove"
 505         select ARCH_REQUIRE_GPIOLIB
 506         select CPU_PJ4
 507         select GENERIC_CLOCKEVENTS
 508         select MIGHT_HAVE_PCI
 509         select MVEBU_MBUS
 510         select PINCTRL
 511         select PINCTRL_DOVE
 512         select PLAT_ORION_LEGACY
 513         help
 514           Support for the Marvell Dove SoC 88AP510
 515
 516 config ARCH_MV78XX0
 517         bool "Marvell MV78xx0"
 518         select ARCH_REQUIRE_GPIOLIB
 519         select CPU_FEROCEON
 520         select GENERIC_CLOCKEVENTS
 521         select MVEBU_MBUS
 522         select PCI
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the following Marvell MV78xx0 series SoCs:
 526           MV781x0, MV782x0.
 527
 528 config ARCH_ORION5X
 529         bool "Marvell Orion"
 530         depends on MMU
 531         select ARCH_REQUIRE_GPIOLIB
 532         select CPU_FEROCEON
 533         select GENERIC_CLOCKEVENTS
 534         select MVEBU_MBUS
 535         select PCI
 536         select PLAT_ORION_LEGACY
 537         help
 538           Support for the following Marvell Orion 5x series SoCs:
 539           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 540           Orion-2 (5281), Orion-1-90 (6183).
 541
 542 config ARCH_MMP
 543         bool "Marvell PXA168/910/MMP2"
 544         depends on MMU
 545         select ARCH_REQUIRE_GPIOLIB
 546         select CLKDEV_LOOKUP
 547         select GENERIC_ALLOCATOR
 548         select GENERIC_CLOCKEVENTS
 549         select GPIO_PXA
 550         select IRQ_DOMAIN
 551         select MULTI_IRQ_HANDLER
 552         select PINCTRL
 553         select PLAT_PXA
 554         select SPARSE_IRQ
 555         help
 556           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 557
 558 config ARCH_KS8695
 559         bool "Micrel/Kendin KS8695"
 560         select ARCH_REQUIRE_GPIOLIB
 561         select CLKSRC_MMIO
 562         select CPU_ARM922T
 563         select GENERIC_CLOCKEVENTS
 564         select NEED_MACH_MEMORY_H
 565         help
 566           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 567           System-on-Chip devices.
 568
 569 config ARCH_W90X900
 570         bool "Nuvoton W90X900 CPU"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKDEV_LOOKUP
 573         select CLKSRC_MMIO
 574         select CPU_ARM926T
 575         select GENERIC_CLOCKEVENTS
 576         help
 577           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 578           At present, the w90x900 has been renamed nuc900, regarding
 579           the ARM series product line, you can login the following
 580           link address to know more.
 581
 582           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 583                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 584
 585 config ARCH_LPC32XX
 586         bool "NXP LPC32XX"
 587         select ARCH_REQUIRE_GPIOLIB
 588         select ARM_AMBA
 589         select CLKDEV_LOOKUP
 590         select CLKSRC_MMIO
 591         select CPU_ARM926T
 592         select GENERIC_CLOCKEVENTS
 593         select HAVE_IDE
 594         select USE_OF
 595         help
 596           Support for the NXP LPC32XX family of processors
 597
 598 config ARCH_PXA
 599         bool "PXA2xx/PXA3xx-based"
 600         depends on MMU
 601         select ARCH_MTD_XIP
 602         select ARCH_REQUIRE_GPIOLIB
 603         select ARM_CPU_SUSPEND if PM
 604         select AUTO_ZRELADDR
 605         select COMMON_CLK
 606         select CLKDEV_LOOKUP
 607         select CLKSRC_MMIO
 608         select CLKSRC_OF
 609         select GENERIC_CLOCKEVENTS
 610         select GPIO_PXA
 611         select HAVE_IDE
 612         select IRQ_DOMAIN
 613         select MULTI_IRQ_HANDLER
 614         select PLAT_PXA
 615         select SPARSE_IRQ
 616         help
 617           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 618
 619 config ARCH_SHMOBILE_LEGACY
 620         bool "Renesas ARM SoCs (non-multiplatform)"
 621         select ARCH_SHMOBILE
 622         select ARM_PATCH_PHYS_VIRT if MMU
 623         select CLKDEV_LOOKUP
 624         select CPU_V7
 625         select GENERIC_CLOCKEVENTS
 626         select HAVE_ARM_SCU if SMP
 627         select HAVE_ARM_TWD if SMP
 628         select HAVE_SMP
 629         select MIGHT_HAVE_CACHE_L2X0
 630         select MULTI_IRQ_HANDLER
 631         select NO_IOPORT_MAP
 632         select PINCTRL
 633         select PM_GENERIC_DOMAINS if PM
 634         select SH_CLK_CPG
 635         select SPARSE_IRQ
 636         help
 637           Support for Renesas ARM SoC platforms using a non-multiplatform
 638           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 639           and RZ families.
 640
 641 config ARCH_RPC
 642         bool "RiscPC"
 643         select ARCH_ACORN
 644         select ARCH_MAY_HAVE_PC_FDC
 645         select ARCH_SPARSEMEM_ENABLE
 646         select ARCH_USES_GETTIMEOFFSET
 647         select CPU_SA110
 648         select FIQ
 649         select HAVE_IDE
 650         select HAVE_PATA_PLATFORM
 651         select ISA_DMA_API
 652         select NEED_MACH_IO_H
 653         select NEED_MACH_MEMORY_H
 654         select NO_IOPORT_MAP
 655         select VIRT_TO_BUS
 656         help
 657           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 658           CD-ROM interface, serial and parallel port, and the floppy drive.
 659
 660 config ARCH_SA1100
 661         bool "SA1100-based"
 662         select ARCH_MTD_XIP
 663         select ARCH_REQUIRE_GPIOLIB
 664         select ARCH_SPARSEMEM_ENABLE
 665         select CLKDEV_LOOKUP
 666         select CLKSRC_MMIO
 667         select CPU_FREQ
 668         select CPU_SA1100
 669         select GENERIC_CLOCKEVENTS
 670         select HAVE_IDE
 671         select IRQ_DOMAIN
 672         select ISA
 673         select MULTI_IRQ_HANDLER
 674         select NEED_MACH_MEMORY_H
 675         select SPARSE_IRQ
 676         help
 677           Support for StrongARM 11x0 based boards.
 678
 679 config ARCH_S3C24XX
 680         bool "Samsung S3C24XX SoCs"
 681         select ARCH_REQUIRE_GPIOLIB
 682         select ATAGS
 683         select CLKDEV_LOOKUP
 684         select CLKSRC_SAMSUNG_PWM
 685         select GENERIC_CLOCKEVENTS
 686         select GPIO_SAMSUNG
 687         select HAVE_S3C2410_I2C if I2C
 688         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 689         select HAVE_S3C_RTC if RTC_CLASS
 690         select MULTI_IRQ_HANDLER
 691         select NEED_MACH_IO_H
 692         select SAMSUNG_ATAGS
 693         help
 694           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 695           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 696           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 697           Samsung SMDK2410 development board (and derivatives).
 698
 699 config ARCH_S3C64XX
 700         bool "Samsung S3C64XX"
 701         select ARCH_REQUIRE_GPIOLIB
 702         select ARM_AMBA
 703         select ARM_VIC
 704         select ATAGS
 705         select CLKDEV_LOOKUP
 706         select CLKSRC_SAMSUNG_PWM
 707         select COMMON_CLK_SAMSUNG
 708         select CPU_V6K
 709         select GENERIC_CLOCKEVENTS
 710         select GPIO_SAMSUNG
 711         select HAVE_S3C2410_I2C if I2C
 712         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 713         select HAVE_TCM
 714         select NO_IOPORT_MAP
 715         select PLAT_SAMSUNG
 716         select PM_GENERIC_DOMAINS if PM
 717         select S3C_DEV_NAND
 718         select S3C_GPIO_TRACK
 719         select SAMSUNG_ATAGS
 720         select SAMSUNG_WAKEMASK
 721         select SAMSUNG_WDT_RESET
 722         help
 723           Samsung S3C64XX series based systems
 724
 725 config ARCH_DAVINCI
 726         bool "TI DaVinci"
 727         select ARCH_HAS_HOLES_MEMORYMODEL
 728         select ARCH_REQUIRE_GPIOLIB
 729         select CLKDEV_LOOKUP
 730         select GENERIC_ALLOCATOR
 731         select GENERIC_CLOCKEVENTS
 732         select GENERIC_IRQ_CHIP
 733         select HAVE_IDE
 734         select TI_PRIV_EDMA
 735         select USE_OF
 736         select ZONE_DMA
 737         help
 738           Support for TI's DaVinci platform.
 739
 740 config ARCH_OMAP1
 741         bool "TI OMAP1"
 742         depends on MMU
 743         select ARCH_HAS_HOLES_MEMORYMODEL
 744         select ARCH_OMAP
 745         select ARCH_REQUIRE_GPIOLIB
 746         select CLKDEV_LOOKUP
 747         select CLKSRC_MMIO
 748         select GENERIC_CLOCKEVENTS
 749         select GENERIC_IRQ_CHIP
 750         select HAVE_IDE
 751         select IRQ_DOMAIN
 752         select MULTI_IRQ_HANDLER
 753         select NEED_MACH_IO_H if PCCARD
 754         select NEED_MACH_MEMORY_H
 755         select SPARSE_IRQ
 756         help
 757           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 758
 759 endchoice
 760
 761 menu "Multiple platform selection"
 762         depends on ARCH_MULTIPLATFORM
 763
 764 comment "CPU Core family selection"
 765
 766 config ARCH_MULTI_V4
 767         bool "ARMv4 based platforms (FA526)"
 768         depends on !ARCH_MULTI_V6_V7
 769         select ARCH_MULTI_V4_V5
 770         select CPU_FA526
 771
 772 config ARCH_MULTI_V4T
 773         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 774         depends on !ARCH_MULTI_V6_V7
 775         select ARCH_MULTI_V4_V5
 776         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 777                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 778                 CPU_ARM925T || CPU_ARM940T)
 779
 780 config ARCH_MULTI_V5
 781         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 782         depends on !ARCH_MULTI_V6_V7
 783         select ARCH_MULTI_V4_V5
 784         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 785                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 786                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 787
 788 config ARCH_MULTI_V4_V5
 789         bool
 790
 791 config ARCH_MULTI_V6
 792         bool "ARMv6 based platforms (ARM11)"
 793         select ARCH_MULTI_V6_V7
 794         select CPU_V6K
 795
 796 config ARCH_MULTI_V7
 797         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 798         default y
 799         select ARCH_MULTI_V6_V7
 800         select CPU_V7
 801         select HAVE_SMP
 802
 803 config ARCH_MULTI_V6_V7
 804         bool
 805         select MIGHT_HAVE_CACHE_L2X0
 806
 807 config ARCH_MULTI_CPU_AUTO
 808         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 809         select ARCH_MULTI_V5
 810
 811 endmenu
 812
 813 config ARCH_VIRT
 814         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 815         select ARM_AMBA
 816         select ARM_GIC
 817         select ARM_PSCI
 818         select HAVE_ARM_ARCH_TIMER
 819
 820 #
 821 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 822 # Kconfigs may be included either alphabetically (according to the
 823 # plat- suffix) or along side the corresponding mach-* source.
 824 #
 825 source "arch/arm/mach-mvebu/Kconfig"
 826
 827 source "arch/arm/mach-alpine/Kconfig"
 828
 829 source "arch/arm/mach-asm9260/Kconfig"
 830
 831 source "arch/arm/mach-at91/Kconfig"
 832
 833 source "arch/arm/mach-axxia/Kconfig"
 834
 835 source "arch/arm/mach-bcm/Kconfig"
 836
 837 source "arch/arm/mach-berlin/Kconfig"
 838
 839 source "arch/arm/mach-clps711x/Kconfig"
 840
 841 source "arch/arm/mach-cns3xxx/Kconfig"
 842
 843 source "arch/arm/mach-davinci/Kconfig"
 844
 845 source "arch/arm/mach-digicolor/Kconfig"
 846
 847 source "arch/arm/mach-dove/Kconfig"
 848
 849 source "arch/arm/mach-ep93xx/Kconfig"
 850
 851 source "arch/arm/mach-footbridge/Kconfig"
 852
 853 source "arch/arm/mach-gemini/Kconfig"
 854
 855 source "arch/arm/mach-highbank/Kconfig"
 856
 857 source "arch/arm/mach-hisi/Kconfig"
 858
 859 source "arch/arm/mach-integrator/Kconfig"
 860
 861 source "arch/arm/mach-iop32x/Kconfig"
 862
 863 source "arch/arm/mach-iop33x/Kconfig"
 864
 865 source "arch/arm/mach-iop13xx/Kconfig"
 866
 867 source "arch/arm/mach-ixp4xx/Kconfig"
 868
 869 source "arch/arm/mach-keystone/Kconfig"
 870
 871 source "arch/arm/mach-ks8695/Kconfig"
 872
 873 source "arch/arm/mach-meson/Kconfig"
 874
 875 source "arch/arm/mach-moxart/Kconfig"
 876
 877 source "arch/arm/mach-mv78xx0/Kconfig"
 878
 879 source "arch/arm/mach-imx/Kconfig"
 880
 881 source "arch/arm/mach-mediatek/Kconfig"
 882
 883 source "arch/arm/mach-mxs/Kconfig"
 884
 885 source "arch/arm/mach-netx/Kconfig"
 886
 887 source "arch/arm/mach-nomadik/Kconfig"
 888
 889 source "arch/arm/mach-nspire/Kconfig"
 890
 891 source "arch/arm/plat-omap/Kconfig"
 892
 893 source "arch/arm/mach-omap1/Kconfig"
 894
 895 source "arch/arm/mach-omap2/Kconfig"
 896
 897 source "arch/arm/mach-orion5x/Kconfig"
 898
 899 source "arch/arm/mach-picoxcell/Kconfig"
 900
 901 source "arch/arm/mach-pxa/Kconfig"
 902 source "arch/arm/plat-pxa/Kconfig"
 903
 904 source "arch/arm/mach-mmp/Kconfig"
 905
 906 source "arch/arm/mach-qcom/Kconfig"
 907
 908 source "arch/arm/mach-realview/Kconfig"
 909
 910 source "arch/arm/mach-rockchip/Kconfig"
 911
 912 source "arch/arm/mach-sa1100/Kconfig"
 913
 914 source "arch/arm/mach-socfpga/Kconfig"
 915
 916 source "arch/arm/mach-spear/Kconfig"
 917
 918 source "arch/arm/mach-sti/Kconfig"
 919
 920 source "arch/arm/mach-s3c24xx/Kconfig"
 921
 922 source "arch/arm/mach-s3c64xx/Kconfig"
 923
 924 source "arch/arm/mach-s5pv210/Kconfig"
 925
 926 source "arch/arm/mach-exynos/Kconfig"
 927 source "arch/arm/plat-samsung/Kconfig"
 928
 929 source "arch/arm/mach-shmobile/Kconfig"
 930
 931 source "arch/arm/mach-sunxi/Kconfig"
 932
 933 source "arch/arm/mach-prima2/Kconfig"
 934
 935 source "arch/arm/mach-tegra/Kconfig"
 936
 937 source "arch/arm/mach-u300/Kconfig"
 938
 939 source "arch/arm/mach-uniphier/Kconfig"
 940
 941 source "arch/arm/mach-ux500/Kconfig"
 942
 943 source "arch/arm/mach-versatile/Kconfig"
 944
 945 source "arch/arm/mach-vexpress/Kconfig"
 946 source "arch/arm/plat-versatile/Kconfig"
 947
 948 source "arch/arm/mach-vt8500/Kconfig"
 949
 950 source "arch/arm/mach-w90x900/Kconfig"
 951
 952 source "arch/arm/mach-zx/Kconfig"
 953
 954 source "arch/arm/mach-zynq/Kconfig"
 955
 956 # ARMv7-M architecture
 957 config ARCH_EFM32
 958         bool "Energy Micro efm32"
 959         depends on ARM_SINGLE_ARMV7M
 960         select ARCH_REQUIRE_GPIOLIB
 961         help
 962           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 963           processors.
 964
 965 config ARCH_LPC18XX
 966         bool "NXP LPC18xx/LPC43xx"
 967         depends on ARM_SINGLE_ARMV7M
 968         select ARCH_HAS_RESET_CONTROLLER
 969         select ARM_AMBA
 970         select CLKSRC_LPC32XX
 971         select PINCTRL
 972         help
 973           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 974           high performance microcontrollers.
 975
 976 config ARCH_STM32
 977         bool "STMicrolectronics STM32"
 978         depends on ARM_SINGLE_ARMV7M
 979         select ARCH_HAS_RESET_CONTROLLER
 980         select ARMV7M_SYSTICK
 981         select CLKSRC_STM32
 982         select RESET_CONTROLLER
 983         help
 984           Support for STMicroelectronics STM32 processors.
 985
 986 # Definitions to make life easier
 987 config ARCH_ACORN
 988         bool
 989
 990 config PLAT_IOP
 991         bool
 992         select GENERIC_CLOCKEVENTS
 993
 994 config PLAT_ORION
 995         bool
 996         select CLKSRC_MMIO
 997         select COMMON_CLK
 998         select GENERIC_IRQ_CHIP
 999         select IRQ_DOMAIN
1000
1001 config PLAT_ORION_LEGACY
1002         bool
1003         select PLAT_ORION
1004
1005 config PLAT_PXA
1006         bool
1007
1008 config PLAT_VERSATILE
1009         bool
1010
1011 config ARM_TIMER_SP804
1012         bool
1013         select CLKSRC_MMIO
1014         select CLKSRC_OF if OF
1015
1016 source "arch/arm/firmware/Kconfig"
1017
1018 source arch/arm/mm/Kconfig
1019
1020 config IWMMXT
1021         bool "Enable iWMMXt support"
1022         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1023         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1024         help
1025           Enable support for iWMMXt context switching at run time if
1026           running on a CPU that supports it.
1027
1028 config MULTI_IRQ_HANDLER
1029         bool
1030         help
1031           Allow each machine to specify it's own IRQ handler at run time.
1032
1033 if !MMU
1034 source "arch/arm/Kconfig-nommu"
1035 endif
1036
1037 config PJ4B_ERRATA_4742
1038         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1039         depends on CPU_PJ4B && MACH_ARMADA_370
1040         default y
1041         help
1042           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1043           Event (WFE) IDLE states, a specific timing sensitivity exists between
1044           the retiring WFI/WFE instructions and the newly issued subsequent
1045           instructions.  This sensitivity can result in a CPU hang scenario.
1046           Workaround:
1047           The software must insert either a Data Synchronization Barrier (DSB)
1048           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1049           instruction
1050
1051 config ARM_ERRATA_326103
1052         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1053         depends on CPU_V6
1054         help
1055           Executing a SWP instruction to read-only memory does not set bit 11
1056           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1057           treat the access as a read, preventing a COW from occurring and
1058           causing the faulting task to livelock.
1059
1060 config ARM_ERRATA_411920
1061         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1062         depends on CPU_V6 || CPU_V6K
1063         help
1064           Invalidation of the Instruction Cache operation can
1065           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1066           It does not affect the MPCore. This option enables the ARM Ltd.
1067           recommended workaround.
1068
1069 config ARM_ERRATA_430973
1070         bool "ARM errata: Stale prediction on replaced interworking branch"
1071         depends on CPU_V7
1072         help
1073           This option enables the workaround for the 430973 Cortex-A8
1074           r1p* erratum. If a code sequence containing an ARM/Thumb
1075           interworking branch is replaced with another code sequence at the
1076           same virtual address, whether due to self-modifying code or virtual
1077           to physical address re-mapping, Cortex-A8 does not recover from the
1078           stale interworking branch prediction. This results in Cortex-A8
1079           executing the new code sequence in the incorrect ARM or Thumb state.
1080           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1081           and also flushes the branch target cache at every context switch.
1082           Note that setting specific bits in the ACTLR register may not be
1083           available in non-secure mode.
1084
1085 config ARM_ERRATA_458693
1086         bool "ARM errata: Processor deadlock when a false hazard is created"
1087         depends on CPU_V7
1088         depends on !ARCH_MULTIPLATFORM
1089         help
1090           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1091           erratum. For very specific sequences of memory operations, it is
1092           possible for a hazard condition intended for a cache line to instead
1093           be incorrectly associated with a different cache line. This false
1094           hazard might then cause a processor deadlock. The workaround enables
1095           the L1 caching of the NEON accesses and disables the PLD instruction
1096           in the ACTLR register. Note that setting specific bits in the ACTLR
1097           register may not be available in non-secure mode.
1098
1099 config ARM_ERRATA_460075
1100         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1101         depends on CPU_V7
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1105           erratum. Any asynchronous access to the L2 cache may encounter a
1106           situation in which recent store transactions to the L2 cache are lost
1107           and overwritten with stale memory contents from external memory. The
1108           workaround disables the write-allocate mode for the L2 cache via the
1109           ACTLR register. Note that setting specific bits in the ACTLR register
1110           may not be available in non-secure mode.
1111
1112 config ARM_ERRATA_742230
1113         bool "ARM errata: DMB operation may be faulty"
1114         depends on CPU_V7 && SMP
1115         depends on !ARCH_MULTIPLATFORM
1116         help
1117           This option enables the workaround for the 742230 Cortex-A9
1118           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1119           between two write operations may not ensure the correct visibility
1120           ordering of the two writes. This workaround sets a specific bit in
1121           the diagnostic register of the Cortex-A9 which causes the DMB
1122           instruction to behave as a DSB, ensuring the correct behaviour of
1123           the two writes.
1124
1125 config ARM_ERRATA_742231
1126         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1127         depends on CPU_V7 && SMP
1128         depends on !ARCH_MULTIPLATFORM
1129         help
1130           This option enables the workaround for the 742231 Cortex-A9
1131           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1132           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1133           accessing some data located in the same cache line, may get corrupted
1134           data due to bad handling of the address hazard when the line gets
1135           replaced from one of the CPUs at the same time as another CPU is
1136           accessing it. This workaround sets specific bits in the diagnostic
1137           register of the Cortex-A9 which reduces the linefill issuing
1138           capabilities of the processor.
1139
1140 config ARM_ERRATA_643719
1141         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1142         depends on CPU_V7 && SMP
1143         default y
1144         help
1145           This option enables the workaround for the 643719 Cortex-A9 (prior to
1146           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1147           register returns zero when it should return one. The workaround
1148           corrects this value, ensuring cache maintenance operations which use
1149           it behave as intended and avoiding data corruption.
1150
1151 config ARM_ERRATA_720789
1152         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1153         depends on CPU_V7
1154         help
1155           This option enables the workaround for the 720789 Cortex-A9 (prior to
1156           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1157           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1158           As a consequence of this erratum, some TLB entries which should be
1159           invalidated are not, resulting in an incoherency in the system page
1160           tables. The workaround changes the TLB flushing routines to invalidate
1161           entries regardless of the ASID.
1162
1163 config ARM_ERRATA_743622
1164         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1165         depends on CPU_V7
1166         depends on !ARCH_MULTIPLATFORM
1167         help
1168           This option enables the workaround for the 743622 Cortex-A9
1169           (r2p*) erratum. Under very rare conditions, a faulty
1170           optimisation in the Cortex-A9 Store Buffer may lead to data
1171           corruption. This workaround sets a specific bit in the diagnostic
1172           register of the Cortex-A9 which disables the Store Buffer
1173           optimisation, preventing the defect from occurring. This has no
1174           visible impact on the overall performance or power consumption of the
1175           processor.
1176
1177 config ARM_ERRATA_751472
1178         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1179         depends on CPU_V7
1180         depends on !ARCH_MULTIPLATFORM
1181         help
1182           This option enables the workaround for the 751472 Cortex-A9 (prior
1183           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1184           completion of a following broadcasted operation if the second
1185           operation is received by a CPU before the ICIALLUIS has completed,
1186           potentially leading to corrupted entries in the cache or TLB.
1187
1188 config ARM_ERRATA_754322
1189         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1190         depends on CPU_V7
1191         help
1192           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1193           r3p*) erratum. A speculative memory access may cause a page table walk
1194           which starts prior to an ASID switch but completes afterwards. This
1195           can populate the micro-TLB with a stale entry which may be hit with
1196           the new ASID. This workaround places two dsb instructions in the mm
1197           switching code so that no page table walks can cross the ASID switch.
1198
1199 config ARM_ERRATA_754327
1200         bool "ARM errata: no automatic Store Buffer drain"
1201         depends on CPU_V7 && SMP
1202         help
1203           This option enables the workaround for the 754327 Cortex-A9 (prior to
1204           r2p0) erratum. The Store Buffer does not have any automatic draining
1205           mechanism and therefore a livelock may occur if an external agent
1206           continuously polls a memory location waiting to observe an update.
1207           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1208           written polling loops from denying visibility of updates to memory.
1209
1210 config ARM_ERRATA_364296
1211         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1212         depends on CPU_V6
1213         help
1214           This options enables the workaround for the 364296 ARM1136
1215           r0p2 erratum (possible cache data corruption with
1216           hit-under-miss enabled). It sets the undocumented bit 31 in
1217           the auxiliary control register and the FI bit in the control
1218           register, thus disabling hit-under-miss without putting the
1219           processor into full low interrupt latency mode. ARM11MPCore
1220           is not affected.
1221
1222 config ARM_ERRATA_764369
1223         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1224         depends on CPU_V7 && SMP
1225         help
1226           This option enables the workaround for erratum 764369
1227           affecting Cortex-A9 MPCore with two or more processors (all
1228           current revisions). Under certain timing circumstances, a data
1229           cache line maintenance operation by MVA targeting an Inner
1230           Shareable memory region may fail to proceed up to either the
1231           Point of Coherency or to the Point of Unification of the
1232           system. This workaround adds a DSB instruction before the
1233           relevant cache maintenance functions and sets a specific bit
1234           in the diagnostic control register of the SCU.
1235
1236 config ARM_ERRATA_775420
1237        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1238        depends on CPU_V7
1239        help
1240          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1241          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1242          operation aborts with MMU exception, it might cause the processor
1243          to deadlock. This workaround puts DSB before executing ISB if
1244          an abort may occur on cache maintenance.
1245
1246 config ARM_ERRATA_798181
1247         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1248         depends on CPU_V7 && SMP
1249         help
1250           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1251           adequately shooting down all use of the old entries. This
1252           option enables the Linux kernel workaround for this erratum
1253           which sends an IPI to the CPUs that are running the same ASID
1254           as the one being invalidated.
1255
1256 config ARM_ERRATA_773022
1257         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1258         depends on CPU_V7
1259         help
1260           This option enables the workaround for the 773022 Cortex-A15
1261           (up to r0p4) erratum. In certain rare sequences of code, the
1262           loop buffer may deliver incorrect instructions. This
1263           workaround disables the loop buffer to avoid the erratum.
1264
1265 endmenu
1266
1267 source "arch/arm/common/Kconfig"
1268
1269 menu "Bus support"
1270
1271 config ISA
1272         bool
1273         help
1274           Find out whether you have ISA slots on your motherboard.  ISA is the
1275           name of a bus system, i.e. the way the CPU talks to the other stuff
1276           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1277           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1278           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1279
1280 # Select ISA DMA controller support
1281 config ISA_DMA
1282         bool
1283         select ISA_DMA_API
1284
1285 # Select ISA DMA interface
1286 config ISA_DMA_API
1287         bool
1288
1289 config PCI
1290         bool "PCI support" if MIGHT_HAVE_PCI
1291         help
1292           Find out whether you have a PCI motherboard. PCI is the name of a
1293           bus system, i.e. the way the CPU talks to the other stuff inside
1294           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1295           VESA. If you have PCI, say Y, otherwise N.
1296
1297 config PCI_DOMAINS
1298         bool
1299         depends on PCI
1300
1301 config PCI_DOMAINS_GENERIC
1302         def_bool PCI_DOMAINS
1303
1304 config PCI_NANOENGINE
1305         bool "BSE nanoEngine PCI support"
1306         depends on SA1100_NANOENGINE
1307         help
1308           Enable PCI on the BSE nanoEngine board.
1309
1310 config PCI_SYSCALL
1311         def_bool PCI
1312
1313 config PCI_HOST_ITE8152
1314         bool
1315         depends on PCI && MACH_ARMCORE
1316         default y
1317         select DMABOUNCE
1318
1319 source "drivers/pci/Kconfig"
1320 source "drivers/pci/pcie/Kconfig"
1321
1322 source "drivers/pcmcia/Kconfig"
1323
1324 endmenu
1325
1326 menu "Kernel Features"
1327
1328 config HAVE_SMP
1329         bool
1330         help
1331           This option should be selected by machines which have an SMP-
1332           capable CPU.
1333
1334           The only effect of this option is to make the SMP-related
1335           options available to the user for configuration.
1336
1337 config SMP
1338         bool "Symmetric Multi-Processing"
1339         depends on CPU_V6K || CPU_V7
1340         depends on GENERIC_CLOCKEVENTS
1341         depends on HAVE_SMP
1342         depends on MMU || ARM_MPU
1343         help
1344           This enables support for systems with more than one CPU. If you have
1345           a system with only one CPU, say N. If you have a system with more
1346           than one CPU, say Y.
1347
1348           If you say N here, the kernel will run on uni- and multiprocessor
1349           machines, but will use only one CPU of a multiprocessor machine. If
1350           you say Y here, the kernel will run on many, but not all,
1351           uniprocessor machines. On a uniprocessor machine, the kernel
1352           will run faster if you say N here.
1353
1354           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1355           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1356           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1357
1358           If you don't know what to do here, say N.
1359
1360 config SMP_ON_UP
1361         bool "Allow booting SMP kernel on uniprocessor systems"
1362         depends on SMP && !XIP_KERNEL && MMU
1363         default y
1364         help
1365           SMP kernels contain instructions which fail on non-SMP processors.
1366           Enabling this option allows the kernel to modify itself to make
1367           these instructions safe.  Disabling it allows about 1K of space
1368           savings.
1369
1370           If you don't know what to do here, say Y.
1371
1372 config ARM_CPU_TOPOLOGY
1373         bool "Support cpu topology definition"
1374         depends on SMP && CPU_V7
1375         default y
1376         help
1377           Support ARM cpu topology definition. The MPIDR register defines
1378           affinity between processors which is then used to describe the cpu
1379           topology of an ARM System.
1380
1381 config SCHED_MC
1382         bool "Multi-core scheduler support"
1383         depends on ARM_CPU_TOPOLOGY
1384         help
1385           Multi-core scheduler support improves the CPU scheduler's decision
1386           making when dealing with multi-core CPU chips at a cost of slightly
1387           increased overhead in some places. If unsure say N here.
1388
1389 config SCHED_SMT
1390         bool "SMT scheduler support"
1391         depends on ARM_CPU_TOPOLOGY
1392         help
1393           Improves the CPU scheduler's decision making when dealing with
1394           MultiThreading at a cost of slightly increased overhead in some
1395           places. If unsure say N here.
1396
1397 config HAVE_ARM_SCU
1398         bool
1399         help
1400           This option enables support for the ARM system coherency unit
1401
1402 config HAVE_ARM_ARCH_TIMER
1403         bool "Architected timer support"
1404         depends on CPU_V7
1405         select ARM_ARCH_TIMER
1406         select GENERIC_CLOCKEVENTS
1407         help
1408           This option enables support for the ARM architected timer
1409
1410 config HAVE_ARM_TWD
1411         bool
1412         depends on SMP
1413         select CLKSRC_OF if OF
1414         help
1415           This options enables support for the ARM timer and watchdog unit
1416
1417 config MCPM
1418         bool "Multi-Cluster Power Management"
1419         depends on CPU_V7 && SMP
1420         help
1421           This option provides the common power management infrastructure
1422           for (multi-)cluster based systems, such as big.LITTLE based
1423           systems.
1424
1425 config MCPM_QUAD_CLUSTER
1426         bool
1427         depends on MCPM
1428         help
1429           To avoid wasting resources unnecessarily, MCPM only supports up
1430           to 2 clusters by default.
1431           Platforms with 3 or 4 clusters that use MCPM must select this
1432           option to allow the additional clusters to be managed.
1433
1434 config BIG_LITTLE
1435         bool "big.LITTLE support (Experimental)"
1436         depends on CPU_V7 && SMP
1437         select MCPM
1438         help
1439           This option enables support selections for the big.LITTLE
1440           system architecture.
1441
1442 config BL_SWITCHER
1443         bool "big.LITTLE switcher support"
1444         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1445         select ARM_CPU_SUSPEND
1446         select CPU_PM
1447         help
1448           The big.LITTLE "switcher" provides the core functionality to
1449           transparently handle transition between a cluster of A15's
1450           and a cluster of A7's in a big.LITTLE system.
1451
1452 config BL_SWITCHER_DUMMY_IF
1453         tristate "Simple big.LITTLE switcher user interface"
1454         depends on BL_SWITCHER && DEBUG_KERNEL
1455         help
1456           This is a simple and dummy char dev interface to control
1457           the big.LITTLE switcher core code.  It is meant for
1458           debugging purposes only.
1459
1460 choice
1461         prompt "Memory split"
1462         depends on MMU
1463         default VMSPLIT_3G
1464         help
1465           Select the desired split between kernel and user memory.
1466
1467           If you are not absolutely sure what you are doing, leave this
1468           option alone!
1469
1470         config VMSPLIT_3G
1471                 bool "3G/1G user/kernel split"
1472         config VMSPLIT_2G
1473                 bool "2G/2G user/kernel split"
1474         config VMSPLIT_1G
1475                 bool "1G/3G user/kernel split"
1476 endchoice
1477
1478 config PAGE_OFFSET
1479         hex
1480         default PHYS_OFFSET if !MMU
1481         default 0x40000000 if VMSPLIT_1G
1482         default 0x80000000 if VMSPLIT_2G
1483         default 0xC0000000
1484
1485 config NR_CPUS
1486         int "Maximum number of CPUs (2-32)"
1487         range 2 32
1488         depends on SMP
1489         default "4"
1490
1491 config HOTPLUG_CPU
1492         bool "Support for hot-pluggable CPUs"
1493         depends on SMP
1494         help
1495           Say Y here to experiment with turning CPUs off and on.  CPUs
1496           can be controlled through /sys/devices/system/cpu.
1497
1498 config ARM_PSCI
1499         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1500         depends on CPU_V7
1501         help
1502           Say Y here if you want Linux to communicate with system firmware
1503           implementing the PSCI specification for CPU-centric power
1504           management operations described in ARM document number ARM DEN
1505           0022A ("Power State Coordination Interface System Software on
1506           ARM processors").
1507
1508 # The GPIO number here must be sorted by descending number. In case of
1509 # a multiplatform kernel, we just want the highest value required by the
1510 # selected platforms.
1511 config ARCH_NR_GPIO
1512         int
1513         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1514                 ARCH_ZYNQ
1515         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1516                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1517         default 416 if ARCH_SUNXI
1518         default 392 if ARCH_U8500
1519         default 352 if ARCH_VT8500
1520         default 288 if ARCH_ROCKCHIP
1521         default 264 if MACH_H4700
1522         default 0
1523         help
1524           Maximum number of GPIOs in the system.
1525
1526           If unsure, leave the default value.
1527
1528 source kernel/Kconfig.preempt
1529
1530 config HZ_FIXED
1531         int
1532         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1533                 ARCH_S5PV210 || ARCH_EXYNOS4
1534         default 128 if SOC_AT91RM9200
1535         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1536         default 0
1537
1538 choice
1539         depends on HZ_FIXED = 0
1540         prompt "Timer frequency"
1541
1542 config HZ_100
1543         bool "100 Hz"
1544
1545 config HZ_200
1546         bool "200 Hz"
1547
1548 config HZ_250
1549         bool "250 Hz"
1550
1551 config HZ_300
1552         bool "300 Hz"
1553
1554 config HZ_500
1555         bool "500 Hz"
1556
1557 config HZ_1000
1558         bool "1000 Hz"
1559
1560 endchoice
1561
1562 config HZ
1563         int
1564         default HZ_FIXED if HZ_FIXED != 0
1565         default 100 if HZ_100
1566         default 200 if HZ_200
1567         default 250 if HZ_250
1568         default 300 if HZ_300
1569         default 500 if HZ_500
1570         default 1000
1571
1572 config SCHED_HRTICK
1573         def_bool HIGH_RES_TIMERS
1574
1575 config THUMB2_KERNEL
1576         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1577         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1578         default y if CPU_THUMBONLY
1579         select AEABI
1580         select ARM_ASM_UNIFIED
1581         select ARM_UNWIND
1582         help
1583           By enabling this option, the kernel will be compiled in
1584           Thumb-2 mode. A compiler/assembler that understand the unified
1585           ARM-Thumb syntax is needed.
1586
1587           If unsure, say N.
1588
1589 config THUMB2_AVOID_R_ARM_THM_JUMP11
1590         bool "Work around buggy Thumb-2 short branch relocations in gas"
1591         depends on THUMB2_KERNEL && MODULES
1592         default y
1593         help
1594           Various binutils versions can resolve Thumb-2 branches to
1595           locally-defined, preemptible global symbols as short-range "b.n"
1596           branch instructions.
1597
1598           This is a problem, because there's no guarantee the final
1599           destination of the symbol, or any candidate locations for a
1600           trampoline, are within range of the branch.  For this reason, the
1601           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1602           relocation in modules at all, and it makes little sense to add
1603           support.
1604
1605           The symptom is that the kernel fails with an "unsupported
1606           relocation" error when loading some modules.
1607
1608           Until fixed tools are available, passing
1609           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1610           code which hits this problem, at the cost of a bit of extra runtime
1611           stack usage in some cases.
1612
1613           The problem is described in more detail at:
1614               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1615
1616           Only Thumb-2 kernels are affected.
1617
1618           Unless you are sure your tools don't have this problem, say Y.
1619
1620 config ARM_ASM_UNIFIED
1621         bool
1622
1623 config AEABI
1624         bool "Use the ARM EABI to compile the kernel"
1625         help
1626           This option allows for the kernel to be compiled using the latest
1627           ARM ABI (aka EABI).  This is only useful if you are using a user
1628           space environment that is also compiled with EABI.
1629
1630           Since there are major incompatibilities between the legacy ABI and
1631           EABI, especially with regard to structure member alignment, this
1632           option also changes the kernel syscall calling convention to
1633           disambiguate both ABIs and allow for backward compatibility support
1634           (selected with CONFIG_OABI_COMPAT).
1635
1636           To use this you need GCC version 4.0.0 or later.
1637
1638 config OABI_COMPAT
1639         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1640         depends on AEABI && !THUMB2_KERNEL
1641         help
1642           This option preserves the old syscall interface along with the
1643           new (ARM EABI) one. It also provides a compatibility layer to
1644           intercept syscalls that have structure arguments which layout
1645           in memory differs between the legacy ABI and the new ARM EABI
1646           (only for non "thumb" binaries). This option adds a tiny
1647           overhead to all syscalls and produces a slightly larger kernel.
1648
1649           The seccomp filter system will not be available when this is
1650           selected, since there is no way yet to sensibly distinguish
1651           between calling conventions during filtering.
1652
1653           If you know you'll be using only pure EABI user space then you
1654           can say N here. If this option is not selected and you attempt
1655           to execute a legacy ABI binary then the result will be
1656           UNPREDICTABLE (in fact it can be predicted that it won't work
1657           at all). If in doubt say N.
1658
1659 config ARCH_HAS_HOLES_MEMORYMODEL
1660         bool
1661
1662 config ARCH_SPARSEMEM_ENABLE
1663         bool
1664
1665 config ARCH_SPARSEMEM_DEFAULT
1666         def_bool ARCH_SPARSEMEM_ENABLE
1667
1668 config ARCH_SELECT_MEMORY_MODEL
1669         def_bool ARCH_SPARSEMEM_ENABLE
1670
1671 config HAVE_ARCH_PFN_VALID
1672         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1673
1674 config HAVE_GENERIC_RCU_GUP
1675         def_bool y
1676         depends on ARM_LPAE
1677
1678 config HIGHMEM
1679         bool "High Memory Support"
1680         depends on MMU
1681         help
1682           The address space of ARM processors is only 4 Gigabytes large
1683           and it has to accommodate user address space, kernel address
1684           space as well as some memory mapped IO. That means that, if you
1685           have a large amount of physical memory and/or IO, not all of the
1686           memory can be "permanently mapped" by the kernel. The physical
1687           memory that is not permanently mapped is called "high memory".
1688
1689           Depending on the selected kernel/user memory split, minimum
1690           vmalloc space and actual amount of RAM, you may not need this
1691           option which should result in a slightly faster kernel.
1692
1693           If unsure, say n.
1694
1695 config HIGHPTE
1696         bool "Allocate 2nd-level pagetables from highmem"
1697         depends on HIGHMEM
1698
1699 config HW_PERF_EVENTS
1700         bool "Enable hardware performance counter support for perf events"
1701         depends on PERF_EVENTS
1702         default y
1703         help
1704           Enable hardware performance counter support for perf events. If
1705           disabled, perf events will use software events only.
1706
1707 config SYS_SUPPORTS_HUGETLBFS
1708        def_bool y
1709        depends on ARM_LPAE
1710
1711 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1712        def_bool y
1713        depends on ARM_LPAE
1714
1715 config ARCH_WANT_GENERAL_HUGETLB
1716         def_bool y
1717
1718 source "mm/Kconfig"
1719
1720 config FORCE_MAX_ZONEORDER
1721         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1722         range 11 64 if ARCH_SHMOBILE_LEGACY
1723         default "12" if SOC_AM33XX
1724         default "9" if SA1111 || ARCH_EFM32
1725         default "11"
1726         help
1727           The kernel memory allocator divides physically contiguous memory
1728           blocks into "zones", where each zone is a power of two number of
1729           pages.  This option selects the largest power of two that the kernel
1730           keeps in the memory allocator.  If you need to allocate very large
1731           blocks of physically contiguous memory, then you may need to
1732           increase this value.
1733
1734           This config option is actually maximum order plus one. For example,
1735           a value of 11 means that the largest free memory block is 2^10 pages.
1736
1737 config ALIGNMENT_TRAP
1738         bool
1739         depends on CPU_CP15_MMU
1740         default y if !ARCH_EBSA110
1741         select HAVE_PROC_CPU if PROC_FS
1742         help
1743           ARM processors cannot fetch/store information which is not
1744           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1745           address divisible by 4. On 32-bit ARM processors, these non-aligned
1746           fetch/store instructions will be emulated in software if you say
1747           here, which has a severe performance impact. This is necessary for
1748           correct operation of some network protocols. With an IP-only
1749           configuration it is safe to say N, otherwise say Y.
1750
1751 config UACCESS_WITH_MEMCPY
1752         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1753         depends on MMU
1754         default y if CPU_FEROCEON
1755         help
1756           Implement faster copy_to_user and clear_user methods for CPU
1757           cores where a 8-word STM instruction give significantly higher
1758           memory write throughput than a sequence of individual 32bit stores.
1759
1760           A possible side effect is a slight increase in scheduling latency
1761           between threads sharing the same address space if they invoke
1762           such copy operations with large buffers.
1763
1764           However, if the CPU data cache is using a write-allocate mode,
1765           this option is unlikely to provide any performance gain.
1766
1767 config SECCOMP
1768         bool
1769         prompt "Enable seccomp to safely compute untrusted bytecode"
1770         ---help---
1771           This kernel feature is useful for number crunching applications
1772           that may need to compute untrusted bytecode during their
1773           execution. By using pipes or other transports made available to
1774           the process as file descriptors supporting the read/write
1775           syscalls, it's possible to isolate those applications in
1776           their own address space using seccomp. Once seccomp is
1777           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1778           and the task is only allowed to execute a few safe syscalls
1779           defined by each seccomp mode.
1780
1781 config SWIOTLB
1782         def_bool y
1783
1784 config IOMMU_HELPER
1785         def_bool SWIOTLB
1786
1787 config XEN_DOM0
1788         def_bool y
1789         depends on XEN
1790
1791 config XEN
1792         bool "Xen guest support on ARM"
1793         depends on ARM && AEABI && OF
1794         depends on CPU_V7 && !CPU_V6
1795         depends on !GENERIC_ATOMIC64
1796         depends on MMU
1797         select ARCH_DMA_ADDR_T_64BIT
1798         select ARM_PSCI
1799         select SWIOTLB_XEN
1800         help
1801           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1802
1803 endmenu
1804
1805 menu "Boot options"
1806
1807 config USE_OF
1808         bool "Flattened Device Tree support"
1809         select IRQ_DOMAIN
1810         select OF
1811         select OF_EARLY_FLATTREE
1812         select OF_RESERVED_MEM
1813         help
1814           Include support for flattened device tree machine descriptions.
1815
1816 config ATAGS
1817         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1818         default y
1819         help
1820           This is the traditional way of passing data to the kernel at boot
1821           time. If you are solely relying on the flattened device tree (or
1822           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1823           to remove ATAGS support from your kernel binary.  If unsure,
1824           leave this to y.
1825
1826 config DEPRECATED_PARAM_STRUCT
1827         bool "Provide old way to pass kernel parameters"
1828         depends on ATAGS
1829         help
1830           This was deprecated in 2001 and announced to live on for 5 years.
1831           Some old boot loaders still use this way.
1832
1833 # Compressed boot loader in ROM.  Yes, we really want to ask about
1834 # TEXT and BSS so we preserve their values in the config files.
1835 config ZBOOT_ROM_TEXT
1836         hex "Compressed ROM boot loader base address"
1837         default "0"
1838         help
1839           The physical address at which the ROM-able zImage is to be
1840           placed in the target.  Platforms which normally make use of
1841           ROM-able zImage formats normally set this to a suitable
1842           value in their defconfig file.
1843
1844           If ZBOOT_ROM is not enabled, this has no effect.
1845
1846 config ZBOOT_ROM_BSS
1847         hex "Compressed ROM boot loader BSS address"
1848         default "0"
1849         help
1850           The base address of an area of read/write memory in the target
1851           for the ROM-able zImage which must be available while the
1852           decompressor is running. It must be large enough to hold the
1853           entire decompressed kernel plus an additional 128 KiB.
1854           Platforms which normally make use of ROM-able zImage formats
1855           normally set this to a suitable value in their defconfig file.
1856
1857           If ZBOOT_ROM is not enabled, this has no effect.
1858
1859 config ZBOOT_ROM
1860         bool "Compressed boot loader in ROM/flash"
1861         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1862         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1863         help
1864           Say Y here if you intend to execute your compressed kernel image
1865           (zImage) directly from ROM or flash.  If unsure, say N.
1866
1867 config ARM_APPENDED_DTB
1868         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1869         depends on OF
1870         help
1871           With this option, the boot code will look for a device tree binary
1872           (DTB) appended to zImage
1873           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1874
1875           This is meant as a backward compatibility convenience for those
1876           systems with a bootloader that can't be upgraded to accommodate
1877           the documented boot protocol using a device tree.
1878
1879           Beware that there is very little in terms of protection against
1880           this option being confused by leftover garbage in memory that might
1881           look like a DTB header after a reboot if no actual DTB is appended
1882           to zImage.  Do not leave this option active in a production kernel
1883           if you don't intend to always append a DTB.  Proper passing of the
1884           location into r2 of a bootloader provided DTB is always preferable
1885           to this option.
1886
1887 config ARM_ATAG_DTB_COMPAT
1888         bool "Supplement the appended DTB with traditional ATAG information"
1889         depends on ARM_APPENDED_DTB
1890         help
1891           Some old bootloaders can't be updated to a DTB capable one, yet
1892           they provide ATAGs with memory configuration, the ramdisk address,
1893           the kernel cmdline string, etc.  Such information is dynamically
1894           provided by the bootloader and can't always be stored in a static
1895           DTB.  To allow a device tree enabled kernel to be used with such
1896           bootloaders, this option allows zImage to extract the information
1897           from the ATAG list and store it at run time into the appended DTB.
1898
1899 choice
1900         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1901         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1902
1903 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1904         bool "Use bootloader kernel arguments if available"
1905         help
1906           Uses the command-line options passed by the boot loader instead of
1907           the device tree bootargs property. If the boot loader doesn't provide
1908           any, the device tree bootargs property will be used.
1909
1910 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1911         bool "Extend with bootloader kernel arguments"
1912         help
1913           The command-line arguments provided by the boot loader will be
1914           appended to the the device tree bootargs property.
1915
1916 endchoice
1917
1918 config CMDLINE
1919         string "Default kernel command string"
1920         default ""
1921         help
1922           On some architectures (EBSA110 and CATS), there is currently no way
1923           for the boot loader to pass arguments to the kernel. For these
1924           architectures, you should supply some command-line options at build
1925           time by entering them here. As a minimum, you should specify the
1926           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1927
1928 choice
1929         prompt "Kernel command line type" if CMDLINE != ""
1930         default CMDLINE_FROM_BOOTLOADER
1931         depends on ATAGS
1932
1933 config CMDLINE_FROM_BOOTLOADER
1934         bool "Use bootloader kernel arguments if available"
1935         help
1936           Uses the command-line options passed by the boot loader. If
1937           the boot loader doesn't provide any, the default kernel command
1938           string provided in CMDLINE will be used.
1939
1940 config CMDLINE_EXTEND
1941         bool "Extend bootloader kernel arguments"
1942         help
1943           The command-line arguments provided by the boot loader will be
1944           appended to the default kernel command string.
1945
1946 config CMDLINE_FORCE
1947         bool "Always use the default kernel command string"
1948         help
1949           Always use the default kernel command string, even if the boot
1950           loader passes other arguments to the kernel.
1951           This is useful if you cannot or don't want to change the
1952           command-line options your boot loader passes to the kernel.
1953 endchoice
1954
1955 config XIP_KERNEL
1956         bool "Kernel Execute-In-Place from ROM"
1957         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1958         help
1959           Execute-In-Place allows the kernel to run from non-volatile storage
1960           directly addressable by the CPU, such as NOR flash. This saves RAM
1961           space since the text section of the kernel is not loaded from flash
1962           to RAM.  Read-write sections, such as the data section and stack,
1963           are still copied to RAM.  The XIP kernel is not compressed since
1964           it has to run directly from flash, so it will take more space to
1965           store it.  The flash address used to link the kernel object files,
1966           and for storing it, is configuration dependent. Therefore, if you
1967           say Y here, you must know the proper physical address where to
1968           store the kernel image depending on your own flash memory usage.
1969
1970           Also note that the make target becomes "make xipImage" rather than
1971           "make zImage" or "make Image".  The final kernel binary to put in
1972           ROM memory will be arch/arm/boot/xipImage.
1973
1974           If unsure, say N.
1975
1976 config XIP_PHYS_ADDR
1977         hex "XIP Kernel Physical Location"
1978         depends on XIP_KERNEL
1979         default "0x00080000"
1980         help
1981           This is the physical address in your flash memory the kernel will
1982           be linked for and stored to.  This address is dependent on your
1983           own flash usage.
1984
1985 config KEXEC
1986         bool "Kexec system call (EXPERIMENTAL)"
1987         depends on (!SMP || PM_SLEEP_SMP)
1988         help
1989           kexec is a system call that implements the ability to shutdown your
1990           current kernel, and to start another kernel.  It is like a reboot
1991           but it is independent of the system firmware.   And like a reboot
1992           you can start any kernel with it, not just Linux.
1993
1994           It is an ongoing process to be certain the hardware in a machine
1995           is properly shutdown, so do not be surprised if this code does not
1996           initially work for you.
1997
1998 config ATAGS_PROC
1999         bool "Export atags in procfs"
2000         depends on ATAGS && KEXEC
2001         default y
2002         help
2003           Should the atags used to boot the kernel be exported in an "atags"
2004           file in procfs. Useful with kexec.
2005
2006 config CRASH_DUMP
2007         bool "Build kdump crash kernel (EXPERIMENTAL)"
2008         help
2009           Generate crash dump after being started by kexec. This should
2010           be normally only set in special crash dump kernels which are
2011           loaded in the main kernel with kexec-tools into a specially
2012           reserved region and then later executed after a crash by
2013           kdump/kexec. The crash dump kernel must be compiled to a
2014           memory address not used by the main kernel
2015
2016           For more details see Documentation/kdump/kdump.txt
2017
2018 config AUTO_ZRELADDR
2019         bool "Auto calculation of the decompressed kernel image address"
2020         help
2021           ZRELADDR is the physical address where the decompressed kernel
2022           image will be placed. If AUTO_ZRELADDR is selected, the address
2023           will be determined at run-time by masking the current IP with
2024           0xf8000000. This assumes the zImage being placed in the first 128MB
2025           from start of memory.
2026
2027 endmenu
2028
2029 menu "CPU Power Management"
2030
2031 source "drivers/cpufreq/Kconfig"
2032
2033 source "drivers/cpuidle/Kconfig"
2034
2035 endmenu
2036
2037 menu "Floating point emulation"
2038
2039 comment "At least one emulation must be selected"
2040
2041 config FPE_NWFPE
2042         bool "NWFPE math emulation"
2043         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2044         ---help---
2045           Say Y to include the NWFPE floating point emulator in the kernel.
2046           This is necessary to run most binaries. Linux does not currently
2047           support floating point hardware so you need to say Y here even if
2048           your machine has an FPA or floating point co-processor podule.
2049
2050           You may say N here if you are going to load the Acorn FPEmulator
2051           early in the bootup.
2052
2053 config FPE_NWFPE_XP
2054         bool "Support extended precision"
2055         depends on FPE_NWFPE
2056         help
2057           Say Y to include 80-bit support in the kernel floating-point
2058           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2059           Note that gcc does not generate 80-bit operations by default,
2060           so in most cases this option only enlarges the size of the
2061           floating point emulator without any good reason.
2062
2063           You almost surely want to say N here.
2064
2065 config FPE_FASTFPE
2066         bool "FastFPE math emulation (EXPERIMENTAL)"
2067         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2068         ---help---
2069           Say Y here to include the FAST floating point emulator in the kernel.
2070           This is an experimental much faster emulator which now also has full
2071           precision for the mantissa.  It does not support any exceptions.
2072           It is very simple, and approximately 3-6 times faster than NWFPE.
2073
2074           It should be sufficient for most programs.  It may be not suitable
2075           for scientific calculations, but you have to check this for yourself.
2076           If you do not feel you need a faster FP emulation you should better
2077           choose NWFPE.
2078
2079 config VFP
2080         bool "VFP-format floating point maths"
2081         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2082         help
2083           Say Y to include VFP support code in the kernel. This is needed
2084           if your hardware includes a VFP unit.
2085
2086           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2087           release notes and additional status information.
2088
2089           Say N if your target does not have VFP hardware.
2090
2091 config VFPv3
2092         bool
2093         depends on VFP
2094         default y if CPU_V7
2095
2096 config NEON
2097         bool "Advanced SIMD (NEON) Extension support"
2098         depends on VFPv3 && CPU_V7
2099         help
2100           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2101           Extension.
2102
2103 config KERNEL_MODE_NEON
2104         bool "Support for NEON in kernel mode"
2105         depends on NEON && AEABI
2106         help
2107           Say Y to include support for NEON in kernel mode.
2108
2109 endmenu
2110
2111 menu "Userspace binary formats"
2112
2113 source "fs/Kconfig.binfmt"
2114
2115 endmenu
2116
2117 menu "Power management options"
2118
2119 source "kernel/power/Kconfig"
2120
2121 config ARCH_SUSPEND_POSSIBLE
2122         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2123                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2124         def_bool y
2125
2126 config ARM_CPU_SUSPEND
2127         def_bool PM_SLEEP
2128
2129 config ARCH_HIBERNATION_POSSIBLE
2130         bool
2131         depends on MMU
2132         default y if ARCH_SUSPEND_POSSIBLE
2133
2134 endmenu
2135
2136 source "net/Kconfig"
2137
2138 source "drivers/Kconfig"
2139
2140 source "drivers/firmware/Kconfig"
2141
2142 source "fs/Kconfig"
2143
2144 source "arch/arm/Kconfig.debug"
2145
2146 source "security/Kconfig"
2147
2148 source "crypto/Kconfig"
2149 if CRYPTO
2150 source "arch/arm/crypto/Kconfig"
2151 endif
2152
2153 source "lib/Kconfig"
2154
2155 source "arch/arm/kvm/Kconfig"