arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  37         select HAVE_ARCH_KGDB
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OLD_SIGACTION
  80         select OLD_SIGSUSPEND3
  81         select PERF_USE_VMALLOC
  82         select RTC_LIB
  83         select SYS_SUPPORTS_APM_EMULATION
  84         # Above selects are sorted alphabetically; please add new ones
  85         # according to that.  Thanks.
  86         help
  87           The ARM series is a line of low-power-consumption RISC chip designs
  88           licensed by ARM Ltd and targeted at embedded applications and
  89           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  90           manufactured, but legacy ARM-based PC hardware remains popular in
  91           Europe.  There is an ARM Linux project with a web page at
  92           <http://www.arm.linux.org.uk/>.
  93
  94 config ARM_HAS_SG_CHAIN
  95         select ARCH_HAS_SG_CHAIN
  96         bool
  97
  98 config NEED_SG_DMA_LENGTH
  99         bool
 100
 101 config ARM_DMA_USE_IOMMU
 102         bool
 103         select ARM_HAS_SG_CHAIN
 104         select NEED_SG_DMA_LENGTH
 105
 106 if ARM_DMA_USE_IOMMU
 107
 108 config ARM_DMA_IOMMU_ALIGNMENT
 109         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 110         range 4 9
 111         default 8
 112         help
 113           DMA mapping framework by default aligns all buffers to the smallest
 114           PAGE_SIZE order which is greater than or equal to the requested buffer
 115           size. This works well for buffers up to a few hundreds kilobytes, but
 116           for larger buffers it just a waste of address space. Drivers which has
 117           relatively small addressing window (like 64Mib) might run out of
 118           virtual space with just a few allocations.
 119
 120           With this parameter you can specify the maximum PAGE_SIZE order for
 121           DMA IOMMU buffers. Larger buffers will be aligned only to this
 122           specified order. The order is expressed as a power of two multiplied
 123           by the PAGE_SIZE.
 124
 125 endif
 126
 127 config MIGHT_HAVE_PCI
 128         bool
 129
 130 config SYS_SUPPORTS_APM_EMULATION
 131         bool
 132
 133 config HAVE_TCM
 134         bool
 135         select GENERIC_ALLOCATOR
 136
 137 config HAVE_PROC_CPU
 138         bool
 139
 140 config NO_IOPORT_MAP
 141         bool
 142
 143 config EISA
 144         bool
 145         ---help---
 146           The Extended Industry Standard Architecture (EISA) bus was
 147           developed as an open alternative to the IBM MicroChannel bus.
 148
 149           The EISA bus provided some of the features of the IBM MicroChannel
 150           bus while maintaining backward compatibility with cards made for
 151           the older ISA bus.  The EISA bus saw limited use between 1988 and
 152           1995 when it was made obsolete by the PCI bus.
 153
 154           Say Y here if you are building a kernel for an EISA-based machine.
 155
 156           Otherwise, say N.
 157
 158 config SBUS
 159         bool
 160
 161 config STACKTRACE_SUPPORT
 162         bool
 163         default y
 164
 165 config HAVE_LATENCYTOP_SUPPORT
 166         bool
 167         depends on !SMP
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default y
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config GENERIC_HWEIGHT
 192         bool
 193         default y
 194
 195 config GENERIC_CALIBRATE_DELAY
 196         bool
 197         default y
 198
 199 config ARCH_MAY_HAVE_PC_FDC
 200         bool
 201
 202 config ZONE_DMA
 203         bool
 204
 205 config NEED_DMA_MAP_STATE
 206        def_bool y
 207
 208 config ARCH_SUPPORTS_UPROBES
 209         def_bool y
 210
 211 config ARCH_HAS_DMA_SET_COHERENT_MASK
 212         bool
 213
 214 config GENERIC_ISA_DMA
 215         bool
 216
 217 config FIQ
 218         bool
 219
 220 config NEED_RET_TO_USER
 221         bool
 222
 223 config ARCH_MTD_XIP
 224         bool
 225
 226 config VECTORS_BASE
 227         hex
 228         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 229         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 230         default 0x00000000
 231         help
 232           The base address of exception vectors.  This must be two pages
 233           in size.
 234
 235 config ARM_PATCH_PHYS_VIRT
 236         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 237         default y
 238         depends on !XIP_KERNEL && MMU
 239         depends on !ARCH_REALVIEW || !SPARSEMEM
 240         help
 241           Patch phys-to-virt and virt-to-phys translation functions at
 242           boot and module load time according to the position of the
 243           kernel in system memory.
 244
 245           This can only be used with non-XIP MMU kernels where the base
 246           of physical memory is at a 16MB boundary.
 247
 248           Only disable this option if you know that you do not require
 249           this feature (eg, building a kernel for a single machine) and
 250           you need to shrink the kernel to the minimal size.
 251
 252 config NEED_MACH_IO_H
 253         bool
 254         help
 255           Select this when mach/io.h is required to provide special
 256           definitions for this platform.  The need for mach/io.h should
 257           be avoided when possible.
 258
 259 config NEED_MACH_MEMORY_H
 260         bool
 261         help
 262           Select this when mach/memory.h is required to provide special
 263           definitions for this platform.  The need for mach/memory.h should
 264           be avoided when possible.
 265
 266 config PHYS_OFFSET
 267         hex "Physical address of main memory" if MMU
 268         depends on !ARM_PATCH_PHYS_VIRT
 269         default DRAM_BASE if !MMU
 270         default 0x00000000 if ARCH_EBSA110 || \
 271                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 272                         ARCH_FOOTBRIDGE || \
 273                         ARCH_INTEGRATOR || \
 274                         ARCH_IOP13XX || \
 275                         ARCH_KS8695 || \
 276                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 277         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 278         default 0x20000000 if ARCH_S5PV210
 279         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 280         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 281         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 282         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 283         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 284         help
 285           Please provide the physical address corresponding to the
 286           location of main memory in your system.
 287
 288 config GENERIC_BUG
 289         def_bool y
 290         depends on BUG
 291
 292 config PGTABLE_LEVELS
 293         int
 294         default 3 if ARM_LPAE
 295         default 2
 296
 297 source "init/Kconfig"
 298
 299 source "kernel/Kconfig.freezer"
 300
 301 menu "System Type"
 302
 303 config MMU
 304         bool "MMU-based Paged Memory Management Support"
 305         default y
 306         help
 307           Select if you want MMU-based virtualised addressing space
 308           support by paged memory management. If unsure, say 'Y'.
 309
 310 #
 311 # The "ARM system type" choice list is ordered alphabetically by option
 312 # text.  Please add new entries in the option alphabetic order.
 313 #
 314 choice
 315         prompt "ARM system type"
 316         default ARCH_VERSATILE if !MMU
 317         default ARCH_MULTIPLATFORM if MMU
 318
 319 config ARCH_MULTIPLATFORM
 320         bool "Allow multiple platforms to be selected"
 321         depends on MMU
 322         select ARCH_WANT_OPTIONAL_GPIOLIB
 323         select ARM_HAS_SG_CHAIN
 324         select ARM_PATCH_PHYS_VIRT
 325         select AUTO_ZRELADDR
 326         select CLKSRC_OF
 327         select COMMON_CLK
 328         select GENERIC_CLOCKEVENTS
 329         select MIGHT_HAVE_PCI
 330         select MULTI_IRQ_HANDLER
 331         select SPARSE_IRQ
 332         select USE_OF
 333
 334 config ARCH_REALVIEW
 335         bool "ARM Ltd. RealView family"
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_AMBA
 338         select ARM_TIMER_SP804
 339         select COMMON_CLK
 340         select COMMON_CLK_VERSATILE
 341         select GENERIC_CLOCKEVENTS
 342         select GPIO_PL061 if GPIOLIB
 343         select ICST
 344         select NEED_MACH_MEMORY_H
 345         select PLAT_VERSATILE
 346         select PLAT_VERSATILE_SCHED_CLOCK
 347         help
 348           This enables support for ARM Ltd RealView boards.
 349
 350 config ARCH_VERSATILE
 351         bool "ARM Ltd. Versatile family"
 352         select ARCH_WANT_OPTIONAL_GPIOLIB
 353         select ARM_AMBA
 354         select ARM_TIMER_SP804
 355         select ARM_VIC
 356         select CLKDEV_LOOKUP
 357         select GENERIC_CLOCKEVENTS
 358         select HAVE_MACH_CLKDEV
 359         select ICST
 360         select PLAT_VERSATILE
 361         select PLAT_VERSATILE_CLOCK
 362         select PLAT_VERSATILE_SCHED_CLOCK
 363         select VERSATILE_FPGA_IRQ
 364         help
 365           This enables support for ARM Ltd Versatile board.
 366
 367 config ARCH_CLPS711X
 368         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 369         select ARCH_REQUIRE_GPIOLIB
 370         select AUTO_ZRELADDR
 371         select CLKSRC_MMIO
 372         select COMMON_CLK
 373         select CPU_ARM720T
 374         select GENERIC_CLOCKEVENTS
 375         select MFD_SYSCON
 376         select SOC_BUS
 377         help
 378           Support for Cirrus Logic 711x/721x/731x based boards.
 379
 380 config ARCH_GEMINI
 381         bool "Cortina Systems Gemini"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select CLKSRC_MMIO
 384         select CPU_FA526
 385         select GENERIC_CLOCKEVENTS
 386         help
 387           Support for the Cortina Systems Gemini family SoCs
 388
 389 config ARCH_EBSA110
 390         bool "EBSA-110"
 391         select ARCH_USES_GETTIMEOFFSET
 392         select CPU_SA110
 393         select ISA
 394         select NEED_MACH_IO_H
 395         select NEED_MACH_MEMORY_H
 396         select NO_IOPORT_MAP
 397         help
 398           This is an evaluation board for the StrongARM processor available
 399           from Digital. It has limited hardware on-board, including an
 400           Ethernet interface, two PCMCIA sockets, two serial ports and a
 401           parallel port.
 402
 403 config ARCH_EFM32
 404         bool "Energy Micro efm32"
 405         depends on !MMU
 406         select ARCH_REQUIRE_GPIOLIB
 407         select ARM_NVIC
 408         select AUTO_ZRELADDR
 409         select CLKSRC_OF
 410         select COMMON_CLK
 411         select CPU_V7M
 412         select GENERIC_CLOCKEVENTS
 413         select NO_DMA
 414         select NO_IOPORT_MAP
 415         select SPARSE_IRQ
 416         select USE_OF
 417         help
 418           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 419           processors.
 420
 421 config ARCH_EP93XX
 422         bool "EP93xx-based"
 423         select ARCH_HAS_HOLES_MEMORYMODEL
 424         select ARCH_REQUIRE_GPIOLIB
 425         select ARCH_USES_GETTIMEOFFSET
 426         select ARM_AMBA
 427         select ARM_VIC
 428         select CLKDEV_LOOKUP
 429         select CPU_ARM920T
 430         help
 431           This enables support for the Cirrus EP93xx series of CPUs.
 432
 433 config ARCH_FOOTBRIDGE
 434         bool "FootBridge"
 435         select CPU_SA110
 436         select FOOTBRIDGE
 437         select GENERIC_CLOCKEVENTS
 438         select HAVE_IDE
 439         select NEED_MACH_IO_H if !MMU
 440         select NEED_MACH_MEMORY_H
 441         help
 442           Support for systems based on the DC21285 companion chip
 443           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 444
 445 config ARCH_NETX
 446         bool "Hilscher NetX based"
 447         select ARM_VIC
 448         select CLKSRC_MMIO
 449         select CPU_ARM926T
 450         select GENERIC_CLOCKEVENTS
 451         help
 452           This enables support for systems based on the Hilscher NetX Soc
 453
 454 config ARCH_IOP13XX
 455         bool "IOP13xx-based"
 456         depends on MMU
 457         select CPU_XSC3
 458         select NEED_MACH_MEMORY_H
 459         select NEED_RET_TO_USER
 460         select PCI
 461         select PLAT_IOP
 462         select VMSPLIT_1G
 463         select SPARSE_IRQ
 464         help
 465           Support for Intel's IOP13XX (XScale) family of processors.
 466
 467 config ARCH_IOP32X
 468         bool "IOP32x-based"
 469         depends on MMU
 470         select ARCH_REQUIRE_GPIOLIB
 471         select CPU_XSCALE
 472         select GPIO_IOP
 473         select NEED_RET_TO_USER
 474         select PCI
 475         select PLAT_IOP
 476         help
 477           Support for Intel's 80219 and IOP32X (XScale) family of
 478           processors.
 479
 480 config ARCH_IOP33X
 481         bool "IOP33x-based"
 482         depends on MMU
 483         select ARCH_REQUIRE_GPIOLIB
 484         select CPU_XSCALE
 485         select GPIO_IOP
 486         select NEED_RET_TO_USER
 487         select PCI
 488         select PLAT_IOP
 489         help
 490           Support for Intel's IOP33X (XScale) family of processors.
 491
 492 config ARCH_IXP4XX
 493         bool "IXP4xx-based"
 494         depends on MMU
 495         select ARCH_HAS_DMA_SET_COHERENT_MASK
 496         select ARCH_REQUIRE_GPIOLIB
 497         select ARCH_SUPPORTS_BIG_ENDIAN
 498         select CLKSRC_MMIO
 499         select CPU_XSCALE
 500         select DMABOUNCE if PCI
 501         select GENERIC_CLOCKEVENTS
 502         select MIGHT_HAVE_PCI
 503         select NEED_MACH_IO_H
 504         select USB_EHCI_BIG_ENDIAN_DESC
 505         select USB_EHCI_BIG_ENDIAN_MMIO
 506         help
 507           Support for Intel's IXP4XX (XScale) family of processors.
 508
 509 config ARCH_DOVE
 510         bool "Marvell Dove"
 511         select ARCH_REQUIRE_GPIOLIB
 512         select CPU_PJ4
 513         select GENERIC_CLOCKEVENTS
 514         select MIGHT_HAVE_PCI
 515         select MVEBU_MBUS
 516         select PINCTRL
 517         select PINCTRL_DOVE
 518         select PLAT_ORION_LEGACY
 519         help
 520           Support for the Marvell Dove SoC 88AP510
 521
 522 config ARCH_MV78XX0
 523         bool "Marvell MV78xx0"
 524         select ARCH_REQUIRE_GPIOLIB
 525         select CPU_FEROCEON
 526         select GENERIC_CLOCKEVENTS
 527         select MVEBU_MBUS
 528         select PCI
 529         select PLAT_ORION_LEGACY
 530         help
 531           Support for the following Marvell MV78xx0 series SoCs:
 532           MV781x0, MV782x0.
 533
 534 config ARCH_ORION5X
 535         bool "Marvell Orion"
 536         depends on MMU
 537         select ARCH_REQUIRE_GPIOLIB
 538         select CPU_FEROCEON
 539         select GENERIC_CLOCKEVENTS
 540         select MVEBU_MBUS
 541         select PCI
 542         select PLAT_ORION_LEGACY
 543         help
 544           Support for the following Marvell Orion 5x series SoCs:
 545           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 546           Orion-2 (5281), Orion-1-90 (6183).
 547
 548 config ARCH_MMP
 549         bool "Marvell PXA168/910/MMP2"
 550         depends on MMU
 551         select ARCH_REQUIRE_GPIOLIB
 552         select CLKDEV_LOOKUP
 553         select GENERIC_ALLOCATOR
 554         select GENERIC_CLOCKEVENTS
 555         select GPIO_PXA
 556         select IRQ_DOMAIN
 557         select MULTI_IRQ_HANDLER
 558         select PINCTRL
 559         select PLAT_PXA
 560         select SPARSE_IRQ
 561         help
 562           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 563
 564 config ARCH_KS8695
 565         bool "Micrel/Kendin KS8695"
 566         select ARCH_REQUIRE_GPIOLIB
 567         select CLKSRC_MMIO
 568         select CPU_ARM922T
 569         select GENERIC_CLOCKEVENTS
 570         select NEED_MACH_MEMORY_H
 571         help
 572           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 573           System-on-Chip devices.
 574
 575 config ARCH_W90X900
 576         bool "Nuvoton W90X900 CPU"
 577         select ARCH_REQUIRE_GPIOLIB
 578         select CLKDEV_LOOKUP
 579         select CLKSRC_MMIO
 580         select CPU_ARM926T
 581         select GENERIC_CLOCKEVENTS
 582         help
 583           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 584           At present, the w90x900 has been renamed nuc900, regarding
 585           the ARM series product line, you can login the following
 586           link address to know more.
 587
 588           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 589                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 590
 591 config ARCH_LPC32XX
 592         bool "NXP LPC32XX"
 593         select ARCH_REQUIRE_GPIOLIB
 594         select ARM_AMBA
 595         select CLKDEV_LOOKUP
 596         select CLKSRC_MMIO
 597         select CPU_ARM926T
 598         select GENERIC_CLOCKEVENTS
 599         select HAVE_IDE
 600         select USE_OF
 601         help
 602           Support for the NXP LPC32XX family of processors
 603
 604 config ARCH_PXA
 605         bool "PXA2xx/PXA3xx-based"
 606         depends on MMU
 607         select ARCH_MTD_XIP
 608         select ARCH_REQUIRE_GPIOLIB
 609         select ARM_CPU_SUSPEND if PM
 610         select AUTO_ZRELADDR
 611         select CLKDEV_LOOKUP
 612         select CLKSRC_MMIO
 613         select CLKSRC_OF
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select IRQ_DOMAIN
 618         select MULTI_IRQ_HANDLER
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_SHMOBILE_LEGACY
 625         bool "Renesas ARM SoCs (non-multiplatform)"
 626         select ARCH_SHMOBILE
 627         select ARM_PATCH_PHYS_VIRT if MMU
 628         select CLKDEV_LOOKUP
 629         select CPU_V7
 630         select GENERIC_CLOCKEVENTS
 631         select HAVE_ARM_SCU if SMP
 632         select HAVE_ARM_TWD if SMP
 633         select HAVE_SMP
 634         select MIGHT_HAVE_CACHE_L2X0
 635         select MULTI_IRQ_HANDLER
 636         select NO_IOPORT_MAP
 637         select PINCTRL
 638         select PM_GENERIC_DOMAINS if PM
 639         select SH_CLK_CPG
 640         select SPARSE_IRQ
 641         help
 642           Support for Renesas ARM SoC platforms using a non-multiplatform
 643           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 644           and RZ families.
 645
 646 config ARCH_RPC
 647         bool "RiscPC"
 648         select ARCH_ACORN
 649         select ARCH_MAY_HAVE_PC_FDC
 650         select ARCH_SPARSEMEM_ENABLE
 651         select ARCH_USES_GETTIMEOFFSET
 652         select CPU_SA110
 653         select FIQ
 654         select HAVE_IDE
 655         select HAVE_PATA_PLATFORM
 656         select ISA_DMA_API
 657         select NEED_MACH_IO_H
 658         select NEED_MACH_MEMORY_H
 659         select NO_IOPORT_MAP
 660         select VIRT_TO_BUS
 661         help
 662           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 663           CD-ROM interface, serial and parallel port, and the floppy drive.
 664
 665 config ARCH_SA1100
 666         bool "SA1100-based"
 667         select ARCH_MTD_XIP
 668         select ARCH_REQUIRE_GPIOLIB
 669         select ARCH_SPARSEMEM_ENABLE
 670         select CLKDEV_LOOKUP
 671         select CLKSRC_MMIO
 672         select CPU_FREQ
 673         select CPU_SA1100
 674         select GENERIC_CLOCKEVENTS
 675         select HAVE_IDE
 676         select IRQ_DOMAIN
 677         select ISA
 678         select MULTI_IRQ_HANDLER
 679         select NEED_MACH_MEMORY_H
 680         select SPARSE_IRQ
 681         help
 682           Support for StrongARM 11x0 based boards.
 683
 684 config ARCH_S3C24XX
 685         bool "Samsung S3C24XX SoCs"
 686         select ARCH_REQUIRE_GPIOLIB
 687         select ATAGS
 688         select CLKDEV_LOOKUP
 689         select CLKSRC_SAMSUNG_PWM
 690         select GENERIC_CLOCKEVENTS
 691         select GPIO_SAMSUNG
 692         select HAVE_S3C2410_I2C if I2C
 693         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 694         select HAVE_S3C_RTC if RTC_CLASS
 695         select MULTI_IRQ_HANDLER
 696         select NEED_MACH_IO_H
 697         select SAMSUNG_ATAGS
 698         help
 699           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 700           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 701           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 702           Samsung SMDK2410 development board (and derivatives).
 703
 704 config ARCH_S3C64XX
 705         bool "Samsung S3C64XX"
 706         select ARCH_REQUIRE_GPIOLIB
 707         select ARM_AMBA
 708         select ARM_VIC
 709         select ATAGS
 710         select CLKDEV_LOOKUP
 711         select CLKSRC_SAMSUNG_PWM
 712         select COMMON_CLK_SAMSUNG
 713         select CPU_V6K
 714         select GENERIC_CLOCKEVENTS
 715         select GPIO_SAMSUNG
 716         select HAVE_S3C2410_I2C if I2C
 717         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 718         select HAVE_TCM
 719         select NO_IOPORT_MAP
 720         select PLAT_SAMSUNG
 721         select PM_GENERIC_DOMAINS if PM
 722         select S3C_DEV_NAND
 723         select S3C_GPIO_TRACK
 724         select SAMSUNG_ATAGS
 725         select SAMSUNG_WAKEMASK
 726         select SAMSUNG_WDT_RESET
 727         help
 728           Samsung S3C64XX series based systems
 729
 730 config ARCH_DAVINCI
 731         bool "TI DaVinci"
 732         select ARCH_HAS_HOLES_MEMORYMODEL
 733         select ARCH_REQUIRE_GPIOLIB
 734         select CLKDEV_LOOKUP
 735         select GENERIC_ALLOCATOR
 736         select GENERIC_CLOCKEVENTS
 737         select GENERIC_IRQ_CHIP
 738         select HAVE_IDE
 739         select TI_PRIV_EDMA
 740         select USE_OF
 741         select ZONE_DMA
 742         help
 743           Support for TI's DaVinci platform.
 744
 745 config ARCH_OMAP1
 746         bool "TI OMAP1"
 747         depends on MMU
 748         select ARCH_HAS_HOLES_MEMORYMODEL
 749         select ARCH_OMAP
 750         select ARCH_REQUIRE_GPIOLIB
 751         select CLKDEV_LOOKUP
 752         select CLKSRC_MMIO
 753         select GENERIC_CLOCKEVENTS
 754         select GENERIC_IRQ_CHIP
 755         select HAVE_IDE
 756         select IRQ_DOMAIN
 757         select NEED_MACH_IO_H if PCCARD
 758         select NEED_MACH_MEMORY_H
 759         help
 760           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 761
 762 endchoice
 763
 764 menu "Multiple platform selection"
 765         depends on ARCH_MULTIPLATFORM
 766
 767 comment "CPU Core family selection"
 768
 769 config ARCH_MULTI_V4
 770         bool "ARMv4 based platforms (FA526)"
 771         depends on !ARCH_MULTI_V6_V7
 772         select ARCH_MULTI_V4_V5
 773         select CPU_FA526
 774
 775 config ARCH_MULTI_V4T
 776         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 777         depends on !ARCH_MULTI_V6_V7
 778         select ARCH_MULTI_V4_V5
 779         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 780                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 781                 CPU_ARM925T || CPU_ARM940T)
 782
 783 config ARCH_MULTI_V5
 784         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 785         depends on !ARCH_MULTI_V6_V7
 786         select ARCH_MULTI_V4_V5
 787         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 788                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 789                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 790
 791 config ARCH_MULTI_V4_V5
 792         bool
 793
 794 config ARCH_MULTI_V6
 795         bool "ARMv6 based platforms (ARM11)"
 796         select ARCH_MULTI_V6_V7
 797         select CPU_V6K
 798
 799 config ARCH_MULTI_V7
 800         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 801         default y
 802         select ARCH_MULTI_V6_V7
 803         select CPU_V7
 804         select HAVE_SMP
 805
 806 config ARCH_MULTI_V6_V7
 807         bool
 808         select MIGHT_HAVE_CACHE_L2X0
 809
 810 config ARCH_MULTI_CPU_AUTO
 811         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 812         select ARCH_MULTI_V5
 813
 814 endmenu
 815
 816 config ARCH_VIRT
 817         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 818         select ARM_AMBA
 819         select ARM_GIC
 820         select ARM_PSCI
 821         select HAVE_ARM_ARCH_TIMER
 822
 823 #
 824 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 825 # Kconfigs may be included either alphabetically (according to the
 826 # plat- suffix) or along side the corresponding mach-* source.
 827 #
 828 source "arch/arm/mach-mvebu/Kconfig"
 829
 830 source "arch/arm/mach-alpine/Kconfig"
 831
 832 source "arch/arm/mach-asm9260/Kconfig"
 833
 834 source "arch/arm/mach-at91/Kconfig"
 835
 836 source "arch/arm/mach-axxia/Kconfig"
 837
 838 source "arch/arm/mach-bcm/Kconfig"
 839
 840 source "arch/arm/mach-berlin/Kconfig"
 841
 842 source "arch/arm/mach-clps711x/Kconfig"
 843
 844 source "arch/arm/mach-cns3xxx/Kconfig"
 845
 846 source "arch/arm/mach-davinci/Kconfig"
 847
 848 source "arch/arm/mach-digicolor/Kconfig"
 849
 850 source "arch/arm/mach-dove/Kconfig"
 851
 852 source "arch/arm/mach-ep93xx/Kconfig"
 853
 854 source "arch/arm/mach-footbridge/Kconfig"
 855
 856 source "arch/arm/mach-gemini/Kconfig"
 857
 858 source "arch/arm/mach-highbank/Kconfig"
 859
 860 source "arch/arm/mach-hisi/Kconfig"
 861
 862 source "arch/arm/mach-integrator/Kconfig"
 863
 864 source "arch/arm/mach-iop32x/Kconfig"
 865
 866 source "arch/arm/mach-iop33x/Kconfig"
 867
 868 source "arch/arm/mach-iop13xx/Kconfig"
 869
 870 source "arch/arm/mach-ixp4xx/Kconfig"
 871
 872 source "arch/arm/mach-keystone/Kconfig"
 873
 874 source "arch/arm/mach-ks8695/Kconfig"
 875
 876 source "arch/arm/mach-meson/Kconfig"
 877
 878 source "arch/arm/mach-moxart/Kconfig"
 879
 880 source "arch/arm/mach-mv78xx0/Kconfig"
 881
 882 source "arch/arm/mach-imx/Kconfig"
 883
 884 source "arch/arm/mach-mediatek/Kconfig"
 885
 886 source "arch/arm/mach-mxs/Kconfig"
 887
 888 source "arch/arm/mach-netx/Kconfig"
 889
 890 source "arch/arm/mach-nomadik/Kconfig"
 891
 892 source "arch/arm/mach-nspire/Kconfig"
 893
 894 source "arch/arm/plat-omap/Kconfig"
 895
 896 source "arch/arm/mach-omap1/Kconfig"
 897
 898 source "arch/arm/mach-omap2/Kconfig"
 899
 900 source "arch/arm/mach-orion5x/Kconfig"
 901
 902 source "arch/arm/mach-picoxcell/Kconfig"
 903
 904 source "arch/arm/mach-pxa/Kconfig"
 905 source "arch/arm/plat-pxa/Kconfig"
 906
 907 source "arch/arm/mach-mmp/Kconfig"
 908
 909 source "arch/arm/mach-qcom/Kconfig"
 910
 911 source "arch/arm/mach-realview/Kconfig"
 912
 913 source "arch/arm/mach-rockchip/Kconfig"
 914
 915 source "arch/arm/mach-sa1100/Kconfig"
 916
 917 source "arch/arm/mach-socfpga/Kconfig"
 918
 919 source "arch/arm/mach-spear/Kconfig"
 920
 921 source "arch/arm/mach-sti/Kconfig"
 922
 923 source "arch/arm/mach-s3c24xx/Kconfig"
 924
 925 source "arch/arm/mach-s3c64xx/Kconfig"
 926
 927 source "arch/arm/mach-s5pv210/Kconfig"
 928
 929 source "arch/arm/mach-exynos/Kconfig"
 930 source "arch/arm/plat-samsung/Kconfig"
 931
 932 source "arch/arm/mach-shmobile/Kconfig"
 933
 934 source "arch/arm/mach-sunxi/Kconfig"
 935
 936 source "arch/arm/mach-prima2/Kconfig"
 937
 938 source "arch/arm/mach-tegra/Kconfig"
 939
 940 source "arch/arm/mach-u300/Kconfig"
 941
 942 source "arch/arm/mach-ux500/Kconfig"
 943
 944 source "arch/arm/mach-versatile/Kconfig"
 945
 946 source "arch/arm/mach-vexpress/Kconfig"
 947 source "arch/arm/plat-versatile/Kconfig"
 948
 949 source "arch/arm/mach-vt8500/Kconfig"
 950
 951 source "arch/arm/mach-w90x900/Kconfig"
 952
 953 source "arch/arm/mach-zynq/Kconfig"
 954
 955 # Definitions to make life easier
 956 config ARCH_ACORN
 957         bool
 958
 959 config PLAT_IOP
 960         bool
 961         select GENERIC_CLOCKEVENTS
 962
 963 config PLAT_ORION
 964         bool
 965         select CLKSRC_MMIO
 966         select COMMON_CLK
 967         select GENERIC_IRQ_CHIP
 968         select IRQ_DOMAIN
 969
 970 config PLAT_ORION_LEGACY
 971         bool
 972         select PLAT_ORION
 973
 974 config PLAT_PXA
 975         bool
 976
 977 config PLAT_VERSATILE
 978         bool
 979
 980 config ARM_TIMER_SP804
 981         bool
 982         select CLKSRC_MMIO
 983         select CLKSRC_OF if OF
 984
 985 source "arch/arm/firmware/Kconfig"
 986
 987 source arch/arm/mm/Kconfig
 988
 989 config IWMMXT
 990         bool "Enable iWMMXt support"
 991         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 992         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 993         help
 994           Enable support for iWMMXt context switching at run time if
 995           running on a CPU that supports it.
 996
 997 config MULTI_IRQ_HANDLER
 998         bool
 999         help
1000           Allow each machine to specify it's own IRQ handler at run time.
1001
1002 if !MMU
1003 source "arch/arm/Kconfig-nommu"
1004 endif
1005
1006 config PJ4B_ERRATA_4742
1007         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1008         depends on CPU_PJ4B && MACH_ARMADA_370
1009         default y
1010         help
1011           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1012           Event (WFE) IDLE states, a specific timing sensitivity exists between
1013           the retiring WFI/WFE instructions and the newly issued subsequent
1014           instructions.  This sensitivity can result in a CPU hang scenario.
1015           Workaround:
1016           The software must insert either a Data Synchronization Barrier (DSB)
1017           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1018           instruction
1019
1020 config ARM_ERRATA_326103
1021         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1022         depends on CPU_V6
1023         help
1024           Executing a SWP instruction to read-only memory does not set bit 11
1025           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1026           treat the access as a read, preventing a COW from occurring and
1027           causing the faulting task to livelock.
1028
1029 config ARM_ERRATA_411920
1030         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1031         depends on CPU_V6 || CPU_V6K
1032         help
1033           Invalidation of the Instruction Cache operation can
1034           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1035           It does not affect the MPCore. This option enables the ARM Ltd.
1036           recommended workaround.
1037
1038 config ARM_ERRATA_430973
1039         bool "ARM errata: Stale prediction on replaced interworking branch"
1040         depends on CPU_V7
1041         help
1042           This option enables the workaround for the 430973 Cortex-A8
1043           r1p* erratum. If a code sequence containing an ARM/Thumb
1044           interworking branch is replaced with another code sequence at the
1045           same virtual address, whether due to self-modifying code or virtual
1046           to physical address re-mapping, Cortex-A8 does not recover from the
1047           stale interworking branch prediction. This results in Cortex-A8
1048           executing the new code sequence in the incorrect ARM or Thumb state.
1049           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1050           and also flushes the branch target cache at every context switch.
1051           Note that setting specific bits in the ACTLR register may not be
1052           available in non-secure mode.
1053
1054 config ARM_ERRATA_458693
1055         bool "ARM errata: Processor deadlock when a false hazard is created"
1056         depends on CPU_V7
1057         depends on !ARCH_MULTIPLATFORM
1058         help
1059           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1060           erratum. For very specific sequences of memory operations, it is
1061           possible for a hazard condition intended for a cache line to instead
1062           be incorrectly associated with a different cache line. This false
1063           hazard might then cause a processor deadlock. The workaround enables
1064           the L1 caching of the NEON accesses and disables the PLD instruction
1065           in the ACTLR register. Note that setting specific bits in the ACTLR
1066           register may not be available in non-secure mode.
1067
1068 config ARM_ERRATA_460075
1069         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1070         depends on CPU_V7
1071         depends on !ARCH_MULTIPLATFORM
1072         help
1073           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1074           erratum. Any asynchronous access to the L2 cache may encounter a
1075           situation in which recent store transactions to the L2 cache are lost
1076           and overwritten with stale memory contents from external memory. The
1077           workaround disables the write-allocate mode for the L2 cache via the
1078           ACTLR register. Note that setting specific bits in the ACTLR register
1079           may not be available in non-secure mode.
1080
1081 config ARM_ERRATA_742230
1082         bool "ARM errata: DMB operation may be faulty"
1083         depends on CPU_V7 && SMP
1084         depends on !ARCH_MULTIPLATFORM
1085         help
1086           This option enables the workaround for the 742230 Cortex-A9
1087           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1088           between two write operations may not ensure the correct visibility
1089           ordering of the two writes. This workaround sets a specific bit in
1090           the diagnostic register of the Cortex-A9 which causes the DMB
1091           instruction to behave as a DSB, ensuring the correct behaviour of
1092           the two writes.
1093
1094 config ARM_ERRATA_742231
1095         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1096         depends on CPU_V7 && SMP
1097         depends on !ARCH_MULTIPLATFORM
1098         help
1099           This option enables the workaround for the 742231 Cortex-A9
1100           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1101           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1102           accessing some data located in the same cache line, may get corrupted
1103           data due to bad handling of the address hazard when the line gets
1104           replaced from one of the CPUs at the same time as another CPU is
1105           accessing it. This workaround sets specific bits in the diagnostic
1106           register of the Cortex-A9 which reduces the linefill issuing
1107           capabilities of the processor.
1108
1109 config ARM_ERRATA_643719
1110         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1111         depends on CPU_V7 && SMP
1112         default y
1113         help
1114           This option enables the workaround for the 643719 Cortex-A9 (prior to
1115           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1116           register returns zero when it should return one. The workaround
1117           corrects this value, ensuring cache maintenance operations which use
1118           it behave as intended and avoiding data corruption.
1119
1120 config ARM_ERRATA_720789
1121         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1122         depends on CPU_V7
1123         help
1124           This option enables the workaround for the 720789 Cortex-A9 (prior to
1125           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1126           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1127           As a consequence of this erratum, some TLB entries which should be
1128           invalidated are not, resulting in an incoherency in the system page
1129           tables. The workaround changes the TLB flushing routines to invalidate
1130           entries regardless of the ASID.
1131
1132 config ARM_ERRATA_743622
1133         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1134         depends on CPU_V7
1135         depends on !ARCH_MULTIPLATFORM
1136         help
1137           This option enables the workaround for the 743622 Cortex-A9
1138           (r2p*) erratum. Under very rare conditions, a faulty
1139           optimisation in the Cortex-A9 Store Buffer may lead to data
1140           corruption. This workaround sets a specific bit in the diagnostic
1141           register of the Cortex-A9 which disables the Store Buffer
1142           optimisation, preventing the defect from occurring. This has no
1143           visible impact on the overall performance or power consumption of the
1144           processor.
1145
1146 config ARM_ERRATA_751472
1147         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1148         depends on CPU_V7
1149         depends on !ARCH_MULTIPLATFORM
1150         help
1151           This option enables the workaround for the 751472 Cortex-A9 (prior
1152           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1153           completion of a following broadcasted operation if the second
1154           operation is received by a CPU before the ICIALLUIS has completed,
1155           potentially leading to corrupted entries in the cache or TLB.
1156
1157 config ARM_ERRATA_754322
1158         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1159         depends on CPU_V7
1160         help
1161           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1162           r3p*) erratum. A speculative memory access may cause a page table walk
1163           which starts prior to an ASID switch but completes afterwards. This
1164           can populate the micro-TLB with a stale entry which may be hit with
1165           the new ASID. This workaround places two dsb instructions in the mm
1166           switching code so that no page table walks can cross the ASID switch.
1167
1168 config ARM_ERRATA_754327
1169         bool "ARM errata: no automatic Store Buffer drain"
1170         depends on CPU_V7 && SMP
1171         help
1172           This option enables the workaround for the 754327 Cortex-A9 (prior to
1173           r2p0) erratum. The Store Buffer does not have any automatic draining
1174           mechanism and therefore a livelock may occur if an external agent
1175           continuously polls a memory location waiting to observe an update.
1176           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1177           written polling loops from denying visibility of updates to memory.
1178
1179 config ARM_ERRATA_364296
1180         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1181         depends on CPU_V6
1182         help
1183           This options enables the workaround for the 364296 ARM1136
1184           r0p2 erratum (possible cache data corruption with
1185           hit-under-miss enabled). It sets the undocumented bit 31 in
1186           the auxiliary control register and the FI bit in the control
1187           register, thus disabling hit-under-miss without putting the
1188           processor into full low interrupt latency mode. ARM11MPCore
1189           is not affected.
1190
1191 config ARM_ERRATA_764369
1192         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1193         depends on CPU_V7 && SMP
1194         help
1195           This option enables the workaround for erratum 764369
1196           affecting Cortex-A9 MPCore with two or more processors (all
1197           current revisions). Under certain timing circumstances, a data
1198           cache line maintenance operation by MVA targeting an Inner
1199           Shareable memory region may fail to proceed up to either the
1200           Point of Coherency or to the Point of Unification of the
1201           system. This workaround adds a DSB instruction before the
1202           relevant cache maintenance functions and sets a specific bit
1203           in the diagnostic control register of the SCU.
1204
1205 config ARM_ERRATA_775420
1206        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1207        depends on CPU_V7
1208        help
1209          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1210          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1211          operation aborts with MMU exception, it might cause the processor
1212          to deadlock. This workaround puts DSB before executing ISB if
1213          an abort may occur on cache maintenance.
1214
1215 config ARM_ERRATA_798181
1216         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1217         depends on CPU_V7 && SMP
1218         help
1219           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1220           adequately shooting down all use of the old entries. This
1221           option enables the Linux kernel workaround for this erratum
1222           which sends an IPI to the CPUs that are running the same ASID
1223           as the one being invalidated.
1224
1225 config ARM_ERRATA_773022
1226         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1227         depends on CPU_V7
1228         help
1229           This option enables the workaround for the 773022 Cortex-A15
1230           (up to r0p4) erratum. In certain rare sequences of code, the
1231           loop buffer may deliver incorrect instructions. This
1232           workaround disables the loop buffer to avoid the erratum.
1233
1234 endmenu
1235
1236 source "arch/arm/common/Kconfig"
1237
1238 menu "Bus support"
1239
1240 config ISA
1241         bool
1242         help
1243           Find out whether you have ISA slots on your motherboard.  ISA is the
1244           name of a bus system, i.e. the way the CPU talks to the other stuff
1245           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1246           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1247           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1248
1249 # Select ISA DMA controller support
1250 config ISA_DMA
1251         bool
1252         select ISA_DMA_API
1253
1254 # Select ISA DMA interface
1255 config ISA_DMA_API
1256         bool
1257
1258 config PCI
1259         bool "PCI support" if MIGHT_HAVE_PCI
1260         help
1261           Find out whether you have a PCI motherboard. PCI is the name of a
1262           bus system, i.e. the way the CPU talks to the other stuff inside
1263           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1264           VESA. If you have PCI, say Y, otherwise N.
1265
1266 config PCI_DOMAINS
1267         bool
1268         depends on PCI
1269
1270 config PCI_DOMAINS_GENERIC
1271         def_bool PCI_DOMAINS
1272
1273 config PCI_NANOENGINE
1274         bool "BSE nanoEngine PCI support"
1275         depends on SA1100_NANOENGINE
1276         help
1277           Enable PCI on the BSE nanoEngine board.
1278
1279 config PCI_SYSCALL
1280         def_bool PCI
1281
1282 config PCI_HOST_ITE8152
1283         bool
1284         depends on PCI && MACH_ARMCORE
1285         default y
1286         select DMABOUNCE
1287
1288 source "drivers/pci/Kconfig"
1289 source "drivers/pci/pcie/Kconfig"
1290
1291 source "drivers/pcmcia/Kconfig"
1292
1293 endmenu
1294
1295 menu "Kernel Features"
1296
1297 config HAVE_SMP
1298         bool
1299         help
1300           This option should be selected by machines which have an SMP-
1301           capable CPU.
1302
1303           The only effect of this option is to make the SMP-related
1304           options available to the user for configuration.
1305
1306 config SMP
1307         bool "Symmetric Multi-Processing"
1308         depends on CPU_V6K || CPU_V7
1309         depends on GENERIC_CLOCKEVENTS
1310         depends on HAVE_SMP
1311         depends on MMU || ARM_MPU
1312         help
1313           This enables support for systems with more than one CPU. If you have
1314           a system with only one CPU, say N. If you have a system with more
1315           than one CPU, say Y.
1316
1317           If you say N here, the kernel will run on uni- and multiprocessor
1318           machines, but will use only one CPU of a multiprocessor machine. If
1319           you say Y here, the kernel will run on many, but not all,
1320           uniprocessor machines. On a uniprocessor machine, the kernel
1321           will run faster if you say N here.
1322
1323           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1324           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1325           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1326
1327           If you don't know what to do here, say N.
1328
1329 config SMP_ON_UP
1330         bool "Allow booting SMP kernel on uniprocessor systems"
1331         depends on SMP && !XIP_KERNEL && MMU
1332         default y
1333         help
1334           SMP kernels contain instructions which fail on non-SMP processors.
1335           Enabling this option allows the kernel to modify itself to make
1336           these instructions safe.  Disabling it allows about 1K of space
1337           savings.
1338
1339           If you don't know what to do here, say Y.
1340
1341 config ARM_CPU_TOPOLOGY
1342         bool "Support cpu topology definition"
1343         depends on SMP && CPU_V7
1344         default y
1345         help
1346           Support ARM cpu topology definition. The MPIDR register defines
1347           affinity between processors which is then used to describe the cpu
1348           topology of an ARM System.
1349
1350 config SCHED_MC
1351         bool "Multi-core scheduler support"
1352         depends on ARM_CPU_TOPOLOGY
1353         help
1354           Multi-core scheduler support improves the CPU scheduler's decision
1355           making when dealing with multi-core CPU chips at a cost of slightly
1356           increased overhead in some places. If unsure say N here.
1357
1358 config SCHED_SMT
1359         bool "SMT scheduler support"
1360         depends on ARM_CPU_TOPOLOGY
1361         help
1362           Improves the CPU scheduler's decision making when dealing with
1363           MultiThreading at a cost of slightly increased overhead in some
1364           places. If unsure say N here.
1365
1366 config HAVE_ARM_SCU
1367         bool
1368         help
1369           This option enables support for the ARM system coherency unit
1370
1371 config HAVE_ARM_ARCH_TIMER
1372         bool "Architected timer support"
1373         depends on CPU_V7
1374         select ARM_ARCH_TIMER
1375         select GENERIC_CLOCKEVENTS
1376         help
1377           This option enables support for the ARM architected timer
1378
1379 config HAVE_ARM_TWD
1380         bool
1381         depends on SMP
1382         select CLKSRC_OF if OF
1383         help
1384           This options enables support for the ARM timer and watchdog unit
1385
1386 config MCPM
1387         bool "Multi-Cluster Power Management"
1388         depends on CPU_V7 && SMP
1389         help
1390           This option provides the common power management infrastructure
1391           for (multi-)cluster based systems, such as big.LITTLE based
1392           systems.
1393
1394 config MCPM_QUAD_CLUSTER
1395         bool
1396         depends on MCPM
1397         help
1398           To avoid wasting resources unnecessarily, MCPM only supports up
1399           to 2 clusters by default.
1400           Platforms with 3 or 4 clusters that use MCPM must select this
1401           option to allow the additional clusters to be managed.
1402
1403 config BIG_LITTLE
1404         bool "big.LITTLE support (Experimental)"
1405         depends on CPU_V7 && SMP
1406         select MCPM
1407         help
1408           This option enables support selections for the big.LITTLE
1409           system architecture.
1410
1411 config BL_SWITCHER
1412         bool "big.LITTLE switcher support"
1413         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1414         select ARM_CPU_SUSPEND
1415         select CPU_PM
1416         help
1417           The big.LITTLE "switcher" provides the core functionality to
1418           transparently handle transition between a cluster of A15's
1419           and a cluster of A7's in a big.LITTLE system.
1420
1421 config BL_SWITCHER_DUMMY_IF
1422         tristate "Simple big.LITTLE switcher user interface"
1423         depends on BL_SWITCHER && DEBUG_KERNEL
1424         help
1425           This is a simple and dummy char dev interface to control
1426           the big.LITTLE switcher core code.  It is meant for
1427           debugging purposes only.
1428
1429 choice
1430         prompt "Memory split"
1431         depends on MMU
1432         default VMSPLIT_3G
1433         help
1434           Select the desired split between kernel and user memory.
1435
1436           If you are not absolutely sure what you are doing, leave this
1437           option alone!
1438
1439         config VMSPLIT_3G
1440                 bool "3G/1G user/kernel split"
1441         config VMSPLIT_2G
1442                 bool "2G/2G user/kernel split"
1443         config VMSPLIT_1G
1444                 bool "1G/3G user/kernel split"
1445 endchoice
1446
1447 config PAGE_OFFSET
1448         hex
1449         default PHYS_OFFSET if !MMU
1450         default 0x40000000 if VMSPLIT_1G
1451         default 0x80000000 if VMSPLIT_2G
1452         default 0xC0000000
1453
1454 config NR_CPUS
1455         int "Maximum number of CPUs (2-32)"
1456         range 2 32
1457         depends on SMP
1458         default "4"
1459
1460 config HOTPLUG_CPU
1461         bool "Support for hot-pluggable CPUs"
1462         depends on SMP
1463         help
1464           Say Y here to experiment with turning CPUs off and on.  CPUs
1465           can be controlled through /sys/devices/system/cpu.
1466
1467 config ARM_PSCI
1468         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1469         depends on CPU_V7
1470         help
1471           Say Y here if you want Linux to communicate with system firmware
1472           implementing the PSCI specification for CPU-centric power
1473           management operations described in ARM document number ARM DEN
1474           0022A ("Power State Coordination Interface System Software on
1475           ARM processors").
1476
1477 # The GPIO number here must be sorted by descending number. In case of
1478 # a multiplatform kernel, we just want the highest value required by the
1479 # selected platforms.
1480 config ARCH_NR_GPIO
1481         int
1482         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1483         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1484                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1485         default 416 if ARCH_SUNXI
1486         default 392 if ARCH_U8500
1487         default 352 if ARCH_VT8500
1488         default 288 if ARCH_ROCKCHIP
1489         default 264 if MACH_H4700
1490         default 0
1491         help
1492           Maximum number of GPIOs in the system.
1493
1494           If unsure, leave the default value.
1495
1496 source kernel/Kconfig.preempt
1497
1498 config HZ_FIXED
1499         int
1500         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1501                 ARCH_S5PV210 || ARCH_EXYNOS4
1502         default 128 if SOC_AT91RM9200
1503         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1504         default 0
1505
1506 choice
1507         depends on HZ_FIXED = 0
1508         prompt "Timer frequency"
1509
1510 config HZ_100
1511         bool "100 Hz"
1512
1513 config HZ_200
1514         bool "200 Hz"
1515
1516 config HZ_250
1517         bool "250 Hz"
1518
1519 config HZ_300
1520         bool "300 Hz"
1521
1522 config HZ_500
1523         bool "500 Hz"
1524
1525 config HZ_1000
1526         bool "1000 Hz"
1527
1528 endchoice
1529
1530 config HZ
1531         int
1532         default HZ_FIXED if HZ_FIXED != 0
1533         default 100 if HZ_100
1534         default 200 if HZ_200
1535         default 250 if HZ_250
1536         default 300 if HZ_300
1537         default 500 if HZ_500
1538         default 1000
1539
1540 config SCHED_HRTICK
1541         def_bool HIGH_RES_TIMERS
1542
1543 config THUMB2_KERNEL
1544         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1545         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1546         default y if CPU_THUMBONLY
1547         select AEABI
1548         select ARM_ASM_UNIFIED
1549         select ARM_UNWIND
1550         help
1551           By enabling this option, the kernel will be compiled in
1552           Thumb-2 mode. A compiler/assembler that understand the unified
1553           ARM-Thumb syntax is needed.
1554
1555           If unsure, say N.
1556
1557 config THUMB2_AVOID_R_ARM_THM_JUMP11
1558         bool "Work around buggy Thumb-2 short branch relocations in gas"
1559         depends on THUMB2_KERNEL && MODULES
1560         default y
1561         help
1562           Various binutils versions can resolve Thumb-2 branches to
1563           locally-defined, preemptible global symbols as short-range "b.n"
1564           branch instructions.
1565
1566           This is a problem, because there's no guarantee the final
1567           destination of the symbol, or any candidate locations for a
1568           trampoline, are within range of the branch.  For this reason, the
1569           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1570           relocation in modules at all, and it makes little sense to add
1571           support.
1572
1573           The symptom is that the kernel fails with an "unsupported
1574           relocation" error when loading some modules.
1575
1576           Until fixed tools are available, passing
1577           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1578           code which hits this problem, at the cost of a bit of extra runtime
1579           stack usage in some cases.
1580
1581           The problem is described in more detail at:
1582               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1583
1584           Only Thumb-2 kernels are affected.
1585
1586           Unless you are sure your tools don't have this problem, say Y.
1587
1588 config ARM_ASM_UNIFIED
1589         bool
1590
1591 config AEABI
1592         bool "Use the ARM EABI to compile the kernel"
1593         help
1594           This option allows for the kernel to be compiled using the latest
1595           ARM ABI (aka EABI).  This is only useful if you are using a user
1596           space environment that is also compiled with EABI.
1597
1598           Since there are major incompatibilities between the legacy ABI and
1599           EABI, especially with regard to structure member alignment, this
1600           option also changes the kernel syscall calling convention to
1601           disambiguate both ABIs and allow for backward compatibility support
1602           (selected with CONFIG_OABI_COMPAT).
1603
1604           To use this you need GCC version 4.0.0 or later.
1605
1606 config OABI_COMPAT
1607         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1608         depends on AEABI && !THUMB2_KERNEL
1609         help
1610           This option preserves the old syscall interface along with the
1611           new (ARM EABI) one. It also provides a compatibility layer to
1612           intercept syscalls that have structure arguments which layout
1613           in memory differs between the legacy ABI and the new ARM EABI
1614           (only for non "thumb" binaries). This option adds a tiny
1615           overhead to all syscalls and produces a slightly larger kernel.
1616
1617           The seccomp filter system will not be available when this is
1618           selected, since there is no way yet to sensibly distinguish
1619           between calling conventions during filtering.
1620
1621           If you know you'll be using only pure EABI user space then you
1622           can say N here. If this option is not selected and you attempt
1623           to execute a legacy ABI binary then the result will be
1624           UNPREDICTABLE (in fact it can be predicted that it won't work
1625           at all). If in doubt say N.
1626
1627 config ARCH_HAS_HOLES_MEMORYMODEL
1628         bool
1629
1630 config ARCH_SPARSEMEM_ENABLE
1631         bool
1632
1633 config ARCH_SPARSEMEM_DEFAULT
1634         def_bool ARCH_SPARSEMEM_ENABLE
1635
1636 config ARCH_SELECT_MEMORY_MODEL
1637         def_bool ARCH_SPARSEMEM_ENABLE
1638
1639 config HAVE_ARCH_PFN_VALID
1640         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1641
1642 config HAVE_GENERIC_RCU_GUP
1643         def_bool y
1644         depends on ARM_LPAE
1645
1646 config HIGHMEM
1647         bool "High Memory Support"
1648         depends on MMU
1649         help
1650           The address space of ARM processors is only 4 Gigabytes large
1651           and it has to accommodate user address space, kernel address
1652           space as well as some memory mapped IO. That means that, if you
1653           have a large amount of physical memory and/or IO, not all of the
1654           memory can be "permanently mapped" by the kernel. The physical
1655           memory that is not permanently mapped is called "high memory".
1656
1657           Depending on the selected kernel/user memory split, minimum
1658           vmalloc space and actual amount of RAM, you may not need this
1659           option which should result in a slightly faster kernel.
1660
1661           If unsure, say n.
1662
1663 config HIGHPTE
1664         bool "Allocate 2nd-level pagetables from highmem"
1665         depends on HIGHMEM
1666
1667 config HW_PERF_EVENTS
1668         bool "Enable hardware performance counter support for perf events"
1669         depends on PERF_EVENTS
1670         default y
1671         help
1672           Enable hardware performance counter support for perf events. If
1673           disabled, perf events will use software events only.
1674
1675 config SYS_SUPPORTS_HUGETLBFS
1676        def_bool y
1677        depends on ARM_LPAE
1678
1679 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1680        def_bool y
1681        depends on ARM_LPAE
1682
1683 config ARCH_WANT_GENERAL_HUGETLB
1684         def_bool y
1685
1686 source "mm/Kconfig"
1687
1688 config FORCE_MAX_ZONEORDER
1689         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1690         range 11 64 if ARCH_SHMOBILE_LEGACY
1691         default "12" if SOC_AM33XX
1692         default "9" if SA1111 || ARCH_EFM32
1693         default "11"
1694         help
1695           The kernel memory allocator divides physically contiguous memory
1696           blocks into "zones", where each zone is a power of two number of
1697           pages.  This option selects the largest power of two that the kernel
1698           keeps in the memory allocator.  If you need to allocate very large
1699           blocks of physically contiguous memory, then you may need to
1700           increase this value.
1701
1702           This config option is actually maximum order plus one. For example,
1703           a value of 11 means that the largest free memory block is 2^10 pages.
1704
1705 config ALIGNMENT_TRAP
1706         bool
1707         depends on CPU_CP15_MMU
1708         default y if !ARCH_EBSA110
1709         select HAVE_PROC_CPU if PROC_FS
1710         help
1711           ARM processors cannot fetch/store information which is not
1712           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1713           address divisible by 4. On 32-bit ARM processors, these non-aligned
1714           fetch/store instructions will be emulated in software if you say
1715           here, which has a severe performance impact. This is necessary for
1716           correct operation of some network protocols. With an IP-only
1717           configuration it is safe to say N, otherwise say Y.
1718
1719 config UACCESS_WITH_MEMCPY
1720         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1721         depends on MMU
1722         default y if CPU_FEROCEON
1723         help
1724           Implement faster copy_to_user and clear_user methods for CPU
1725           cores where a 8-word STM instruction give significantly higher
1726           memory write throughput than a sequence of individual 32bit stores.
1727
1728           A possible side effect is a slight increase in scheduling latency
1729           between threads sharing the same address space if they invoke
1730           such copy operations with large buffers.
1731
1732           However, if the CPU data cache is using a write-allocate mode,
1733           this option is unlikely to provide any performance gain.
1734
1735 config SECCOMP
1736         bool
1737         prompt "Enable seccomp to safely compute untrusted bytecode"
1738         ---help---
1739           This kernel feature is useful for number crunching applications
1740           that may need to compute untrusted bytecode during their
1741           execution. By using pipes or other transports made available to
1742           the process as file descriptors supporting the read/write
1743           syscalls, it's possible to isolate those applications in
1744           their own address space using seccomp. Once seccomp is
1745           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1746           and the task is only allowed to execute a few safe syscalls
1747           defined by each seccomp mode.
1748
1749 config SWIOTLB
1750         def_bool y
1751
1752 config IOMMU_HELPER
1753         def_bool SWIOTLB
1754
1755 config XEN_DOM0
1756         def_bool y
1757         depends on XEN
1758
1759 config XEN
1760         bool "Xen guest support on ARM"
1761         depends on ARM && AEABI && OF
1762         depends on CPU_V7 && !CPU_V6
1763         depends on !GENERIC_ATOMIC64
1764         depends on MMU
1765         select ARCH_DMA_ADDR_T_64BIT
1766         select ARM_PSCI
1767         select SWIOTLB_XEN
1768         help
1769           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1770
1771 endmenu
1772
1773 menu "Boot options"
1774
1775 config USE_OF
1776         bool "Flattened Device Tree support"
1777         select IRQ_DOMAIN
1778         select OF
1779         select OF_EARLY_FLATTREE
1780         select OF_RESERVED_MEM
1781         help
1782           Include support for flattened device tree machine descriptions.
1783
1784 config ATAGS
1785         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1786         default y
1787         help
1788           This is the traditional way of passing data to the kernel at boot
1789           time. If you are solely relying on the flattened device tree (or
1790           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1791           to remove ATAGS support from your kernel binary.  If unsure,
1792           leave this to y.
1793
1794 config DEPRECATED_PARAM_STRUCT
1795         bool "Provide old way to pass kernel parameters"
1796         depends on ATAGS
1797         help
1798           This was deprecated in 2001 and announced to live on for 5 years.
1799           Some old boot loaders still use this way.
1800
1801 # Compressed boot loader in ROM.  Yes, we really want to ask about
1802 # TEXT and BSS so we preserve their values in the config files.
1803 config ZBOOT_ROM_TEXT
1804         hex "Compressed ROM boot loader base address"
1805         default "0"
1806         help
1807           The physical address at which the ROM-able zImage is to be
1808           placed in the target.  Platforms which normally make use of
1809           ROM-able zImage formats normally set this to a suitable
1810           value in their defconfig file.
1811
1812           If ZBOOT_ROM is not enabled, this has no effect.
1813
1814 config ZBOOT_ROM_BSS
1815         hex "Compressed ROM boot loader BSS address"
1816         default "0"
1817         help
1818           The base address of an area of read/write memory in the target
1819           for the ROM-able zImage which must be available while the
1820           decompressor is running. It must be large enough to hold the
1821           entire decompressed kernel plus an additional 128 KiB.
1822           Platforms which normally make use of ROM-able zImage formats
1823           normally set this to a suitable value in their defconfig file.
1824
1825           If ZBOOT_ROM is not enabled, this has no effect.
1826
1827 config ZBOOT_ROM
1828         bool "Compressed boot loader in ROM/flash"
1829         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1830         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1831         help
1832           Say Y here if you intend to execute your compressed kernel image
1833           (zImage) directly from ROM or flash.  If unsure, say N.
1834
1835 config ARM_APPENDED_DTB
1836         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1837         depends on OF
1838         help
1839           With this option, the boot code will look for a device tree binary
1840           (DTB) appended to zImage
1841           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1842
1843           This is meant as a backward compatibility convenience for those
1844           systems with a bootloader that can't be upgraded to accommodate
1845           the documented boot protocol using a device tree.
1846
1847           Beware that there is very little in terms of protection against
1848           this option being confused by leftover garbage in memory that might
1849           look like a DTB header after a reboot if no actual DTB is appended
1850           to zImage.  Do not leave this option active in a production kernel
1851           if you don't intend to always append a DTB.  Proper passing of the
1852           location into r2 of a bootloader provided DTB is always preferable
1853           to this option.
1854
1855 config ARM_ATAG_DTB_COMPAT
1856         bool "Supplement the appended DTB with traditional ATAG information"
1857         depends on ARM_APPENDED_DTB
1858         help
1859           Some old bootloaders can't be updated to a DTB capable one, yet
1860           they provide ATAGs with memory configuration, the ramdisk address,
1861           the kernel cmdline string, etc.  Such information is dynamically
1862           provided by the bootloader and can't always be stored in a static
1863           DTB.  To allow a device tree enabled kernel to be used with such
1864           bootloaders, this option allows zImage to extract the information
1865           from the ATAG list and store it at run time into the appended DTB.
1866
1867 choice
1868         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1869         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1870
1871 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1872         bool "Use bootloader kernel arguments if available"
1873         help
1874           Uses the command-line options passed by the boot loader instead of
1875           the device tree bootargs property. If the boot loader doesn't provide
1876           any, the device tree bootargs property will be used.
1877
1878 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1879         bool "Extend with bootloader kernel arguments"
1880         help
1881           The command-line arguments provided by the boot loader will be
1882           appended to the the device tree bootargs property.
1883
1884 endchoice
1885
1886 config CMDLINE
1887         string "Default kernel command string"
1888         default ""
1889         help
1890           On some architectures (EBSA110 and CATS), there is currently no way
1891           for the boot loader to pass arguments to the kernel. For these
1892           architectures, you should supply some command-line options at build
1893           time by entering them here. As a minimum, you should specify the
1894           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1895
1896 choice
1897         prompt "Kernel command line type" if CMDLINE != ""
1898         default CMDLINE_FROM_BOOTLOADER
1899         depends on ATAGS
1900
1901 config CMDLINE_FROM_BOOTLOADER
1902         bool "Use bootloader kernel arguments if available"
1903         help
1904           Uses the command-line options passed by the boot loader. If
1905           the boot loader doesn't provide any, the default kernel command
1906           string provided in CMDLINE will be used.
1907
1908 config CMDLINE_EXTEND
1909         bool "Extend bootloader kernel arguments"
1910         help
1911           The command-line arguments provided by the boot loader will be
1912           appended to the default kernel command string.
1913
1914 config CMDLINE_FORCE
1915         bool "Always use the default kernel command string"
1916         help
1917           Always use the default kernel command string, even if the boot
1918           loader passes other arguments to the kernel.
1919           This is useful if you cannot or don't want to change the
1920           command-line options your boot loader passes to the kernel.
1921 endchoice
1922
1923 config XIP_KERNEL
1924         bool "Kernel Execute-In-Place from ROM"
1925         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1926         help
1927           Execute-In-Place allows the kernel to run from non-volatile storage
1928           directly addressable by the CPU, such as NOR flash. This saves RAM
1929           space since the text section of the kernel is not loaded from flash
1930           to RAM.  Read-write sections, such as the data section and stack,
1931           are still copied to RAM.  The XIP kernel is not compressed since
1932           it has to run directly from flash, so it will take more space to
1933           store it.  The flash address used to link the kernel object files,
1934           and for storing it, is configuration dependent. Therefore, if you
1935           say Y here, you must know the proper physical address where to
1936           store the kernel image depending on your own flash memory usage.
1937
1938           Also note that the make target becomes "make xipImage" rather than
1939           "make zImage" or "make Image".  The final kernel binary to put in
1940           ROM memory will be arch/arm/boot/xipImage.
1941
1942           If unsure, say N.
1943
1944 config XIP_PHYS_ADDR
1945         hex "XIP Kernel Physical Location"
1946         depends on XIP_KERNEL
1947         default "0x00080000"
1948         help
1949           This is the physical address in your flash memory the kernel will
1950           be linked for and stored to.  This address is dependent on your
1951           own flash usage.
1952
1953 config KEXEC
1954         bool "Kexec system call (EXPERIMENTAL)"
1955         depends on (!SMP || PM_SLEEP_SMP)
1956         help
1957           kexec is a system call that implements the ability to shutdown your
1958           current kernel, and to start another kernel.  It is like a reboot
1959           but it is independent of the system firmware.   And like a reboot
1960           you can start any kernel with it, not just Linux.
1961
1962           It is an ongoing process to be certain the hardware in a machine
1963           is properly shutdown, so do not be surprised if this code does not
1964           initially work for you.
1965
1966 config ATAGS_PROC
1967         bool "Export atags in procfs"
1968         depends on ATAGS && KEXEC
1969         default y
1970         help
1971           Should the atags used to boot the kernel be exported in an "atags"
1972           file in procfs. Useful with kexec.
1973
1974 config CRASH_DUMP
1975         bool "Build kdump crash kernel (EXPERIMENTAL)"
1976         help
1977           Generate crash dump after being started by kexec. This should
1978           be normally only set in special crash dump kernels which are
1979           loaded in the main kernel with kexec-tools into a specially
1980           reserved region and then later executed after a crash by
1981           kdump/kexec. The crash dump kernel must be compiled to a
1982           memory address not used by the main kernel
1983
1984           For more details see Documentation/kdump/kdump.txt
1985
1986 config AUTO_ZRELADDR
1987         bool "Auto calculation of the decompressed kernel image address"
1988         help
1989           ZRELADDR is the physical address where the decompressed kernel
1990           image will be placed. If AUTO_ZRELADDR is selected, the address
1991           will be determined at run-time by masking the current IP with
1992           0xf8000000. This assumes the zImage being placed in the first 128MB
1993           from start of memory.
1994
1995 endmenu
1996
1997 menu "CPU Power Management"
1998
1999 source "drivers/cpufreq/Kconfig"
2000
2001 source "drivers/cpuidle/Kconfig"
2002
2003 endmenu
2004
2005 menu "Floating point emulation"
2006
2007 comment "At least one emulation must be selected"
2008
2009 config FPE_NWFPE
2010         bool "NWFPE math emulation"
2011         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2012         ---help---
2013           Say Y to include the NWFPE floating point emulator in the kernel.
2014           This is necessary to run most binaries. Linux does not currently
2015           support floating point hardware so you need to say Y here even if
2016           your machine has an FPA or floating point co-processor podule.
2017
2018           You may say N here if you are going to load the Acorn FPEmulator
2019           early in the bootup.
2020
2021 config FPE_NWFPE_XP
2022         bool "Support extended precision"
2023         depends on FPE_NWFPE
2024         help
2025           Say Y to include 80-bit support in the kernel floating-point
2026           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2027           Note that gcc does not generate 80-bit operations by default,
2028           so in most cases this option only enlarges the size of the
2029           floating point emulator without any good reason.
2030
2031           You almost surely want to say N here.
2032
2033 config FPE_FASTFPE
2034         bool "FastFPE math emulation (EXPERIMENTAL)"
2035         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2036         ---help---
2037           Say Y here to include the FAST floating point emulator in the kernel.
2038           This is an experimental much faster emulator which now also has full
2039           precision for the mantissa.  It does not support any exceptions.
2040           It is very simple, and approximately 3-6 times faster than NWFPE.
2041
2042           It should be sufficient for most programs.  It may be not suitable
2043           for scientific calculations, but you have to check this for yourself.
2044           If you do not feel you need a faster FP emulation you should better
2045           choose NWFPE.
2046
2047 config VFP
2048         bool "VFP-format floating point maths"
2049         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2050         help
2051           Say Y to include VFP support code in the kernel. This is needed
2052           if your hardware includes a VFP unit.
2053
2054           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2055           release notes and additional status information.
2056
2057           Say N if your target does not have VFP hardware.
2058
2059 config VFPv3
2060         bool
2061         depends on VFP
2062         default y if CPU_V7
2063
2064 config NEON
2065         bool "Advanced SIMD (NEON) Extension support"
2066         depends on VFPv3 && CPU_V7
2067         help
2068           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2069           Extension.
2070
2071 config KERNEL_MODE_NEON
2072         bool "Support for NEON in kernel mode"
2073         depends on NEON && AEABI
2074         help
2075           Say Y to include support for NEON in kernel mode.
2076
2077 endmenu
2078
2079 menu "Userspace binary formats"
2080
2081 source "fs/Kconfig.binfmt"
2082
2083 endmenu
2084
2085 menu "Power management options"
2086
2087 source "kernel/power/Kconfig"
2088
2089 config ARCH_SUSPEND_POSSIBLE
2090         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2091                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2092         def_bool y
2093
2094 config ARM_CPU_SUSPEND
2095         def_bool PM_SLEEP
2096
2097 config ARCH_HIBERNATION_POSSIBLE
2098         bool
2099         depends on MMU
2100         default y if ARCH_SUSPEND_POSSIBLE
2101
2102 endmenu
2103
2104 source "net/Kconfig"
2105
2106 source "drivers/Kconfig"
2107
2108 source "drivers/firmware/Kconfig"
2109
2110 source "fs/Kconfig"
2111
2112 source "arch/arm/Kconfig.debug"
2113
2114 source "security/Kconfig"
2115
2116 source "crypto/Kconfig"
2117 if CRYPTO
2118 source "arch/arm/crypto/Kconfig"
2119 endif
2120
2121 source "lib/Kconfig"
2122
2123 source "arch/arm/kvm/Kconfig"