arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_PCI_IOMAP
  25         select GENERIC_SCHED_CLOCK
  26         select GENERIC_SMP_IDLE_THREAD
  27         select GENERIC_STRNCPY_FROM_USER
  28         select GENERIC_STRNLEN_USER
  29         select HANDLE_DOMAIN_IRQ
  30         select HARDIRQS_SW_RESEND
  31         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  33         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  34         select HAVE_ARCH_KGDB
  35         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  36         select HAVE_ARCH_TRACEHOOK
  37         select HAVE_BPF_JIT
  38         select HAVE_CC_STACKPROTECTOR
  39         select HAVE_CONTEXT_TRACKING
  40         select HAVE_C_RECORDMCOUNT
  41         select HAVE_DEBUG_KMEMLEAK
  42         select HAVE_DMA_API_DEBUG
  43         select HAVE_DMA_ATTRS
  44         select HAVE_DMA_CONTIGUOUS if MMU
  45         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  46         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  47         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  48         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  49         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  50         select HAVE_GENERIC_DMA_COHERENT
  51         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  52         select HAVE_IDE if PCI || ISA || PCMCIA
  53         select HAVE_IRQ_TIME_ACCOUNTING
  54         select HAVE_KERNEL_GZIP
  55         select HAVE_KERNEL_LZ4
  56         select HAVE_KERNEL_LZMA
  57         select HAVE_KERNEL_LZO
  58         select HAVE_KERNEL_XZ
  59         select HAVE_KPROBES if !XIP_KERNEL
  60         select HAVE_KRETPROBES if (HAVE_KPROBES)
  61         select HAVE_MEMBLOCK
  62         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  63         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  64         select HAVE_OPTPROBES if !THUMB2_KERNEL
  65         select HAVE_PERF_EVENTS
  66         select HAVE_PERF_REGS
  67         select HAVE_PERF_USER_STACK_DUMP
  68         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  69         select HAVE_REGS_AND_STACK_ACCESS_API
  70         select HAVE_SYSCALL_TRACEPOINTS
  71         select HAVE_UID16
  72         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  73         select IRQ_FORCED_THREADING
  74         select MODULES_USE_ELF_REL
  75         select NO_BOOTMEM
  76         select OLD_SIGACTION
  77         select OLD_SIGSUSPEND3
  78         select PERF_USE_VMALLOC
  79         select RTC_LIB
  80         select SYS_SUPPORTS_APM_EMULATION
  81         # Above selects are sorted alphabetically; please add new ones
  82         # according to that.  Thanks.
  83         help
  84           The ARM series is a line of low-power-consumption RISC chip designs
  85           licensed by ARM Ltd and targeted at embedded applications and
  86           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  87           manufactured, but legacy ARM-based PC hardware remains popular in
  88           Europe.  There is an ARM Linux project with a web page at
  89           <http://www.arm.linux.org.uk/>.
  90
  91 config ARM_HAS_SG_CHAIN
  92         select ARCH_HAS_SG_CHAIN
  93         bool
  94
  95 config NEED_SG_DMA_LENGTH
  96         bool
  97
  98 config ARM_DMA_USE_IOMMU
  99         bool
 100         select ARM_HAS_SG_CHAIN
 101         select NEED_SG_DMA_LENGTH
 102
 103 if ARM_DMA_USE_IOMMU
 104
 105 config ARM_DMA_IOMMU_ALIGNMENT
 106         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 107         range 4 9
 108         default 8
 109         help
 110           DMA mapping framework by default aligns all buffers to the smallest
 111           PAGE_SIZE order which is greater than or equal to the requested buffer
 112           size. This works well for buffers up to a few hundreds kilobytes, but
 113           for larger buffers it just a waste of address space. Drivers which has
 114           relatively small addressing window (like 64Mib) might run out of
 115           virtual space with just a few allocations.
 116
 117           With this parameter you can specify the maximum PAGE_SIZE order for
 118           DMA IOMMU buffers. Larger buffers will be aligned only to this
 119           specified order. The order is expressed as a power of two multiplied
 120           by the PAGE_SIZE.
 121
 122 endif
 123
 124 config MIGHT_HAVE_PCI
 125         bool
 126
 127 config SYS_SUPPORTS_APM_EMULATION
 128         bool
 129
 130 config HAVE_TCM
 131         bool
 132         select GENERIC_ALLOCATOR
 133
 134 config HAVE_PROC_CPU
 135         bool
 136
 137 config NO_IOPORT_MAP
 138         bool
 139
 140 config EISA
 141         bool
 142         ---help---
 143           The Extended Industry Standard Architecture (EISA) bus was
 144           developed as an open alternative to the IBM MicroChannel bus.
 145
 146           The EISA bus provided some of the features of the IBM MicroChannel
 147           bus while maintaining backward compatibility with cards made for
 148           the older ISA bus.  The EISA bus saw limited use between 1988 and
 149           1995 when it was made obsolete by the PCI bus.
 150
 151           Say Y here if you are building a kernel for an EISA-based machine.
 152
 153           Otherwise, say N.
 154
 155 config SBUS
 156         bool
 157
 158 config STACKTRACE_SUPPORT
 159         bool
 160         default y
 161
 162 config HAVE_LATENCYTOP_SUPPORT
 163         bool
 164         depends on !SMP
 165         default y
 166
 167 config LOCKDEP_SUPPORT
 168         bool
 169         default y
 170
 171 config TRACE_IRQFLAGS_SUPPORT
 172         bool
 173         default y
 174
 175 config RWSEM_XCHGADD_ALGORITHM
 176         bool
 177         default y
 178
 179 config ARCH_HAS_ILOG2_U32
 180         bool
 181
 182 config ARCH_HAS_ILOG2_U64
 183         bool
 184
 185 config ARCH_HAS_BANDGAP
 186         bool
 187
 188 config GENERIC_HWEIGHT
 189         bool
 190         default y
 191
 192 config GENERIC_CALIBRATE_DELAY
 193         bool
 194         default y
 195
 196 config ARCH_MAY_HAVE_PC_FDC
 197         bool
 198
 199 config ZONE_DMA
 200         bool
 201
 202 config NEED_DMA_MAP_STATE
 203        def_bool y
 204
 205 config ARCH_SUPPORTS_UPROBES
 206         def_bool y
 207
 208 config ARCH_HAS_DMA_SET_COHERENT_MASK
 209         bool
 210
 211 config GENERIC_ISA_DMA
 212         bool
 213
 214 config FIQ
 215         bool
 216
 217 config NEED_RET_TO_USER
 218         bool
 219
 220 config ARCH_MTD_XIP
 221         bool
 222
 223 config VECTORS_BASE
 224         hex
 225         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 226         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 227         default 0x00000000
 228         help
 229           The base address of exception vectors.  This must be two pages
 230           in size.
 231
 232 config ARM_PATCH_PHYS_VIRT
 233         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 234         default y
 235         depends on !XIP_KERNEL && MMU
 236         depends on !ARCH_REALVIEW || !SPARSEMEM
 237         help
 238           Patch phys-to-virt and virt-to-phys translation functions at
 239           boot and module load time according to the position of the
 240           kernel in system memory.
 241
 242           This can only be used with non-XIP MMU kernels where the base
 243           of physical memory is at a 16MB boundary.
 244
 245           Only disable this option if you know that you do not require
 246           this feature (eg, building a kernel for a single machine) and
 247           you need to shrink the kernel to the minimal size.
 248
 249 config NEED_MACH_IO_H
 250         bool
 251         help
 252           Select this when mach/io.h is required to provide special
 253           definitions for this platform.  The need for mach/io.h should
 254           be avoided when possible.
 255
 256 config NEED_MACH_MEMORY_H
 257         bool
 258         help
 259           Select this when mach/memory.h is required to provide special
 260           definitions for this platform.  The need for mach/memory.h should
 261           be avoided when possible.
 262
 263 config PHYS_OFFSET
 264         hex "Physical address of main memory" if MMU
 265         depends on !ARM_PATCH_PHYS_VIRT
 266         default DRAM_BASE if !MMU
 267         default 0x00000000 if ARCH_EBSA110 || \
 268                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 269                         ARCH_FOOTBRIDGE || \
 270                         ARCH_INTEGRATOR || \
 271                         ARCH_IOP13XX || \
 272                         ARCH_KS8695 || \
 273                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 274         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 275         default 0x20000000 if ARCH_S5PV210
 276         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 277         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 278         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 279         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 280         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 281         help
 282           Please provide the physical address corresponding to the
 283           location of main memory in your system.
 284
 285 config GENERIC_BUG
 286         def_bool y
 287         depends on BUG
 288
 289 source "init/Kconfig"
 290
 291 source "kernel/Kconfig.freezer"
 292
 293 menu "System Type"
 294
 295 config MMU
 296         bool "MMU-based Paged Memory Management Support"
 297         default y
 298         help
 299           Select if you want MMU-based virtualised addressing space
 300           support by paged memory management. If unsure, say 'Y'.
 301
 302 #
 303 # The "ARM system type" choice list is ordered alphabetically by option
 304 # text.  Please add new entries in the option alphabetic order.
 305 #
 306 choice
 307         prompt "ARM system type"
 308         default ARCH_VERSATILE if !MMU
 309         default ARCH_MULTIPLATFORM if MMU
 310
 311 config ARCH_MULTIPLATFORM
 312         bool "Allow multiple platforms to be selected"
 313         depends on MMU
 314         select ARCH_WANT_OPTIONAL_GPIOLIB
 315         select ARM_HAS_SG_CHAIN
 316         select ARM_PATCH_PHYS_VIRT
 317         select AUTO_ZRELADDR
 318         select CLKSRC_OF
 319         select COMMON_CLK
 320         select GENERIC_CLOCKEVENTS
 321         select MIGHT_HAVE_PCI
 322         select MULTI_IRQ_HANDLER
 323         select SPARSE_IRQ
 324         select USE_OF
 325
 326 config ARCH_REALVIEW
 327         bool "ARM Ltd. RealView family"
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_AMBA
 330         select ARM_TIMER_SP804
 331         select COMMON_CLK
 332         select COMMON_CLK_VERSATILE
 333         select GENERIC_CLOCKEVENTS
 334         select GPIO_PL061 if GPIOLIB
 335         select ICST
 336         select NEED_MACH_MEMORY_H
 337         select PLAT_VERSATILE
 338         select PLAT_VERSATILE_SCHED_CLOCK
 339         help
 340           This enables support for ARM Ltd RealView boards.
 341
 342 config ARCH_VERSATILE
 343         bool "ARM Ltd. Versatile family"
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_AMBA
 346         select ARM_TIMER_SP804
 347         select ARM_VIC
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select HAVE_MACH_CLKDEV
 351         select ICST
 352         select PLAT_VERSATILE
 353         select PLAT_VERSATILE_CLOCK
 354         select PLAT_VERSATILE_SCHED_CLOCK
 355         select VERSATILE_FPGA_IRQ
 356         help
 357           This enables support for ARM Ltd Versatile board.
 358
 359 config ARCH_AT91
 360         bool "Atmel AT91"
 361         select ARCH_REQUIRE_GPIOLIB
 362         select CLKDEV_LOOKUP
 363         select IRQ_DOMAIN
 364         select NEED_MACH_IO_H if PCCARD
 365         select PINCTRL
 366         select PINCTRL_AT91
 367         select USE_OF
 368         help
 369           This enables support for systems based on Atmel
 370           AT91RM9200, AT91SAM9 and SAMA5 processors.
 371
 372 config ARCH_CLPS711X
 373         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select AUTO_ZRELADDR
 376         select CLKSRC_MMIO
 377         select COMMON_CLK
 378         select CPU_ARM720T
 379         select GENERIC_CLOCKEVENTS
 380         select MFD_SYSCON
 381         select SOC_BUS
 382         help
 383           Support for Cirrus Logic 711x/721x/731x based boards.
 384
 385 config ARCH_GEMINI
 386         bool "Cortina Systems Gemini"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select CLKSRC_MMIO
 389         select CPU_FA526
 390         select GENERIC_CLOCKEVENTS
 391         help
 392           Support for the Cortina Systems Gemini family SoCs
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select ARCH_USES_GETTIMEOFFSET
 397         select CPU_SA110
 398         select ISA
 399         select NEED_MACH_IO_H
 400         select NEED_MACH_MEMORY_H
 401         select NO_IOPORT_MAP
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EFM32
 409         bool "Energy Micro efm32"
 410         depends on !MMU
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARM_NVIC
 413         select AUTO_ZRELADDR
 414         select CLKSRC_OF
 415         select COMMON_CLK
 416         select CPU_V7M
 417         select GENERIC_CLOCKEVENTS
 418         select NO_DMA
 419         select NO_IOPORT_MAP
 420         select SPARSE_IRQ
 421         select USE_OF
 422         help
 423           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 424           processors.
 425
 426 config ARCH_EP93XX
 427         bool "EP93xx-based"
 428         select ARCH_HAS_HOLES_MEMORYMODEL
 429         select ARCH_REQUIRE_GPIOLIB
 430         select ARCH_USES_GETTIMEOFFSET
 431         select ARM_AMBA
 432         select ARM_VIC
 433         select CLKDEV_LOOKUP
 434         select CPU_ARM920T
 435         help
 436           This enables support for the Cirrus EP93xx series of CPUs.
 437
 438 config ARCH_FOOTBRIDGE
 439         bool "FootBridge"
 440         select CPU_SA110
 441         select FOOTBRIDGE
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_IDE
 444         select NEED_MACH_IO_H if !MMU
 445         select NEED_MACH_MEMORY_H
 446         help
 447           Support for systems based on the DC21285 companion chip
 448           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 449
 450 config ARCH_NETX
 451         bool "Hilscher NetX based"
 452         select ARM_VIC
 453         select CLKSRC_MMIO
 454         select CPU_ARM926T
 455         select GENERIC_CLOCKEVENTS
 456         help
 457           This enables support for systems based on the Hilscher NetX Soc
 458
 459 config ARCH_IOP13XX
 460         bool "IOP13xx-based"
 461         depends on MMU
 462         select CPU_XSC3
 463         select NEED_MACH_MEMORY_H
 464         select NEED_RET_TO_USER
 465         select PCI
 466         select PLAT_IOP
 467         select VMSPLIT_1G
 468         select SPARSE_IRQ
 469         help
 470           Support for Intel's IOP13XX (XScale) family of processors.
 471
 472 config ARCH_IOP32X
 473         bool "IOP32x-based"
 474         depends on MMU
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CPU_XSCALE
 477         select GPIO_IOP
 478         select NEED_RET_TO_USER
 479         select PCI
 480         select PLAT_IOP
 481         help
 482           Support for Intel's 80219 and IOP32X (XScale) family of
 483           processors.
 484
 485 config ARCH_IOP33X
 486         bool "IOP33x-based"
 487         depends on MMU
 488         select ARCH_REQUIRE_GPIOLIB
 489         select CPU_XSCALE
 490         select GPIO_IOP
 491         select NEED_RET_TO_USER
 492         select PCI
 493         select PLAT_IOP
 494         help
 495           Support for Intel's IOP33X (XScale) family of processors.
 496
 497 config ARCH_IXP4XX
 498         bool "IXP4xx-based"
 499         depends on MMU
 500         select ARCH_HAS_DMA_SET_COHERENT_MASK
 501         select ARCH_REQUIRE_GPIOLIB
 502         select ARCH_SUPPORTS_BIG_ENDIAN
 503         select CLKSRC_MMIO
 504         select CPU_XSCALE
 505         select DMABOUNCE if PCI
 506         select GENERIC_CLOCKEVENTS
 507         select MIGHT_HAVE_PCI
 508         select NEED_MACH_IO_H
 509         select USB_EHCI_BIG_ENDIAN_DESC
 510         select USB_EHCI_BIG_ENDIAN_MMIO
 511         help
 512           Support for Intel's IXP4XX (XScale) family of processors.
 513
 514 config ARCH_DOVE
 515         bool "Marvell Dove"
 516         select ARCH_REQUIRE_GPIOLIB
 517         select CPU_PJ4
 518         select GENERIC_CLOCKEVENTS
 519         select MIGHT_HAVE_PCI
 520         select MVEBU_MBUS
 521         select PINCTRL
 522         select PINCTRL_DOVE
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the Marvell Dove SoC 88AP510
 526
 527 config ARCH_MV78XX0
 528         bool "Marvell MV78xx0"
 529         select ARCH_REQUIRE_GPIOLIB
 530         select CPU_FEROCEON
 531         select GENERIC_CLOCKEVENTS
 532         select MVEBU_MBUS
 533         select PCI
 534         select PLAT_ORION_LEGACY
 535         help
 536           Support for the following Marvell MV78xx0 series SoCs:
 537           MV781x0, MV782x0.
 538
 539 config ARCH_ORION5X
 540         bool "Marvell Orion"
 541         depends on MMU
 542         select ARCH_REQUIRE_GPIOLIB
 543         select CPU_FEROCEON
 544         select GENERIC_CLOCKEVENTS
 545         select MVEBU_MBUS
 546         select PCI
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Orion 5x series SoCs:
 550           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 551           Orion-2 (5281), Orion-1-90 (6183).
 552
 553 config ARCH_MMP
 554         bool "Marvell PXA168/910/MMP2"
 555         depends on MMU
 556         select ARCH_REQUIRE_GPIOLIB
 557         select CLKDEV_LOOKUP
 558         select GENERIC_ALLOCATOR
 559         select GENERIC_CLOCKEVENTS
 560         select GPIO_PXA
 561         select IRQ_DOMAIN
 562         select MULTI_IRQ_HANDLER
 563         select PINCTRL
 564         select PLAT_PXA
 565         select SPARSE_IRQ
 566         help
 567           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 568
 569 config ARCH_KS8695
 570         bool "Micrel/Kendin KS8695"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKSRC_MMIO
 573         select CPU_ARM922T
 574         select GENERIC_CLOCKEVENTS
 575         select NEED_MACH_MEMORY_H
 576         help
 577           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 578           System-on-Chip devices.
 579
 580 config ARCH_W90X900
 581         bool "Nuvoton W90X900 CPU"
 582         select ARCH_REQUIRE_GPIOLIB
 583         select CLKDEV_LOOKUP
 584         select CLKSRC_MMIO
 585         select CPU_ARM926T
 586         select GENERIC_CLOCKEVENTS
 587         help
 588           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 589           At present, the w90x900 has been renamed nuc900, regarding
 590           the ARM series product line, you can login the following
 591           link address to know more.
 592
 593           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 594                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 595
 596 config ARCH_LPC32XX
 597         bool "NXP LPC32XX"
 598         select ARCH_REQUIRE_GPIOLIB
 599         select ARM_AMBA
 600         select CLKDEV_LOOKUP
 601         select CLKSRC_MMIO
 602         select CPU_ARM926T
 603         select GENERIC_CLOCKEVENTS
 604         select HAVE_IDE
 605         select USE_OF
 606         help
 607           Support for the NXP LPC32XX family of processors
 608
 609 config ARCH_PXA
 610         bool "PXA2xx/PXA3xx-based"
 611         depends on MMU
 612         select ARCH_MTD_XIP
 613         select ARCH_REQUIRE_GPIOLIB
 614         select ARM_CPU_SUSPEND if PM
 615         select AUTO_ZRELADDR
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select IRQ_DOMAIN
 623         select MULTI_IRQ_HANDLER
 624         select PLAT_PXA
 625         select SPARSE_IRQ
 626         help
 627           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 628
 629 config ARCH_MSM
 630         bool "Qualcomm MSM (non-multiplatform)"
 631         select ARCH_REQUIRE_GPIOLIB
 632         select COMMON_CLK
 633         select GENERIC_CLOCKEVENTS
 634         help
 635           Support for Qualcomm MSM/QSD based systems.  This runs on the
 636           apps processor of the MSM/QSD and depends on a shared memory
 637           interface to the modem processor which runs the baseband
 638           stack and controls some vital subsystems
 639           (clock and power control, etc).
 640
 641 config ARCH_SHMOBILE_LEGACY
 642         bool "Renesas ARM SoCs (non-multiplatform)"
 643         select ARCH_SHMOBILE
 644         select ARM_PATCH_PHYS_VIRT if MMU
 645         select CLKDEV_LOOKUP
 646         select CPU_V7
 647         select GENERIC_CLOCKEVENTS
 648         select HAVE_ARM_SCU if SMP
 649         select HAVE_ARM_TWD if SMP
 650         select HAVE_MACH_CLKDEV
 651         select HAVE_SMP
 652         select MIGHT_HAVE_CACHE_L2X0
 653         select MULTI_IRQ_HANDLER
 654         select NO_IOPORT_MAP
 655         select PINCTRL
 656         select PM_GENERIC_DOMAINS if PM
 657         select SH_CLK_CPG
 658         select SPARSE_IRQ
 659         help
 660           Support for Renesas ARM SoC platforms using a non-multiplatform
 661           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 662           and RZ families.
 663
 664 config ARCH_RPC
 665         bool "RiscPC"
 666         select ARCH_ACORN
 667         select ARCH_MAY_HAVE_PC_FDC
 668         select ARCH_SPARSEMEM_ENABLE
 669         select ARCH_USES_GETTIMEOFFSET
 670         select CPU_SA110
 671         select FIQ
 672         select HAVE_IDE
 673         select HAVE_PATA_PLATFORM
 674         select ISA_DMA_API
 675         select NEED_MACH_IO_H
 676         select NEED_MACH_MEMORY_H
 677         select NO_IOPORT_MAP
 678         select VIRT_TO_BUS
 679         help
 680           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 681           CD-ROM interface, serial and parallel port, and the floppy drive.
 682
 683 config ARCH_SA1100
 684         bool "SA1100-based"
 685         select ARCH_MTD_XIP
 686         select ARCH_REQUIRE_GPIOLIB
 687         select ARCH_SPARSEMEM_ENABLE
 688         select CLKDEV_LOOKUP
 689         select CLKSRC_MMIO
 690         select CPU_FREQ
 691         select CPU_SA1100
 692         select GENERIC_CLOCKEVENTS
 693         select HAVE_IDE
 694         select IRQ_DOMAIN
 695         select ISA
 696         select MULTI_IRQ_HANDLER
 697         select NEED_MACH_MEMORY_H
 698         select SPARSE_IRQ
 699         help
 700           Support for StrongARM 11x0 based boards.
 701
 702 config ARCH_S3C24XX
 703         bool "Samsung S3C24XX SoCs"
 704         select ARCH_REQUIRE_GPIOLIB
 705         select ATAGS
 706         select CLKDEV_LOOKUP
 707         select CLKSRC_SAMSUNG_PWM
 708         select GENERIC_CLOCKEVENTS
 709         select GPIO_SAMSUNG
 710         select HAVE_S3C2410_I2C if I2C
 711         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 712         select HAVE_S3C_RTC if RTC_CLASS
 713         select MULTI_IRQ_HANDLER
 714         select NEED_MACH_IO_H
 715         select SAMSUNG_ATAGS
 716         help
 717           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 718           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 719           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 720           Samsung SMDK2410 development board (and derivatives).
 721
 722 config ARCH_S3C64XX
 723         bool "Samsung S3C64XX"
 724         select ARCH_REQUIRE_GPIOLIB
 725         select ARM_AMBA
 726         select ARM_VIC
 727         select ATAGS
 728         select CLKDEV_LOOKUP
 729         select CLKSRC_SAMSUNG_PWM
 730         select COMMON_CLK_SAMSUNG
 731         select CPU_V6K
 732         select GENERIC_CLOCKEVENTS
 733         select GPIO_SAMSUNG
 734         select HAVE_S3C2410_I2C if I2C
 735         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 736         select HAVE_TCM
 737         select NO_IOPORT_MAP
 738         select PLAT_SAMSUNG
 739         select PM_GENERIC_DOMAINS if PM
 740         select S3C_DEV_NAND
 741         select S3C_GPIO_TRACK
 742         select SAMSUNG_ATAGS
 743         select SAMSUNG_WAKEMASK
 744         select SAMSUNG_WDT_RESET
 745         help
 746           Samsung S3C64XX series based systems
 747
 748 config ARCH_DAVINCI
 749         bool "TI DaVinci"
 750         select ARCH_HAS_HOLES_MEMORYMODEL
 751         select ARCH_REQUIRE_GPIOLIB
 752         select CLKDEV_LOOKUP
 753         select GENERIC_ALLOCATOR
 754         select GENERIC_CLOCKEVENTS
 755         select GENERIC_IRQ_CHIP
 756         select HAVE_IDE
 757         select TI_PRIV_EDMA
 758         select USE_OF
 759         select ZONE_DMA
 760         help
 761           Support for TI's DaVinci platform.
 762
 763 config ARCH_OMAP1
 764         bool "TI OMAP1"
 765         depends on MMU
 766         select ARCH_HAS_HOLES_MEMORYMODEL
 767         select ARCH_OMAP
 768         select ARCH_REQUIRE_GPIOLIB
 769         select CLKDEV_LOOKUP
 770         select CLKSRC_MMIO
 771         select GENERIC_CLOCKEVENTS
 772         select GENERIC_IRQ_CHIP
 773         select HAVE_IDE
 774         select IRQ_DOMAIN
 775         select NEED_MACH_IO_H if PCCARD
 776         select NEED_MACH_MEMORY_H
 777         help
 778           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 779
 780 endchoice
 781
 782 menu "Multiple platform selection"
 783         depends on ARCH_MULTIPLATFORM
 784
 785 comment "CPU Core family selection"
 786
 787 config ARCH_MULTI_V4
 788         bool "ARMv4 based platforms (FA526)"
 789         depends on !ARCH_MULTI_V6_V7
 790         select ARCH_MULTI_V4_V5
 791         select CPU_FA526
 792
 793 config ARCH_MULTI_V4T
 794         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 795         depends on !ARCH_MULTI_V6_V7
 796         select ARCH_MULTI_V4_V5
 797         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 798                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 799                 CPU_ARM925T || CPU_ARM940T)
 800
 801 config ARCH_MULTI_V5
 802         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 803         depends on !ARCH_MULTI_V6_V7
 804         select ARCH_MULTI_V4_V5
 805         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 806                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 807                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 808
 809 config ARCH_MULTI_V4_V5
 810         bool
 811
 812 config ARCH_MULTI_V6
 813         bool "ARMv6 based platforms (ARM11)"
 814         select ARCH_MULTI_V6_V7
 815         select CPU_V6K
 816
 817 config ARCH_MULTI_V7
 818         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 819         default y
 820         select ARCH_MULTI_V6_V7
 821         select CPU_V7
 822         select HAVE_SMP
 823
 824 config ARCH_MULTI_V6_V7
 825         bool
 826         select MIGHT_HAVE_CACHE_L2X0
 827
 828 config ARCH_MULTI_CPU_AUTO
 829         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 830         select ARCH_MULTI_V5
 831
 832 endmenu
 833
 834 config ARCH_VIRT
 835         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 836         select ARM_AMBA
 837         select ARM_GIC
 838         select ARM_PSCI
 839         select HAVE_ARM_ARCH_TIMER
 840
 841 #
 842 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 843 # Kconfigs may be included either alphabetically (according to the
 844 # plat- suffix) or along side the corresponding mach-* source.
 845 #
 846 source "arch/arm/mach-mvebu/Kconfig"
 847
 848 source "arch/arm/mach-asm9260/Kconfig"
 849
 850 source "arch/arm/mach-at91/Kconfig"
 851
 852 source "arch/arm/mach-axxia/Kconfig"
 853
 854 source "arch/arm/mach-bcm/Kconfig"
 855
 856 source "arch/arm/mach-berlin/Kconfig"
 857
 858 source "arch/arm/mach-clps711x/Kconfig"
 859
 860 source "arch/arm/mach-cns3xxx/Kconfig"
 861
 862 source "arch/arm/mach-davinci/Kconfig"
 863
 864 source "arch/arm/mach-digicolor/Kconfig"
 865
 866 source "arch/arm/mach-dove/Kconfig"
 867
 868 source "arch/arm/mach-ep93xx/Kconfig"
 869
 870 source "arch/arm/mach-footbridge/Kconfig"
 871
 872 source "arch/arm/mach-gemini/Kconfig"
 873
 874 source "arch/arm/mach-highbank/Kconfig"
 875
 876 source "arch/arm/mach-hisi/Kconfig"
 877
 878 source "arch/arm/mach-integrator/Kconfig"
 879
 880 source "arch/arm/mach-iop32x/Kconfig"
 881
 882 source "arch/arm/mach-iop33x/Kconfig"
 883
 884 source "arch/arm/mach-iop13xx/Kconfig"
 885
 886 source "arch/arm/mach-ixp4xx/Kconfig"
 887
 888 source "arch/arm/mach-keystone/Kconfig"
 889
 890 source "arch/arm/mach-ks8695/Kconfig"
 891
 892 source "arch/arm/mach-meson/Kconfig"
 893
 894 source "arch/arm/mach-msm/Kconfig"
 895
 896 source "arch/arm/mach-moxart/Kconfig"
 897
 898 source "arch/arm/mach-mv78xx0/Kconfig"
 899
 900 source "arch/arm/mach-imx/Kconfig"
 901
 902 source "arch/arm/mach-mediatek/Kconfig"
 903
 904 source "arch/arm/mach-mxs/Kconfig"
 905
 906 source "arch/arm/mach-netx/Kconfig"
 907
 908 source "arch/arm/mach-nomadik/Kconfig"
 909
 910 source "arch/arm/mach-nspire/Kconfig"
 911
 912 source "arch/arm/plat-omap/Kconfig"
 913
 914 source "arch/arm/mach-omap1/Kconfig"
 915
 916 source "arch/arm/mach-omap2/Kconfig"
 917
 918 source "arch/arm/mach-orion5x/Kconfig"
 919
 920 source "arch/arm/mach-picoxcell/Kconfig"
 921
 922 source "arch/arm/mach-pxa/Kconfig"
 923 source "arch/arm/plat-pxa/Kconfig"
 924
 925 source "arch/arm/mach-mmp/Kconfig"
 926
 927 source "arch/arm/mach-qcom/Kconfig"
 928
 929 source "arch/arm/mach-realview/Kconfig"
 930
 931 source "arch/arm/mach-rockchip/Kconfig"
 932
 933 source "arch/arm/mach-sa1100/Kconfig"
 934
 935 source "arch/arm/mach-socfpga/Kconfig"
 936
 937 source "arch/arm/mach-spear/Kconfig"
 938
 939 source "arch/arm/mach-sti/Kconfig"
 940
 941 source "arch/arm/mach-s3c24xx/Kconfig"
 942
 943 source "arch/arm/mach-s3c64xx/Kconfig"
 944
 945 source "arch/arm/mach-s5pv210/Kconfig"
 946
 947 source "arch/arm/mach-exynos/Kconfig"
 948 source "arch/arm/plat-samsung/Kconfig"
 949
 950 source "arch/arm/mach-shmobile/Kconfig"
 951
 952 source "arch/arm/mach-sunxi/Kconfig"
 953
 954 source "arch/arm/mach-prima2/Kconfig"
 955
 956 source "arch/arm/mach-tegra/Kconfig"
 957
 958 source "arch/arm/mach-u300/Kconfig"
 959
 960 source "arch/arm/mach-ux500/Kconfig"
 961
 962 source "arch/arm/mach-versatile/Kconfig"
 963
 964 source "arch/arm/mach-vexpress/Kconfig"
 965 source "arch/arm/plat-versatile/Kconfig"
 966
 967 source "arch/arm/mach-vt8500/Kconfig"
 968
 969 source "arch/arm/mach-w90x900/Kconfig"
 970
 971 source "arch/arm/mach-zynq/Kconfig"
 972
 973 # Definitions to make life easier
 974 config ARCH_ACORN
 975         bool
 976
 977 config PLAT_IOP
 978         bool
 979         select GENERIC_CLOCKEVENTS
 980
 981 config PLAT_ORION
 982         bool
 983         select CLKSRC_MMIO
 984         select COMMON_CLK
 985         select GENERIC_IRQ_CHIP
 986         select IRQ_DOMAIN
 987
 988 config PLAT_ORION_LEGACY
 989         bool
 990         select PLAT_ORION
 991
 992 config PLAT_PXA
 993         bool
 994
 995 config PLAT_VERSATILE
 996         bool
 997
 998 config ARM_TIMER_SP804
 999         bool
1000         select CLKSRC_MMIO
1001         select CLKSRC_OF if OF
1002
1003 source "arch/arm/firmware/Kconfig"
1004
1005 source arch/arm/mm/Kconfig
1006
1007 config IWMMXT
1008         bool "Enable iWMMXt support"
1009         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1010         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1011         help
1012           Enable support for iWMMXt context switching at run time if
1013           running on a CPU that supports it.
1014
1015 config MULTI_IRQ_HANDLER
1016         bool
1017         help
1018           Allow each machine to specify it's own IRQ handler at run time.
1019
1020 if !MMU
1021 source "arch/arm/Kconfig-nommu"
1022 endif
1023
1024 config PJ4B_ERRATA_4742
1025         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1026         depends on CPU_PJ4B && MACH_ARMADA_370
1027         default y
1028         help
1029           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1030           Event (WFE) IDLE states, a specific timing sensitivity exists between
1031           the retiring WFI/WFE instructions and the newly issued subsequent
1032           instructions.  This sensitivity can result in a CPU hang scenario.
1033           Workaround:
1034           The software must insert either a Data Synchronization Barrier (DSB)
1035           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1036           instruction
1037
1038 config ARM_ERRATA_326103
1039         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1040         depends on CPU_V6
1041         help
1042           Executing a SWP instruction to read-only memory does not set bit 11
1043           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1044           treat the access as a read, preventing a COW from occurring and
1045           causing the faulting task to livelock.
1046
1047 config ARM_ERRATA_411920
1048         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1049         depends on CPU_V6 || CPU_V6K
1050         help
1051           Invalidation of the Instruction Cache operation can
1052           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1053           It does not affect the MPCore. This option enables the ARM Ltd.
1054           recommended workaround.
1055
1056 config ARM_ERRATA_430973
1057         bool "ARM errata: Stale prediction on replaced interworking branch"
1058         depends on CPU_V7
1059         help
1060           This option enables the workaround for the 430973 Cortex-A8
1061           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1062           interworking branch is replaced with another code sequence at the
1063           same virtual address, whether due to self-modifying code or virtual
1064           to physical address re-mapping, Cortex-A8 does not recover from the
1065           stale interworking branch prediction. This results in Cortex-A8
1066           executing the new code sequence in the incorrect ARM or Thumb state.
1067           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1068           and also flushes the branch target cache at every context switch.
1069           Note that setting specific bits in the ACTLR register may not be
1070           available in non-secure mode.
1071
1072 config ARM_ERRATA_458693
1073         bool "ARM errata: Processor deadlock when a false hazard is created"
1074         depends on CPU_V7
1075         depends on !ARCH_MULTIPLATFORM
1076         help
1077           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1078           erratum. For very specific sequences of memory operations, it is
1079           possible for a hazard condition intended for a cache line to instead
1080           be incorrectly associated with a different cache line. This false
1081           hazard might then cause a processor deadlock. The workaround enables
1082           the L1 caching of the NEON accesses and disables the PLD instruction
1083           in the ACTLR register. Note that setting specific bits in the ACTLR
1084           register may not be available in non-secure mode.
1085
1086 config ARM_ERRATA_460075
1087         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1088         depends on CPU_V7
1089         depends on !ARCH_MULTIPLATFORM
1090         help
1091           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1092           erratum. Any asynchronous access to the L2 cache may encounter a
1093           situation in which recent store transactions to the L2 cache are lost
1094           and overwritten with stale memory contents from external memory. The
1095           workaround disables the write-allocate mode for the L2 cache via the
1096           ACTLR register. Note that setting specific bits in the ACTLR register
1097           may not be available in non-secure mode.
1098
1099 config ARM_ERRATA_742230
1100         bool "ARM errata: DMB operation may be faulty"
1101         depends on CPU_V7 && SMP
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 742230 Cortex-A9
1105           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1106           between two write operations may not ensure the correct visibility
1107           ordering of the two writes. This workaround sets a specific bit in
1108           the diagnostic register of the Cortex-A9 which causes the DMB
1109           instruction to behave as a DSB, ensuring the correct behaviour of
1110           the two writes.
1111
1112 config ARM_ERRATA_742231
1113         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1114         depends on CPU_V7 && SMP
1115         depends on !ARCH_MULTIPLATFORM
1116         help
1117           This option enables the workaround for the 742231 Cortex-A9
1118           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1119           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1120           accessing some data located in the same cache line, may get corrupted
1121           data due to bad handling of the address hazard when the line gets
1122           replaced from one of the CPUs at the same time as another CPU is
1123           accessing it. This workaround sets specific bits in the diagnostic
1124           register of the Cortex-A9 which reduces the linefill issuing
1125           capabilities of the processor.
1126
1127 config ARM_ERRATA_643719
1128         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1129         depends on CPU_V7 && SMP
1130         help
1131           This option enables the workaround for the 643719 Cortex-A9 (prior to
1132           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1133           register returns zero when it should return one. The workaround
1134           corrects this value, ensuring cache maintenance operations which use
1135           it behave as intended and avoiding data corruption.
1136
1137 config ARM_ERRATA_720789
1138         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1139         depends on CPU_V7
1140         help
1141           This option enables the workaround for the 720789 Cortex-A9 (prior to
1142           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1143           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1144           As a consequence of this erratum, some TLB entries which should be
1145           invalidated are not, resulting in an incoherency in the system page
1146           tables. The workaround changes the TLB flushing routines to invalidate
1147           entries regardless of the ASID.
1148
1149 config ARM_ERRATA_743622
1150         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1151         depends on CPU_V7
1152         depends on !ARCH_MULTIPLATFORM
1153         help
1154           This option enables the workaround for the 743622 Cortex-A9
1155           (r2p*) erratum. Under very rare conditions, a faulty
1156           optimisation in the Cortex-A9 Store Buffer may lead to data
1157           corruption. This workaround sets a specific bit in the diagnostic
1158           register of the Cortex-A9 which disables the Store Buffer
1159           optimisation, preventing the defect from occurring. This has no
1160           visible impact on the overall performance or power consumption of the
1161           processor.
1162
1163 config ARM_ERRATA_751472
1164         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1165         depends on CPU_V7
1166         depends on !ARCH_MULTIPLATFORM
1167         help
1168           This option enables the workaround for the 751472 Cortex-A9 (prior
1169           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1170           completion of a following broadcasted operation if the second
1171           operation is received by a CPU before the ICIALLUIS has completed,
1172           potentially leading to corrupted entries in the cache or TLB.
1173
1174 config ARM_ERRATA_754322
1175         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1176         depends on CPU_V7
1177         help
1178           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1179           r3p*) erratum. A speculative memory access may cause a page table walk
1180           which starts prior to an ASID switch but completes afterwards. This
1181           can populate the micro-TLB with a stale entry which may be hit with
1182           the new ASID. This workaround places two dsb instructions in the mm
1183           switching code so that no page table walks can cross the ASID switch.
1184
1185 config ARM_ERRATA_754327
1186         bool "ARM errata: no automatic Store Buffer drain"
1187         depends on CPU_V7 && SMP
1188         help
1189           This option enables the workaround for the 754327 Cortex-A9 (prior to
1190           r2p0) erratum. The Store Buffer does not have any automatic draining
1191           mechanism and therefore a livelock may occur if an external agent
1192           continuously polls a memory location waiting to observe an update.
1193           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1194           written polling loops from denying visibility of updates to memory.
1195
1196 config ARM_ERRATA_364296
1197         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1198         depends on CPU_V6
1199         help
1200           This options enables the workaround for the 364296 ARM1136
1201           r0p2 erratum (possible cache data corruption with
1202           hit-under-miss enabled). It sets the undocumented bit 31 in
1203           the auxiliary control register and the FI bit in the control
1204           register, thus disabling hit-under-miss without putting the
1205           processor into full low interrupt latency mode. ARM11MPCore
1206           is not affected.
1207
1208 config ARM_ERRATA_764369
1209         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1210         depends on CPU_V7 && SMP
1211         help
1212           This option enables the workaround for erratum 764369
1213           affecting Cortex-A9 MPCore with two or more processors (all
1214           current revisions). Under certain timing circumstances, a data
1215           cache line maintenance operation by MVA targeting an Inner
1216           Shareable memory region may fail to proceed up to either the
1217           Point of Coherency or to the Point of Unification of the
1218           system. This workaround adds a DSB instruction before the
1219           relevant cache maintenance functions and sets a specific bit
1220           in the diagnostic control register of the SCU.
1221
1222 config ARM_ERRATA_775420
1223        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1224        depends on CPU_V7
1225        help
1226          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1227          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1228          operation aborts with MMU exception, it might cause the processor
1229          to deadlock. This workaround puts DSB before executing ISB if
1230          an abort may occur on cache maintenance.
1231
1232 config ARM_ERRATA_798181
1233         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1234         depends on CPU_V7 && SMP
1235         help
1236           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1237           adequately shooting down all use of the old entries. This
1238           option enables the Linux kernel workaround for this erratum
1239           which sends an IPI to the CPUs that are running the same ASID
1240           as the one being invalidated.
1241
1242 config ARM_ERRATA_773022
1243         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1244         depends on CPU_V7
1245         help
1246           This option enables the workaround for the 773022 Cortex-A15
1247           (up to r0p4) erratum. In certain rare sequences of code, the
1248           loop buffer may deliver incorrect instructions. This
1249           workaround disables the loop buffer to avoid the erratum.
1250
1251 endmenu
1252
1253 source "arch/arm/common/Kconfig"
1254
1255 menu "Bus support"
1256
1257 config ISA
1258         bool
1259         help
1260           Find out whether you have ISA slots on your motherboard.  ISA is the
1261           name of a bus system, i.e. the way the CPU talks to the other stuff
1262           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1263           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1264           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1265
1266 # Select ISA DMA controller support
1267 config ISA_DMA
1268         bool
1269         select ISA_DMA_API
1270
1271 # Select ISA DMA interface
1272 config ISA_DMA_API
1273         bool
1274
1275 config PCI
1276         bool "PCI support" if MIGHT_HAVE_PCI
1277         help
1278           Find out whether you have a PCI motherboard. PCI is the name of a
1279           bus system, i.e. the way the CPU talks to the other stuff inside
1280           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1281           VESA. If you have PCI, say Y, otherwise N.
1282
1283 config PCI_DOMAINS
1284         bool
1285         depends on PCI
1286
1287 config PCI_DOMAINS_GENERIC
1288         def_bool PCI_DOMAINS
1289
1290 config PCI_NANOENGINE
1291         bool "BSE nanoEngine PCI support"
1292         depends on SA1100_NANOENGINE
1293         help
1294           Enable PCI on the BSE nanoEngine board.
1295
1296 config PCI_SYSCALL
1297         def_bool PCI
1298
1299 config PCI_HOST_ITE8152
1300         bool
1301         depends on PCI && MACH_ARMCORE
1302         default y
1303         select DMABOUNCE
1304
1305 source "drivers/pci/Kconfig"
1306 source "drivers/pci/pcie/Kconfig"
1307
1308 source "drivers/pcmcia/Kconfig"
1309
1310 endmenu
1311
1312 menu "Kernel Features"
1313
1314 config HAVE_SMP
1315         bool
1316         help
1317           This option should be selected by machines which have an SMP-
1318           capable CPU.
1319
1320           The only effect of this option is to make the SMP-related
1321           options available to the user for configuration.
1322
1323 config SMP
1324         bool "Symmetric Multi-Processing"
1325         depends on CPU_V6K || CPU_V7
1326         depends on GENERIC_CLOCKEVENTS
1327         depends on HAVE_SMP
1328         depends on MMU || ARM_MPU
1329         help
1330           This enables support for systems with more than one CPU. If you have
1331           a system with only one CPU, say N. If you have a system with more
1332           than one CPU, say Y.
1333
1334           If you say N here, the kernel will run on uni- and multiprocessor
1335           machines, but will use only one CPU of a multiprocessor machine. If
1336           you say Y here, the kernel will run on many, but not all,
1337           uniprocessor machines. On a uniprocessor machine, the kernel
1338           will run faster if you say N here.
1339
1340           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1341           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1342           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1343
1344           If you don't know what to do here, say N.
1345
1346 config SMP_ON_UP
1347         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1348         depends on SMP && !XIP_KERNEL && MMU
1349         default y
1350         help
1351           SMP kernels contain instructions which fail on non-SMP processors.
1352           Enabling this option allows the kernel to modify itself to make
1353           these instructions safe.  Disabling it allows about 1K of space
1354           savings.
1355
1356           If you don't know what to do here, say Y.
1357
1358 config ARM_CPU_TOPOLOGY
1359         bool "Support cpu topology definition"
1360         depends on SMP && CPU_V7
1361         default y
1362         help
1363           Support ARM cpu topology definition. The MPIDR register defines
1364           affinity between processors which is then used to describe the cpu
1365           topology of an ARM System.
1366
1367 config SCHED_MC
1368         bool "Multi-core scheduler support"
1369         depends on ARM_CPU_TOPOLOGY
1370         help
1371           Multi-core scheduler support improves the CPU scheduler's decision
1372           making when dealing with multi-core CPU chips at a cost of slightly
1373           increased overhead in some places. If unsure say N here.
1374
1375 config SCHED_SMT
1376         bool "SMT scheduler support"
1377         depends on ARM_CPU_TOPOLOGY
1378         help
1379           Improves the CPU scheduler's decision making when dealing with
1380           MultiThreading at a cost of slightly increased overhead in some
1381           places. If unsure say N here.
1382
1383 config HAVE_ARM_SCU
1384         bool
1385         help
1386           This option enables support for the ARM system coherency unit
1387
1388 config HAVE_ARM_ARCH_TIMER
1389         bool "Architected timer support"
1390         depends on CPU_V7
1391         select ARM_ARCH_TIMER
1392         select GENERIC_CLOCKEVENTS
1393         help
1394           This option enables support for the ARM architected timer
1395
1396 config HAVE_ARM_TWD
1397         bool
1398         depends on SMP
1399         select CLKSRC_OF if OF
1400         help
1401           This options enables support for the ARM timer and watchdog unit
1402
1403 config MCPM
1404         bool "Multi-Cluster Power Management"
1405         depends on CPU_V7 && SMP
1406         help
1407           This option provides the common power management infrastructure
1408           for (multi-)cluster based systems, such as big.LITTLE based
1409           systems.
1410
1411 config MCPM_QUAD_CLUSTER
1412         bool
1413         depends on MCPM
1414         help
1415           To avoid wasting resources unnecessarily, MCPM only supports up
1416           to 2 clusters by default.
1417           Platforms with 3 or 4 clusters that use MCPM must select this
1418           option to allow the additional clusters to be managed.
1419
1420 config BIG_LITTLE
1421         bool "big.LITTLE support (Experimental)"
1422         depends on CPU_V7 && SMP
1423         select MCPM
1424         help
1425           This option enables support selections for the big.LITTLE
1426           system architecture.
1427
1428 config BL_SWITCHER
1429         bool "big.LITTLE switcher support"
1430         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1431         select ARM_CPU_SUSPEND
1432         select CPU_PM
1433         help
1434           The big.LITTLE "switcher" provides the core functionality to
1435           transparently handle transition between a cluster of A15's
1436           and a cluster of A7's in a big.LITTLE system.
1437
1438 config BL_SWITCHER_DUMMY_IF
1439         tristate "Simple big.LITTLE switcher user interface"
1440         depends on BL_SWITCHER && DEBUG_KERNEL
1441         help
1442           This is a simple and dummy char dev interface to control
1443           the big.LITTLE switcher core code.  It is meant for
1444           debugging purposes only.
1445
1446 choice
1447         prompt "Memory split"
1448         depends on MMU
1449         default VMSPLIT_3G
1450         help
1451           Select the desired split between kernel and user memory.
1452
1453           If you are not absolutely sure what you are doing, leave this
1454           option alone!
1455
1456         config VMSPLIT_3G
1457                 bool "3G/1G user/kernel split"
1458         config VMSPLIT_2G
1459                 bool "2G/2G user/kernel split"
1460         config VMSPLIT_1G
1461                 bool "1G/3G user/kernel split"
1462 endchoice
1463
1464 config PAGE_OFFSET
1465         hex
1466         default PHYS_OFFSET if !MMU
1467         default 0x40000000 if VMSPLIT_1G
1468         default 0x80000000 if VMSPLIT_2G
1469         default 0xC0000000
1470
1471 config NR_CPUS
1472         int "Maximum number of CPUs (2-32)"
1473         range 2 32
1474         depends on SMP
1475         default "4"
1476
1477 config HOTPLUG_CPU
1478         bool "Support for hot-pluggable CPUs"
1479         depends on SMP
1480         help
1481           Say Y here to experiment with turning CPUs off and on.  CPUs
1482           can be controlled through /sys/devices/system/cpu.
1483
1484 config ARM_PSCI
1485         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1486         depends on CPU_V7
1487         help
1488           Say Y here if you want Linux to communicate with system firmware
1489           implementing the PSCI specification for CPU-centric power
1490           management operations described in ARM document number ARM DEN
1491           0022A ("Power State Coordination Interface System Software on
1492           ARM processors").
1493
1494 # The GPIO number here must be sorted by descending number. In case of
1495 # a multiplatform kernel, we just want the highest value required by the
1496 # selected platforms.
1497 config ARCH_NR_GPIO
1498         int
1499         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1500         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1501                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1502         default 416 if ARCH_SUNXI
1503         default 392 if ARCH_U8500
1504         default 352 if ARCH_VT8500
1505         default 288 if ARCH_ROCKCHIP
1506         default 264 if MACH_H4700
1507         default 0
1508         help
1509           Maximum number of GPIOs in the system.
1510
1511           If unsure, leave the default value.
1512
1513 source kernel/Kconfig.preempt
1514
1515 config HZ_FIXED
1516         int
1517         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1518                 ARCH_S5PV210 || ARCH_EXYNOS4
1519         default AT91_TIMER_HZ if ARCH_AT91
1520         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1521         default 0
1522
1523 choice
1524         depends on HZ_FIXED = 0
1525         prompt "Timer frequency"
1526
1527 config HZ_100
1528         bool "100 Hz"
1529
1530 config HZ_200
1531         bool "200 Hz"
1532
1533 config HZ_250
1534         bool "250 Hz"
1535
1536 config HZ_300
1537         bool "300 Hz"
1538
1539 config HZ_500
1540         bool "500 Hz"
1541
1542 config HZ_1000
1543         bool "1000 Hz"
1544
1545 endchoice
1546
1547 config HZ
1548         int
1549         default HZ_FIXED if HZ_FIXED != 0
1550         default 100 if HZ_100
1551         default 200 if HZ_200
1552         default 250 if HZ_250
1553         default 300 if HZ_300
1554         default 500 if HZ_500
1555         default 1000
1556
1557 config SCHED_HRTICK
1558         def_bool HIGH_RES_TIMERS
1559
1560 config THUMB2_KERNEL
1561         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1562         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1563         default y if CPU_THUMBONLY
1564         select AEABI
1565         select ARM_ASM_UNIFIED
1566         select ARM_UNWIND
1567         help
1568           By enabling this option, the kernel will be compiled in
1569           Thumb-2 mode. A compiler/assembler that understand the unified
1570           ARM-Thumb syntax is needed.
1571
1572           If unsure, say N.
1573
1574 config THUMB2_AVOID_R_ARM_THM_JUMP11
1575         bool "Work around buggy Thumb-2 short branch relocations in gas"
1576         depends on THUMB2_KERNEL && MODULES
1577         default y
1578         help
1579           Various binutils versions can resolve Thumb-2 branches to
1580           locally-defined, preemptible global symbols as short-range "b.n"
1581           branch instructions.
1582
1583           This is a problem, because there's no guarantee the final
1584           destination of the symbol, or any candidate locations for a
1585           trampoline, are within range of the branch.  For this reason, the
1586           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1587           relocation in modules at all, and it makes little sense to add
1588           support.
1589
1590           The symptom is that the kernel fails with an "unsupported
1591           relocation" error when loading some modules.
1592
1593           Until fixed tools are available, passing
1594           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1595           code which hits this problem, at the cost of a bit of extra runtime
1596           stack usage in some cases.
1597
1598           The problem is described in more detail at:
1599               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1600
1601           Only Thumb-2 kernels are affected.
1602
1603           Unless you are sure your tools don't have this problem, say Y.
1604
1605 config ARM_ASM_UNIFIED
1606         bool
1607
1608 config AEABI
1609         bool "Use the ARM EABI to compile the kernel"
1610         help
1611           This option allows for the kernel to be compiled using the latest
1612           ARM ABI (aka EABI).  This is only useful if you are using a user
1613           space environment that is also compiled with EABI.
1614
1615           Since there are major incompatibilities between the legacy ABI and
1616           EABI, especially with regard to structure member alignment, this
1617           option also changes the kernel syscall calling convention to
1618           disambiguate both ABIs and allow for backward compatibility support
1619           (selected with CONFIG_OABI_COMPAT).
1620
1621           To use this you need GCC version 4.0.0 or later.
1622
1623 config OABI_COMPAT
1624         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1625         depends on AEABI && !THUMB2_KERNEL
1626         help
1627           This option preserves the old syscall interface along with the
1628           new (ARM EABI) one. It also provides a compatibility layer to
1629           intercept syscalls that have structure arguments which layout
1630           in memory differs between the legacy ABI and the new ARM EABI
1631           (only for non "thumb" binaries). This option adds a tiny
1632           overhead to all syscalls and produces a slightly larger kernel.
1633
1634           The seccomp filter system will not be available when this is
1635           selected, since there is no way yet to sensibly distinguish
1636           between calling conventions during filtering.
1637
1638           If you know you'll be using only pure EABI user space then you
1639           can say N here. If this option is not selected and you attempt
1640           to execute a legacy ABI binary then the result will be
1641           UNPREDICTABLE (in fact it can be predicted that it won't work
1642           at all). If in doubt say N.
1643
1644 config ARCH_HAS_HOLES_MEMORYMODEL
1645         bool
1646
1647 config ARCH_SPARSEMEM_ENABLE
1648         bool
1649
1650 config ARCH_SPARSEMEM_DEFAULT
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config ARCH_SELECT_MEMORY_MODEL
1654         def_bool ARCH_SPARSEMEM_ENABLE
1655
1656 config HAVE_ARCH_PFN_VALID
1657         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1658
1659 config HAVE_GENERIC_RCU_GUP
1660         def_bool y
1661         depends on ARM_LPAE
1662
1663 config HIGHMEM
1664         bool "High Memory Support"
1665         depends on MMU
1666         help
1667           The address space of ARM processors is only 4 Gigabytes large
1668           and it has to accommodate user address space, kernel address
1669           space as well as some memory mapped IO. That means that, if you
1670           have a large amount of physical memory and/or IO, not all of the
1671           memory can be "permanently mapped" by the kernel. The physical
1672           memory that is not permanently mapped is called "high memory".
1673
1674           Depending on the selected kernel/user memory split, minimum
1675           vmalloc space and actual amount of RAM, you may not need this
1676           option which should result in a slightly faster kernel.
1677
1678           If unsure, say n.
1679
1680 config HIGHPTE
1681         bool "Allocate 2nd-level pagetables from highmem"
1682         depends on HIGHMEM
1683
1684 config HW_PERF_EVENTS
1685         bool "Enable hardware performance counter support for perf events"
1686         depends on PERF_EVENTS
1687         default y
1688         help
1689           Enable hardware performance counter support for perf events. If
1690           disabled, perf events will use software events only.
1691
1692 config SYS_SUPPORTS_HUGETLBFS
1693        def_bool y
1694        depends on ARM_LPAE
1695
1696 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1697        def_bool y
1698        depends on ARM_LPAE
1699
1700 config ARCH_WANT_GENERAL_HUGETLB
1701         def_bool y
1702
1703 source "mm/Kconfig"
1704
1705 config FORCE_MAX_ZONEORDER
1706         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1707         range 11 64 if ARCH_SHMOBILE_LEGACY
1708         default "12" if SOC_AM33XX
1709         default "9" if SA1111 || ARCH_EFM32
1710         default "11"
1711         help
1712           The kernel memory allocator divides physically contiguous memory
1713           blocks into "zones", where each zone is a power of two number of
1714           pages.  This option selects the largest power of two that the kernel
1715           keeps in the memory allocator.  If you need to allocate very large
1716           blocks of physically contiguous memory, then you may need to
1717           increase this value.
1718
1719           This config option is actually maximum order plus one. For example,
1720           a value of 11 means that the largest free memory block is 2^10 pages.
1721
1722 config ALIGNMENT_TRAP
1723         bool
1724         depends on CPU_CP15_MMU
1725         default y if !ARCH_EBSA110
1726         select HAVE_PROC_CPU if PROC_FS
1727         help
1728           ARM processors cannot fetch/store information which is not
1729           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1730           address divisible by 4. On 32-bit ARM processors, these non-aligned
1731           fetch/store instructions will be emulated in software if you say
1732           here, which has a severe performance impact. This is necessary for
1733           correct operation of some network protocols. With an IP-only
1734           configuration it is safe to say N, otherwise say Y.
1735
1736 config UACCESS_WITH_MEMCPY
1737         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1738         depends on MMU
1739         default y if CPU_FEROCEON
1740         help
1741           Implement faster copy_to_user and clear_user methods for CPU
1742           cores where a 8-word STM instruction give significantly higher
1743           memory write throughput than a sequence of individual 32bit stores.
1744
1745           A possible side effect is a slight increase in scheduling latency
1746           between threads sharing the same address space if they invoke
1747           such copy operations with large buffers.
1748
1749           However, if the CPU data cache is using a write-allocate mode,
1750           this option is unlikely to provide any performance gain.
1751
1752 config SECCOMP
1753         bool
1754         prompt "Enable seccomp to safely compute untrusted bytecode"
1755         ---help---
1756           This kernel feature is useful for number crunching applications
1757           that may need to compute untrusted bytecode during their
1758           execution. By using pipes or other transports made available to
1759           the process as file descriptors supporting the read/write
1760           syscalls, it's possible to isolate those applications in
1761           their own address space using seccomp. Once seccomp is
1762           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1763           and the task is only allowed to execute a few safe syscalls
1764           defined by each seccomp mode.
1765
1766 config SWIOTLB
1767         def_bool y
1768
1769 config IOMMU_HELPER
1770         def_bool SWIOTLB
1771
1772 config XEN_DOM0
1773         def_bool y
1774         depends on XEN
1775
1776 config XEN
1777         bool "Xen guest support on ARM"
1778         depends on ARM && AEABI && OF
1779         depends on CPU_V7 && !CPU_V6
1780         depends on !GENERIC_ATOMIC64
1781         depends on MMU
1782         select ARCH_DMA_ADDR_T_64BIT
1783         select ARM_PSCI
1784         select SWIOTLB_XEN
1785         help
1786           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1787
1788 endmenu
1789
1790 menu "Boot options"
1791
1792 config USE_OF
1793         bool "Flattened Device Tree support"
1794         select IRQ_DOMAIN
1795         select OF
1796         select OF_EARLY_FLATTREE
1797         select OF_RESERVED_MEM
1798         help
1799           Include support for flattened device tree machine descriptions.
1800
1801 config ATAGS
1802         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1803         default y
1804         help
1805           This is the traditional way of passing data to the kernel at boot
1806           time. If you are solely relying on the flattened device tree (or
1807           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1808           to remove ATAGS support from your kernel binary.  If unsure,
1809           leave this to y.
1810
1811 config DEPRECATED_PARAM_STRUCT
1812         bool "Provide old way to pass kernel parameters"
1813         depends on ATAGS
1814         help
1815           This was deprecated in 2001 and announced to live on for 5 years.
1816           Some old boot loaders still use this way.
1817
1818 # Compressed boot loader in ROM.  Yes, we really want to ask about
1819 # TEXT and BSS so we preserve their values in the config files.
1820 config ZBOOT_ROM_TEXT
1821         hex "Compressed ROM boot loader base address"
1822         default "0"
1823         help
1824           The physical address at which the ROM-able zImage is to be
1825           placed in the target.  Platforms which normally make use of
1826           ROM-able zImage formats normally set this to a suitable
1827           value in their defconfig file.
1828
1829           If ZBOOT_ROM is not enabled, this has no effect.
1830
1831 config ZBOOT_ROM_BSS
1832         hex "Compressed ROM boot loader BSS address"
1833         default "0"
1834         help
1835           The base address of an area of read/write memory in the target
1836           for the ROM-able zImage which must be available while the
1837           decompressor is running. It must be large enough to hold the
1838           entire decompressed kernel plus an additional 128 KiB.
1839           Platforms which normally make use of ROM-able zImage formats
1840           normally set this to a suitable value in their defconfig file.
1841
1842           If ZBOOT_ROM is not enabled, this has no effect.
1843
1844 config ZBOOT_ROM
1845         bool "Compressed boot loader in ROM/flash"
1846         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1847         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1848         help
1849           Say Y here if you intend to execute your compressed kernel image
1850           (zImage) directly from ROM or flash.  If unsure, say N.
1851
1852 choice
1853         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1854         depends on ZBOOT_ROM && ARCH_SH7372
1855         default ZBOOT_ROM_NONE
1856         help
1857           Include experimental SD/MMC loading code in the ROM-able zImage.
1858           With this enabled it is possible to write the ROM-able zImage
1859           kernel image to an MMC or SD card and boot the kernel straight
1860           from the reset vector. At reset the processor Mask ROM will load
1861           the first part of the ROM-able zImage which in turn loads the
1862           rest the kernel image to RAM.
1863
1864 config ZBOOT_ROM_NONE
1865         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1866         help
1867           Do not load image from SD or MMC
1868
1869 config ZBOOT_ROM_MMCIF
1870         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1871         help
1872           Load image from MMCIF hardware block.
1873
1874 config ZBOOT_ROM_SH_MOBILE_SDHI
1875         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1876         help
1877           Load image from SDHI hardware block
1878
1879 endchoice
1880
1881 config ARM_APPENDED_DTB
1882         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1883         depends on OF
1884         help
1885           With this option, the boot code will look for a device tree binary
1886           (DTB) appended to zImage
1887           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1888
1889           This is meant as a backward compatibility convenience for those
1890           systems with a bootloader that can't be upgraded to accommodate
1891           the documented boot protocol using a device tree.
1892
1893           Beware that there is very little in terms of protection against
1894           this option being confused by leftover garbage in memory that might
1895           look like a DTB header after a reboot if no actual DTB is appended
1896           to zImage.  Do not leave this option active in a production kernel
1897           if you don't intend to always append a DTB.  Proper passing of the
1898           location into r2 of a bootloader provided DTB is always preferable
1899           to this option.
1900
1901 config ARM_ATAG_DTB_COMPAT
1902         bool "Supplement the appended DTB with traditional ATAG information"
1903         depends on ARM_APPENDED_DTB
1904         help
1905           Some old bootloaders can't be updated to a DTB capable one, yet
1906           they provide ATAGs with memory configuration, the ramdisk address,
1907           the kernel cmdline string, etc.  Such information is dynamically
1908           provided by the bootloader and can't always be stored in a static
1909           DTB.  To allow a device tree enabled kernel to be used with such
1910           bootloaders, this option allows zImage to extract the information
1911           from the ATAG list and store it at run time into the appended DTB.
1912
1913 choice
1914         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1915         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1916
1917 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918         bool "Use bootloader kernel arguments if available"
1919         help
1920           Uses the command-line options passed by the boot loader instead of
1921           the device tree bootargs property. If the boot loader doesn't provide
1922           any, the device tree bootargs property will be used.
1923
1924 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1925         bool "Extend with bootloader kernel arguments"
1926         help
1927           The command-line arguments provided by the boot loader will be
1928           appended to the the device tree bootargs property.
1929
1930 endchoice
1931
1932 config CMDLINE
1933         string "Default kernel command string"
1934         default ""
1935         help
1936           On some architectures (EBSA110 and CATS), there is currently no way
1937           for the boot loader to pass arguments to the kernel. For these
1938           architectures, you should supply some command-line options at build
1939           time by entering them here. As a minimum, you should specify the
1940           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1941
1942 choice
1943         prompt "Kernel command line type" if CMDLINE != ""
1944         default CMDLINE_FROM_BOOTLOADER
1945         depends on ATAGS
1946
1947 config CMDLINE_FROM_BOOTLOADER
1948         bool "Use bootloader kernel arguments if available"
1949         help
1950           Uses the command-line options passed by the boot loader. If
1951           the boot loader doesn't provide any, the default kernel command
1952           string provided in CMDLINE will be used.
1953
1954 config CMDLINE_EXTEND
1955         bool "Extend bootloader kernel arguments"
1956         help
1957           The command-line arguments provided by the boot loader will be
1958           appended to the default kernel command string.
1959
1960 config CMDLINE_FORCE
1961         bool "Always use the default kernel command string"
1962         help
1963           Always use the default kernel command string, even if the boot
1964           loader passes other arguments to the kernel.
1965           This is useful if you cannot or don't want to change the
1966           command-line options your boot loader passes to the kernel.
1967 endchoice
1968
1969 config XIP_KERNEL
1970         bool "Kernel Execute-In-Place from ROM"
1971         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1972         help
1973           Execute-In-Place allows the kernel to run from non-volatile storage
1974           directly addressable by the CPU, such as NOR flash. This saves RAM
1975           space since the text section of the kernel is not loaded from flash
1976           to RAM.  Read-write sections, such as the data section and stack,
1977           are still copied to RAM.  The XIP kernel is not compressed since
1978           it has to run directly from flash, so it will take more space to
1979           store it.  The flash address used to link the kernel object files,
1980           and for storing it, is configuration dependent. Therefore, if you
1981           say Y here, you must know the proper physical address where to
1982           store the kernel image depending on your own flash memory usage.
1983
1984           Also note that the make target becomes "make xipImage" rather than
1985           "make zImage" or "make Image".  The final kernel binary to put in
1986           ROM memory will be arch/arm/boot/xipImage.
1987
1988           If unsure, say N.
1989
1990 config XIP_PHYS_ADDR
1991         hex "XIP Kernel Physical Location"
1992         depends on XIP_KERNEL
1993         default "0x00080000"
1994         help
1995           This is the physical address in your flash memory the kernel will
1996           be linked for and stored to.  This address is dependent on your
1997           own flash usage.
1998
1999 config KEXEC
2000         bool "Kexec system call (EXPERIMENTAL)"
2001         depends on (!SMP || PM_SLEEP_SMP)
2002         help
2003           kexec is a system call that implements the ability to shutdown your
2004           current kernel, and to start another kernel.  It is like a reboot
2005           but it is independent of the system firmware.   And like a reboot
2006           you can start any kernel with it, not just Linux.
2007
2008           It is an ongoing process to be certain the hardware in a machine
2009           is properly shutdown, so do not be surprised if this code does not
2010           initially work for you.
2011
2012 config ATAGS_PROC
2013         bool "Export atags in procfs"
2014         depends on ATAGS && KEXEC
2015         default y
2016         help
2017           Should the atags used to boot the kernel be exported in an "atags"
2018           file in procfs. Useful with kexec.
2019
2020 config CRASH_DUMP
2021         bool "Build kdump crash kernel (EXPERIMENTAL)"
2022         help
2023           Generate crash dump after being started by kexec. This should
2024           be normally only set in special crash dump kernels which are
2025           loaded in the main kernel with kexec-tools into a specially
2026           reserved region and then later executed after a crash by
2027           kdump/kexec. The crash dump kernel must be compiled to a
2028           memory address not used by the main kernel
2029
2030           For more details see Documentation/kdump/kdump.txt
2031
2032 config AUTO_ZRELADDR
2033         bool "Auto calculation of the decompressed kernel image address"
2034         help
2035           ZRELADDR is the physical address where the decompressed kernel
2036           image will be placed. If AUTO_ZRELADDR is selected, the address
2037           will be determined at run-time by masking the current IP with
2038           0xf8000000. This assumes the zImage being placed in the first 128MB
2039           from start of memory.
2040
2041 endmenu
2042
2043 menu "CPU Power Management"
2044
2045 source "drivers/cpufreq/Kconfig"
2046
2047 source "drivers/cpuidle/Kconfig"
2048
2049 endmenu
2050
2051 menu "Floating point emulation"
2052
2053 comment "At least one emulation must be selected"
2054
2055 config FPE_NWFPE
2056         bool "NWFPE math emulation"
2057         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2058         ---help---
2059           Say Y to include the NWFPE floating point emulator in the kernel.
2060           This is necessary to run most binaries. Linux does not currently
2061           support floating point hardware so you need to say Y here even if
2062           your machine has an FPA or floating point co-processor podule.
2063
2064           You may say N here if you are going to load the Acorn FPEmulator
2065           early in the bootup.
2066
2067 config FPE_NWFPE_XP
2068         bool "Support extended precision"
2069         depends on FPE_NWFPE
2070         help
2071           Say Y to include 80-bit support in the kernel floating-point
2072           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2073           Note that gcc does not generate 80-bit operations by default,
2074           so in most cases this option only enlarges the size of the
2075           floating point emulator without any good reason.
2076
2077           You almost surely want to say N here.
2078
2079 config FPE_FASTFPE
2080         bool "FastFPE math emulation (EXPERIMENTAL)"
2081         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2082         ---help---
2083           Say Y here to include the FAST floating point emulator in the kernel.
2084           This is an experimental much faster emulator which now also has full
2085           precision for the mantissa.  It does not support any exceptions.
2086           It is very simple, and approximately 3-6 times faster than NWFPE.
2087
2088           It should be sufficient for most programs.  It may be not suitable
2089           for scientific calculations, but you have to check this for yourself.
2090           If you do not feel you need a faster FP emulation you should better
2091           choose NWFPE.
2092
2093 config VFP
2094         bool "VFP-format floating point maths"
2095         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2096         help
2097           Say Y to include VFP support code in the kernel. This is needed
2098           if your hardware includes a VFP unit.
2099
2100           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2101           release notes and additional status information.
2102
2103           Say N if your target does not have VFP hardware.
2104
2105 config VFPv3
2106         bool
2107         depends on VFP
2108         default y if CPU_V7
2109
2110 config NEON
2111         bool "Advanced SIMD (NEON) Extension support"
2112         depends on VFPv3 && CPU_V7
2113         help
2114           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2115           Extension.
2116
2117 config KERNEL_MODE_NEON
2118         bool "Support for NEON in kernel mode"
2119         depends on NEON && AEABI
2120         help
2121           Say Y to include support for NEON in kernel mode.
2122
2123 endmenu
2124
2125 menu "Userspace binary formats"
2126
2127 source "fs/Kconfig.binfmt"
2128
2129 config ARTHUR
2130         tristate "RISC OS personality"
2131         depends on !AEABI
2132         help
2133           Say Y here to include the kernel code necessary if you want to run
2134           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2135           experimental; if this sounds frightening, say N and sleep in peace.
2136           You can also say M here to compile this support as a module (which
2137           will be called arthur).
2138
2139 endmenu
2140
2141 menu "Power management options"
2142
2143 source "kernel/power/Kconfig"
2144
2145 config ARCH_SUSPEND_POSSIBLE
2146         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2147                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2148         def_bool y
2149
2150 config ARM_CPU_SUSPEND
2151         def_bool PM_SLEEP
2152
2153 config ARCH_HIBERNATION_POSSIBLE
2154         bool
2155         depends on MMU
2156         default y if ARCH_SUSPEND_POSSIBLE
2157
2158 endmenu
2159
2160 source "net/Kconfig"
2161
2162 source "drivers/Kconfig"
2163
2164 source "fs/Kconfig"
2165
2166 source "arch/arm/Kconfig.debug"
2167
2168 source "security/Kconfig"
2169
2170 source "crypto/Kconfig"
2171
2172 source "lib/Kconfig"
2173
2174 source "arch/arm/kvm/Kconfig"