4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_EXIT_THREAD
54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59 select HAVE_IDE if PCI || ISA || PCMCIA
60 select HAVE_IRQ_TIME_ACCOUNTING
61 select HAVE_KERNEL_GZIP
62 select HAVE_KERNEL_LZ4
63 select HAVE_KERNEL_LZMA
64 select HAVE_KERNEL_LZO
66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67 select HAVE_KRETPROBES if (HAVE_KPROBES)
69 select HAVE_MOD_ARCH_SPECIFIC
71 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
72 select HAVE_OPTPROBES if !THUMB2_KERNEL
73 select HAVE_PERF_EVENTS
75 select HAVE_PERF_USER_STACK_DUMP
76 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
77 select HAVE_REGS_AND_STACK_ACCESS_API
78 select HAVE_SYSCALL_TRACEPOINTS
80 select HAVE_VIRT_CPU_ACCOUNTING_GEN
81 select IRQ_FORCED_THREADING
82 select MODULES_USE_ELF_REL
84 select OF_EARLY_FLATTREE if OF
85 select OF_RESERVED_MEM if OF
87 select OLD_SIGSUSPEND3
88 select PERF_USE_VMALLOC
90 select SYS_SUPPORTS_APM_EMULATION
91 # Above selects are sorted alphabetically; please add new ones
92 # according to that. Thanks.
94 The ARM series is a line of low-power-consumption RISC chip designs
95 licensed by ARM Ltd and targeted at embedded applications and
96 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
97 manufactured, but legacy ARM-based PC hardware remains popular in
98 Europe. There is an ARM Linux project with a web page at
99 <http://www.arm.linux.org.uk/>.
101 config ARM_HAS_SG_CHAIN
102 select ARCH_HAS_SG_CHAIN
105 config NEED_SG_DMA_LENGTH
108 config ARM_DMA_USE_IOMMU
110 select ARM_HAS_SG_CHAIN
111 select NEED_SG_DMA_LENGTH
115 config ARM_DMA_IOMMU_ALIGNMENT
116 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
120 DMA mapping framework by default aligns all buffers to the smallest
121 PAGE_SIZE order which is greater than or equal to the requested buffer
122 size. This works well for buffers up to a few hundreds kilobytes, but
123 for larger buffers it just a waste of address space. Drivers which has
124 relatively small addressing window (like 64Mib) might run out of
125 virtual space with just a few allocations.
127 With this parameter you can specify the maximum PAGE_SIZE order for
128 DMA IOMMU buffers. Larger buffers will be aligned only to this
129 specified order. The order is expressed as a power of two multiplied
134 config MIGHT_HAVE_PCI
137 config SYS_SUPPORTS_APM_EMULATION
142 select GENERIC_ALLOCATOR
153 The Extended Industry Standard Architecture (EISA) bus was
154 developed as an open alternative to the IBM MicroChannel bus.
156 The EISA bus provided some of the features of the IBM MicroChannel
157 bus while maintaining backward compatibility with cards made for
158 the older ISA bus. The EISA bus saw limited use between 1988 and
159 1995 when it was made obsolete by the PCI bus.
161 Say Y here if you are building a kernel for an EISA-based machine.
168 config STACKTRACE_SUPPORT
172 config LOCKDEP_SUPPORT
176 config TRACE_IRQFLAGS_SUPPORT
180 config RWSEM_XCHGADD_ALGORITHM
184 config ARCH_HAS_ILOG2_U32
187 config ARCH_HAS_ILOG2_U64
190 config ARCH_HAS_BANDGAP
193 config FIX_EARLYCON_MEM
196 config GENERIC_HWEIGHT
200 config GENERIC_CALIBRATE_DELAY
204 config ARCH_MAY_HAVE_PC_FDC
210 config NEED_DMA_MAP_STATE
213 config ARCH_SUPPORTS_UPROBES
216 config ARCH_HAS_DMA_SET_COHERENT_MASK
219 config GENERIC_ISA_DMA
225 config NEED_RET_TO_USER
233 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
234 default DRAM_BASE if REMAP_VECTORS_TO_RAM
237 The base address of exception vectors. This must be two pages
240 config ARM_PATCH_PHYS_VIRT
241 bool "Patch physical to virtual translations at runtime" if EMBEDDED
243 depends on !XIP_KERNEL && MMU
245 Patch phys-to-virt and virt-to-phys translation functions at
246 boot and module load time according to the position of the
247 kernel in system memory.
249 This can only be used with non-XIP MMU kernels where the base
250 of physical memory is at a 16MB boundary.
252 Only disable this option if you know that you do not require
253 this feature (eg, building a kernel for a single machine) and
254 you need to shrink the kernel to the minimal size.
256 config NEED_MACH_IO_H
259 Select this when mach/io.h is required to provide special
260 definitions for this platform. The need for mach/io.h should
261 be avoided when possible.
263 config NEED_MACH_MEMORY_H
266 Select this when mach/memory.h is required to provide special
267 definitions for this platform. The need for mach/memory.h should
268 be avoided when possible.
271 hex "Physical address of main memory" if MMU
272 depends on !ARM_PATCH_PHYS_VIRT
273 default DRAM_BASE if !MMU
274 default 0x00000000 if ARCH_EBSA110 || \
279 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
281 default 0x20000000 if ARCH_S5PV210
282 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
283 default 0xc0000000 if ARCH_SA1100
285 Please provide the physical address corresponding to the
286 location of main memory in your system.
292 config PGTABLE_LEVELS
294 default 3 if ARM_LPAE
297 source "init/Kconfig"
299 source "kernel/Kconfig.freezer"
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
310 config ARCH_MMAP_RND_BITS_MIN
313 config ARCH_MMAP_RND_BITS_MAX
314 default 14 if PAGE_OFFSET=0x40000000
315 default 15 if PAGE_OFFSET=0x80000000
319 # The "ARM system type" choice list is ordered alphabetically by option
320 # text. Please add new entries in the option alphabetic order.
323 prompt "ARM system type"
324 default ARM_SINGLE_ARMV7M if !MMU
325 default ARCH_MULTIPLATFORM if MMU
327 config ARCH_MULTIPLATFORM
328 bool "Allow multiple platforms to be selected"
330 select ARCH_WANT_OPTIONAL_GPIOLIB
331 select ARM_HAS_SG_CHAIN
332 select ARM_PATCH_PHYS_VIRT
336 select GENERIC_CLOCKEVENTS
337 select MIGHT_HAVE_PCI
338 select MULTI_IRQ_HANDLER
342 config ARM_SINGLE_ARMV7M
343 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select GENERIC_CLOCKEVENTS
358 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
359 select ARCH_REQUIRE_GPIOLIB
364 select GENERIC_CLOCKEVENTS
368 Support for Cirrus Logic 711x/721x/731x based boards.
371 bool "Cortina Systems Gemini"
372 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
377 Support for the Cortina Systems Gemini family SoCs
381 select ARCH_USES_GETTIMEOFFSET
384 select NEED_MACH_IO_H
385 select NEED_MACH_MEMORY_H
388 This is an evaluation board for the StrongARM processor available
389 from Digital. It has limited hardware on-board, including an
390 Ethernet interface, two PCMCIA sockets, two serial ports and a
395 select ARCH_HAS_HOLES_MEMORYMODEL
396 select ARCH_REQUIRE_GPIOLIB
398 select ARM_PATCH_PHYS_VIRT
404 select GENERIC_CLOCKEVENTS
406 This enables support for the Cirrus EP93xx series of CPUs.
408 config ARCH_FOOTBRIDGE
412 select GENERIC_CLOCKEVENTS
414 select NEED_MACH_IO_H if !MMU
415 select NEED_MACH_MEMORY_H
417 Support for systems based on the DC21285 companion chip
418 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
421 bool "Hilscher NetX based"
425 select GENERIC_CLOCKEVENTS
427 This enables support for systems based on the Hilscher NetX Soc
433 select NEED_MACH_MEMORY_H
434 select NEED_RET_TO_USER
440 Support for Intel's IOP13XX (XScale) family of processors.
445 select ARCH_REQUIRE_GPIOLIB
448 select NEED_RET_TO_USER
452 Support for Intel's 80219 and IOP32X (XScale) family of
458 select ARCH_REQUIRE_GPIOLIB
461 select NEED_RET_TO_USER
465 Support for Intel's IOP33X (XScale) family of processors.
470 select ARCH_HAS_DMA_SET_COHERENT_MASK
471 select ARCH_REQUIRE_GPIOLIB
472 select ARCH_SUPPORTS_BIG_ENDIAN
475 select DMABOUNCE if PCI
476 select GENERIC_CLOCKEVENTS
477 select MIGHT_HAVE_PCI
478 select NEED_MACH_IO_H
479 select USB_EHCI_BIG_ENDIAN_DESC
480 select USB_EHCI_BIG_ENDIAN_MMIO
482 Support for Intel's IXP4XX (XScale) family of processors.
486 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
489 select MIGHT_HAVE_PCI
490 select MULTI_IRQ_HANDLER
494 select PLAT_ORION_LEGACY
496 select PM_GENERIC_DOMAINS if PM
498 Support for the Marvell Dove SoC 88AP510
501 bool "Micrel/Kendin KS8695"
502 select ARCH_REQUIRE_GPIOLIB
505 select GENERIC_CLOCKEVENTS
506 select NEED_MACH_MEMORY_H
508 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
509 System-on-Chip devices.
512 bool "Nuvoton W90X900 CPU"
513 select ARCH_REQUIRE_GPIOLIB
517 select GENERIC_CLOCKEVENTS
519 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
520 At present, the w90x900 has been renamed nuc900, regarding
521 the ARM series product line, you can login the following
522 link address to know more.
524 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
525 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
529 select ARCH_REQUIRE_GPIOLIB
532 select CLKSRC_LPC32XX
535 select GENERIC_CLOCKEVENTS
536 select MULTI_IRQ_HANDLER
540 Support for the NXP LPC32XX family of processors
543 bool "PXA2xx/PXA3xx-based"
546 select ARCH_REQUIRE_GPIOLIB
547 select ARM_CPU_SUSPEND if PM
554 select CPU_XSCALE if !CPU_XSC3
555 select GENERIC_CLOCKEVENTS
559 select MULTI_IRQ_HANDLER
563 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
569 select ARCH_MAY_HAVE_PC_FDC
570 select ARCH_SPARSEMEM_ENABLE
571 select ARCH_USES_GETTIMEOFFSET
575 select HAVE_PATA_PLATFORM
577 select NEED_MACH_IO_H
578 select NEED_MACH_MEMORY_H
581 On the Acorn Risc-PC, Linux can support the internal IDE disk and
582 CD-ROM interface, serial and parallel port, and the floppy drive.
587 select ARCH_REQUIRE_GPIOLIB
588 select ARCH_SPARSEMEM_ENABLE
592 select CLKSRC_OF if OF
595 select GENERIC_CLOCKEVENTS
599 select MULTI_IRQ_HANDLER
600 select NEED_MACH_MEMORY_H
603 Support for StrongARM 11x0 based boards.
606 bool "Samsung S3C24XX SoCs"
607 select ARCH_REQUIRE_GPIOLIB
610 select CLKSRC_SAMSUNG_PWM
611 select GENERIC_CLOCKEVENTS
613 select HAVE_S3C2410_I2C if I2C
614 select HAVE_S3C2410_WATCHDOG if WATCHDOG
615 select HAVE_S3C_RTC if RTC_CLASS
616 select MULTI_IRQ_HANDLER
617 select NEED_MACH_IO_H
620 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
621 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
622 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
623 Samsung SMDK2410 development board (and derivatives).
627 select ARCH_HAS_HOLES_MEMORYMODEL
628 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_ALLOCATOR
632 select GENERIC_CLOCKEVENTS
633 select GENERIC_IRQ_CHIP
638 Support for TI's DaVinci platform.
643 select ARCH_HAS_HOLES_MEMORYMODEL
645 select ARCH_REQUIRE_GPIOLIB
648 select GENERIC_CLOCKEVENTS
649 select GENERIC_IRQ_CHIP
652 select MULTI_IRQ_HANDLER
653 select NEED_MACH_IO_H if PCCARD
654 select NEED_MACH_MEMORY_H
657 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
661 menu "Multiple platform selection"
662 depends on ARCH_MULTIPLATFORM
664 comment "CPU Core family selection"
667 bool "ARMv4 based platforms (FA526)"
668 depends on !ARCH_MULTI_V6_V7
669 select ARCH_MULTI_V4_V5
672 config ARCH_MULTI_V4T
673 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
674 depends on !ARCH_MULTI_V6_V7
675 select ARCH_MULTI_V4_V5
676 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
677 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
678 CPU_ARM925T || CPU_ARM940T)
681 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
682 depends on !ARCH_MULTI_V6_V7
683 select ARCH_MULTI_V4_V5
684 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
685 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
686 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
688 config ARCH_MULTI_V4_V5
692 bool "ARMv6 based platforms (ARM11)"
693 select ARCH_MULTI_V6_V7
697 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
699 select ARCH_MULTI_V6_V7
703 config ARCH_MULTI_V6_V7
705 select MIGHT_HAVE_CACHE_L2X0
707 config ARCH_MULTI_CPU_AUTO
708 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
714 bool "Dummy Virtual Machine"
715 depends on ARCH_MULTI_V7
718 select ARM_GIC_V2M if PCI_MSI
721 select HAVE_ARM_ARCH_TIMER
724 # This is sorted alphabetically by mach-* pathname. However, plat-*
725 # Kconfigs may be included either alphabetically (according to the
726 # plat- suffix) or along side the corresponding mach-* source.
728 source "arch/arm/mach-mvebu/Kconfig"
730 source "arch/arm/mach-alpine/Kconfig"
732 source "arch/arm/mach-artpec/Kconfig"
734 source "arch/arm/mach-asm9260/Kconfig"
736 source "arch/arm/mach-at91/Kconfig"
738 source "arch/arm/mach-axxia/Kconfig"
740 source "arch/arm/mach-bcm/Kconfig"
742 source "arch/arm/mach-berlin/Kconfig"
744 source "arch/arm/mach-clps711x/Kconfig"
746 source "arch/arm/mach-cns3xxx/Kconfig"
748 source "arch/arm/mach-davinci/Kconfig"
750 source "arch/arm/mach-digicolor/Kconfig"
752 source "arch/arm/mach-dove/Kconfig"
754 source "arch/arm/mach-ep93xx/Kconfig"
756 source "arch/arm/mach-footbridge/Kconfig"
758 source "arch/arm/mach-gemini/Kconfig"
760 source "arch/arm/mach-highbank/Kconfig"
762 source "arch/arm/mach-hisi/Kconfig"
764 source "arch/arm/mach-integrator/Kconfig"
766 source "arch/arm/mach-iop32x/Kconfig"
768 source "arch/arm/mach-iop33x/Kconfig"
770 source "arch/arm/mach-iop13xx/Kconfig"
772 source "arch/arm/mach-ixp4xx/Kconfig"
774 source "arch/arm/mach-keystone/Kconfig"
776 source "arch/arm/mach-ks8695/Kconfig"
778 source "arch/arm/mach-meson/Kconfig"
780 source "arch/arm/mach-moxart/Kconfig"
782 source "arch/arm/mach-aspeed/Kconfig"
784 source "arch/arm/mach-mv78xx0/Kconfig"
786 source "arch/arm/mach-imx/Kconfig"
788 source "arch/arm/mach-mediatek/Kconfig"
790 source "arch/arm/mach-mxs/Kconfig"
792 source "arch/arm/mach-netx/Kconfig"
794 source "arch/arm/mach-nomadik/Kconfig"
796 source "arch/arm/mach-nspire/Kconfig"
798 source "arch/arm/plat-omap/Kconfig"
800 source "arch/arm/mach-omap1/Kconfig"
802 source "arch/arm/mach-omap2/Kconfig"
804 source "arch/arm/mach-orion5x/Kconfig"
806 source "arch/arm/mach-picoxcell/Kconfig"
808 source "arch/arm/mach-pxa/Kconfig"
809 source "arch/arm/plat-pxa/Kconfig"
811 source "arch/arm/mach-mmp/Kconfig"
813 source "arch/arm/mach-oxnas/Kconfig"
815 source "arch/arm/mach-qcom/Kconfig"
817 source "arch/arm/mach-realview/Kconfig"
819 source "arch/arm/mach-rockchip/Kconfig"
821 source "arch/arm/mach-sa1100/Kconfig"
823 source "arch/arm/mach-socfpga/Kconfig"
825 source "arch/arm/mach-spear/Kconfig"
827 source "arch/arm/mach-sti/Kconfig"
829 source "arch/arm/mach-s3c24xx/Kconfig"
831 source "arch/arm/mach-s3c64xx/Kconfig"
833 source "arch/arm/mach-s5pv210/Kconfig"
835 source "arch/arm/mach-exynos/Kconfig"
836 source "arch/arm/plat-samsung/Kconfig"
838 source "arch/arm/mach-shmobile/Kconfig"
840 source "arch/arm/mach-sunxi/Kconfig"
842 source "arch/arm/mach-prima2/Kconfig"
844 source "arch/arm/mach-tango/Kconfig"
846 source "arch/arm/mach-tegra/Kconfig"
848 source "arch/arm/mach-u300/Kconfig"
850 source "arch/arm/mach-uniphier/Kconfig"
852 source "arch/arm/mach-ux500/Kconfig"
854 source "arch/arm/mach-versatile/Kconfig"
856 source "arch/arm/mach-vexpress/Kconfig"
857 source "arch/arm/plat-versatile/Kconfig"
859 source "arch/arm/mach-vt8500/Kconfig"
861 source "arch/arm/mach-w90x900/Kconfig"
863 source "arch/arm/mach-zx/Kconfig"
865 source "arch/arm/mach-zynq/Kconfig"
867 # ARMv7-M architecture
869 bool "Energy Micro efm32"
870 depends on ARM_SINGLE_ARMV7M
871 select ARCH_REQUIRE_GPIOLIB
873 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
877 bool "NXP LPC18xx/LPC43xx"
878 depends on ARM_SINGLE_ARMV7M
879 select ARCH_HAS_RESET_CONTROLLER
881 select CLKSRC_LPC32XX
884 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
885 high performance microcontrollers.
888 bool "STMicrolectronics STM32"
889 depends on ARM_SINGLE_ARMV7M
890 select ARCH_HAS_RESET_CONTROLLER
891 select ARMV7M_SYSTICK
894 select RESET_CONTROLLER
896 Support for STMicroelectronics STM32 processors.
898 config MACH_STM32F429
899 bool "STMicrolectronics STM32F429"
900 depends on ARCH_STM32
904 bool "ARM MPS2 paltform"
905 depends on ARM_SINGLE_ARMV7M
909 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
910 with a range of available cores like Cortex-M3/M4/M7.
912 Please, note that depends which Application Note is used memory map
913 for the platform may vary, so adjustment of RAM base might be needed.
915 # Definitions to make life easier
921 select GENERIC_CLOCKEVENTS
927 select GENERIC_IRQ_CHIP
930 config PLAT_ORION_LEGACY
937 config PLAT_VERSATILE
940 source "arch/arm/firmware/Kconfig"
942 source arch/arm/mm/Kconfig
945 bool "Enable iWMMXt support"
946 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
947 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
949 Enable support for iWMMXt context switching at run time if
950 running on a CPU that supports it.
952 config MULTI_IRQ_HANDLER
955 Allow each machine to specify it's own IRQ handler at run time.
958 source "arch/arm/Kconfig-nommu"
961 config PJ4B_ERRATA_4742
962 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
963 depends on CPU_PJ4B && MACH_ARMADA_370
966 When coming out of either a Wait for Interrupt (WFI) or a Wait for
967 Event (WFE) IDLE states, a specific timing sensitivity exists between
968 the retiring WFI/WFE instructions and the newly issued subsequent
969 instructions. This sensitivity can result in a CPU hang scenario.
971 The software must insert either a Data Synchronization Barrier (DSB)
972 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
975 config ARM_ERRATA_326103
976 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
979 Executing a SWP instruction to read-only memory does not set bit 11
980 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
981 treat the access as a read, preventing a COW from occurring and
982 causing the faulting task to livelock.
984 config ARM_ERRATA_411920
985 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
986 depends on CPU_V6 || CPU_V6K
988 Invalidation of the Instruction Cache operation can
989 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
990 It does not affect the MPCore. This option enables the ARM Ltd.
991 recommended workaround.
993 config ARM_ERRATA_430973
994 bool "ARM errata: Stale prediction on replaced interworking branch"
997 This option enables the workaround for the 430973 Cortex-A8
998 r1p* erratum. If a code sequence containing an ARM/Thumb
999 interworking branch is replaced with another code sequence at the
1000 same virtual address, whether due to self-modifying code or virtual
1001 to physical address re-mapping, Cortex-A8 does not recover from the
1002 stale interworking branch prediction. This results in Cortex-A8
1003 executing the new code sequence in the incorrect ARM or Thumb state.
1004 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1005 and also flushes the branch target cache at every context switch.
1006 Note that setting specific bits in the ACTLR register may not be
1007 available in non-secure mode.
1009 config ARM_ERRATA_458693
1010 bool "ARM errata: Processor deadlock when a false hazard is created"
1012 depends on !ARCH_MULTIPLATFORM
1014 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1015 erratum. For very specific sequences of memory operations, it is
1016 possible for a hazard condition intended for a cache line to instead
1017 be incorrectly associated with a different cache line. This false
1018 hazard might then cause a processor deadlock. The workaround enables
1019 the L1 caching of the NEON accesses and disables the PLD instruction
1020 in the ACTLR register. Note that setting specific bits in the ACTLR
1021 register may not be available in non-secure mode.
1023 config ARM_ERRATA_460075
1024 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1026 depends on !ARCH_MULTIPLATFORM
1028 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1029 erratum. Any asynchronous access to the L2 cache may encounter a
1030 situation in which recent store transactions to the L2 cache are lost
1031 and overwritten with stale memory contents from external memory. The
1032 workaround disables the write-allocate mode for the L2 cache via the
1033 ACTLR register. Note that setting specific bits in the ACTLR register
1034 may not be available in non-secure mode.
1036 config ARM_ERRATA_742230
1037 bool "ARM errata: DMB operation may be faulty"
1038 depends on CPU_V7 && SMP
1039 depends on !ARCH_MULTIPLATFORM
1041 This option enables the workaround for the 742230 Cortex-A9
1042 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1043 between two write operations may not ensure the correct visibility
1044 ordering of the two writes. This workaround sets a specific bit in
1045 the diagnostic register of the Cortex-A9 which causes the DMB
1046 instruction to behave as a DSB, ensuring the correct behaviour of
1049 config ARM_ERRATA_742231
1050 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1051 depends on CPU_V7 && SMP
1052 depends on !ARCH_MULTIPLATFORM
1054 This option enables the workaround for the 742231 Cortex-A9
1055 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1056 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1057 accessing some data located in the same cache line, may get corrupted
1058 data due to bad handling of the address hazard when the line gets
1059 replaced from one of the CPUs at the same time as another CPU is
1060 accessing it. This workaround sets specific bits in the diagnostic
1061 register of the Cortex-A9 which reduces the linefill issuing
1062 capabilities of the processor.
1064 config ARM_ERRATA_643719
1065 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1066 depends on CPU_V7 && SMP
1069 This option enables the workaround for the 643719 Cortex-A9 (prior to
1070 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1071 register returns zero when it should return one. The workaround
1072 corrects this value, ensuring cache maintenance operations which use
1073 it behave as intended and avoiding data corruption.
1075 config ARM_ERRATA_720789
1076 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1079 This option enables the workaround for the 720789 Cortex-A9 (prior to
1080 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1081 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1082 As a consequence of this erratum, some TLB entries which should be
1083 invalidated are not, resulting in an incoherency in the system page
1084 tables. The workaround changes the TLB flushing routines to invalidate
1085 entries regardless of the ASID.
1087 config ARM_ERRATA_743622
1088 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1090 depends on !ARCH_MULTIPLATFORM
1092 This option enables the workaround for the 743622 Cortex-A9
1093 (r2p*) erratum. Under very rare conditions, a faulty
1094 optimisation in the Cortex-A9 Store Buffer may lead to data
1095 corruption. This workaround sets a specific bit in the diagnostic
1096 register of the Cortex-A9 which disables the Store Buffer
1097 optimisation, preventing the defect from occurring. This has no
1098 visible impact on the overall performance or power consumption of the
1101 config ARM_ERRATA_751472
1102 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1104 depends on !ARCH_MULTIPLATFORM
1106 This option enables the workaround for the 751472 Cortex-A9 (prior
1107 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1108 completion of a following broadcasted operation if the second
1109 operation is received by a CPU before the ICIALLUIS has completed,
1110 potentially leading to corrupted entries in the cache or TLB.
1112 config ARM_ERRATA_754322
1113 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1116 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1117 r3p*) erratum. A speculative memory access may cause a page table walk
1118 which starts prior to an ASID switch but completes afterwards. This
1119 can populate the micro-TLB with a stale entry which may be hit with
1120 the new ASID. This workaround places two dsb instructions in the mm
1121 switching code so that no page table walks can cross the ASID switch.
1123 config ARM_ERRATA_754327
1124 bool "ARM errata: no automatic Store Buffer drain"
1125 depends on CPU_V7 && SMP
1127 This option enables the workaround for the 754327 Cortex-A9 (prior to
1128 r2p0) erratum. The Store Buffer does not have any automatic draining
1129 mechanism and therefore a livelock may occur if an external agent
1130 continuously polls a memory location waiting to observe an update.
1131 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1132 written polling loops from denying visibility of updates to memory.
1134 config ARM_ERRATA_364296
1135 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1138 This options enables the workaround for the 364296 ARM1136
1139 r0p2 erratum (possible cache data corruption with
1140 hit-under-miss enabled). It sets the undocumented bit 31 in
1141 the auxiliary control register and the FI bit in the control
1142 register, thus disabling hit-under-miss without putting the
1143 processor into full low interrupt latency mode. ARM11MPCore
1146 config ARM_ERRATA_764369
1147 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1148 depends on CPU_V7 && SMP
1150 This option enables the workaround for erratum 764369
1151 affecting Cortex-A9 MPCore with two or more processors (all
1152 current revisions). Under certain timing circumstances, a data
1153 cache line maintenance operation by MVA targeting an Inner
1154 Shareable memory region may fail to proceed up to either the
1155 Point of Coherency or to the Point of Unification of the
1156 system. This workaround adds a DSB instruction before the
1157 relevant cache maintenance functions and sets a specific bit
1158 in the diagnostic control register of the SCU.
1160 config ARM_ERRATA_775420
1161 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1164 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1165 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1166 operation aborts with MMU exception, it might cause the processor
1167 to deadlock. This workaround puts DSB before executing ISB if
1168 an abort may occur on cache maintenance.
1170 config ARM_ERRATA_798181
1171 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1172 depends on CPU_V7 && SMP
1174 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1175 adequately shooting down all use of the old entries. This
1176 option enables the Linux kernel workaround for this erratum
1177 which sends an IPI to the CPUs that are running the same ASID
1178 as the one being invalidated.
1180 config ARM_ERRATA_773022
1181 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1184 This option enables the workaround for the 773022 Cortex-A15
1185 (up to r0p4) erratum. In certain rare sequences of code, the
1186 loop buffer may deliver incorrect instructions. This
1187 workaround disables the loop buffer to avoid the erratum.
1189 config ARM_ERRATA_818325_852422
1190 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1193 This option enables the workaround for:
1194 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1195 instruction might deadlock. Fixed in r0p1.
1196 - Cortex-A12 852422: Execution of a sequence of instructions might
1197 lead to either a data corruption or a CPU deadlock. Not fixed in
1198 any Cortex-A12 cores yet.
1199 This workaround for all both errata involves setting bit[12] of the
1200 Feature Register. This bit disables an optimisation applied to a
1201 sequence of 2 instructions that use opposing condition codes.
1203 config ARM_ERRATA_821420
1204 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1207 This option enables the workaround for the 821420 Cortex-A12
1208 (all revs) erratum. In very rare timing conditions, a sequence
1209 of VMOV to Core registers instructions, for which the second
1210 one is in the shadow of a branch or abort, can lead to a
1211 deadlock when the VMOV instructions are issued out-of-order.
1213 config ARM_ERRATA_852423
1214 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1217 This option enables the workaround for:
1218 - Cortex-A17 852423: Execution of a sequence of instructions might
1219 lead to either a data corruption or a CPU deadlock. Not fixed in
1220 any Cortex-A17 cores yet.
1221 This is identical to Cortex-A12 erratum 852422. It is a separate
1222 config option from the A12 erratum due to the way errata are checked
1227 source "arch/arm/common/Kconfig"
1234 Find out whether you have ISA slots on your motherboard. ISA is the
1235 name of a bus system, i.e. the way the CPU talks to the other stuff
1236 inside your box. Other bus systems are PCI, EISA, MicroChannel
1237 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1238 newer boards don't support it. If you have ISA, say Y, otherwise N.
1240 # Select ISA DMA controller support
1245 # Select ISA DMA interface
1250 bool "PCI support" if MIGHT_HAVE_PCI
1252 Find out whether you have a PCI motherboard. PCI is the name of a
1253 bus system, i.e. the way the CPU talks to the other stuff inside
1254 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1255 VESA. If you have PCI, say Y, otherwise N.
1261 config PCI_DOMAINS_GENERIC
1262 def_bool PCI_DOMAINS
1264 config PCI_NANOENGINE
1265 bool "BSE nanoEngine PCI support"
1266 depends on SA1100_NANOENGINE
1268 Enable PCI on the BSE nanoEngine board.
1273 config PCI_HOST_ITE8152
1275 depends on PCI && MACH_ARMCORE
1279 source "drivers/pci/Kconfig"
1281 source "drivers/pcmcia/Kconfig"
1285 menu "Kernel Features"
1290 This option should be selected by machines which have an SMP-
1293 The only effect of this option is to make the SMP-related
1294 options available to the user for configuration.
1297 bool "Symmetric Multi-Processing"
1298 depends on CPU_V6K || CPU_V7
1299 depends on GENERIC_CLOCKEVENTS
1301 depends on MMU || ARM_MPU
1304 This enables support for systems with more than one CPU. If you have
1305 a system with only one CPU, say N. If you have a system with more
1306 than one CPU, say Y.
1308 If you say N here, the kernel will run on uni- and multiprocessor
1309 machines, but will use only one CPU of a multiprocessor machine. If
1310 you say Y here, the kernel will run on many, but not all,
1311 uniprocessor machines. On a uniprocessor machine, the kernel
1312 will run faster if you say N here.
1314 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1315 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1316 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1318 If you don't know what to do here, say N.
1321 bool "Allow booting SMP kernel on uniprocessor systems"
1322 depends on SMP && !XIP_KERNEL && MMU
1325 SMP kernels contain instructions which fail on non-SMP processors.
1326 Enabling this option allows the kernel to modify itself to make
1327 these instructions safe. Disabling it allows about 1K of space
1330 If you don't know what to do here, say Y.
1332 config ARM_CPU_TOPOLOGY
1333 bool "Support cpu topology definition"
1334 depends on SMP && CPU_V7
1337 Support ARM cpu topology definition. The MPIDR register defines
1338 affinity between processors which is then used to describe the cpu
1339 topology of an ARM System.
1342 bool "Multi-core scheduler support"
1343 depends on ARM_CPU_TOPOLOGY
1345 Multi-core scheduler support improves the CPU scheduler's decision
1346 making when dealing with multi-core CPU chips at a cost of slightly
1347 increased overhead in some places. If unsure say N here.
1350 bool "SMT scheduler support"
1351 depends on ARM_CPU_TOPOLOGY
1353 Improves the CPU scheduler's decision making when dealing with
1354 MultiThreading at a cost of slightly increased overhead in some
1355 places. If unsure say N here.
1360 This option enables support for the ARM system coherency unit
1362 config HAVE_ARM_ARCH_TIMER
1363 bool "Architected timer support"
1365 select ARM_ARCH_TIMER
1366 select GENERIC_CLOCKEVENTS
1368 This option enables support for the ARM architected timer
1372 select CLKSRC_OF if OF
1374 This options enables support for the ARM timer and watchdog unit
1377 bool "Multi-Cluster Power Management"
1378 depends on CPU_V7 && SMP
1380 This option provides the common power management infrastructure
1381 for (multi-)cluster based systems, such as big.LITTLE based
1384 config MCPM_QUAD_CLUSTER
1388 To avoid wasting resources unnecessarily, MCPM only supports up
1389 to 2 clusters by default.
1390 Platforms with 3 or 4 clusters that use MCPM must select this
1391 option to allow the additional clusters to be managed.
1394 bool "big.LITTLE support (Experimental)"
1395 depends on CPU_V7 && SMP
1398 This option enables support selections for the big.LITTLE
1399 system architecture.
1402 bool "big.LITTLE switcher support"
1403 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1406 The big.LITTLE "switcher" provides the core functionality to
1407 transparently handle transition between a cluster of A15's
1408 and a cluster of A7's in a big.LITTLE system.
1410 config BL_SWITCHER_DUMMY_IF
1411 tristate "Simple big.LITTLE switcher user interface"
1412 depends on BL_SWITCHER && DEBUG_KERNEL
1414 This is a simple and dummy char dev interface to control
1415 the big.LITTLE switcher core code. It is meant for
1416 debugging purposes only.
1419 prompt "Memory split"
1423 Select the desired split between kernel and user memory.
1425 If you are not absolutely sure what you are doing, leave this
1429 bool "3G/1G user/kernel split"
1430 config VMSPLIT_3G_OPT
1431 bool "3G/1G user/kernel split (for full 1G low memory)"
1433 bool "2G/2G user/kernel split"
1435 bool "1G/3G user/kernel split"
1440 default PHYS_OFFSET if !MMU
1441 default 0x40000000 if VMSPLIT_1G
1442 default 0x80000000 if VMSPLIT_2G
1443 default 0xB0000000 if VMSPLIT_3G_OPT
1447 int "Maximum number of CPUs (2-32)"
1453 bool "Support for hot-pluggable CPUs"
1456 Say Y here to experiment with turning CPUs off and on. CPUs
1457 can be controlled through /sys/devices/system/cpu.
1460 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1461 depends on HAVE_ARM_SMCCC
1464 Say Y here if you want Linux to communicate with system firmware
1465 implementing the PSCI specification for CPU-centric power
1466 management operations described in ARM document number ARM DEN
1467 0022A ("Power State Coordination Interface System Software on
1470 # The GPIO number here must be sorted by descending number. In case of
1471 # a multiplatform kernel, we just want the highest value required by the
1472 # selected platforms.
1475 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1477 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1478 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1479 default 416 if ARCH_SUNXI
1480 default 392 if ARCH_U8500
1481 default 352 if ARCH_VT8500
1482 default 288 if ARCH_ROCKCHIP
1483 default 264 if MACH_H4700
1486 Maximum number of GPIOs in the system.
1488 If unsure, leave the default value.
1490 source kernel/Kconfig.preempt
1494 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1495 ARCH_S5PV210 || ARCH_EXYNOS4
1496 default 128 if SOC_AT91RM9200
1500 depends on HZ_FIXED = 0
1501 prompt "Timer frequency"
1525 default HZ_FIXED if HZ_FIXED != 0
1526 default 100 if HZ_100
1527 default 200 if HZ_200
1528 default 250 if HZ_250
1529 default 300 if HZ_300
1530 default 500 if HZ_500
1534 def_bool HIGH_RES_TIMERS
1536 config THUMB2_KERNEL
1537 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1538 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1539 default y if CPU_THUMBONLY
1541 select ARM_ASM_UNIFIED
1544 By enabling this option, the kernel will be compiled in
1545 Thumb-2 mode. A compiler/assembler that understand the unified
1546 ARM-Thumb syntax is needed.
1550 config THUMB2_AVOID_R_ARM_THM_JUMP11
1551 bool "Work around buggy Thumb-2 short branch relocations in gas"
1552 depends on THUMB2_KERNEL && MODULES
1555 Various binutils versions can resolve Thumb-2 branches to
1556 locally-defined, preemptible global symbols as short-range "b.n"
1557 branch instructions.
1559 This is a problem, because there's no guarantee the final
1560 destination of the symbol, or any candidate locations for a
1561 trampoline, are within range of the branch. For this reason, the
1562 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1563 relocation in modules at all, and it makes little sense to add
1566 The symptom is that the kernel fails with an "unsupported
1567 relocation" error when loading some modules.
1569 Until fixed tools are available, passing
1570 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1571 code which hits this problem, at the cost of a bit of extra runtime
1572 stack usage in some cases.
1574 The problem is described in more detail at:
1575 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1577 Only Thumb-2 kernels are affected.
1579 Unless you are sure your tools don't have this problem, say Y.
1581 config ARM_ASM_UNIFIED
1584 config ARM_PATCH_IDIV
1585 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1586 depends on CPU_32v7 && !XIP_KERNEL
1589 The ARM compiler inserts calls to __aeabi_idiv() and
1590 __aeabi_uidiv() when it needs to perform division on signed
1591 and unsigned integers. Some v7 CPUs have support for the sdiv
1592 and udiv instructions that can be used to implement those
1595 Enabling this option allows the kernel to modify itself to
1596 replace the first two instructions of these library functions
1597 with the sdiv or udiv plus "bx lr" instructions when the CPU
1598 it is running on supports them. Typically this will be faster
1599 and less power intensive than running the original library
1600 code to do integer division.
1603 bool "Use the ARM EABI to compile the kernel"
1605 This option allows for the kernel to be compiled using the latest
1606 ARM ABI (aka EABI). This is only useful if you are using a user
1607 space environment that is also compiled with EABI.
1609 Since there are major incompatibilities between the legacy ABI and
1610 EABI, especially with regard to structure member alignment, this
1611 option also changes the kernel syscall calling convention to
1612 disambiguate both ABIs and allow for backward compatibility support
1613 (selected with CONFIG_OABI_COMPAT).
1615 To use this you need GCC version 4.0.0 or later.
1618 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1619 depends on AEABI && !THUMB2_KERNEL
1621 This option preserves the old syscall interface along with the
1622 new (ARM EABI) one. It also provides a compatibility layer to
1623 intercept syscalls that have structure arguments which layout
1624 in memory differs between the legacy ABI and the new ARM EABI
1625 (only for non "thumb" binaries). This option adds a tiny
1626 overhead to all syscalls and produces a slightly larger kernel.
1628 The seccomp filter system will not be available when this is
1629 selected, since there is no way yet to sensibly distinguish
1630 between calling conventions during filtering.
1632 If you know you'll be using only pure EABI user space then you
1633 can say N here. If this option is not selected and you attempt
1634 to execute a legacy ABI binary then the result will be
1635 UNPREDICTABLE (in fact it can be predicted that it won't work
1636 at all). If in doubt say N.
1638 config ARCH_HAS_HOLES_MEMORYMODEL
1641 config ARCH_SPARSEMEM_ENABLE
1644 config ARCH_SPARSEMEM_DEFAULT
1645 def_bool ARCH_SPARSEMEM_ENABLE
1647 config ARCH_SELECT_MEMORY_MODEL
1648 def_bool ARCH_SPARSEMEM_ENABLE
1650 config HAVE_ARCH_PFN_VALID
1651 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1653 config HAVE_GENERIC_RCU_GUP
1658 bool "High Memory Support"
1661 The address space of ARM processors is only 4 Gigabytes large
1662 and it has to accommodate user address space, kernel address
1663 space as well as some memory mapped IO. That means that, if you
1664 have a large amount of physical memory and/or IO, not all of the
1665 memory can be "permanently mapped" by the kernel. The physical
1666 memory that is not permanently mapped is called "high memory".
1668 Depending on the selected kernel/user memory split, minimum
1669 vmalloc space and actual amount of RAM, you may not need this
1670 option which should result in a slightly faster kernel.
1675 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1679 The VM uses one page of physical memory for each page table.
1680 For systems with a lot of processes, this can use a lot of
1681 precious low memory, eventually leading to low memory being
1682 consumed by page tables. Setting this option will allow
1683 user-space 2nd level page tables to reside in high memory.
1685 config CPU_SW_DOMAIN_PAN
1686 bool "Enable use of CPU domains to implement privileged no-access"
1687 depends on MMU && !ARM_LPAE
1690 Increase kernel security by ensuring that normal kernel accesses
1691 are unable to access userspace addresses. This can help prevent
1692 use-after-free bugs becoming an exploitable privilege escalation
1693 by ensuring that magic values (such as LIST_POISON) will always
1694 fault when dereferenced.
1696 CPUs with low-vector mappings use a best-efforts implementation.
1697 Their lower 1MB needs to remain accessible for the vectors, but
1698 the remainder of userspace will become appropriately inaccessible.
1700 config HW_PERF_EVENTS
1704 config SYS_SUPPORTS_HUGETLBFS
1708 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1712 config ARCH_WANT_GENERAL_HUGETLB
1715 config ARM_MODULE_PLTS
1716 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1719 Allocate PLTs when loading modules so that jumps and calls whose
1720 targets are too far away for their relative offsets to be encoded
1721 in the instructions themselves can be bounced via veneers in the
1722 module's PLT. This allows modules to be allocated in the generic
1723 vmalloc area after the dedicated module memory area has been
1724 exhausted. The modules will use slightly more memory, but after
1725 rounding up to page size, the actual memory footprint is usually
1728 Say y if you are getting out of memory errors while loading modules
1732 config FORCE_MAX_ZONEORDER
1733 int "Maximum zone order"
1734 default "12" if SOC_AM33XX
1735 default "9" if SA1111 || ARCH_EFM32
1738 The kernel memory allocator divides physically contiguous memory
1739 blocks into "zones", where each zone is a power of two number of
1740 pages. This option selects the largest power of two that the kernel
1741 keeps in the memory allocator. If you need to allocate very large
1742 blocks of physically contiguous memory, then you may need to
1743 increase this value.
1745 This config option is actually maximum order plus one. For example,
1746 a value of 11 means that the largest free memory block is 2^10 pages.
1748 config ALIGNMENT_TRAP
1750 depends on CPU_CP15_MMU
1751 default y if !ARCH_EBSA110
1752 select HAVE_PROC_CPU if PROC_FS
1754 ARM processors cannot fetch/store information which is not
1755 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1756 address divisible by 4. On 32-bit ARM processors, these non-aligned
1757 fetch/store instructions will be emulated in software if you say
1758 here, which has a severe performance impact. This is necessary for
1759 correct operation of some network protocols. With an IP-only
1760 configuration it is safe to say N, otherwise say Y.
1762 config UACCESS_WITH_MEMCPY
1763 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1765 default y if CPU_FEROCEON
1767 Implement faster copy_to_user and clear_user methods for CPU
1768 cores where a 8-word STM instruction give significantly higher
1769 memory write throughput than a sequence of individual 32bit stores.
1771 A possible side effect is a slight increase in scheduling latency
1772 between threads sharing the same address space if they invoke
1773 such copy operations with large buffers.
1775 However, if the CPU data cache is using a write-allocate mode,
1776 this option is unlikely to provide any performance gain.
1780 prompt "Enable seccomp to safely compute untrusted bytecode"
1782 This kernel feature is useful for number crunching applications
1783 that may need to compute untrusted bytecode during their
1784 execution. By using pipes or other transports made available to
1785 the process as file descriptors supporting the read/write
1786 syscalls, it's possible to isolate those applications in
1787 their own address space using seccomp. Once seccomp is
1788 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1789 and the task is only allowed to execute a few safe syscalls
1790 defined by each seccomp mode.
1799 bool "Enable paravirtualization code"
1801 This changes the kernel so it can modify itself when it is run
1802 under a hypervisor, potentially improving performance significantly
1803 over full virtualization.
1805 config PARAVIRT_TIME_ACCOUNTING
1806 bool "Paravirtual steal time accounting"
1810 Select this option to enable fine granularity task steal time
1811 accounting. Time spent executing other tasks in parallel with
1812 the current vCPU is discounted from the vCPU power. To account for
1813 that, there can be a small performance impact.
1815 If in doubt, say N here.
1822 bool "Xen guest support on ARM"
1823 depends on ARM && AEABI && OF
1824 depends on CPU_V7 && !CPU_V6
1825 depends on !GENERIC_ATOMIC64
1827 select ARCH_DMA_ADDR_T_64BIT
1832 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1839 bool "Flattened Device Tree support"
1843 Include support for flattened device tree machine descriptions.
1846 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1849 This is the traditional way of passing data to the kernel at boot
1850 time. If you are solely relying on the flattened device tree (or
1851 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1852 to remove ATAGS support from your kernel binary. If unsure,
1855 config DEPRECATED_PARAM_STRUCT
1856 bool "Provide old way to pass kernel parameters"
1859 This was deprecated in 2001 and announced to live on for 5 years.
1860 Some old boot loaders still use this way.
1862 # Compressed boot loader in ROM. Yes, we really want to ask about
1863 # TEXT and BSS so we preserve their values in the config files.
1864 config ZBOOT_ROM_TEXT
1865 hex "Compressed ROM boot loader base address"
1868 The physical address at which the ROM-able zImage is to be
1869 placed in the target. Platforms which normally make use of
1870 ROM-able zImage formats normally set this to a suitable
1871 value in their defconfig file.
1873 If ZBOOT_ROM is not enabled, this has no effect.
1875 config ZBOOT_ROM_BSS
1876 hex "Compressed ROM boot loader BSS address"
1879 The base address of an area of read/write memory in the target
1880 for the ROM-able zImage which must be available while the
1881 decompressor is running. It must be large enough to hold the
1882 entire decompressed kernel plus an additional 128 KiB.
1883 Platforms which normally make use of ROM-able zImage formats
1884 normally set this to a suitable value in their defconfig file.
1886 If ZBOOT_ROM is not enabled, this has no effect.
1889 bool "Compressed boot loader in ROM/flash"
1890 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1891 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1893 Say Y here if you intend to execute your compressed kernel image
1894 (zImage) directly from ROM or flash. If unsure, say N.
1896 config ARM_APPENDED_DTB
1897 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1900 With this option, the boot code will look for a device tree binary
1901 (DTB) appended to zImage
1902 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1904 This is meant as a backward compatibility convenience for those
1905 systems with a bootloader that can't be upgraded to accommodate
1906 the documented boot protocol using a device tree.
1908 Beware that there is very little in terms of protection against
1909 this option being confused by leftover garbage in memory that might
1910 look like a DTB header after a reboot if no actual DTB is appended
1911 to zImage. Do not leave this option active in a production kernel
1912 if you don't intend to always append a DTB. Proper passing of the
1913 location into r2 of a bootloader provided DTB is always preferable
1916 config ARM_ATAG_DTB_COMPAT
1917 bool "Supplement the appended DTB with traditional ATAG information"
1918 depends on ARM_APPENDED_DTB
1920 Some old bootloaders can't be updated to a DTB capable one, yet
1921 they provide ATAGs with memory configuration, the ramdisk address,
1922 the kernel cmdline string, etc. Such information is dynamically
1923 provided by the bootloader and can't always be stored in a static
1924 DTB. To allow a device tree enabled kernel to be used with such
1925 bootloaders, this option allows zImage to extract the information
1926 from the ATAG list and store it at run time into the appended DTB.
1929 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1930 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1932 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1933 bool "Use bootloader kernel arguments if available"
1935 Uses the command-line options passed by the boot loader instead of
1936 the device tree bootargs property. If the boot loader doesn't provide
1937 any, the device tree bootargs property will be used.
1939 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1940 bool "Extend with bootloader kernel arguments"
1942 The command-line arguments provided by the boot loader will be
1943 appended to the the device tree bootargs property.
1948 string "Default kernel command string"
1951 On some architectures (EBSA110 and CATS), there is currently no way
1952 for the boot loader to pass arguments to the kernel. For these
1953 architectures, you should supply some command-line options at build
1954 time by entering them here. As a minimum, you should specify the
1955 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1958 prompt "Kernel command line type" if CMDLINE != ""
1959 default CMDLINE_FROM_BOOTLOADER
1962 config CMDLINE_FROM_BOOTLOADER
1963 bool "Use bootloader kernel arguments if available"
1965 Uses the command-line options passed by the boot loader. If
1966 the boot loader doesn't provide any, the default kernel command
1967 string provided in CMDLINE will be used.
1969 config CMDLINE_EXTEND
1970 bool "Extend bootloader kernel arguments"
1972 The command-line arguments provided by the boot loader will be
1973 appended to the default kernel command string.
1975 config CMDLINE_FORCE
1976 bool "Always use the default kernel command string"
1978 Always use the default kernel command string, even if the boot
1979 loader passes other arguments to the kernel.
1980 This is useful if you cannot or don't want to change the
1981 command-line options your boot loader passes to the kernel.
1985 bool "Kernel Execute-In-Place from ROM"
1986 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1988 Execute-In-Place allows the kernel to run from non-volatile storage
1989 directly addressable by the CPU, such as NOR flash. This saves RAM
1990 space since the text section of the kernel is not loaded from flash
1991 to RAM. Read-write sections, such as the data section and stack,
1992 are still copied to RAM. The XIP kernel is not compressed since
1993 it has to run directly from flash, so it will take more space to
1994 store it. The flash address used to link the kernel object files,
1995 and for storing it, is configuration dependent. Therefore, if you
1996 say Y here, you must know the proper physical address where to
1997 store the kernel image depending on your own flash memory usage.
1999 Also note that the make target becomes "make xipImage" rather than
2000 "make zImage" or "make Image". The final kernel binary to put in
2001 ROM memory will be arch/arm/boot/xipImage.
2005 config XIP_PHYS_ADDR
2006 hex "XIP Kernel Physical Location"
2007 depends on XIP_KERNEL
2008 default "0x00080000"
2010 This is the physical address in your flash memory the kernel will
2011 be linked for and stored to. This address is dependent on your
2015 bool "Kexec system call (EXPERIMENTAL)"
2016 depends on (!SMP || PM_SLEEP_SMP)
2020 kexec is a system call that implements the ability to shutdown your
2021 current kernel, and to start another kernel. It is like a reboot
2022 but it is independent of the system firmware. And like a reboot
2023 you can start any kernel with it, not just Linux.
2025 It is an ongoing process to be certain the hardware in a machine
2026 is properly shutdown, so do not be surprised if this code does not
2027 initially work for you.
2030 bool "Export atags in procfs"
2031 depends on ATAGS && KEXEC
2034 Should the atags used to boot the kernel be exported in an "atags"
2035 file in procfs. Useful with kexec.
2038 bool "Build kdump crash kernel (EXPERIMENTAL)"
2040 Generate crash dump after being started by kexec. This should
2041 be normally only set in special crash dump kernels which are
2042 loaded in the main kernel with kexec-tools into a specially
2043 reserved region and then later executed after a crash by
2044 kdump/kexec. The crash dump kernel must be compiled to a
2045 memory address not used by the main kernel
2047 For more details see Documentation/kdump/kdump.txt
2049 config AUTO_ZRELADDR
2050 bool "Auto calculation of the decompressed kernel image address"
2052 ZRELADDR is the physical address where the decompressed kernel
2053 image will be placed. If AUTO_ZRELADDR is selected, the address
2054 will be determined at run-time by masking the current IP with
2055 0xf8000000. This assumes the zImage being placed in the first 128MB
2056 from start of memory.
2062 bool "UEFI runtime support"
2063 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2065 select EFI_PARAMS_FROM_FDT
2068 select EFI_RUNTIME_WRAPPERS
2070 This option provides support for runtime services provided
2071 by UEFI firmware (such as non-volatile variables, realtime
2072 clock, and platform reset). A UEFI stub is also provided to
2073 allow the kernel to be booted as an EFI application. This
2074 is only useful for kernels that may run on systems that have
2079 menu "CPU Power Management"
2081 source "drivers/cpufreq/Kconfig"
2083 source "drivers/cpuidle/Kconfig"
2087 menu "Floating point emulation"
2089 comment "At least one emulation must be selected"
2092 bool "NWFPE math emulation"
2093 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2095 Say Y to include the NWFPE floating point emulator in the kernel.
2096 This is necessary to run most binaries. Linux does not currently
2097 support floating point hardware so you need to say Y here even if
2098 your machine has an FPA or floating point co-processor podule.
2100 You may say N here if you are going to load the Acorn FPEmulator
2101 early in the bootup.
2104 bool "Support extended precision"
2105 depends on FPE_NWFPE
2107 Say Y to include 80-bit support in the kernel floating-point
2108 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2109 Note that gcc does not generate 80-bit operations by default,
2110 so in most cases this option only enlarges the size of the
2111 floating point emulator without any good reason.
2113 You almost surely want to say N here.
2116 bool "FastFPE math emulation (EXPERIMENTAL)"
2117 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2119 Say Y here to include the FAST floating point emulator in the kernel.
2120 This is an experimental much faster emulator which now also has full
2121 precision for the mantissa. It does not support any exceptions.
2122 It is very simple, and approximately 3-6 times faster than NWFPE.
2124 It should be sufficient for most programs. It may be not suitable
2125 for scientific calculations, but you have to check this for yourself.
2126 If you do not feel you need a faster FP emulation you should better
2130 bool "VFP-format floating point maths"
2131 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2133 Say Y to include VFP support code in the kernel. This is needed
2134 if your hardware includes a VFP unit.
2136 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2137 release notes and additional status information.
2139 Say N if your target does not have VFP hardware.
2147 bool "Advanced SIMD (NEON) Extension support"
2148 depends on VFPv3 && CPU_V7
2150 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2153 config KERNEL_MODE_NEON
2154 bool "Support for NEON in kernel mode"
2155 depends on NEON && AEABI
2157 Say Y to include support for NEON in kernel mode.
2161 menu "Userspace binary formats"
2163 source "fs/Kconfig.binfmt"
2167 menu "Power management options"
2169 source "kernel/power/Kconfig"
2171 config ARCH_SUSPEND_POSSIBLE
2172 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2173 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2176 config ARM_CPU_SUSPEND
2177 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2178 depends on ARCH_SUSPEND_POSSIBLE
2180 config ARCH_HIBERNATION_POSSIBLE
2183 default y if ARCH_SUSPEND_POSSIBLE
2187 source "net/Kconfig"
2189 source "drivers/Kconfig"
2191 source "drivers/firmware/Kconfig"
2195 source "arch/arm/Kconfig.debug"
2197 source "security/Kconfig"
2199 source "crypto/Kconfig"
2201 source "arch/arm/crypto/Kconfig"
2204 source "lib/Kconfig"
2206 source "arch/arm/kvm/Kconfig"