Documentation/filesystems/00-INDEX: updates
[deliverable/linux.git] / arch / arm / Kconfig
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_KGDB
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
30 select HAVE_BPF_JIT
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_ATTRS
37 select HAVE_DMA_CONTIGUOUS if MMU
38 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
39 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
40 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
41 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
42 select HAVE_GENERIC_DMA_COHERENT
43 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
44 select HAVE_IDE if PCI || ISA || PCMCIA
45 select HAVE_IRQ_TIME_ACCOUNTING
46 select HAVE_KERNEL_GZIP
47 select HAVE_KERNEL_LZ4
48 select HAVE_KERNEL_LZMA
49 select HAVE_KERNEL_LZO
50 select HAVE_KERNEL_XZ
51 select HAVE_KPROBES if !XIP_KERNEL
52 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MEMBLOCK
54 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
55 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
56 select HAVE_PERF_EVENTS
57 select HAVE_PERF_REGS
58 select HAVE_PERF_USER_STACK_DUMP
59 select HAVE_REGS_AND_STACK_ACCESS_API
60 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_UID16
62 select HAVE_VIRT_CPU_ACCOUNTING_GEN
63 select IRQ_FORCED_THREADING
64 select KTIME_SCALAR
65 select MODULES_USE_ELF_REL
66 select OLD_SIGACTION
67 select OLD_SIGSUSPEND3
68 select PERF_USE_VMALLOC
69 select RTC_LIB
70 select SYS_SUPPORTS_APM_EMULATION
71 # Above selects are sorted alphabetically; please add new ones
72 # according to that. Thanks.
73 help
74 The ARM series is a line of low-power-consumption RISC chip designs
75 licensed by ARM Ltd and targeted at embedded applications and
76 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
77 manufactured, but legacy ARM-based PC hardware remains popular in
78 Europe. There is an ARM Linux project with a web page at
79 <http://www.arm.linux.org.uk/>.
80
81 config ARM_HAS_SG_CHAIN
82 bool
83
84 config NEED_SG_DMA_LENGTH
85 bool
86
87 config ARM_DMA_USE_IOMMU
88 bool
89 select ARM_HAS_SG_CHAIN
90 select NEED_SG_DMA_LENGTH
91
92 if ARM_DMA_USE_IOMMU
93
94 config ARM_DMA_IOMMU_ALIGNMENT
95 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
96 range 4 9
97 default 8
98 help
99 DMA mapping framework by default aligns all buffers to the smallest
100 PAGE_SIZE order which is greater than or equal to the requested buffer
101 size. This works well for buffers up to a few hundreds kilobytes, but
102 for larger buffers it just a waste of address space. Drivers which has
103 relatively small addressing window (like 64Mib) might run out of
104 virtual space with just a few allocations.
105
106 With this parameter you can specify the maximum PAGE_SIZE order for
107 DMA IOMMU buffers. Larger buffers will be aligned only to this
108 specified order. The order is expressed as a power of two multiplied
109 by the PAGE_SIZE.
110
111 endif
112
113 config HAVE_PWM
114 bool
115
116 config MIGHT_HAVE_PCI
117 bool
118
119 config SYS_SUPPORTS_APM_EMULATION
120 bool
121
122 config HAVE_TCM
123 bool
124 select GENERIC_ALLOCATOR
125
126 config HAVE_PROC_CPU
127 bool
128
129 config NO_IOPORT
130 bool
131
132 config EISA
133 bool
134 ---help---
135 The Extended Industry Standard Architecture (EISA) bus was
136 developed as an open alternative to the IBM MicroChannel bus.
137
138 The EISA bus provided some of the features of the IBM MicroChannel
139 bus while maintaining backward compatibility with cards made for
140 the older ISA bus. The EISA bus saw limited use between 1988 and
141 1995 when it was made obsolete by the PCI bus.
142
143 Say Y here if you are building a kernel for an EISA-based machine.
144
145 Otherwise, say N.
146
147 config SBUS
148 bool
149
150 config STACKTRACE_SUPPORT
151 bool
152 default y
153
154 config HAVE_LATENCYTOP_SUPPORT
155 bool
156 depends on !SMP
157 default y
158
159 config LOCKDEP_SUPPORT
160 bool
161 default y
162
163 config TRACE_IRQFLAGS_SUPPORT
164 bool
165 default y
166
167 config RWSEM_GENERIC_SPINLOCK
168 bool
169 default y
170
171 config RWSEM_XCHGADD_ALGORITHM
172 bool
173
174 config ARCH_HAS_ILOG2_U32
175 bool
176
177 config ARCH_HAS_ILOG2_U64
178 bool
179
180 config ARCH_HAS_CPUFREQ
181 bool
182 help
183 Internal node to signify that the ARCH has CPUFREQ support
184 and that the relevant menu configurations are displayed for
185 it.
186
187 config ARCH_HAS_BANDGAP
188 bool
189
190 config GENERIC_HWEIGHT
191 bool
192 default y
193
194 config GENERIC_CALIBRATE_DELAY
195 bool
196 default y
197
198 config ARCH_MAY_HAVE_PC_FDC
199 bool
200
201 config ZONE_DMA
202 bool
203
204 config NEED_DMA_MAP_STATE
205 def_bool y
206
207 config ARCH_HAS_DMA_SET_COHERENT_MASK
208 bool
209
210 config GENERIC_ISA_DMA
211 bool
212
213 config FIQ
214 bool
215
216 config NEED_RET_TO_USER
217 bool
218
219 config ARCH_MTD_XIP
220 bool
221
222 config VECTORS_BASE
223 hex
224 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
225 default DRAM_BASE if REMAP_VECTORS_TO_RAM
226 default 0x00000000
227 help
228 The base address of exception vectors. This must be two pages
229 in size.
230
231 config ARM_PATCH_PHYS_VIRT
232 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 default y
234 depends on !XIP_KERNEL && MMU
235 depends on !ARCH_REALVIEW || !SPARSEMEM
236 help
237 Patch phys-to-virt and virt-to-phys translation functions at
238 boot and module load time according to the position of the
239 kernel in system memory.
240
241 This can only be used with non-XIP MMU kernels where the base
242 of physical memory is at a 16MB boundary.
243
244 Only disable this option if you know that you do not require
245 this feature (eg, building a kernel for a single machine) and
246 you need to shrink the kernel to the minimal size.
247
248 config NEED_MACH_GPIO_H
249 bool
250 help
251 Select this when mach/gpio.h is required to provide special
252 definitions for this platform. The need for mach/gpio.h should
253 be avoided when possible.
254
255 config NEED_MACH_IO_H
256 bool
257 help
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
261
262 config NEED_MACH_MEMORY_H
263 bool
264 help
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
268
269 config PHYS_OFFSET
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
272 default DRAM_BASE if !MMU
273 help
274 Please provide the physical address corresponding to the
275 location of main memory in your system.
276
277 config GENERIC_BUG
278 def_bool y
279 depends on BUG
280
281 source "init/Kconfig"
282
283 source "kernel/Kconfig.freezer"
284
285 menu "System Type"
286
287 config MMU
288 bool "MMU-based Paged Memory Management Support"
289 default y
290 help
291 Select if you want MMU-based virtualised addressing space
292 support by paged memory management. If unsure, say 'Y'.
293
294 #
295 # The "ARM system type" choice list is ordered alphabetically by option
296 # text. Please add new entries in the option alphabetic order.
297 #
298 choice
299 prompt "ARM system type"
300 default ARCH_VERSATILE if !MMU
301 default ARCH_MULTIPLATFORM if MMU
302
303 config ARCH_MULTIPLATFORM
304 bool "Allow multiple platforms to be selected"
305 depends on MMU
306 select ARM_PATCH_PHYS_VIRT
307 select AUTO_ZRELADDR
308 select COMMON_CLK
309 select MULTI_IRQ_HANDLER
310 select SPARSE_IRQ
311 select USE_OF
312
313 config ARCH_INTEGRATOR
314 bool "ARM Ltd. Integrator family"
315 select ARCH_HAS_CPUFREQ
316 select ARM_AMBA
317 select COMMON_CLK
318 select COMMON_CLK_VERSATILE
319 select GENERIC_CLOCKEVENTS
320 select HAVE_TCM
321 select ICST
322 select MULTI_IRQ_HANDLER
323 select NEED_MACH_MEMORY_H
324 select PLAT_VERSATILE
325 select SPARSE_IRQ
326 select USE_OF
327 select VERSATILE_FPGA_IRQ
328 help
329 Support for ARM's Integrator platform.
330
331 config ARCH_REALVIEW
332 bool "ARM Ltd. RealView family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_AMBA
335 select ARM_TIMER_SP804
336 select COMMON_CLK
337 select COMMON_CLK_VERSATILE
338 select GENERIC_CLOCKEVENTS
339 select GPIO_PL061 if GPIOLIB
340 select ICST
341 select NEED_MACH_MEMORY_H
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
344 help
345 This enables support for ARM Ltd RealView boards.
346
347 config ARCH_VERSATILE
348 bool "ARM Ltd. Versatile family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_AMBA
351 select ARM_TIMER_SP804
352 select ARM_VIC
353 select CLKDEV_LOOKUP
354 select GENERIC_CLOCKEVENTS
355 select HAVE_MACH_CLKDEV
356 select ICST
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLCD
359 select PLAT_VERSATILE_CLOCK
360 select VERSATILE_FPGA_IRQ
361 help
362 This enables support for ARM Ltd Versatile board.
363
364 config ARCH_AT91
365 bool "Atmel AT91"
366 select ARCH_REQUIRE_GPIOLIB
367 select CLKDEV_LOOKUP
368 select IRQ_DOMAIN
369 select NEED_MACH_GPIO_H
370 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL
372 select PINCTRL_AT91 if USE_OF
373 help
374 This enables support for systems based on Atmel
375 AT91RM9200 and AT91SAM9* processors.
376
377 config ARCH_CLPS711X
378 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
379 select ARCH_REQUIRE_GPIOLIB
380 select AUTO_ZRELADDR
381 select CLKSRC_MMIO
382 select COMMON_CLK
383 select CPU_ARM720T
384 select GENERIC_CLOCKEVENTS
385 select MFD_SYSCON
386 select MULTI_IRQ_HANDLER
387 select SPARSE_IRQ
388 help
389 Support for Cirrus Logic 711x/721x/731x based boards.
390
391 config ARCH_GEMINI
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
394 select CLKSRC_MMIO
395 select CPU_FA526
396 select GENERIC_CLOCKEVENTS
397 help
398 Support for the Cortina Systems Gemini family SoCs
399
400 config ARCH_EBSA110
401 bool "EBSA-110"
402 select ARCH_USES_GETTIMEOFFSET
403 select CPU_SA110
404 select ISA
405 select NEED_MACH_IO_H
406 select NEED_MACH_MEMORY_H
407 select NO_IOPORT
408 help
409 This is an evaluation board for the StrongARM processor available
410 from Digital. It has limited hardware on-board, including an
411 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 parallel port.
413
414 config ARCH_EP93XX
415 bool "EP93xx-based"
416 select ARCH_HAS_HOLES_MEMORYMODEL
417 select ARCH_REQUIRE_GPIOLIB
418 select ARCH_USES_GETTIMEOFFSET
419 select ARM_AMBA
420 select ARM_VIC
421 select CLKDEV_LOOKUP
422 select CPU_ARM920T
423 select NEED_MACH_MEMORY_H
424 help
425 This enables support for the Cirrus EP93xx series of CPUs.
426
427 config ARCH_FOOTBRIDGE
428 bool "FootBridge"
429 select CPU_SA110
430 select FOOTBRIDGE
431 select GENERIC_CLOCKEVENTS
432 select HAVE_IDE
433 select NEED_MACH_IO_H if !MMU
434 select NEED_MACH_MEMORY_H
435 help
436 Support for systems based on the DC21285 companion chip
437 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438
439 config ARCH_NETX
440 bool "Hilscher NetX based"
441 select ARM_VIC
442 select CLKSRC_MMIO
443 select CPU_ARM926T
444 select GENERIC_CLOCKEVENTS
445 help
446 This enables support for systems based on the Hilscher NetX Soc
447
448 config ARCH_IOP13XX
449 bool "IOP13xx-based"
450 depends on MMU
451 select CPU_XSC3
452 select NEED_MACH_MEMORY_H
453 select NEED_RET_TO_USER
454 select PCI
455 select PLAT_IOP
456 select VMSPLIT_1G
457 help
458 Support for Intel's IOP13XX (XScale) family of processors.
459
460 config ARCH_IOP32X
461 bool "IOP32x-based"
462 depends on MMU
463 select ARCH_REQUIRE_GPIOLIB
464 select CPU_XSCALE
465 select GPIO_IOP
466 select NEED_RET_TO_USER
467 select PCI
468 select PLAT_IOP
469 help
470 Support for Intel's 80219 and IOP32X (XScale) family of
471 processors.
472
473 config ARCH_IOP33X
474 bool "IOP33x-based"
475 depends on MMU
476 select ARCH_REQUIRE_GPIOLIB
477 select CPU_XSCALE
478 select GPIO_IOP
479 select NEED_RET_TO_USER
480 select PCI
481 select PLAT_IOP
482 help
483 Support for Intel's IOP33X (XScale) family of processors.
484
485 config ARCH_IXP4XX
486 bool "IXP4xx-based"
487 depends on MMU
488 select ARCH_HAS_DMA_SET_COHERENT_MASK
489 select ARCH_SUPPORTS_BIG_ENDIAN
490 select ARCH_REQUIRE_GPIOLIB
491 select CLKSRC_MMIO
492 select CPU_XSCALE
493 select DMABOUNCE if PCI
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
496 select NEED_MACH_IO_H
497 select USB_EHCI_BIG_ENDIAN_DESC
498 select USB_EHCI_BIG_ENDIAN_MMIO
499 help
500 Support for Intel's IXP4XX (XScale) family of processors.
501
502 config ARCH_DOVE
503 bool "Marvell Dove"
504 select ARCH_REQUIRE_GPIOLIB
505 select CPU_PJ4
506 select GENERIC_CLOCKEVENTS
507 select MIGHT_HAVE_PCI
508 select MVEBU_MBUS
509 select PINCTRL
510 select PINCTRL_DOVE
511 select PLAT_ORION_LEGACY
512 select USB_ARCH_HAS_EHCI
513 help
514 Support for the Marvell Dove SoC 88AP510
515
516 config ARCH_KIRKWOOD
517 bool "Marvell Kirkwood"
518 select ARCH_HAS_CPUFREQ
519 select ARCH_REQUIRE_GPIOLIB
520 select CPU_FEROCEON
521 select GENERIC_CLOCKEVENTS
522 select MVEBU_MBUS
523 select PCI
524 select PCI_QUIRKS
525 select PINCTRL
526 select PINCTRL_KIRKWOOD
527 select PLAT_ORION_LEGACY
528 help
529 Support for the following Marvell Kirkwood series SoCs:
530 88F6180, 88F6192 and 88F6281.
531
532 config ARCH_MV78XX0
533 bool "Marvell MV78xx0"
534 select ARCH_REQUIRE_GPIOLIB
535 select CPU_FEROCEON
536 select GENERIC_CLOCKEVENTS
537 select MVEBU_MBUS
538 select PCI
539 select PLAT_ORION_LEGACY
540 help
541 Support for the following Marvell MV78xx0 series SoCs:
542 MV781x0, MV782x0.
543
544 config ARCH_ORION5X
545 bool "Marvell Orion"
546 depends on MMU
547 select ARCH_REQUIRE_GPIOLIB
548 select CPU_FEROCEON
549 select GENERIC_CLOCKEVENTS
550 select MVEBU_MBUS
551 select PCI
552 select PLAT_ORION_LEGACY
553 help
554 Support for the following Marvell Orion 5x series SoCs:
555 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
556 Orion-2 (5281), Orion-1-90 (6183).
557
558 config ARCH_MMP
559 bool "Marvell PXA168/910/MMP2"
560 depends on MMU
561 select ARCH_REQUIRE_GPIOLIB
562 select CLKDEV_LOOKUP
563 select GENERIC_ALLOCATOR
564 select GENERIC_CLOCKEVENTS
565 select GPIO_PXA
566 select IRQ_DOMAIN
567 select MULTI_IRQ_HANDLER
568 select PINCTRL
569 select PLAT_PXA
570 select SPARSE_IRQ
571 help
572 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
573
574 config ARCH_KS8695
575 bool "Micrel/Kendin KS8695"
576 select ARCH_REQUIRE_GPIOLIB
577 select CLKSRC_MMIO
578 select CPU_ARM922T
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_MEMORY_H
581 help
582 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
583 System-on-Chip devices.
584
585 config ARCH_W90X900
586 bool "Nuvoton W90X900 CPU"
587 select ARCH_REQUIRE_GPIOLIB
588 select CLKDEV_LOOKUP
589 select CLKSRC_MMIO
590 select CPU_ARM926T
591 select GENERIC_CLOCKEVENTS
592 help
593 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
594 At present, the w90x900 has been renamed nuc900, regarding
595 the ARM series product line, you can login the following
596 link address to know more.
597
598 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
599 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
600
601 config ARCH_LPC32XX
602 bool "NXP LPC32XX"
603 select ARCH_REQUIRE_GPIOLIB
604 select ARM_AMBA
605 select CLKDEV_LOOKUP
606 select CLKSRC_MMIO
607 select CPU_ARM926T
608 select GENERIC_CLOCKEVENTS
609 select HAVE_IDE
610 select HAVE_PWM
611 select USB_ARCH_HAS_OHCI
612 select USE_OF
613 help
614 Support for the NXP LPC32XX family of processors
615
616 config ARCH_PXA
617 bool "PXA2xx/PXA3xx-based"
618 depends on MMU
619 select ARCH_HAS_CPUFREQ
620 select ARCH_MTD_XIP
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
623 select AUTO_ZRELADDR
624 select CLKDEV_LOOKUP
625 select CLKSRC_MMIO
626 select GENERIC_CLOCKEVENTS
627 select GPIO_PXA
628 select HAVE_IDE
629 select MULTI_IRQ_HANDLER
630 select PLAT_PXA
631 select SPARSE_IRQ
632 help
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
634
635 config ARCH_MSM
636 bool "Qualcomm MSM"
637 select ARCH_REQUIRE_GPIOLIB
638 select CLKSRC_OF if OF
639 select COMMON_CLK
640 select GENERIC_CLOCKEVENTS
641 help
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
647
648 config ARCH_SHMOBILE
649 bool "Renesas SH-Mobile / R-Mobile"
650 select ARM_PATCH_PHYS_VIRT
651 select CLKDEV_LOOKUP
652 select GENERIC_CLOCKEVENTS
653 select HAVE_ARM_SCU if SMP
654 select HAVE_ARM_TWD if SMP
655 select HAVE_MACH_CLKDEV
656 select HAVE_SMP
657 select MIGHT_HAVE_CACHE_L2X0
658 select MULTI_IRQ_HANDLER
659 select NO_IOPORT
660 select PINCTRL
661 select PM_GENERIC_DOMAINS if PM
662 select SPARSE_IRQ
663 help
664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
665
666 config ARCH_RPC
667 bool "RiscPC"
668 select ARCH_ACORN
669 select ARCH_MAY_HAVE_PC_FDC
670 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_USES_GETTIMEOFFSET
672 select FIQ
673 select HAVE_IDE
674 select HAVE_PATA_PLATFORM
675 select ISA_DMA_API
676 select NEED_MACH_IO_H
677 select NEED_MACH_MEMORY_H
678 select NO_IOPORT
679 select VIRT_TO_BUS
680 help
681 On the Acorn Risc-PC, Linux can support the internal IDE disk and
682 CD-ROM interface, serial and parallel port, and the floppy drive.
683
684 config ARCH_SA1100
685 bool "SA1100-based"
686 select ARCH_HAS_CPUFREQ
687 select ARCH_MTD_XIP
688 select ARCH_REQUIRE_GPIOLIB
689 select ARCH_SPARSEMEM_ENABLE
690 select CLKDEV_LOOKUP
691 select CLKSRC_MMIO
692 select CPU_FREQ
693 select CPU_SA1100
694 select GENERIC_CLOCKEVENTS
695 select HAVE_IDE
696 select ISA
697 select NEED_MACH_MEMORY_H
698 select SPARSE_IRQ
699 help
700 Support for StrongARM 11x0 based boards.
701
702 config ARCH_S3C24XX
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
706 select CLKDEV_LOOKUP
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
709 select GPIO_SAMSUNG
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select HAVE_S3C_RTC if RTC_CLASS
713 select MULTI_IRQ_HANDLER
714 select NEED_MACH_IO_H
715 select SAMSUNG_ATAGS
716 help
717 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
718 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
719 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
720 Samsung SMDK2410 development board (and derivatives).
721
722 config ARCH_S3C64XX
723 bool "Samsung S3C64XX"
724 select ARCH_HAS_CPUFREQ
725 select ARCH_REQUIRE_GPIOLIB
726 select ARM_AMBA
727 select ARM_VIC
728 select CLKDEV_LOOKUP
729 select CLKSRC_SAMSUNG_PWM
730 select COMMON_CLK
731 select CPU_V6
732 select GENERIC_CLOCKEVENTS
733 select GPIO_SAMSUNG
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
736 select HAVE_TCM
737 select NO_IOPORT
738 select PLAT_SAMSUNG
739 select PM_GENERIC_DOMAINS
740 select S3C_DEV_NAND
741 select S3C_GPIO_TRACK
742 select SAMSUNG_ATAGS
743 select SAMSUNG_GPIOLIB_4BIT
744 select SAMSUNG_WAKEMASK
745 select SAMSUNG_WDT_RESET
746 select USB_ARCH_HAS_OHCI
747 help
748 Samsung S3C64XX series based systems
749
750 config ARCH_S5P64X0
751 bool "Samsung S5P6440 S5P6450"
752 select CLKDEV_LOOKUP
753 select CLKSRC_SAMSUNG_PWM
754 select CPU_V6
755 select GENERIC_CLOCKEVENTS
756 select GPIO_SAMSUNG
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
759 select HAVE_S3C_RTC if RTC_CLASS
760 select NEED_MACH_GPIO_H
761 select SAMSUNG_ATAGS
762 select SAMSUNG_WDT_RESET
763 help
764 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
765 SMDK6450.
766
767 config ARCH_S5PC100
768 bool "Samsung S5PC100"
769 select ARCH_REQUIRE_GPIOLIB
770 select CLKDEV_LOOKUP
771 select CLKSRC_SAMSUNG_PWM
772 select CPU_V7
773 select GENERIC_CLOCKEVENTS
774 select GPIO_SAMSUNG
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select HAVE_S3C_RTC if RTC_CLASS
778 select NEED_MACH_GPIO_H
779 select SAMSUNG_ATAGS
780 select SAMSUNG_WDT_RESET
781 help
782 Samsung S5PC100 series based systems
783
784 config ARCH_S5PV210
785 bool "Samsung S5PV210/S5PC110"
786 select ARCH_HAS_CPUFREQ
787 select ARCH_HAS_HOLES_MEMORYMODEL
788 select ARCH_SPARSEMEM_ENABLE
789 select CLKDEV_LOOKUP
790 select CLKSRC_SAMSUNG_PWM
791 select CPU_V7
792 select GENERIC_CLOCKEVENTS
793 select GPIO_SAMSUNG
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
798 select NEED_MACH_MEMORY_H
799 select SAMSUNG_ATAGS
800 help
801 Samsung S5PV210/S5PC110 series based systems
802
803 config ARCH_EXYNOS
804 bool "Samsung EXYNOS"
805 select ARCH_HAS_CPUFREQ
806 select ARCH_HAS_HOLES_MEMORYMODEL
807 select ARCH_REQUIRE_GPIOLIB
808 select ARCH_SPARSEMEM_ENABLE
809 select ARM_GIC
810 select COMMON_CLK
811 select CPU_V7
812 select GENERIC_CLOCKEVENTS
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select HAVE_S3C_RTC if RTC_CLASS
816 select NEED_MACH_MEMORY_H
817 select SPARSE_IRQ
818 select USE_OF
819 help
820 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
821
822 config ARCH_DAVINCI
823 bool "TI DaVinci"
824 select ARCH_HAS_HOLES_MEMORYMODEL
825 select ARCH_REQUIRE_GPIOLIB
826 select CLKDEV_LOOKUP
827 select GENERIC_ALLOCATOR
828 select GENERIC_CLOCKEVENTS
829 select GENERIC_IRQ_CHIP
830 select HAVE_IDE
831 select TI_PRIV_EDMA
832 select USE_OF
833 select ZONE_DMA
834 help
835 Support for TI's DaVinci platform.
836
837 config ARCH_OMAP1
838 bool "TI OMAP1"
839 depends on MMU
840 select ARCH_HAS_CPUFREQ
841 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_OMAP
843 select ARCH_REQUIRE_GPIOLIB
844 select CLKDEV_LOOKUP
845 select CLKSRC_MMIO
846 select GENERIC_CLOCKEVENTS
847 select GENERIC_IRQ_CHIP
848 select HAVE_IDE
849 select IRQ_DOMAIN
850 select NEED_MACH_IO_H if PCCARD
851 select NEED_MACH_MEMORY_H
852 help
853 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
854
855 endchoice
856
857 menu "Multiple platform selection"
858 depends on ARCH_MULTIPLATFORM
859
860 comment "CPU Core family selection"
861
862 config ARCH_MULTI_V4T
863 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
864 depends on !ARCH_MULTI_V6_V7
865 select ARCH_MULTI_V4_V5
866 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
867 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
868 CPU_ARM925T || CPU_ARM940T)
869
870 config ARCH_MULTI_V5
871 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
872 depends on !ARCH_MULTI_V6_V7
873 select ARCH_MULTI_V4_V5
874 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
875 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
876 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
877
878 config ARCH_MULTI_V4_V5
879 bool
880
881 config ARCH_MULTI_V6
882 bool "ARMv6 based platforms (ARM11)"
883 select ARCH_MULTI_V6_V7
884 select CPU_V6
885
886 config ARCH_MULTI_V7
887 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
888 default y
889 select ARCH_MULTI_V6_V7
890 select CPU_V7
891
892 config ARCH_MULTI_V6_V7
893 bool
894
895 config ARCH_MULTI_CPU_AUTO
896 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
897 select ARCH_MULTI_V5
898
899 endmenu
900
901 #
902 # This is sorted alphabetically by mach-* pathname. However, plat-*
903 # Kconfigs may be included either alphabetically (according to the
904 # plat- suffix) or along side the corresponding mach-* source.
905 #
906 source "arch/arm/mach-mvebu/Kconfig"
907
908 source "arch/arm/mach-at91/Kconfig"
909
910 source "arch/arm/mach-bcm/Kconfig"
911
912 source "arch/arm/mach-bcm2835/Kconfig"
913
914 source "arch/arm/mach-clps711x/Kconfig"
915
916 source "arch/arm/mach-cns3xxx/Kconfig"
917
918 source "arch/arm/mach-davinci/Kconfig"
919
920 source "arch/arm/mach-dove/Kconfig"
921
922 source "arch/arm/mach-ep93xx/Kconfig"
923
924 source "arch/arm/mach-footbridge/Kconfig"
925
926 source "arch/arm/mach-gemini/Kconfig"
927
928 source "arch/arm/mach-highbank/Kconfig"
929
930 source "arch/arm/mach-integrator/Kconfig"
931
932 source "arch/arm/mach-iop32x/Kconfig"
933
934 source "arch/arm/mach-iop33x/Kconfig"
935
936 source "arch/arm/mach-iop13xx/Kconfig"
937
938 source "arch/arm/mach-ixp4xx/Kconfig"
939
940 source "arch/arm/mach-keystone/Kconfig"
941
942 source "arch/arm/mach-kirkwood/Kconfig"
943
944 source "arch/arm/mach-ks8695/Kconfig"
945
946 source "arch/arm/mach-msm/Kconfig"
947
948 source "arch/arm/mach-mv78xx0/Kconfig"
949
950 source "arch/arm/mach-imx/Kconfig"
951
952 source "arch/arm/mach-mxs/Kconfig"
953
954 source "arch/arm/mach-netx/Kconfig"
955
956 source "arch/arm/mach-nomadik/Kconfig"
957
958 source "arch/arm/mach-nspire/Kconfig"
959
960 source "arch/arm/plat-omap/Kconfig"
961
962 source "arch/arm/mach-omap1/Kconfig"
963
964 source "arch/arm/mach-omap2/Kconfig"
965
966 source "arch/arm/mach-orion5x/Kconfig"
967
968 source "arch/arm/mach-picoxcell/Kconfig"
969
970 source "arch/arm/mach-pxa/Kconfig"
971 source "arch/arm/plat-pxa/Kconfig"
972
973 source "arch/arm/mach-mmp/Kconfig"
974
975 source "arch/arm/mach-realview/Kconfig"
976
977 source "arch/arm/mach-rockchip/Kconfig"
978
979 source "arch/arm/mach-sa1100/Kconfig"
980
981 source "arch/arm/plat-samsung/Kconfig"
982
983 source "arch/arm/mach-socfpga/Kconfig"
984
985 source "arch/arm/mach-spear/Kconfig"
986
987 source "arch/arm/mach-sti/Kconfig"
988
989 source "arch/arm/mach-s3c24xx/Kconfig"
990
991 source "arch/arm/mach-s3c64xx/Kconfig"
992
993 source "arch/arm/mach-s5p64x0/Kconfig"
994
995 source "arch/arm/mach-s5pc100/Kconfig"
996
997 source "arch/arm/mach-s5pv210/Kconfig"
998
999 source "arch/arm/mach-exynos/Kconfig"
1000
1001 source "arch/arm/mach-shmobile/Kconfig"
1002
1003 source "arch/arm/mach-sunxi/Kconfig"
1004
1005 source "arch/arm/mach-prima2/Kconfig"
1006
1007 source "arch/arm/mach-tegra/Kconfig"
1008
1009 source "arch/arm/mach-u300/Kconfig"
1010
1011 source "arch/arm/mach-ux500/Kconfig"
1012
1013 source "arch/arm/mach-versatile/Kconfig"
1014
1015 source "arch/arm/mach-vexpress/Kconfig"
1016 source "arch/arm/plat-versatile/Kconfig"
1017
1018 source "arch/arm/mach-virt/Kconfig"
1019
1020 source "arch/arm/mach-vt8500/Kconfig"
1021
1022 source "arch/arm/mach-w90x900/Kconfig"
1023
1024 source "arch/arm/mach-zynq/Kconfig"
1025
1026 # Definitions to make life easier
1027 config ARCH_ACORN
1028 bool
1029
1030 config PLAT_IOP
1031 bool
1032 select GENERIC_CLOCKEVENTS
1033
1034 config PLAT_ORION
1035 bool
1036 select CLKSRC_MMIO
1037 select COMMON_CLK
1038 select GENERIC_IRQ_CHIP
1039 select IRQ_DOMAIN
1040
1041 config PLAT_ORION_LEGACY
1042 bool
1043 select PLAT_ORION
1044
1045 config PLAT_PXA
1046 bool
1047
1048 config PLAT_VERSATILE
1049 bool
1050
1051 config ARM_TIMER_SP804
1052 bool
1053 select CLKSRC_MMIO
1054 select CLKSRC_OF if OF
1055
1056 source arch/arm/mm/Kconfig
1057
1058 config ARM_NR_BANKS
1059 int
1060 default 16 if ARCH_EP93XX
1061 default 8
1062
1063 config IWMMXT
1064 bool "Enable iWMMXt support" if !CPU_PJ4
1065 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1066 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1067 help
1068 Enable support for iWMMXt context switching at run time if
1069 running on a CPU that supports it.
1070
1071 config MULTI_IRQ_HANDLER
1072 bool
1073 help
1074 Allow each machine to specify it's own IRQ handler at run time.
1075
1076 if !MMU
1077 source "arch/arm/Kconfig-nommu"
1078 endif
1079
1080 config PJ4B_ERRATA_4742
1081 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1082 depends on CPU_PJ4B && MACH_ARMADA_370
1083 default y
1084 help
1085 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1086 Event (WFE) IDLE states, a specific timing sensitivity exists between
1087 the retiring WFI/WFE instructions and the newly issued subsequent
1088 instructions. This sensitivity can result in a CPU hang scenario.
1089 Workaround:
1090 The software must insert either a Data Synchronization Barrier (DSB)
1091 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1092 instruction
1093
1094 config ARM_ERRATA_326103
1095 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1096 depends on CPU_V6
1097 help
1098 Executing a SWP instruction to read-only memory does not set bit 11
1099 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1100 treat the access as a read, preventing a COW from occurring and
1101 causing the faulting task to livelock.
1102
1103 config ARM_ERRATA_411920
1104 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1105 depends on CPU_V6 || CPU_V6K
1106 help
1107 Invalidation of the Instruction Cache operation can
1108 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1109 It does not affect the MPCore. This option enables the ARM Ltd.
1110 recommended workaround.
1111
1112 config ARM_ERRATA_430973
1113 bool "ARM errata: Stale prediction on replaced interworking branch"
1114 depends on CPU_V7
1115 help
1116 This option enables the workaround for the 430973 Cortex-A8
1117 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1118 interworking branch is replaced with another code sequence at the
1119 same virtual address, whether due to self-modifying code or virtual
1120 to physical address re-mapping, Cortex-A8 does not recover from the
1121 stale interworking branch prediction. This results in Cortex-A8
1122 executing the new code sequence in the incorrect ARM or Thumb state.
1123 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1124 and also flushes the branch target cache at every context switch.
1125 Note that setting specific bits in the ACTLR register may not be
1126 available in non-secure mode.
1127
1128 config ARM_ERRATA_458693
1129 bool "ARM errata: Processor deadlock when a false hazard is created"
1130 depends on CPU_V7
1131 depends on !ARCH_MULTIPLATFORM
1132 help
1133 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1134 erratum. For very specific sequences of memory operations, it is
1135 possible for a hazard condition intended for a cache line to instead
1136 be incorrectly associated with a different cache line. This false
1137 hazard might then cause a processor deadlock. The workaround enables
1138 the L1 caching of the NEON accesses and disables the PLD instruction
1139 in the ACTLR register. Note that setting specific bits in the ACTLR
1140 register may not be available in non-secure mode.
1141
1142 config ARM_ERRATA_460075
1143 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1144 depends on CPU_V7
1145 depends on !ARCH_MULTIPLATFORM
1146 help
1147 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1148 erratum. Any asynchronous access to the L2 cache may encounter a
1149 situation in which recent store transactions to the L2 cache are lost
1150 and overwritten with stale memory contents from external memory. The
1151 workaround disables the write-allocate mode for the L2 cache via the
1152 ACTLR register. Note that setting specific bits in the ACTLR register
1153 may not be available in non-secure mode.
1154
1155 config ARM_ERRATA_742230
1156 bool "ARM errata: DMB operation may be faulty"
1157 depends on CPU_V7 && SMP
1158 depends on !ARCH_MULTIPLATFORM
1159 help
1160 This option enables the workaround for the 742230 Cortex-A9
1161 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1162 between two write operations may not ensure the correct visibility
1163 ordering of the two writes. This workaround sets a specific bit in
1164 the diagnostic register of the Cortex-A9 which causes the DMB
1165 instruction to behave as a DSB, ensuring the correct behaviour of
1166 the two writes.
1167
1168 config ARM_ERRATA_742231
1169 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1170 depends on CPU_V7 && SMP
1171 depends on !ARCH_MULTIPLATFORM
1172 help
1173 This option enables the workaround for the 742231 Cortex-A9
1174 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1175 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1176 accessing some data located in the same cache line, may get corrupted
1177 data due to bad handling of the address hazard when the line gets
1178 replaced from one of the CPUs at the same time as another CPU is
1179 accessing it. This workaround sets specific bits in the diagnostic
1180 register of the Cortex-A9 which reduces the linefill issuing
1181 capabilities of the processor.
1182
1183 config PL310_ERRATA_588369
1184 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1185 depends on CACHE_L2X0
1186 help
1187 The PL310 L2 cache controller implements three types of Clean &
1188 Invalidate maintenance operations: by Physical Address
1189 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1190 They are architecturally defined to behave as the execution of a
1191 clean operation followed immediately by an invalidate operation,
1192 both performing to the same memory location. This functionality
1193 is not correctly implemented in PL310 as clean lines are not
1194 invalidated as a result of these operations.
1195
1196 config ARM_ERRATA_643719
1197 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1198 depends on CPU_V7 && SMP
1199 help
1200 This option enables the workaround for the 643719 Cortex-A9 (prior to
1201 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1202 register returns zero when it should return one. The workaround
1203 corrects this value, ensuring cache maintenance operations which use
1204 it behave as intended and avoiding data corruption.
1205
1206 config ARM_ERRATA_720789
1207 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1208 depends on CPU_V7
1209 help
1210 This option enables the workaround for the 720789 Cortex-A9 (prior to
1211 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1212 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1213 As a consequence of this erratum, some TLB entries which should be
1214 invalidated are not, resulting in an incoherency in the system page
1215 tables. The workaround changes the TLB flushing routines to invalidate
1216 entries regardless of the ASID.
1217
1218 config PL310_ERRATA_727915
1219 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1220 depends on CACHE_L2X0
1221 help
1222 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1223 operation (offset 0x7FC). This operation runs in background so that
1224 PL310 can handle normal accesses while it is in progress. Under very
1225 rare circumstances, due to this erratum, write data can be lost when
1226 PL310 treats a cacheable write transaction during a Clean &
1227 Invalidate by Way operation.
1228
1229 config ARM_ERRATA_743622
1230 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231 depends on CPU_V7
1232 depends on !ARCH_MULTIPLATFORM
1233 help
1234 This option enables the workaround for the 743622 Cortex-A9
1235 (r2p*) erratum. Under very rare conditions, a faulty
1236 optimisation in the Cortex-A9 Store Buffer may lead to data
1237 corruption. This workaround sets a specific bit in the diagnostic
1238 register of the Cortex-A9 which disables the Store Buffer
1239 optimisation, preventing the defect from occurring. This has no
1240 visible impact on the overall performance or power consumption of the
1241 processor.
1242
1243 config ARM_ERRATA_751472
1244 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1245 depends on CPU_V7
1246 depends on !ARCH_MULTIPLATFORM
1247 help
1248 This option enables the workaround for the 751472 Cortex-A9 (prior
1249 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1250 completion of a following broadcasted operation if the second
1251 operation is received by a CPU before the ICIALLUIS has completed,
1252 potentially leading to corrupted entries in the cache or TLB.
1253
1254 config PL310_ERRATA_753970
1255 bool "PL310 errata: cache sync operation may be faulty"
1256 depends on CACHE_PL310
1257 help
1258 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1259
1260 Under some condition the effect of cache sync operation on
1261 the store buffer still remains when the operation completes.
1262 This means that the store buffer is always asked to drain and
1263 this prevents it from merging any further writes. The workaround
1264 is to replace the normal offset of cache sync operation (0x730)
1265 by another offset targeting an unmapped PL310 register 0x740.
1266 This has the same effect as the cache sync operation: store buffer
1267 drain and waiting for all buffers empty.
1268
1269 config ARM_ERRATA_754322
1270 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1271 depends on CPU_V7
1272 help
1273 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1274 r3p*) erratum. A speculative memory access may cause a page table walk
1275 which starts prior to an ASID switch but completes afterwards. This
1276 can populate the micro-TLB with a stale entry which may be hit with
1277 the new ASID. This workaround places two dsb instructions in the mm
1278 switching code so that no page table walks can cross the ASID switch.
1279
1280 config ARM_ERRATA_754327
1281 bool "ARM errata: no automatic Store Buffer drain"
1282 depends on CPU_V7 && SMP
1283 help
1284 This option enables the workaround for the 754327 Cortex-A9 (prior to
1285 r2p0) erratum. The Store Buffer does not have any automatic draining
1286 mechanism and therefore a livelock may occur if an external agent
1287 continuously polls a memory location waiting to observe an update.
1288 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1289 written polling loops from denying visibility of updates to memory.
1290
1291 config ARM_ERRATA_364296
1292 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1293 depends on CPU_V6
1294 help
1295 This options enables the workaround for the 364296 ARM1136
1296 r0p2 erratum (possible cache data corruption with
1297 hit-under-miss enabled). It sets the undocumented bit 31 in
1298 the auxiliary control register and the FI bit in the control
1299 register, thus disabling hit-under-miss without putting the
1300 processor into full low interrupt latency mode. ARM11MPCore
1301 is not affected.
1302
1303 config ARM_ERRATA_764369
1304 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1305 depends on CPU_V7 && SMP
1306 help
1307 This option enables the workaround for erratum 764369
1308 affecting Cortex-A9 MPCore with two or more processors (all
1309 current revisions). Under certain timing circumstances, a data
1310 cache line maintenance operation by MVA targeting an Inner
1311 Shareable memory region may fail to proceed up to either the
1312 Point of Coherency or to the Point of Unification of the
1313 system. This workaround adds a DSB instruction before the
1314 relevant cache maintenance functions and sets a specific bit
1315 in the diagnostic control register of the SCU.
1316
1317 config PL310_ERRATA_769419
1318 bool "PL310 errata: no automatic Store Buffer drain"
1319 depends on CACHE_L2X0
1320 help
1321 On revisions of the PL310 prior to r3p2, the Store Buffer does
1322 not automatically drain. This can cause normal, non-cacheable
1323 writes to be retained when the memory system is idle, leading
1324 to suboptimal I/O performance for drivers using coherent DMA.
1325 This option adds a write barrier to the cpu_idle loop so that,
1326 on systems with an outer cache, the store buffer is drained
1327 explicitly.
1328
1329 config ARM_ERRATA_775420
1330 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1331 depends on CPU_V7
1332 help
1333 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1334 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1335 operation aborts with MMU exception, it might cause the processor
1336 to deadlock. This workaround puts DSB before executing ISB if
1337 an abort may occur on cache maintenance.
1338
1339 config ARM_ERRATA_798181
1340 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1341 depends on CPU_V7 && SMP
1342 help
1343 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1344 adequately shooting down all use of the old entries. This
1345 option enables the Linux kernel workaround for this erratum
1346 which sends an IPI to the CPUs that are running the same ASID
1347 as the one being invalidated.
1348
1349 config ARM_ERRATA_773022
1350 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1351 depends on CPU_V7
1352 help
1353 This option enables the workaround for the 773022 Cortex-A15
1354 (up to r0p4) erratum. In certain rare sequences of code, the
1355 loop buffer may deliver incorrect instructions. This
1356 workaround disables the loop buffer to avoid the erratum.
1357
1358 endmenu
1359
1360 source "arch/arm/common/Kconfig"
1361
1362 menu "Bus support"
1363
1364 config ARM_AMBA
1365 bool
1366
1367 config ISA
1368 bool
1369 help
1370 Find out whether you have ISA slots on your motherboard. ISA is the
1371 name of a bus system, i.e. the way the CPU talks to the other stuff
1372 inside your box. Other bus systems are PCI, EISA, MicroChannel
1373 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1374 newer boards don't support it. If you have ISA, say Y, otherwise N.
1375
1376 # Select ISA DMA controller support
1377 config ISA_DMA
1378 bool
1379 select ISA_DMA_API
1380
1381 # Select ISA DMA interface
1382 config ISA_DMA_API
1383 bool
1384
1385 config PCI
1386 bool "PCI support" if MIGHT_HAVE_PCI
1387 help
1388 Find out whether you have a PCI motherboard. PCI is the name of a
1389 bus system, i.e. the way the CPU talks to the other stuff inside
1390 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1391 VESA. If you have PCI, say Y, otherwise N.
1392
1393 config PCI_DOMAINS
1394 bool
1395 depends on PCI
1396
1397 config PCI_NANOENGINE
1398 bool "BSE nanoEngine PCI support"
1399 depends on SA1100_NANOENGINE
1400 help
1401 Enable PCI on the BSE nanoEngine board.
1402
1403 config PCI_SYSCALL
1404 def_bool PCI
1405
1406 config PCI_HOST_ITE8152
1407 bool
1408 depends on PCI && MACH_ARMCORE
1409 default y
1410 select DMABOUNCE
1411
1412 source "drivers/pci/Kconfig"
1413 source "drivers/pci/pcie/Kconfig"
1414
1415 source "drivers/pcmcia/Kconfig"
1416
1417 endmenu
1418
1419 menu "Kernel Features"
1420
1421 config HAVE_SMP
1422 bool
1423 help
1424 This option should be selected by machines which have an SMP-
1425 capable CPU.
1426
1427 The only effect of this option is to make the SMP-related
1428 options available to the user for configuration.
1429
1430 config SMP
1431 bool "Symmetric Multi-Processing"
1432 depends on CPU_V6K || CPU_V7
1433 depends on GENERIC_CLOCKEVENTS
1434 depends on HAVE_SMP
1435 depends on MMU || ARM_MPU
1436 help
1437 This enables support for systems with more than one CPU. If you have
1438 a system with only one CPU, like most personal computers, say N. If
1439 you have a system with more than one CPU, say Y.
1440
1441 If you say N here, the kernel will run on single and multiprocessor
1442 machines, but will use only one CPU of a multiprocessor machine. If
1443 you say Y here, the kernel will run on many, but not all, single
1444 processor machines. On a single processor machine, the kernel will
1445 run faster if you say N here.
1446
1447 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1448 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1449 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1450
1451 If you don't know what to do here, say N.
1452
1453 config SMP_ON_UP
1454 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1455 depends on SMP && !XIP_KERNEL && MMU
1456 default y
1457 help
1458 SMP kernels contain instructions which fail on non-SMP processors.
1459 Enabling this option allows the kernel to modify itself to make
1460 these instructions safe. Disabling it allows about 1K of space
1461 savings.
1462
1463 If you don't know what to do here, say Y.
1464
1465 config ARM_CPU_TOPOLOGY
1466 bool "Support cpu topology definition"
1467 depends on SMP && CPU_V7
1468 default y
1469 help
1470 Support ARM cpu topology definition. The MPIDR register defines
1471 affinity between processors which is then used to describe the cpu
1472 topology of an ARM System.
1473
1474 config SCHED_MC
1475 bool "Multi-core scheduler support"
1476 depends on ARM_CPU_TOPOLOGY
1477 help
1478 Multi-core scheduler support improves the CPU scheduler's decision
1479 making when dealing with multi-core CPU chips at a cost of slightly
1480 increased overhead in some places. If unsure say N here.
1481
1482 config SCHED_SMT
1483 bool "SMT scheduler support"
1484 depends on ARM_CPU_TOPOLOGY
1485 help
1486 Improves the CPU scheduler's decision making when dealing with
1487 MultiThreading at a cost of slightly increased overhead in some
1488 places. If unsure say N here.
1489
1490 config HAVE_ARM_SCU
1491 bool
1492 help
1493 This option enables support for the ARM system coherency unit
1494
1495 config HAVE_ARM_ARCH_TIMER
1496 bool "Architected timer support"
1497 depends on CPU_V7
1498 select ARM_ARCH_TIMER
1499 select GENERIC_CLOCKEVENTS
1500 help
1501 This option enables support for the ARM architected timer
1502
1503 config HAVE_ARM_TWD
1504 bool
1505 depends on SMP
1506 select CLKSRC_OF if OF
1507 help
1508 This options enables support for the ARM timer and watchdog unit
1509
1510 config MCPM
1511 bool "Multi-Cluster Power Management"
1512 depends on CPU_V7 && SMP
1513 help
1514 This option provides the common power management infrastructure
1515 for (multi-)cluster based systems, such as big.LITTLE based
1516 systems.
1517
1518 config BIG_LITTLE
1519 bool "big.LITTLE support (Experimental)"
1520 depends on CPU_V7 && SMP
1521 select MCPM
1522 help
1523 This option enables support selections for the big.LITTLE
1524 system architecture.
1525
1526 config BL_SWITCHER
1527 bool "big.LITTLE switcher support"
1528 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1529 select CPU_PM
1530 select ARM_CPU_SUSPEND
1531 help
1532 The big.LITTLE "switcher" provides the core functionality to
1533 transparently handle transition between a cluster of A15's
1534 and a cluster of A7's in a big.LITTLE system.
1535
1536 config BL_SWITCHER_DUMMY_IF
1537 tristate "Simple big.LITTLE switcher user interface"
1538 depends on BL_SWITCHER && DEBUG_KERNEL
1539 help
1540 This is a simple and dummy char dev interface to control
1541 the big.LITTLE switcher core code. It is meant for
1542 debugging purposes only.
1543
1544 choice
1545 prompt "Memory split"
1546 default VMSPLIT_3G
1547 help
1548 Select the desired split between kernel and user memory.
1549
1550 If you are not absolutely sure what you are doing, leave this
1551 option alone!
1552
1553 config VMSPLIT_3G
1554 bool "3G/1G user/kernel split"
1555 config VMSPLIT_2G
1556 bool "2G/2G user/kernel split"
1557 config VMSPLIT_1G
1558 bool "1G/3G user/kernel split"
1559 endchoice
1560
1561 config PAGE_OFFSET
1562 hex
1563 default 0x40000000 if VMSPLIT_1G
1564 default 0x80000000 if VMSPLIT_2G
1565 default 0xC0000000
1566
1567 config NR_CPUS
1568 int "Maximum number of CPUs (2-32)"
1569 range 2 32
1570 depends on SMP
1571 default "4"
1572
1573 config HOTPLUG_CPU
1574 bool "Support for hot-pluggable CPUs"
1575 depends on SMP
1576 help
1577 Say Y here to experiment with turning CPUs off and on. CPUs
1578 can be controlled through /sys/devices/system/cpu.
1579
1580 config ARM_PSCI
1581 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1582 depends on CPU_V7
1583 help
1584 Say Y here if you want Linux to communicate with system firmware
1585 implementing the PSCI specification for CPU-centric power
1586 management operations described in ARM document number ARM DEN
1587 0022A ("Power State Coordination Interface System Software on
1588 ARM processors").
1589
1590 # The GPIO number here must be sorted by descending number. In case of
1591 # a multiplatform kernel, we just want the highest value required by the
1592 # selected platforms.
1593 config ARCH_NR_GPIO
1594 int
1595 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1596 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1597 default 392 if ARCH_U8500
1598 default 352 if ARCH_VT8500
1599 default 288 if ARCH_SUNXI
1600 default 264 if MACH_H4700
1601 default 0
1602 help
1603 Maximum number of GPIOs in the system.
1604
1605 If unsure, leave the default value.
1606
1607 source kernel/Kconfig.preempt
1608
1609 config HZ_FIXED
1610 int
1611 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1612 ARCH_S5PV210 || ARCH_EXYNOS4
1613 default AT91_TIMER_HZ if ARCH_AT91
1614 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1615 default 0
1616
1617 choice
1618 depends on HZ_FIXED = 0
1619 prompt "Timer frequency"
1620
1621 config HZ_100
1622 bool "100 Hz"
1623
1624 config HZ_200
1625 bool "200 Hz"
1626
1627 config HZ_250
1628 bool "250 Hz"
1629
1630 config HZ_300
1631 bool "300 Hz"
1632
1633 config HZ_500
1634 bool "500 Hz"
1635
1636 config HZ_1000
1637 bool "1000 Hz"
1638
1639 endchoice
1640
1641 config HZ
1642 int
1643 default HZ_FIXED if HZ_FIXED != 0
1644 default 100 if HZ_100
1645 default 200 if HZ_200
1646 default 250 if HZ_250
1647 default 300 if HZ_300
1648 default 500 if HZ_500
1649 default 1000
1650
1651 config SCHED_HRTICK
1652 def_bool HIGH_RES_TIMERS
1653
1654 config SCHED_HRTICK
1655 def_bool HIGH_RES_TIMERS
1656
1657 config THUMB2_KERNEL
1658 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1659 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1660 default y if CPU_THUMBONLY
1661 select AEABI
1662 select ARM_ASM_UNIFIED
1663 select ARM_UNWIND
1664 help
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1668
1669 If unsure, say N.
1670
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1674 default y
1675 help
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1679
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1685 support.
1686
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1689
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1694
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1697
1698 Only Thumb-2 kernels are affected.
1699
1700 Unless you are sure your tools don't have this problem, say Y.
1701
1702 config ARM_ASM_UNIFIED
1703 bool
1704
1705 config AEABI
1706 bool "Use the ARM EABI to compile the kernel"
1707 help
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1711
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1717
1718 To use this you need GCC version 4.0.0 or later.
1719
1720 config OABI_COMPAT
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && !THUMB2_KERNEL
1723 help
1724 This option preserves the old syscall interface along with the
1725 new (ARM EABI) one. It also provides a compatibility layer to
1726 intercept syscalls that have structure arguments which layout
1727 in memory differs between the legacy ABI and the new ARM EABI
1728 (only for non "thumb" binaries). This option adds a tiny
1729 overhead to all syscalls and produces a slightly larger kernel.
1730
1731 The seccomp filter system will not be available when this is
1732 selected, since there is no way yet to sensibly distinguish
1733 between calling conventions during filtering.
1734
1735 If you know you'll be using only pure EABI user space then you
1736 can say N here. If this option is not selected and you attempt
1737 to execute a legacy ABI binary then the result will be
1738 UNPREDICTABLE (in fact it can be predicted that it won't work
1739 at all). If in doubt say N.
1740
1741 config ARCH_HAS_HOLES_MEMORYMODEL
1742 bool
1743
1744 config ARCH_SPARSEMEM_ENABLE
1745 bool
1746
1747 config ARCH_SPARSEMEM_DEFAULT
1748 def_bool ARCH_SPARSEMEM_ENABLE
1749
1750 config ARCH_SELECT_MEMORY_MODEL
1751 def_bool ARCH_SPARSEMEM_ENABLE
1752
1753 config HAVE_ARCH_PFN_VALID
1754 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1755
1756 config HIGHMEM
1757 bool "High Memory Support"
1758 depends on MMU
1759 help
1760 The address space of ARM processors is only 4 Gigabytes large
1761 and it has to accommodate user address space, kernel address
1762 space as well as some memory mapped IO. That means that, if you
1763 have a large amount of physical memory and/or IO, not all of the
1764 memory can be "permanently mapped" by the kernel. The physical
1765 memory that is not permanently mapped is called "high memory".
1766
1767 Depending on the selected kernel/user memory split, minimum
1768 vmalloc space and actual amount of RAM, you may not need this
1769 option which should result in a slightly faster kernel.
1770
1771 If unsure, say n.
1772
1773 config HIGHPTE
1774 bool "Allocate 2nd-level pagetables from highmem"
1775 depends on HIGHMEM
1776
1777 config HW_PERF_EVENTS
1778 bool "Enable hardware performance counter support for perf events"
1779 depends on PERF_EVENTS
1780 default y
1781 help
1782 Enable hardware performance counter support for perf events. If
1783 disabled, perf events will use software events only.
1784
1785 config SYS_SUPPORTS_HUGETLBFS
1786 def_bool y
1787 depends on ARM_LPAE
1788
1789 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1790 def_bool y
1791 depends on ARM_LPAE
1792
1793 config ARCH_WANT_GENERAL_HUGETLB
1794 def_bool y
1795
1796 source "mm/Kconfig"
1797
1798 config FORCE_MAX_ZONEORDER
1799 int "Maximum zone order" if ARCH_SHMOBILE
1800 range 11 64 if ARCH_SHMOBILE
1801 default "12" if SOC_AM33XX
1802 default "9" if SA1111
1803 default "11"
1804 help
1805 The kernel memory allocator divides physically contiguous memory
1806 blocks into "zones", where each zone is a power of two number of
1807 pages. This option selects the largest power of two that the kernel
1808 keeps in the memory allocator. If you need to allocate very large
1809 blocks of physically contiguous memory, then you may need to
1810 increase this value.
1811
1812 This config option is actually maximum order plus one. For example,
1813 a value of 11 means that the largest free memory block is 2^10 pages.
1814
1815 config ALIGNMENT_TRAP
1816 bool
1817 depends on CPU_CP15_MMU
1818 default y if !ARCH_EBSA110
1819 select HAVE_PROC_CPU if PROC_FS
1820 help
1821 ARM processors cannot fetch/store information which is not
1822 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1823 address divisible by 4. On 32-bit ARM processors, these non-aligned
1824 fetch/store instructions will be emulated in software if you say
1825 here, which has a severe performance impact. This is necessary for
1826 correct operation of some network protocols. With an IP-only
1827 configuration it is safe to say N, otherwise say Y.
1828
1829 config UACCESS_WITH_MEMCPY
1830 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1831 depends on MMU
1832 default y if CPU_FEROCEON
1833 help
1834 Implement faster copy_to_user and clear_user methods for CPU
1835 cores where a 8-word STM instruction give significantly higher
1836 memory write throughput than a sequence of individual 32bit stores.
1837
1838 A possible side effect is a slight increase in scheduling latency
1839 between threads sharing the same address space if they invoke
1840 such copy operations with large buffers.
1841
1842 However, if the CPU data cache is using a write-allocate mode,
1843 this option is unlikely to provide any performance gain.
1844
1845 config SECCOMP
1846 bool
1847 prompt "Enable seccomp to safely compute untrusted bytecode"
1848 ---help---
1849 This kernel feature is useful for number crunching applications
1850 that may need to compute untrusted bytecode during their
1851 execution. By using pipes or other transports made available to
1852 the process as file descriptors supporting the read/write
1853 syscalls, it's possible to isolate those applications in
1854 their own address space using seccomp. Once seccomp is
1855 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1856 and the task is only allowed to execute a few safe syscalls
1857 defined by each seccomp mode.
1858
1859 config SWIOTLB
1860 def_bool y
1861
1862 config IOMMU_HELPER
1863 def_bool SWIOTLB
1864
1865 config XEN_DOM0
1866 def_bool y
1867 depends on XEN
1868
1869 config XEN
1870 bool "Xen guest support on ARM (EXPERIMENTAL)"
1871 depends on ARM && AEABI && OF
1872 depends on CPU_V7 && !CPU_V6
1873 depends on !GENERIC_ATOMIC64
1874 select ARM_PSCI
1875 select SWIOTLB_XEN
1876 help
1877 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1878
1879 endmenu
1880
1881 menu "Boot options"
1882
1883 config USE_OF
1884 bool "Flattened Device Tree support"
1885 select IRQ_DOMAIN
1886 select OF
1887 select OF_EARLY_FLATTREE
1888 help
1889 Include support for flattened device tree machine descriptions.
1890
1891 config ATAGS
1892 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1893 default y
1894 help
1895 This is the traditional way of passing data to the kernel at boot
1896 time. If you are solely relying on the flattened device tree (or
1897 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1898 to remove ATAGS support from your kernel binary. If unsure,
1899 leave this to y.
1900
1901 config DEPRECATED_PARAM_STRUCT
1902 bool "Provide old way to pass kernel parameters"
1903 depends on ATAGS
1904 help
1905 This was deprecated in 2001 and announced to live on for 5 years.
1906 Some old boot loaders still use this way.
1907
1908 # Compressed boot loader in ROM. Yes, we really want to ask about
1909 # TEXT and BSS so we preserve their values in the config files.
1910 config ZBOOT_ROM_TEXT
1911 hex "Compressed ROM boot loader base address"
1912 default "0"
1913 help
1914 The physical address at which the ROM-able zImage is to be
1915 placed in the target. Platforms which normally make use of
1916 ROM-able zImage formats normally set this to a suitable
1917 value in their defconfig file.
1918
1919 If ZBOOT_ROM is not enabled, this has no effect.
1920
1921 config ZBOOT_ROM_BSS
1922 hex "Compressed ROM boot loader BSS address"
1923 default "0"
1924 help
1925 The base address of an area of read/write memory in the target
1926 for the ROM-able zImage which must be available while the
1927 decompressor is running. It must be large enough to hold the
1928 entire decompressed kernel plus an additional 128 KiB.
1929 Platforms which normally make use of ROM-able zImage formats
1930 normally set this to a suitable value in their defconfig file.
1931
1932 If ZBOOT_ROM is not enabled, this has no effect.
1933
1934 config ZBOOT_ROM
1935 bool "Compressed boot loader in ROM/flash"
1936 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1937 help
1938 Say Y here if you intend to execute your compressed kernel image
1939 (zImage) directly from ROM or flash. If unsure, say N.
1940
1941 choice
1942 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1943 depends on ZBOOT_ROM && ARCH_SH7372
1944 default ZBOOT_ROM_NONE
1945 help
1946 Include experimental SD/MMC loading code in the ROM-able zImage.
1947 With this enabled it is possible to write the ROM-able zImage
1948 kernel image to an MMC or SD card and boot the kernel straight
1949 from the reset vector. At reset the processor Mask ROM will load
1950 the first part of the ROM-able zImage which in turn loads the
1951 rest the kernel image to RAM.
1952
1953 config ZBOOT_ROM_NONE
1954 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1955 help
1956 Do not load image from SD or MMC
1957
1958 config ZBOOT_ROM_MMCIF
1959 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1960 help
1961 Load image from MMCIF hardware block.
1962
1963 config ZBOOT_ROM_SH_MOBILE_SDHI
1964 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1965 help
1966 Load image from SDHI hardware block
1967
1968 endchoice
1969
1970 config ARM_APPENDED_DTB
1971 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1972 depends on OF && !ZBOOT_ROM
1973 help
1974 With this option, the boot code will look for a device tree binary
1975 (DTB) appended to zImage
1976 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1977
1978 This is meant as a backward compatibility convenience for those
1979 systems with a bootloader that can't be upgraded to accommodate
1980 the documented boot protocol using a device tree.
1981
1982 Beware that there is very little in terms of protection against
1983 this option being confused by leftover garbage in memory that might
1984 look like a DTB header after a reboot if no actual DTB is appended
1985 to zImage. Do not leave this option active in a production kernel
1986 if you don't intend to always append a DTB. Proper passing of the
1987 location into r2 of a bootloader provided DTB is always preferable
1988 to this option.
1989
1990 config ARM_ATAG_DTB_COMPAT
1991 bool "Supplement the appended DTB with traditional ATAG information"
1992 depends on ARM_APPENDED_DTB
1993 help
1994 Some old bootloaders can't be updated to a DTB capable one, yet
1995 they provide ATAGs with memory configuration, the ramdisk address,
1996 the kernel cmdline string, etc. Such information is dynamically
1997 provided by the bootloader and can't always be stored in a static
1998 DTB. To allow a device tree enabled kernel to be used with such
1999 bootloaders, this option allows zImage to extract the information
2000 from the ATAG list and store it at run time into the appended DTB.
2001
2002 choice
2003 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2004 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005
2006 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2007 bool "Use bootloader kernel arguments if available"
2008 help
2009 Uses the command-line options passed by the boot loader instead of
2010 the device tree bootargs property. If the boot loader doesn't provide
2011 any, the device tree bootargs property will be used.
2012
2013 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2014 bool "Extend with bootloader kernel arguments"
2015 help
2016 The command-line arguments provided by the boot loader will be
2017 appended to the the device tree bootargs property.
2018
2019 endchoice
2020
2021 config CMDLINE
2022 string "Default kernel command string"
2023 default ""
2024 help
2025 On some architectures (EBSA110 and CATS), there is currently no way
2026 for the boot loader to pass arguments to the kernel. For these
2027 architectures, you should supply some command-line options at build
2028 time by entering them here. As a minimum, you should specify the
2029 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2030
2031 choice
2032 prompt "Kernel command line type" if CMDLINE != ""
2033 default CMDLINE_FROM_BOOTLOADER
2034 depends on ATAGS
2035
2036 config CMDLINE_FROM_BOOTLOADER
2037 bool "Use bootloader kernel arguments if available"
2038 help
2039 Uses the command-line options passed by the boot loader. If
2040 the boot loader doesn't provide any, the default kernel command
2041 string provided in CMDLINE will be used.
2042
2043 config CMDLINE_EXTEND
2044 bool "Extend bootloader kernel arguments"
2045 help
2046 The command-line arguments provided by the boot loader will be
2047 appended to the default kernel command string.
2048
2049 config CMDLINE_FORCE
2050 bool "Always use the default kernel command string"
2051 help
2052 Always use the default kernel command string, even if the boot
2053 loader passes other arguments to the kernel.
2054 This is useful if you cannot or don't want to change the
2055 command-line options your boot loader passes to the kernel.
2056 endchoice
2057
2058 config XIP_KERNEL
2059 bool "Kernel Execute-In-Place from ROM"
2060 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2061 help
2062 Execute-In-Place allows the kernel to run from non-volatile storage
2063 directly addressable by the CPU, such as NOR flash. This saves RAM
2064 space since the text section of the kernel is not loaded from flash
2065 to RAM. Read-write sections, such as the data section and stack,
2066 are still copied to RAM. The XIP kernel is not compressed since
2067 it has to run directly from flash, so it will take more space to
2068 store it. The flash address used to link the kernel object files,
2069 and for storing it, is configuration dependent. Therefore, if you
2070 say Y here, you must know the proper physical address where to
2071 store the kernel image depending on your own flash memory usage.
2072
2073 Also note that the make target becomes "make xipImage" rather than
2074 "make zImage" or "make Image". The final kernel binary to put in
2075 ROM memory will be arch/arm/boot/xipImage.
2076
2077 If unsure, say N.
2078
2079 config XIP_PHYS_ADDR
2080 hex "XIP Kernel Physical Location"
2081 depends on XIP_KERNEL
2082 default "0x00080000"
2083 help
2084 This is the physical address in your flash memory the kernel will
2085 be linked for and stored to. This address is dependent on your
2086 own flash usage.
2087
2088 config KEXEC
2089 bool "Kexec system call (EXPERIMENTAL)"
2090 depends on (!SMP || PM_SLEEP_SMP)
2091 help
2092 kexec is a system call that implements the ability to shutdown your
2093 current kernel, and to start another kernel. It is like a reboot
2094 but it is independent of the system firmware. And like a reboot
2095 you can start any kernel with it, not just Linux.
2096
2097 It is an ongoing process to be certain the hardware in a machine
2098 is properly shutdown, so do not be surprised if this code does not
2099 initially work for you.
2100
2101 config ATAGS_PROC
2102 bool "Export atags in procfs"
2103 depends on ATAGS && KEXEC
2104 default y
2105 help
2106 Should the atags used to boot the kernel be exported in an "atags"
2107 file in procfs. Useful with kexec.
2108
2109 config CRASH_DUMP
2110 bool "Build kdump crash kernel (EXPERIMENTAL)"
2111 help
2112 Generate crash dump after being started by kexec. This should
2113 be normally only set in special crash dump kernels which are
2114 loaded in the main kernel with kexec-tools into a specially
2115 reserved region and then later executed after a crash by
2116 kdump/kexec. The crash dump kernel must be compiled to a
2117 memory address not used by the main kernel
2118
2119 For more details see Documentation/kdump/kdump.txt
2120
2121 config AUTO_ZRELADDR
2122 bool "Auto calculation of the decompressed kernel image address"
2123 depends on !ZBOOT_ROM
2124 help
2125 ZRELADDR is the physical address where the decompressed kernel
2126 image will be placed. If AUTO_ZRELADDR is selected, the address
2127 will be determined at run-time by masking the current IP with
2128 0xf8000000. This assumes the zImage being placed in the first 128MB
2129 from start of memory.
2130
2131 endmenu
2132
2133 menu "CPU Power Management"
2134
2135 if ARCH_HAS_CPUFREQ
2136 source "drivers/cpufreq/Kconfig"
2137 endif
2138
2139 source "drivers/cpuidle/Kconfig"
2140
2141 endmenu
2142
2143 menu "Floating point emulation"
2144
2145 comment "At least one emulation must be selected"
2146
2147 config FPE_NWFPE
2148 bool "NWFPE math emulation"
2149 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2150 ---help---
2151 Say Y to include the NWFPE floating point emulator in the kernel.
2152 This is necessary to run most binaries. Linux does not currently
2153 support floating point hardware so you need to say Y here even if
2154 your machine has an FPA or floating point co-processor podule.
2155
2156 You may say N here if you are going to load the Acorn FPEmulator
2157 early in the bootup.
2158
2159 config FPE_NWFPE_XP
2160 bool "Support extended precision"
2161 depends on FPE_NWFPE
2162 help
2163 Say Y to include 80-bit support in the kernel floating-point
2164 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2165 Note that gcc does not generate 80-bit operations by default,
2166 so in most cases this option only enlarges the size of the
2167 floating point emulator without any good reason.
2168
2169 You almost surely want to say N here.
2170
2171 config FPE_FASTFPE
2172 bool "FastFPE math emulation (EXPERIMENTAL)"
2173 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2174 ---help---
2175 Say Y here to include the FAST floating point emulator in the kernel.
2176 This is an experimental much faster emulator which now also has full
2177 precision for the mantissa. It does not support any exceptions.
2178 It is very simple, and approximately 3-6 times faster than NWFPE.
2179
2180 It should be sufficient for most programs. It may be not suitable
2181 for scientific calculations, but you have to check this for yourself.
2182 If you do not feel you need a faster FP emulation you should better
2183 choose NWFPE.
2184
2185 config VFP
2186 bool "VFP-format floating point maths"
2187 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2188 help
2189 Say Y to include VFP support code in the kernel. This is needed
2190 if your hardware includes a VFP unit.
2191
2192 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2193 release notes and additional status information.
2194
2195 Say N if your target does not have VFP hardware.
2196
2197 config VFPv3
2198 bool
2199 depends on VFP
2200 default y if CPU_V7
2201
2202 config NEON
2203 bool "Advanced SIMD (NEON) Extension support"
2204 depends on VFPv3 && CPU_V7
2205 help
2206 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2207 Extension.
2208
2209 config KERNEL_MODE_NEON
2210 bool "Support for NEON in kernel mode"
2211 depends on NEON && AEABI
2212 help
2213 Say Y to include support for NEON in kernel mode.
2214
2215 endmenu
2216
2217 menu "Userspace binary formats"
2218
2219 source "fs/Kconfig.binfmt"
2220
2221 config ARTHUR
2222 tristate "RISC OS personality"
2223 depends on !AEABI
2224 help
2225 Say Y here to include the kernel code necessary if you want to run
2226 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2227 experimental; if this sounds frightening, say N and sleep in peace.
2228 You can also say M here to compile this support as a module (which
2229 will be called arthur).
2230
2231 endmenu
2232
2233 menu "Power management options"
2234
2235 source "kernel/power/Kconfig"
2236
2237 config ARCH_SUSPEND_POSSIBLE
2238 depends on !ARCH_S5PC100
2239 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2240 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2241 def_bool y
2242
2243 config ARM_CPU_SUSPEND
2244 def_bool PM_SLEEP
2245
2246 endmenu
2247
2248 source "net/Kconfig"
2249
2250 source "drivers/Kconfig"
2251
2252 source "fs/Kconfig"
2253
2254 source "arch/arm/Kconfig.debug"
2255
2256 source "security/Kconfig"
2257
2258 source "crypto/Kconfig"
2259
2260 source "lib/Kconfig"
2261
2262 source "arch/arm/kvm/Kconfig"
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