arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
  37         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OLD_SIGACTION
  80         select OLD_SIGSUSPEND3
  81         select PERF_USE_VMALLOC
  82         select RTC_LIB
  83         select SYS_SUPPORTS_APM_EMULATION
  84         # Above selects are sorted alphabetically; please add new ones
  85         # according to that.  Thanks.
  86         help
  87           The ARM series is a line of low-power-consumption RISC chip designs
  88           licensed by ARM Ltd and targeted at embedded applications and
  89           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  90           manufactured, but legacy ARM-based PC hardware remains popular in
  91           Europe.  There is an ARM Linux project with a web page at
  92           <http://www.arm.linux.org.uk/>.
  93
  94 config ARM_HAS_SG_CHAIN
  95         select ARCH_HAS_SG_CHAIN
  96         bool
  97
  98 config NEED_SG_DMA_LENGTH
  99         bool
 100
 101 config ARM_DMA_USE_IOMMU
 102         bool
 103         select ARM_HAS_SG_CHAIN
 104         select NEED_SG_DMA_LENGTH
 105
 106 if ARM_DMA_USE_IOMMU
 107
 108 config ARM_DMA_IOMMU_ALIGNMENT
 109         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 110         range 4 9
 111         default 8
 112         help
 113           DMA mapping framework by default aligns all buffers to the smallest
 114           PAGE_SIZE order which is greater than or equal to the requested buffer
 115           size. This works well for buffers up to a few hundreds kilobytes, but
 116           for larger buffers it just a waste of address space. Drivers which has
 117           relatively small addressing window (like 64Mib) might run out of
 118           virtual space with just a few allocations.
 119
 120           With this parameter you can specify the maximum PAGE_SIZE order for
 121           DMA IOMMU buffers. Larger buffers will be aligned only to this
 122           specified order. The order is expressed as a power of two multiplied
 123           by the PAGE_SIZE.
 124
 125 endif
 126
 127 config MIGHT_HAVE_PCI
 128         bool
 129
 130 config SYS_SUPPORTS_APM_EMULATION
 131         bool
 132
 133 config HAVE_TCM
 134         bool
 135         select GENERIC_ALLOCATOR
 136
 137 config HAVE_PROC_CPU
 138         bool
 139
 140 config NO_IOPORT_MAP
 141         bool
 142
 143 config EISA
 144         bool
 145         ---help---
 146           The Extended Industry Standard Architecture (EISA) bus was
 147           developed as an open alternative to the IBM MicroChannel bus.
 148
 149           The EISA bus provided some of the features of the IBM MicroChannel
 150           bus while maintaining backward compatibility with cards made for
 151           the older ISA bus.  The EISA bus saw limited use between 1988 and
 152           1995 when it was made obsolete by the PCI bus.
 153
 154           Say Y here if you are building a kernel for an EISA-based machine.
 155
 156           Otherwise, say N.
 157
 158 config SBUS
 159         bool
 160
 161 config STACKTRACE_SUPPORT
 162         bool
 163         default y
 164
 165 config HAVE_LATENCYTOP_SUPPORT
 166         bool
 167         depends on !SMP
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         depends on !ARCH_REALVIEW || !SPARSEMEM
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 16MB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_EBSA110 || \
 274                         ARCH_FOOTBRIDGE || \
 275                         ARCH_INTEGRATOR || \
 276                         ARCH_IOP13XX || \
 277                         ARCH_KS8695 || \
 278                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 279         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 280         default 0x20000000 if ARCH_S5PV210
 281         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 282         default 0xc0000000 if ARCH_SA1100
 283         help
 284           Please provide the physical address corresponding to the
 285           location of main memory in your system.
 286
 287 config GENERIC_BUG
 288         def_bool y
 289         depends on BUG
 290
 291 config PGTABLE_LEVELS
 292         int
 293         default 3 if ARM_LPAE
 294         default 2
 295
 296 source "init/Kconfig"
 297
 298 source "kernel/Kconfig.freezer"
 299
 300 menu "System Type"
 301
 302 config MMU
 303         bool "MMU-based Paged Memory Management Support"
 304         default y
 305         help
 306           Select if you want MMU-based virtualised addressing space
 307           support by paged memory management. If unsure, say 'Y'.
 308
 309 #
 310 # The "ARM system type" choice list is ordered alphabetically by option
 311 # text.  Please add new entries in the option alphabetic order.
 312 #
 313 choice
 314         prompt "ARM system type"
 315         default ARCH_VERSATILE if !MMU
 316         default ARCH_MULTIPLATFORM if MMU
 317
 318 config ARCH_MULTIPLATFORM
 319         bool "Allow multiple platforms to be selected"
 320         depends on MMU
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_HAS_SG_CHAIN
 323         select ARM_PATCH_PHYS_VIRT
 324         select AUTO_ZRELADDR
 325         select CLKSRC_OF
 326         select COMMON_CLK
 327         select GENERIC_CLOCKEVENTS
 328         select MIGHT_HAVE_PCI
 329         select MULTI_IRQ_HANDLER
 330         select SPARSE_IRQ
 331         select USE_OF
 332
 333 config ARM_SINGLE_ARMV7M
 334         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 335         depends on !MMU
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_NVIC
 338         select AUTO_ZRELADDR
 339         select CLKSRC_OF
 340         select COMMON_CLK
 341         select CPU_V7M
 342         select GENERIC_CLOCKEVENTS
 343         select NO_IOPORT_MAP
 344         select SPARSE_IRQ
 345         select USE_OF
 346
 347 config ARCH_REALVIEW
 348         bool "ARM Ltd. RealView family"
 349         select ARCH_WANT_OPTIONAL_GPIOLIB
 350         select ARM_AMBA
 351         select ARM_TIMER_SP804
 352         select COMMON_CLK
 353         select COMMON_CLK_VERSATILE
 354         select GENERIC_CLOCKEVENTS
 355         select GPIO_PL061 if GPIOLIB
 356         select ICST
 357         select NEED_MACH_MEMORY_H
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_SCHED_CLOCK
 360         help
 361           This enables support for ARM Ltd RealView boards.
 362
 363 config ARCH_VERSATILE
 364         bool "ARM Ltd. Versatile family"
 365         select ARCH_WANT_OPTIONAL_GPIOLIB
 366         select ARM_AMBA
 367         select ARM_TIMER_SP804
 368         select ARM_VIC
 369         select CLKDEV_LOOKUP
 370         select GENERIC_CLOCKEVENTS
 371         select HAVE_MACH_CLKDEV
 372         select ICST
 373         select PLAT_VERSATILE
 374         select PLAT_VERSATILE_CLOCK
 375         select PLAT_VERSATILE_SCHED_CLOCK
 376         select VERSATILE_FPGA_IRQ
 377         help
 378           This enables support for ARM Ltd Versatile board.
 379
 380 config ARCH_CLPS711X
 381         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select AUTO_ZRELADDR
 384         select CLKSRC_MMIO
 385         select COMMON_CLK
 386         select CPU_ARM720T
 387         select GENERIC_CLOCKEVENTS
 388         select MFD_SYSCON
 389         select SOC_BUS
 390         help
 391           Support for Cirrus Logic 711x/721x/731x based boards.
 392
 393 config ARCH_GEMINI
 394         bool "Cortina Systems Gemini"
 395         select ARCH_REQUIRE_GPIOLIB
 396         select CLKSRC_MMIO
 397         select CPU_FA526
 398         select GENERIC_CLOCKEVENTS
 399         help
 400           Support for the Cortina Systems Gemini family SoCs
 401
 402 config ARCH_EBSA110
 403         bool "EBSA-110"
 404         select ARCH_USES_GETTIMEOFFSET
 405         select CPU_SA110
 406         select ISA
 407         select NEED_MACH_IO_H
 408         select NEED_MACH_MEMORY_H
 409         select NO_IOPORT_MAP
 410         help
 411           This is an evaluation board for the StrongARM processor available
 412           from Digital. It has limited hardware on-board, including an
 413           Ethernet interface, two PCMCIA sockets, two serial ports and a
 414           parallel port.
 415
 416 config ARCH_EP93XX
 417         bool "EP93xx-based"
 418         select ARCH_HAS_HOLES_MEMORYMODEL
 419         select ARCH_REQUIRE_GPIOLIB
 420         select ARM_AMBA
 421         select ARM_PATCH_PHYS_VIRT
 422         select ARM_VIC
 423         select AUTO_ZRELADDR
 424         select CLKDEV_LOOKUP
 425         select CLKSRC_MMIO
 426         select CPU_ARM920T
 427         select GENERIC_CLOCKEVENTS
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         select MULTI_IRQ_HANDLER
 542         help
 543           Support for the following Marvell Orion 5x series SoCs:
 544           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 545           Orion-2 (5281), Orion-1-90 (6183).
 546
 547 config ARCH_MMP
 548         bool "Marvell PXA168/910/MMP2"
 549         depends on MMU
 550         select ARCH_REQUIRE_GPIOLIB
 551         select CLKDEV_LOOKUP
 552         select GENERIC_ALLOCATOR
 553         select GENERIC_CLOCKEVENTS
 554         select GPIO_PXA
 555         select IRQ_DOMAIN
 556         select MULTI_IRQ_HANDLER
 557         select PINCTRL
 558         select PLAT_PXA
 559         select SPARSE_IRQ
 560         help
 561           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 562
 563 config ARCH_KS8695
 564         bool "Micrel/Kendin KS8695"
 565         select ARCH_REQUIRE_GPIOLIB
 566         select CLKSRC_MMIO
 567         select CPU_ARM922T
 568         select GENERIC_CLOCKEVENTS
 569         select NEED_MACH_MEMORY_H
 570         help
 571           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 572           System-on-Chip devices.
 573
 574 config ARCH_W90X900
 575         bool "Nuvoton W90X900 CPU"
 576         select ARCH_REQUIRE_GPIOLIB
 577         select CLKDEV_LOOKUP
 578         select CLKSRC_MMIO
 579         select CPU_ARM926T
 580         select GENERIC_CLOCKEVENTS
 581         help
 582           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 583           At present, the w90x900 has been renamed nuc900, regarding
 584           the ARM series product line, you can login the following
 585           link address to know more.
 586
 587           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 588                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 589
 590 config ARCH_LPC32XX
 591         bool "NXP LPC32XX"
 592         select ARCH_REQUIRE_GPIOLIB
 593         select ARM_AMBA
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_MMIO
 596         select CPU_ARM926T
 597         select GENERIC_CLOCKEVENTS
 598         select HAVE_IDE
 599         select USE_OF
 600         help
 601           Support for the NXP LPC32XX family of processors
 602
 603 config ARCH_PXA
 604         bool "PXA2xx/PXA3xx-based"
 605         depends on MMU
 606         select ARCH_MTD_XIP
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_CPU_SUSPEND if PM
 609         select AUTO_ZRELADDR
 610         select COMMON_CLK
 611         select CLKDEV_LOOKUP
 612         select CLKSRC_MMIO
 613         select CLKSRC_OF
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select IRQ_DOMAIN
 618         select MULTI_IRQ_HANDLER
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_SHMOBILE_LEGACY
 625         bool "Renesas ARM SoCs (non-multiplatform)"
 626         select ARCH_SHMOBILE
 627         select ARM_PATCH_PHYS_VIRT if MMU
 628         select CLKDEV_LOOKUP
 629         select CPU_V7
 630         select GENERIC_CLOCKEVENTS
 631         select HAVE_ARM_SCU if SMP
 632         select HAVE_ARM_TWD if SMP
 633         select HAVE_SMP
 634         select MIGHT_HAVE_CACHE_L2X0
 635         select MULTI_IRQ_HANDLER
 636         select NO_IOPORT_MAP
 637         select PINCTRL
 638         select PM_GENERIC_DOMAINS if PM
 639         select SH_CLK_CPG
 640         select SPARSE_IRQ
 641         help
 642           Support for Renesas ARM SoC platforms using a non-multiplatform
 643           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 644           and RZ families.
 645
 646 config ARCH_RPC
 647         bool "RiscPC"
 648         depends on MMU
 649         select ARCH_ACORN
 650         select ARCH_MAY_HAVE_PC_FDC
 651         select ARCH_SPARSEMEM_ENABLE
 652         select ARCH_USES_GETTIMEOFFSET
 653         select CPU_SA110
 654         select FIQ
 655         select HAVE_IDE
 656         select HAVE_PATA_PLATFORM
 657         select ISA_DMA_API
 658         select NEED_MACH_IO_H
 659         select NEED_MACH_MEMORY_H
 660         select NO_IOPORT_MAP
 661         select VIRT_TO_BUS
 662         help
 663           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 664           CD-ROM interface, serial and parallel port, and the floppy drive.
 665
 666 config ARCH_SA1100
 667         bool "SA1100-based"
 668         select ARCH_MTD_XIP
 669         select ARCH_REQUIRE_GPIOLIB
 670         select ARCH_SPARSEMEM_ENABLE
 671         select CLKDEV_LOOKUP
 672         select CLKSRC_MMIO
 673         select CPU_FREQ
 674         select CPU_SA1100
 675         select GENERIC_CLOCKEVENTS
 676         select HAVE_IDE
 677         select IRQ_DOMAIN
 678         select ISA
 679         select MULTI_IRQ_HANDLER
 680         select NEED_MACH_MEMORY_H
 681         select SPARSE_IRQ
 682         help
 683           Support for StrongARM 11x0 based boards.
 684
 685 config ARCH_S3C24XX
 686         bool "Samsung S3C24XX SoCs"
 687         select ARCH_REQUIRE_GPIOLIB
 688         select ATAGS
 689         select CLKDEV_LOOKUP
 690         select CLKSRC_SAMSUNG_PWM
 691         select GENERIC_CLOCKEVENTS
 692         select GPIO_SAMSUNG
 693         select HAVE_S3C2410_I2C if I2C
 694         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 695         select HAVE_S3C_RTC if RTC_CLASS
 696         select MULTI_IRQ_HANDLER
 697         select NEED_MACH_IO_H
 698         select SAMSUNG_ATAGS
 699         help
 700           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 701           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 702           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 703           Samsung SMDK2410 development board (and derivatives).
 704
 705 config ARCH_S3C64XX
 706         bool "Samsung S3C64XX"
 707         select ARCH_REQUIRE_GPIOLIB
 708         select ARM_AMBA
 709         select ARM_VIC
 710         select ATAGS
 711         select CLKDEV_LOOKUP
 712         select CLKSRC_SAMSUNG_PWM
 713         select COMMON_CLK_SAMSUNG
 714         select CPU_V6K
 715         select GENERIC_CLOCKEVENTS
 716         select GPIO_SAMSUNG
 717         select HAVE_S3C2410_I2C if I2C
 718         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 719         select HAVE_TCM
 720         select NO_IOPORT_MAP
 721         select PLAT_SAMSUNG
 722         select PM_GENERIC_DOMAINS if PM
 723         select S3C_DEV_NAND
 724         select S3C_GPIO_TRACK
 725         select SAMSUNG_ATAGS
 726         select SAMSUNG_WAKEMASK
 727         select SAMSUNG_WDT_RESET
 728         help
 729           Samsung S3C64XX series based systems
 730
 731 config ARCH_DAVINCI
 732         bool "TI DaVinci"
 733         select ARCH_HAS_HOLES_MEMORYMODEL
 734         select ARCH_REQUIRE_GPIOLIB
 735         select CLKDEV_LOOKUP
 736         select GENERIC_ALLOCATOR
 737         select GENERIC_CLOCKEVENTS
 738         select GENERIC_IRQ_CHIP
 739         select HAVE_IDE
 740         select TI_PRIV_EDMA
 741         select USE_OF
 742         select ZONE_DMA
 743         help
 744           Support for TI's DaVinci platform.
 745
 746 config ARCH_OMAP1
 747         bool "TI OMAP1"
 748         depends on MMU
 749         select ARCH_HAS_HOLES_MEMORYMODEL
 750         select ARCH_OMAP
 751         select ARCH_REQUIRE_GPIOLIB
 752         select CLKDEV_LOOKUP
 753         select CLKSRC_MMIO
 754         select GENERIC_CLOCKEVENTS
 755         select GENERIC_IRQ_CHIP
 756         select HAVE_IDE
 757         select IRQ_DOMAIN
 758         select MULTI_IRQ_HANDLER
 759         select NEED_MACH_IO_H if PCCARD
 760         select NEED_MACH_MEMORY_H
 761         select SPARSE_IRQ
 762         help
 763           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 764
 765 endchoice
 766
 767 menu "Multiple platform selection"
 768         depends on ARCH_MULTIPLATFORM
 769
 770 comment "CPU Core family selection"
 771
 772 config ARCH_MULTI_V4
 773         bool "ARMv4 based platforms (FA526)"
 774         depends on !ARCH_MULTI_V6_V7
 775         select ARCH_MULTI_V4_V5
 776         select CPU_FA526
 777
 778 config ARCH_MULTI_V4T
 779         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 780         depends on !ARCH_MULTI_V6_V7
 781         select ARCH_MULTI_V4_V5
 782         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 783                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 784                 CPU_ARM925T || CPU_ARM940T)
 785
 786 config ARCH_MULTI_V5
 787         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 788         depends on !ARCH_MULTI_V6_V7
 789         select ARCH_MULTI_V4_V5
 790         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 791                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 792                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 793
 794 config ARCH_MULTI_V4_V5
 795         bool
 796
 797 config ARCH_MULTI_V6
 798         bool "ARMv6 based platforms (ARM11)"
 799         select ARCH_MULTI_V6_V7
 800         select CPU_V6K
 801
 802 config ARCH_MULTI_V7
 803         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 804         default y
 805         select ARCH_MULTI_V6_V7
 806         select CPU_V7
 807         select HAVE_SMP
 808
 809 config ARCH_MULTI_V6_V7
 810         bool
 811         select MIGHT_HAVE_CACHE_L2X0
 812
 813 config ARCH_MULTI_CPU_AUTO
 814         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 815         select ARCH_MULTI_V5
 816
 817 endmenu
 818
 819 config ARCH_VIRT
 820         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 821         select ARM_AMBA
 822         select ARM_GIC
 823         select ARM_GIC_V3
 824         select ARM_PSCI
 825         select HAVE_ARM_ARCH_TIMER
 826
 827 #
 828 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 829 # Kconfigs may be included either alphabetically (according to the
 830 # plat- suffix) or along side the corresponding mach-* source.
 831 #
 832 source "arch/arm/mach-mvebu/Kconfig"
 833
 834 source "arch/arm/mach-alpine/Kconfig"
 835
 836 source "arch/arm/mach-asm9260/Kconfig"
 837
 838 source "arch/arm/mach-at91/Kconfig"
 839
 840 source "arch/arm/mach-axxia/Kconfig"
 841
 842 source "arch/arm/mach-bcm/Kconfig"
 843
 844 source "arch/arm/mach-berlin/Kconfig"
 845
 846 source "arch/arm/mach-clps711x/Kconfig"
 847
 848 source "arch/arm/mach-cns3xxx/Kconfig"
 849
 850 source "arch/arm/mach-davinci/Kconfig"
 851
 852 source "arch/arm/mach-digicolor/Kconfig"
 853
 854 source "arch/arm/mach-dove/Kconfig"
 855
 856 source "arch/arm/mach-ep93xx/Kconfig"
 857
 858 source "arch/arm/mach-footbridge/Kconfig"
 859
 860 source "arch/arm/mach-gemini/Kconfig"
 861
 862 source "arch/arm/mach-highbank/Kconfig"
 863
 864 source "arch/arm/mach-hisi/Kconfig"
 865
 866 source "arch/arm/mach-integrator/Kconfig"
 867
 868 source "arch/arm/mach-iop32x/Kconfig"
 869
 870 source "arch/arm/mach-iop33x/Kconfig"
 871
 872 source "arch/arm/mach-iop13xx/Kconfig"
 873
 874 source "arch/arm/mach-ixp4xx/Kconfig"
 875
 876 source "arch/arm/mach-keystone/Kconfig"
 877
 878 source "arch/arm/mach-ks8695/Kconfig"
 879
 880 source "arch/arm/mach-meson/Kconfig"
 881
 882 source "arch/arm/mach-moxart/Kconfig"
 883
 884 source "arch/arm/mach-mv78xx0/Kconfig"
 885
 886 source "arch/arm/mach-imx/Kconfig"
 887
 888 source "arch/arm/mach-mediatek/Kconfig"
 889
 890 source "arch/arm/mach-mxs/Kconfig"
 891
 892 source "arch/arm/mach-netx/Kconfig"
 893
 894 source "arch/arm/mach-nomadik/Kconfig"
 895
 896 source "arch/arm/mach-nspire/Kconfig"
 897
 898 source "arch/arm/plat-omap/Kconfig"
 899
 900 source "arch/arm/mach-omap1/Kconfig"
 901
 902 source "arch/arm/mach-omap2/Kconfig"
 903
 904 source "arch/arm/mach-orion5x/Kconfig"
 905
 906 source "arch/arm/mach-picoxcell/Kconfig"
 907
 908 source "arch/arm/mach-pxa/Kconfig"
 909 source "arch/arm/plat-pxa/Kconfig"
 910
 911 source "arch/arm/mach-mmp/Kconfig"
 912
 913 source "arch/arm/mach-qcom/Kconfig"
 914
 915 source "arch/arm/mach-realview/Kconfig"
 916
 917 source "arch/arm/mach-rockchip/Kconfig"
 918
 919 source "arch/arm/mach-sa1100/Kconfig"
 920
 921 source "arch/arm/mach-socfpga/Kconfig"
 922
 923 source "arch/arm/mach-spear/Kconfig"
 924
 925 source "arch/arm/mach-sti/Kconfig"
 926
 927 source "arch/arm/mach-s3c24xx/Kconfig"
 928
 929 source "arch/arm/mach-s3c64xx/Kconfig"
 930
 931 source "arch/arm/mach-s5pv210/Kconfig"
 932
 933 source "arch/arm/mach-exynos/Kconfig"
 934 source "arch/arm/plat-samsung/Kconfig"
 935
 936 source "arch/arm/mach-shmobile/Kconfig"
 937
 938 source "arch/arm/mach-sunxi/Kconfig"
 939
 940 source "arch/arm/mach-prima2/Kconfig"
 941
 942 source "arch/arm/mach-tegra/Kconfig"
 943
 944 source "arch/arm/mach-u300/Kconfig"
 945
 946 source "arch/arm/mach-uniphier/Kconfig"
 947
 948 source "arch/arm/mach-ux500/Kconfig"
 949
 950 source "arch/arm/mach-versatile/Kconfig"
 951
 952 source "arch/arm/mach-vexpress/Kconfig"
 953 source "arch/arm/plat-versatile/Kconfig"
 954
 955 source "arch/arm/mach-vt8500/Kconfig"
 956
 957 source "arch/arm/mach-w90x900/Kconfig"
 958
 959 source "arch/arm/mach-zx/Kconfig"
 960
 961 source "arch/arm/mach-zynq/Kconfig"
 962
 963 # ARMv7-M architecture
 964 config ARCH_EFM32
 965         bool "Energy Micro efm32"
 966         depends on ARM_SINGLE_ARMV7M
 967         select ARCH_REQUIRE_GPIOLIB
 968         help
 969           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 970           processors.
 971
 972 config ARCH_LPC18XX
 973         bool "NXP LPC18xx/LPC43xx"
 974         depends on ARM_SINGLE_ARMV7M
 975         select ARCH_HAS_RESET_CONTROLLER
 976         select ARM_AMBA
 977         select CLKSRC_LPC32XX
 978         select PINCTRL
 979         help
 980           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 981           high performance microcontrollers.
 982
 983 config ARCH_STM32
 984         bool "STMicrolectronics STM32"
 985         depends on ARM_SINGLE_ARMV7M
 986         select ARCH_HAS_RESET_CONTROLLER
 987         select ARMV7M_SYSTICK
 988         select CLKSRC_STM32
 989         select RESET_CONTROLLER
 990         help
 991           Support for STMicroelectronics STM32 processors.
 992
 993 # Definitions to make life easier
 994 config ARCH_ACORN
 995         bool
 996
 997 config PLAT_IOP
 998         bool
 999         select GENERIC_CLOCKEVENTS
1000
1001 config PLAT_ORION
1002         bool
1003         select CLKSRC_MMIO
1004         select COMMON_CLK
1005         select GENERIC_IRQ_CHIP
1006         select IRQ_DOMAIN
1007
1008 config PLAT_ORION_LEGACY
1009         bool
1010         select PLAT_ORION
1011
1012 config PLAT_PXA
1013         bool
1014
1015 config PLAT_VERSATILE
1016         bool
1017
1018 source "arch/arm/firmware/Kconfig"
1019
1020 source arch/arm/mm/Kconfig
1021
1022 config IWMMXT
1023         bool "Enable iWMMXt support"
1024         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1025         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1026         help
1027           Enable support for iWMMXt context switching at run time if
1028           running on a CPU that supports it.
1029
1030 config MULTI_IRQ_HANDLER
1031         bool
1032         help
1033           Allow each machine to specify it's own IRQ handler at run time.
1034
1035 if !MMU
1036 source "arch/arm/Kconfig-nommu"
1037 endif
1038
1039 config PJ4B_ERRATA_4742
1040         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1041         depends on CPU_PJ4B && MACH_ARMADA_370
1042         default y
1043         help
1044           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1045           Event (WFE) IDLE states, a specific timing sensitivity exists between
1046           the retiring WFI/WFE instructions and the newly issued subsequent
1047           instructions.  This sensitivity can result in a CPU hang scenario.
1048           Workaround:
1049           The software must insert either a Data Synchronization Barrier (DSB)
1050           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1051           instruction
1052
1053 config ARM_ERRATA_326103
1054         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1055         depends on CPU_V6
1056         help
1057           Executing a SWP instruction to read-only memory does not set bit 11
1058           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1059           treat the access as a read, preventing a COW from occurring and
1060           causing the faulting task to livelock.
1061
1062 config ARM_ERRATA_411920
1063         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1064         depends on CPU_V6 || CPU_V6K
1065         help
1066           Invalidation of the Instruction Cache operation can
1067           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1068           It does not affect the MPCore. This option enables the ARM Ltd.
1069           recommended workaround.
1070
1071 config ARM_ERRATA_430973
1072         bool "ARM errata: Stale prediction on replaced interworking branch"
1073         depends on CPU_V7
1074         help
1075           This option enables the workaround for the 430973 Cortex-A8
1076           r1p* erratum. If a code sequence containing an ARM/Thumb
1077           interworking branch is replaced with another code sequence at the
1078           same virtual address, whether due to self-modifying code or virtual
1079           to physical address re-mapping, Cortex-A8 does not recover from the
1080           stale interworking branch prediction. This results in Cortex-A8
1081           executing the new code sequence in the incorrect ARM or Thumb state.
1082           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1083           and also flushes the branch target cache at every context switch.
1084           Note that setting specific bits in the ACTLR register may not be
1085           available in non-secure mode.
1086
1087 config ARM_ERRATA_458693
1088         bool "ARM errata: Processor deadlock when a false hazard is created"
1089         depends on CPU_V7
1090         depends on !ARCH_MULTIPLATFORM
1091         help
1092           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1093           erratum. For very specific sequences of memory operations, it is
1094           possible for a hazard condition intended for a cache line to instead
1095           be incorrectly associated with a different cache line. This false
1096           hazard might then cause a processor deadlock. The workaround enables
1097           the L1 caching of the NEON accesses and disables the PLD instruction
1098           in the ACTLR register. Note that setting specific bits in the ACTLR
1099           register may not be available in non-secure mode.
1100
1101 config ARM_ERRATA_460075
1102         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1103         depends on CPU_V7
1104         depends on !ARCH_MULTIPLATFORM
1105         help
1106           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1107           erratum. Any asynchronous access to the L2 cache may encounter a
1108           situation in which recent store transactions to the L2 cache are lost
1109           and overwritten with stale memory contents from external memory. The
1110           workaround disables the write-allocate mode for the L2 cache via the
1111           ACTLR register. Note that setting specific bits in the ACTLR register
1112           may not be available in non-secure mode.
1113
1114 config ARM_ERRATA_742230
1115         bool "ARM errata: DMB operation may be faulty"
1116         depends on CPU_V7 && SMP
1117         depends on !ARCH_MULTIPLATFORM
1118         help
1119           This option enables the workaround for the 742230 Cortex-A9
1120           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1121           between two write operations may not ensure the correct visibility
1122           ordering of the two writes. This workaround sets a specific bit in
1123           the diagnostic register of the Cortex-A9 which causes the DMB
1124           instruction to behave as a DSB, ensuring the correct behaviour of
1125           the two writes.
1126
1127 config ARM_ERRATA_742231
1128         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1129         depends on CPU_V7 && SMP
1130         depends on !ARCH_MULTIPLATFORM
1131         help
1132           This option enables the workaround for the 742231 Cortex-A9
1133           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1134           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1135           accessing some data located in the same cache line, may get corrupted
1136           data due to bad handling of the address hazard when the line gets
1137           replaced from one of the CPUs at the same time as another CPU is
1138           accessing it. This workaround sets specific bits in the diagnostic
1139           register of the Cortex-A9 which reduces the linefill issuing
1140           capabilities of the processor.
1141
1142 config ARM_ERRATA_643719
1143         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1144         depends on CPU_V7 && SMP
1145         default y
1146         help
1147           This option enables the workaround for the 643719 Cortex-A9 (prior to
1148           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1149           register returns zero when it should return one. The workaround
1150           corrects this value, ensuring cache maintenance operations which use
1151           it behave as intended and avoiding data corruption.
1152
1153 config ARM_ERRATA_720789
1154         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1155         depends on CPU_V7
1156         help
1157           This option enables the workaround for the 720789 Cortex-A9 (prior to
1158           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1159           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1160           As a consequence of this erratum, some TLB entries which should be
1161           invalidated are not, resulting in an incoherency in the system page
1162           tables. The workaround changes the TLB flushing routines to invalidate
1163           entries regardless of the ASID.
1164
1165 config ARM_ERRATA_743622
1166         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1167         depends on CPU_V7
1168         depends on !ARCH_MULTIPLATFORM
1169         help
1170           This option enables the workaround for the 743622 Cortex-A9
1171           (r2p*) erratum. Under very rare conditions, a faulty
1172           optimisation in the Cortex-A9 Store Buffer may lead to data
1173           corruption. This workaround sets a specific bit in the diagnostic
1174           register of the Cortex-A9 which disables the Store Buffer
1175           optimisation, preventing the defect from occurring. This has no
1176           visible impact on the overall performance or power consumption of the
1177           processor.
1178
1179 config ARM_ERRATA_751472
1180         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1181         depends on CPU_V7
1182         depends on !ARCH_MULTIPLATFORM
1183         help
1184           This option enables the workaround for the 751472 Cortex-A9 (prior
1185           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1186           completion of a following broadcasted operation if the second
1187           operation is received by a CPU before the ICIALLUIS has completed,
1188           potentially leading to corrupted entries in the cache or TLB.
1189
1190 config ARM_ERRATA_754322
1191         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1192         depends on CPU_V7
1193         help
1194           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1195           r3p*) erratum. A speculative memory access may cause a page table walk
1196           which starts prior to an ASID switch but completes afterwards. This
1197           can populate the micro-TLB with a stale entry which may be hit with
1198           the new ASID. This workaround places two dsb instructions in the mm
1199           switching code so that no page table walks can cross the ASID switch.
1200
1201 config ARM_ERRATA_754327
1202         bool "ARM errata: no automatic Store Buffer drain"
1203         depends on CPU_V7 && SMP
1204         help
1205           This option enables the workaround for the 754327 Cortex-A9 (prior to
1206           r2p0) erratum. The Store Buffer does not have any automatic draining
1207           mechanism and therefore a livelock may occur if an external agent
1208           continuously polls a memory location waiting to observe an update.
1209           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1210           written polling loops from denying visibility of updates to memory.
1211
1212 config ARM_ERRATA_364296
1213         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1214         depends on CPU_V6
1215         help
1216           This options enables the workaround for the 364296 ARM1136
1217           r0p2 erratum (possible cache data corruption with
1218           hit-under-miss enabled). It sets the undocumented bit 31 in
1219           the auxiliary control register and the FI bit in the control
1220           register, thus disabling hit-under-miss without putting the
1221           processor into full low interrupt latency mode. ARM11MPCore
1222           is not affected.
1223
1224 config ARM_ERRATA_764369
1225         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1226         depends on CPU_V7 && SMP
1227         help
1228           This option enables the workaround for erratum 764369
1229           affecting Cortex-A9 MPCore with two or more processors (all
1230           current revisions). Under certain timing circumstances, a data
1231           cache line maintenance operation by MVA targeting an Inner
1232           Shareable memory region may fail to proceed up to either the
1233           Point of Coherency or to the Point of Unification of the
1234           system. This workaround adds a DSB instruction before the
1235           relevant cache maintenance functions and sets a specific bit
1236           in the diagnostic control register of the SCU.
1237
1238 config ARM_ERRATA_775420
1239        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1240        depends on CPU_V7
1241        help
1242          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1243          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1244          operation aborts with MMU exception, it might cause the processor
1245          to deadlock. This workaround puts DSB before executing ISB if
1246          an abort may occur on cache maintenance.
1247
1248 config ARM_ERRATA_798181
1249         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1250         depends on CPU_V7 && SMP
1251         help
1252           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1253           adequately shooting down all use of the old entries. This
1254           option enables the Linux kernel workaround for this erratum
1255           which sends an IPI to the CPUs that are running the same ASID
1256           as the one being invalidated.
1257
1258 config ARM_ERRATA_773022
1259         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1260         depends on CPU_V7
1261         help
1262           This option enables the workaround for the 773022 Cortex-A15
1263           (up to r0p4) erratum. In certain rare sequences of code, the
1264           loop buffer may deliver incorrect instructions. This
1265           workaround disables the loop buffer to avoid the erratum.
1266
1267 endmenu
1268
1269 source "arch/arm/common/Kconfig"
1270
1271 menu "Bus support"
1272
1273 config ISA
1274         bool
1275         help
1276           Find out whether you have ISA slots on your motherboard.  ISA is the
1277           name of a bus system, i.e. the way the CPU talks to the other stuff
1278           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1279           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1280           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1281
1282 # Select ISA DMA controller support
1283 config ISA_DMA
1284         bool
1285         select ISA_DMA_API
1286
1287 # Select ISA DMA interface
1288 config ISA_DMA_API
1289         bool
1290
1291 config PCI
1292         bool "PCI support" if MIGHT_HAVE_PCI
1293         help
1294           Find out whether you have a PCI motherboard. PCI is the name of a
1295           bus system, i.e. the way the CPU talks to the other stuff inside
1296           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1297           VESA. If you have PCI, say Y, otherwise N.
1298
1299 config PCI_DOMAINS
1300         bool
1301         depends on PCI
1302
1303 config PCI_DOMAINS_GENERIC
1304         def_bool PCI_DOMAINS
1305
1306 config PCI_NANOENGINE
1307         bool "BSE nanoEngine PCI support"
1308         depends on SA1100_NANOENGINE
1309         help
1310           Enable PCI on the BSE nanoEngine board.
1311
1312 config PCI_SYSCALL
1313         def_bool PCI
1314
1315 config PCI_HOST_ITE8152
1316         bool
1317         depends on PCI && MACH_ARMCORE
1318         default y
1319         select DMABOUNCE
1320
1321 source "drivers/pci/Kconfig"
1322 source "drivers/pci/pcie/Kconfig"
1323
1324 source "drivers/pcmcia/Kconfig"
1325
1326 endmenu
1327
1328 menu "Kernel Features"
1329
1330 config HAVE_SMP
1331         bool
1332         help
1333           This option should be selected by machines which have an SMP-
1334           capable CPU.
1335
1336           The only effect of this option is to make the SMP-related
1337           options available to the user for configuration.
1338
1339 config SMP
1340         bool "Symmetric Multi-Processing"
1341         depends on CPU_V6K || CPU_V7
1342         depends on GENERIC_CLOCKEVENTS
1343         depends on HAVE_SMP
1344         depends on MMU || ARM_MPU
1345         select IRQ_WORK
1346         help
1347           This enables support for systems with more than one CPU. If you have
1348           a system with only one CPU, say N. If you have a system with more
1349           than one CPU, say Y.
1350
1351           If you say N here, the kernel will run on uni- and multiprocessor
1352           machines, but will use only one CPU of a multiprocessor machine. If
1353           you say Y here, the kernel will run on many, but not all,
1354           uniprocessor machines. On a uniprocessor machine, the kernel
1355           will run faster if you say N here.
1356
1357           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1358           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1359           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1360
1361           If you don't know what to do here, say N.
1362
1363 config SMP_ON_UP
1364         bool "Allow booting SMP kernel on uniprocessor systems"
1365         depends on SMP && !XIP_KERNEL && MMU
1366         default y
1367         help
1368           SMP kernels contain instructions which fail on non-SMP processors.
1369           Enabling this option allows the kernel to modify itself to make
1370           these instructions safe.  Disabling it allows about 1K of space
1371           savings.
1372
1373           If you don't know what to do here, say Y.
1374
1375 config ARM_CPU_TOPOLOGY
1376         bool "Support cpu topology definition"
1377         depends on SMP && CPU_V7
1378         default y
1379         help
1380           Support ARM cpu topology definition. The MPIDR register defines
1381           affinity between processors which is then used to describe the cpu
1382           topology of an ARM System.
1383
1384 config SCHED_MC
1385         bool "Multi-core scheduler support"
1386         depends on ARM_CPU_TOPOLOGY
1387         help
1388           Multi-core scheduler support improves the CPU scheduler's decision
1389           making when dealing with multi-core CPU chips at a cost of slightly
1390           increased overhead in some places. If unsure say N here.
1391
1392 config SCHED_SMT
1393         bool "SMT scheduler support"
1394         depends on ARM_CPU_TOPOLOGY
1395         help
1396           Improves the CPU scheduler's decision making when dealing with
1397           MultiThreading at a cost of slightly increased overhead in some
1398           places. If unsure say N here.
1399
1400 config HAVE_ARM_SCU
1401         bool
1402         help
1403           This option enables support for the ARM system coherency unit
1404
1405 config HAVE_ARM_ARCH_TIMER
1406         bool "Architected timer support"
1407         depends on CPU_V7
1408         select ARM_ARCH_TIMER
1409         select GENERIC_CLOCKEVENTS
1410         help
1411           This option enables support for the ARM architected timer
1412
1413 config HAVE_ARM_TWD
1414         bool
1415         select CLKSRC_OF if OF
1416         help
1417           This options enables support for the ARM timer and watchdog unit
1418
1419 config MCPM
1420         bool "Multi-Cluster Power Management"
1421         depends on CPU_V7 && SMP
1422         help
1423           This option provides the common power management infrastructure
1424           for (multi-)cluster based systems, such as big.LITTLE based
1425           systems.
1426
1427 config MCPM_QUAD_CLUSTER
1428         bool
1429         depends on MCPM
1430         help
1431           To avoid wasting resources unnecessarily, MCPM only supports up
1432           to 2 clusters by default.
1433           Platforms with 3 or 4 clusters that use MCPM must select this
1434           option to allow the additional clusters to be managed.
1435
1436 config BIG_LITTLE
1437         bool "big.LITTLE support (Experimental)"
1438         depends on CPU_V7 && SMP
1439         select MCPM
1440         help
1441           This option enables support selections for the big.LITTLE
1442           system architecture.
1443
1444 config BL_SWITCHER
1445         bool "big.LITTLE switcher support"
1446         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1447         select ARM_CPU_SUSPEND
1448         select CPU_PM
1449         help
1450           The big.LITTLE "switcher" provides the core functionality to
1451           transparently handle transition between a cluster of A15's
1452           and a cluster of A7's in a big.LITTLE system.
1453
1454 config BL_SWITCHER_DUMMY_IF
1455         tristate "Simple big.LITTLE switcher user interface"
1456         depends on BL_SWITCHER && DEBUG_KERNEL
1457         help
1458           This is a simple and dummy char dev interface to control
1459           the big.LITTLE switcher core code.  It is meant for
1460           debugging purposes only.
1461
1462 choice
1463         prompt "Memory split"
1464         depends on MMU
1465         default VMSPLIT_3G
1466         help
1467           Select the desired split between kernel and user memory.
1468
1469           If you are not absolutely sure what you are doing, leave this
1470           option alone!
1471
1472         config VMSPLIT_3G
1473                 bool "3G/1G user/kernel split"
1474         config VMSPLIT_3G_OPT
1475                 bool "3G/1G user/kernel split (for full 1G low memory)"
1476         config VMSPLIT_2G
1477                 bool "2G/2G user/kernel split"
1478         config VMSPLIT_1G
1479                 bool "1G/3G user/kernel split"
1480 endchoice
1481
1482 config PAGE_OFFSET
1483         hex
1484         default PHYS_OFFSET if !MMU
1485         default 0x40000000 if VMSPLIT_1G
1486         default 0x80000000 if VMSPLIT_2G
1487         default 0xB0000000 if VMSPLIT_3G_OPT
1488         default 0xC0000000
1489
1490 config NR_CPUS
1491         int "Maximum number of CPUs (2-32)"
1492         range 2 32
1493         depends on SMP
1494         default "4"
1495
1496 config HOTPLUG_CPU
1497         bool "Support for hot-pluggable CPUs"
1498         depends on SMP
1499         help
1500           Say Y here to experiment with turning CPUs off and on.  CPUs
1501           can be controlled through /sys/devices/system/cpu.
1502
1503 config ARM_PSCI
1504         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1505         depends on CPU_V7
1506         select ARM_PSCI_FW
1507         help
1508           Say Y here if you want Linux to communicate with system firmware
1509           implementing the PSCI specification for CPU-centric power
1510           management operations described in ARM document number ARM DEN
1511           0022A ("Power State Coordination Interface System Software on
1512           ARM processors").
1513
1514 # The GPIO number here must be sorted by descending number. In case of
1515 # a multiplatform kernel, we just want the highest value required by the
1516 # selected platforms.
1517 config ARCH_NR_GPIO
1518         int
1519         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1520                 ARCH_ZYNQ
1521         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1522                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1523         default 416 if ARCH_SUNXI
1524         default 392 if ARCH_U8500
1525         default 352 if ARCH_VT8500
1526         default 288 if ARCH_ROCKCHIP
1527         default 264 if MACH_H4700
1528         default 0
1529         help
1530           Maximum number of GPIOs in the system.
1531
1532           If unsure, leave the default value.
1533
1534 source kernel/Kconfig.preempt
1535
1536 config HZ_FIXED
1537         int
1538         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1539                 ARCH_S5PV210 || ARCH_EXYNOS4
1540         default 128 if SOC_AT91RM9200
1541         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1542         default 0
1543
1544 choice
1545         depends on HZ_FIXED = 0
1546         prompt "Timer frequency"
1547
1548 config HZ_100
1549         bool "100 Hz"
1550
1551 config HZ_200
1552         bool "200 Hz"
1553
1554 config HZ_250
1555         bool "250 Hz"
1556
1557 config HZ_300
1558         bool "300 Hz"
1559
1560 config HZ_500
1561         bool "500 Hz"
1562
1563 config HZ_1000
1564         bool "1000 Hz"
1565
1566 endchoice
1567
1568 config HZ
1569         int
1570         default HZ_FIXED if HZ_FIXED != 0
1571         default 100 if HZ_100
1572         default 200 if HZ_200
1573         default 250 if HZ_250
1574         default 300 if HZ_300
1575         default 500 if HZ_500
1576         default 1000
1577
1578 config SCHED_HRTICK
1579         def_bool HIGH_RES_TIMERS
1580
1581 config THUMB2_KERNEL
1582         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1583         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1584         default y if CPU_THUMBONLY
1585         select AEABI
1586         select ARM_ASM_UNIFIED
1587         select ARM_UNWIND
1588         help
1589           By enabling this option, the kernel will be compiled in
1590           Thumb-2 mode. A compiler/assembler that understand the unified
1591           ARM-Thumb syntax is needed.
1592
1593           If unsure, say N.
1594
1595 config THUMB2_AVOID_R_ARM_THM_JUMP11
1596         bool "Work around buggy Thumb-2 short branch relocations in gas"
1597         depends on THUMB2_KERNEL && MODULES
1598         default y
1599         help
1600           Various binutils versions can resolve Thumb-2 branches to
1601           locally-defined, preemptible global symbols as short-range "b.n"
1602           branch instructions.
1603
1604           This is a problem, because there's no guarantee the final
1605           destination of the symbol, or any candidate locations for a
1606           trampoline, are within range of the branch.  For this reason, the
1607           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1608           relocation in modules at all, and it makes little sense to add
1609           support.
1610
1611           The symptom is that the kernel fails with an "unsupported
1612           relocation" error when loading some modules.
1613
1614           Until fixed tools are available, passing
1615           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1616           code which hits this problem, at the cost of a bit of extra runtime
1617           stack usage in some cases.
1618
1619           The problem is described in more detail at:
1620               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1621
1622           Only Thumb-2 kernels are affected.
1623
1624           Unless you are sure your tools don't have this problem, say Y.
1625
1626 config ARM_ASM_UNIFIED
1627         bool
1628
1629 config AEABI
1630         bool "Use the ARM EABI to compile the kernel"
1631         help
1632           This option allows for the kernel to be compiled using the latest
1633           ARM ABI (aka EABI).  This is only useful if you are using a user
1634           space environment that is also compiled with EABI.
1635
1636           Since there are major incompatibilities between the legacy ABI and
1637           EABI, especially with regard to structure member alignment, this
1638           option also changes the kernel syscall calling convention to
1639           disambiguate both ABIs and allow for backward compatibility support
1640           (selected with CONFIG_OABI_COMPAT).
1641
1642           To use this you need GCC version 4.0.0 or later.
1643
1644 config OABI_COMPAT
1645         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1646         depends on AEABI && !THUMB2_KERNEL
1647         help
1648           This option preserves the old syscall interface along with the
1649           new (ARM EABI) one. It also provides a compatibility layer to
1650           intercept syscalls that have structure arguments which layout
1651           in memory differs between the legacy ABI and the new ARM EABI
1652           (only for non "thumb" binaries). This option adds a tiny
1653           overhead to all syscalls and produces a slightly larger kernel.
1654
1655           The seccomp filter system will not be available when this is
1656           selected, since there is no way yet to sensibly distinguish
1657           between calling conventions during filtering.
1658
1659           If you know you'll be using only pure EABI user space then you
1660           can say N here. If this option is not selected and you attempt
1661           to execute a legacy ABI binary then the result will be
1662           UNPREDICTABLE (in fact it can be predicted that it won't work
1663           at all). If in doubt say N.
1664
1665 config ARCH_HAS_HOLES_MEMORYMODEL
1666         bool
1667
1668 config ARCH_SPARSEMEM_ENABLE
1669         bool
1670
1671 config ARCH_SPARSEMEM_DEFAULT
1672         def_bool ARCH_SPARSEMEM_ENABLE
1673
1674 config ARCH_SELECT_MEMORY_MODEL
1675         def_bool ARCH_SPARSEMEM_ENABLE
1676
1677 config HAVE_ARCH_PFN_VALID
1678         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1679
1680 config HAVE_GENERIC_RCU_GUP
1681         def_bool y
1682         depends on ARM_LPAE
1683
1684 config HIGHMEM
1685         bool "High Memory Support"
1686         depends on MMU
1687         help
1688           The address space of ARM processors is only 4 Gigabytes large
1689           and it has to accommodate user address space, kernel address
1690           space as well as some memory mapped IO. That means that, if you
1691           have a large amount of physical memory and/or IO, not all of the
1692           memory can be "permanently mapped" by the kernel. The physical
1693           memory that is not permanently mapped is called "high memory".
1694
1695           Depending on the selected kernel/user memory split, minimum
1696           vmalloc space and actual amount of RAM, you may not need this
1697           option which should result in a slightly faster kernel.
1698
1699           If unsure, say n.
1700
1701 config HIGHPTE
1702         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1703         depends on HIGHMEM
1704         default y
1705         help
1706           The VM uses one page of physical memory for each page table.
1707           For systems with a lot of processes, this can use a lot of
1708           precious low memory, eventually leading to low memory being
1709           consumed by page tables.  Setting this option will allow
1710           user-space 2nd level page tables to reside in high memory.
1711
1712 config CPU_SW_DOMAIN_PAN
1713         bool "Enable use of CPU domains to implement privileged no-access"
1714         depends on MMU && !ARM_LPAE
1715         default y
1716         help
1717           Increase kernel security by ensuring that normal kernel accesses
1718           are unable to access userspace addresses.  This can help prevent
1719           use-after-free bugs becoming an exploitable privilege escalation
1720           by ensuring that magic values (such as LIST_POISON) will always
1721           fault when dereferenced.
1722
1723           CPUs with low-vector mappings use a best-efforts implementation.
1724           Their lower 1MB needs to remain accessible for the vectors, but
1725           the remainder of userspace will become appropriately inaccessible.
1726
1727 config HW_PERF_EVENTS
1728         def_bool y
1729         depends on ARM_PMU
1730
1731 config SYS_SUPPORTS_HUGETLBFS
1732        def_bool y
1733        depends on ARM_LPAE
1734
1735 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1736        def_bool y
1737        depends on ARM_LPAE
1738
1739 config ARCH_WANT_GENERAL_HUGETLB
1740         def_bool y
1741
1742 config ARM_MODULE_PLTS
1743         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1744         depends on MODULES
1745         help
1746           Allocate PLTs when loading modules so that jumps and calls whose
1747           targets are too far away for their relative offsets to be encoded
1748           in the instructions themselves can be bounced via veneers in the
1749           module's PLT. This allows modules to be allocated in the generic
1750           vmalloc area after the dedicated module memory area has been
1751           exhausted. The modules will use slightly more memory, but after
1752           rounding up to page size, the actual memory footprint is usually
1753           the same.
1754
1755           Say y if you are getting out of memory errors while loading modules
1756
1757 source "mm/Kconfig"
1758
1759 config FORCE_MAX_ZONEORDER
1760         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1761         range 11 64 if ARCH_SHMOBILE_LEGACY
1762         default "12" if SOC_AM33XX
1763         default "9" if SA1111 || ARCH_EFM32
1764         default "11"
1765         help
1766           The kernel memory allocator divides physically contiguous memory
1767           blocks into "zones", where each zone is a power of two number of
1768           pages.  This option selects the largest power of two that the kernel
1769           keeps in the memory allocator.  If you need to allocate very large
1770           blocks of physically contiguous memory, then you may need to
1771           increase this value.
1772
1773           This config option is actually maximum order plus one. For example,
1774           a value of 11 means that the largest free memory block is 2^10 pages.
1775
1776 config ALIGNMENT_TRAP
1777         bool
1778         depends on CPU_CP15_MMU
1779         default y if !ARCH_EBSA110
1780         select HAVE_PROC_CPU if PROC_FS
1781         help
1782           ARM processors cannot fetch/store information which is not
1783           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1784           address divisible by 4. On 32-bit ARM processors, these non-aligned
1785           fetch/store instructions will be emulated in software if you say
1786           here, which has a severe performance impact. This is necessary for
1787           correct operation of some network protocols. With an IP-only
1788           configuration it is safe to say N, otherwise say Y.
1789
1790 config UACCESS_WITH_MEMCPY
1791         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1792         depends on MMU
1793         default y if CPU_FEROCEON
1794         help
1795           Implement faster copy_to_user and clear_user methods for CPU
1796           cores where a 8-word STM instruction give significantly higher
1797           memory write throughput than a sequence of individual 32bit stores.
1798
1799           A possible side effect is a slight increase in scheduling latency
1800           between threads sharing the same address space if they invoke
1801           such copy operations with large buffers.
1802
1803           However, if the CPU data cache is using a write-allocate mode,
1804           this option is unlikely to provide any performance gain.
1805
1806 config SECCOMP
1807         bool
1808         prompt "Enable seccomp to safely compute untrusted bytecode"
1809         ---help---
1810           This kernel feature is useful for number crunching applications
1811           that may need to compute untrusted bytecode during their
1812           execution. By using pipes or other transports made available to
1813           the process as file descriptors supporting the read/write
1814           syscalls, it's possible to isolate those applications in
1815           their own address space using seccomp. Once seccomp is
1816           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1817           and the task is only allowed to execute a few safe syscalls
1818           defined by each seccomp mode.
1819
1820 config SWIOTLB
1821         def_bool y
1822
1823 config IOMMU_HELPER
1824         def_bool SWIOTLB
1825
1826 config XEN_DOM0
1827         def_bool y
1828         depends on XEN
1829
1830 config XEN
1831         bool "Xen guest support on ARM"
1832         depends on ARM && AEABI && OF
1833         depends on CPU_V7 && !CPU_V6
1834         depends on !GENERIC_ATOMIC64
1835         depends on MMU
1836         select ARCH_DMA_ADDR_T_64BIT
1837         select ARM_PSCI
1838         select SWIOTLB_XEN
1839         help
1840           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1841
1842 endmenu
1843
1844 menu "Boot options"
1845
1846 config USE_OF
1847         bool "Flattened Device Tree support"
1848         select IRQ_DOMAIN
1849         select OF
1850         select OF_EARLY_FLATTREE
1851         select OF_RESERVED_MEM
1852         help
1853           Include support for flattened device tree machine descriptions.
1854
1855 config ATAGS
1856         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1857         default y
1858         help
1859           This is the traditional way of passing data to the kernel at boot
1860           time. If you are solely relying on the flattened device tree (or
1861           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1862           to remove ATAGS support from your kernel binary.  If unsure,
1863           leave this to y.
1864
1865 config DEPRECATED_PARAM_STRUCT
1866         bool "Provide old way to pass kernel parameters"
1867         depends on ATAGS
1868         help
1869           This was deprecated in 2001 and announced to live on for 5 years.
1870           Some old boot loaders still use this way.
1871
1872 # Compressed boot loader in ROM.  Yes, we really want to ask about
1873 # TEXT and BSS so we preserve their values in the config files.
1874 config ZBOOT_ROM_TEXT
1875         hex "Compressed ROM boot loader base address"
1876         default "0"
1877         help
1878           The physical address at which the ROM-able zImage is to be
1879           placed in the target.  Platforms which normally make use of
1880           ROM-able zImage formats normally set this to a suitable
1881           value in their defconfig file.
1882
1883           If ZBOOT_ROM is not enabled, this has no effect.
1884
1885 config ZBOOT_ROM_BSS
1886         hex "Compressed ROM boot loader BSS address"
1887         default "0"
1888         help
1889           The base address of an area of read/write memory in the target
1890           for the ROM-able zImage which must be available while the
1891           decompressor is running. It must be large enough to hold the
1892           entire decompressed kernel plus an additional 128 KiB.
1893           Platforms which normally make use of ROM-able zImage formats
1894           normally set this to a suitable value in their defconfig file.
1895
1896           If ZBOOT_ROM is not enabled, this has no effect.
1897
1898 config ZBOOT_ROM
1899         bool "Compressed boot loader in ROM/flash"
1900         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1901         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1902         help
1903           Say Y here if you intend to execute your compressed kernel image
1904           (zImage) directly from ROM or flash.  If unsure, say N.
1905
1906 config ARM_APPENDED_DTB
1907         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1908         depends on OF
1909         help
1910           With this option, the boot code will look for a device tree binary
1911           (DTB) appended to zImage
1912           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1913
1914           This is meant as a backward compatibility convenience for those
1915           systems with a bootloader that can't be upgraded to accommodate
1916           the documented boot protocol using a device tree.
1917
1918           Beware that there is very little in terms of protection against
1919           this option being confused by leftover garbage in memory that might
1920           look like a DTB header after a reboot if no actual DTB is appended
1921           to zImage.  Do not leave this option active in a production kernel
1922           if you don't intend to always append a DTB.  Proper passing of the
1923           location into r2 of a bootloader provided DTB is always preferable
1924           to this option.
1925
1926 config ARM_ATAG_DTB_COMPAT
1927         bool "Supplement the appended DTB with traditional ATAG information"
1928         depends on ARM_APPENDED_DTB
1929         help
1930           Some old bootloaders can't be updated to a DTB capable one, yet
1931           they provide ATAGs with memory configuration, the ramdisk address,
1932           the kernel cmdline string, etc.  Such information is dynamically
1933           provided by the bootloader and can't always be stored in a static
1934           DTB.  To allow a device tree enabled kernel to be used with such
1935           bootloaders, this option allows zImage to extract the information
1936           from the ATAG list and store it at run time into the appended DTB.
1937
1938 choice
1939         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1940         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1941
1942 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1943         bool "Use bootloader kernel arguments if available"
1944         help
1945           Uses the command-line options passed by the boot loader instead of
1946           the device tree bootargs property. If the boot loader doesn't provide
1947           any, the device tree bootargs property will be used.
1948
1949 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1950         bool "Extend with bootloader kernel arguments"
1951         help
1952           The command-line arguments provided by the boot loader will be
1953           appended to the the device tree bootargs property.
1954
1955 endchoice
1956
1957 config CMDLINE
1958         string "Default kernel command string"
1959         default ""
1960         help
1961           On some architectures (EBSA110 and CATS), there is currently no way
1962           for the boot loader to pass arguments to the kernel. For these
1963           architectures, you should supply some command-line options at build
1964           time by entering them here. As a minimum, you should specify the
1965           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1966
1967 choice
1968         prompt "Kernel command line type" if CMDLINE != ""
1969         default CMDLINE_FROM_BOOTLOADER
1970         depends on ATAGS
1971
1972 config CMDLINE_FROM_BOOTLOADER
1973         bool "Use bootloader kernel arguments if available"
1974         help
1975           Uses the command-line options passed by the boot loader. If
1976           the boot loader doesn't provide any, the default kernel command
1977           string provided in CMDLINE will be used.
1978
1979 config CMDLINE_EXTEND
1980         bool "Extend bootloader kernel arguments"
1981         help
1982           The command-line arguments provided by the boot loader will be
1983           appended to the default kernel command string.
1984
1985 config CMDLINE_FORCE
1986         bool "Always use the default kernel command string"
1987         help
1988           Always use the default kernel command string, even if the boot
1989           loader passes other arguments to the kernel.
1990           This is useful if you cannot or don't want to change the
1991           command-line options your boot loader passes to the kernel.
1992 endchoice
1993
1994 config XIP_KERNEL
1995         bool "Kernel Execute-In-Place from ROM"
1996         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1997         help
1998           Execute-In-Place allows the kernel to run from non-volatile storage
1999           directly addressable by the CPU, such as NOR flash. This saves RAM
2000           space since the text section of the kernel is not loaded from flash
2001           to RAM.  Read-write sections, such as the data section and stack,
2002           are still copied to RAM.  The XIP kernel is not compressed since
2003           it has to run directly from flash, so it will take more space to
2004           store it.  The flash address used to link the kernel object files,
2005           and for storing it, is configuration dependent. Therefore, if you
2006           say Y here, you must know the proper physical address where to
2007           store the kernel image depending on your own flash memory usage.
2008
2009           Also note that the make target becomes "make xipImage" rather than
2010           "make zImage" or "make Image".  The final kernel binary to put in
2011           ROM memory will be arch/arm/boot/xipImage.
2012
2013           If unsure, say N.
2014
2015 config XIP_PHYS_ADDR
2016         hex "XIP Kernel Physical Location"
2017         depends on XIP_KERNEL
2018         default "0x00080000"
2019         help
2020           This is the physical address in your flash memory the kernel will
2021           be linked for and stored to.  This address is dependent on your
2022           own flash usage.
2023
2024 config KEXEC
2025         bool "Kexec system call (EXPERIMENTAL)"
2026         depends on (!SMP || PM_SLEEP_SMP)
2027         depends on !CPU_V7M
2028         select KEXEC_CORE
2029         help
2030           kexec is a system call that implements the ability to shutdown your
2031           current kernel, and to start another kernel.  It is like a reboot
2032           but it is independent of the system firmware.   And like a reboot
2033           you can start any kernel with it, not just Linux.
2034
2035           It is an ongoing process to be certain the hardware in a machine
2036           is properly shutdown, so do not be surprised if this code does not
2037           initially work for you.
2038
2039 config ATAGS_PROC
2040         bool "Export atags in procfs"
2041         depends on ATAGS && KEXEC
2042         default y
2043         help
2044           Should the atags used to boot the kernel be exported in an "atags"
2045           file in procfs. Useful with kexec.
2046
2047 config CRASH_DUMP
2048         bool "Build kdump crash kernel (EXPERIMENTAL)"
2049         help
2050           Generate crash dump after being started by kexec. This should
2051           be normally only set in special crash dump kernels which are
2052           loaded in the main kernel with kexec-tools into a specially
2053           reserved region and then later executed after a crash by
2054           kdump/kexec. The crash dump kernel must be compiled to a
2055           memory address not used by the main kernel
2056
2057           For more details see Documentation/kdump/kdump.txt
2058
2059 config AUTO_ZRELADDR
2060         bool "Auto calculation of the decompressed kernel image address"
2061         help
2062           ZRELADDR is the physical address where the decompressed kernel
2063           image will be placed. If AUTO_ZRELADDR is selected, the address
2064           will be determined at run-time by masking the current IP with
2065           0xf8000000. This assumes the zImage being placed in the first 128MB
2066           from start of memory.
2067
2068 endmenu
2069
2070 menu "CPU Power Management"
2071
2072 source "drivers/cpufreq/Kconfig"
2073
2074 source "drivers/cpuidle/Kconfig"
2075
2076 endmenu
2077
2078 menu "Floating point emulation"
2079
2080 comment "At least one emulation must be selected"
2081
2082 config FPE_NWFPE
2083         bool "NWFPE math emulation"
2084         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2085         ---help---
2086           Say Y to include the NWFPE floating point emulator in the kernel.
2087           This is necessary to run most binaries. Linux does not currently
2088           support floating point hardware so you need to say Y here even if
2089           your machine has an FPA or floating point co-processor podule.
2090
2091           You may say N here if you are going to load the Acorn FPEmulator
2092           early in the bootup.
2093
2094 config FPE_NWFPE_XP
2095         bool "Support extended precision"
2096         depends on FPE_NWFPE
2097         help
2098           Say Y to include 80-bit support in the kernel floating-point
2099           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2100           Note that gcc does not generate 80-bit operations by default,
2101           so in most cases this option only enlarges the size of the
2102           floating point emulator without any good reason.
2103
2104           You almost surely want to say N here.
2105
2106 config FPE_FASTFPE
2107         bool "FastFPE math emulation (EXPERIMENTAL)"
2108         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2109         ---help---
2110           Say Y here to include the FAST floating point emulator in the kernel.
2111           This is an experimental much faster emulator which now also has full
2112           precision for the mantissa.  It does not support any exceptions.
2113           It is very simple, and approximately 3-6 times faster than NWFPE.
2114
2115           It should be sufficient for most programs.  It may be not suitable
2116           for scientific calculations, but you have to check this for yourself.
2117           If you do not feel you need a faster FP emulation you should better
2118           choose NWFPE.
2119
2120 config VFP
2121         bool "VFP-format floating point maths"
2122         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2123         help
2124           Say Y to include VFP support code in the kernel. This is needed
2125           if your hardware includes a VFP unit.
2126
2127           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2128           release notes and additional status information.
2129
2130           Say N if your target does not have VFP hardware.
2131
2132 config VFPv3
2133         bool
2134         depends on VFP
2135         default y if CPU_V7
2136
2137 config NEON
2138         bool "Advanced SIMD (NEON) Extension support"
2139         depends on VFPv3 && CPU_V7
2140         help
2141           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2142           Extension.
2143
2144 config KERNEL_MODE_NEON
2145         bool "Support for NEON in kernel mode"
2146         depends on NEON && AEABI
2147         help
2148           Say Y to include support for NEON in kernel mode.
2149
2150 endmenu
2151
2152 menu "Userspace binary formats"
2153
2154 source "fs/Kconfig.binfmt"
2155
2156 endmenu
2157
2158 menu "Power management options"
2159
2160 source "kernel/power/Kconfig"
2161
2162 config ARCH_SUSPEND_POSSIBLE
2163         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2164                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2165         def_bool y
2166
2167 config ARM_CPU_SUSPEND
2168         def_bool PM_SLEEP
2169
2170 config ARCH_HIBERNATION_POSSIBLE
2171         bool
2172         depends on MMU
2173         default y if ARCH_SUSPEND_POSSIBLE
2174
2175 endmenu
2176
2177 source "net/Kconfig"
2178
2179 source "drivers/Kconfig"
2180
2181 source "drivers/firmware/Kconfig"
2182
2183 source "fs/Kconfig"
2184
2185 source "arch/arm/Kconfig.debug"
2186
2187 source "security/Kconfig"
2188
2189 source "crypto/Kconfig"
2190 if CRYPTO
2191 source "arch/arm/crypto/Kconfig"
2192 endif
2193
2194 source "lib/Kconfig"
2195
2196 source "arch/arm/kvm/Kconfig"