4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
80 config ARM_DMA_IOMMU_ALIGNMENT
81 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
85 DMA mapping framework by default aligns all buffers to the smallest
86 PAGE_SIZE order which is greater than or equal to the requested buffer
87 size. This works well for buffers up to a few hundreds kilobytes, but
88 for larger buffers it just a waste of address space. Drivers which has
89 relatively small addressing window (like 64Mib) might run out of
90 virtual space with just a few allocations.
92 With this parameter you can specify the maximum PAGE_SIZE order for
93 DMA IOMMU buffers. Larger buffers will be aligned only to this
94 specified order. The order is expressed as a power of two multiplied
102 config MIGHT_HAVE_PCI
105 config SYS_SUPPORTS_APM_EMULATION
113 select GENERIC_ALLOCATOR
124 The Extended Industry Standard Architecture (EISA) bus was
125 developed as an open alternative to the IBM MicroChannel bus.
127 The EISA bus provided some of the features of the IBM MicroChannel
128 bus while maintaining backward compatibility with cards made for
129 the older ISA bus. The EISA bus saw limited use between 1988 and
130 1995 when it was made obsolete by the PCI bus.
132 Say Y here if you are building a kernel for an EISA-based machine.
139 config STACKTRACE_SUPPORT
143 config HAVE_LATENCYTOP_SUPPORT
148 config LOCKDEP_SUPPORT
152 config TRACE_IRQFLAGS_SUPPORT
156 config RWSEM_GENERIC_SPINLOCK
160 config RWSEM_XCHGADD_ALGORITHM
163 config ARCH_HAS_ILOG2_U32
166 config ARCH_HAS_ILOG2_U64
169 config ARCH_HAS_CPUFREQ
172 Internal node to signify that the ARCH has CPUFREQ support
173 and that the relevant menu configurations are displayed for
176 config GENERIC_HWEIGHT
180 config GENERIC_CALIBRATE_DELAY
184 config ARCH_MAY_HAVE_PC_FDC
190 config NEED_DMA_MAP_STATE
193 config ARCH_HAS_DMA_SET_COHERENT_MASK
196 config GENERIC_ISA_DMA
202 config NEED_RET_TO_USER
210 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
211 default DRAM_BASE if REMAP_VECTORS_TO_RAM
214 The base address of exception vectors.
216 config ARM_PATCH_PHYS_VIRT
217 bool "Patch physical to virtual translations at runtime" if EMBEDDED
219 depends on !XIP_KERNEL && MMU
220 depends on !ARCH_REALVIEW || !SPARSEMEM
222 Patch phys-to-virt and virt-to-phys translation functions at
223 boot and module load time according to the position of the
224 kernel in system memory.
226 This can only be used with non-XIP MMU kernels where the base
227 of physical memory is at a 16MB boundary.
229 Only disable this option if you know that you do not require
230 this feature (eg, building a kernel for a single machine) and
231 you need to shrink the kernel to the minimal size.
233 config NEED_MACH_GPIO_H
236 Select this when mach/gpio.h is required to provide special
237 definitions for this platform. The need for mach/gpio.h should
238 be avoided when possible.
240 config NEED_MACH_IO_H
243 Select this when mach/io.h is required to provide special
244 definitions for this platform. The need for mach/io.h should
245 be avoided when possible.
247 config NEED_MACH_MEMORY_H
250 Select this when mach/memory.h is required to provide special
251 definitions for this platform. The need for mach/memory.h should
252 be avoided when possible.
255 hex "Physical address of main memory" if MMU
256 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
257 default DRAM_BASE if !MMU
259 Please provide the physical address corresponding to the
260 location of main memory in your system.
266 source "init/Kconfig"
268 source "kernel/Kconfig.freezer"
273 bool "MMU-based Paged Memory Management Support"
276 Select if you want MMU-based virtualised addressing space
277 support by paged memory management. If unsure, say 'Y'.
280 # The "ARM system type" choice list is ordered alphabetically by option
281 # text. Please add new entries in the option alphabetic order.
284 prompt "ARM system type"
285 default ARCH_MULTIPLATFORM
287 config ARCH_MULTIPLATFORM
288 bool "Allow multiple platforms to be selected"
290 select ARM_PATCH_PHYS_VIRT
293 select MULTI_IRQ_HANDLER
297 config ARCH_INTEGRATOR
298 bool "ARM Ltd. Integrator family"
299 select ARCH_HAS_CPUFREQ
302 select COMMON_CLK_VERSATILE
303 select GENERIC_CLOCKEVENTS
306 select MULTI_IRQ_HANDLER
307 select NEED_MACH_MEMORY_H
308 select PLAT_VERSATILE
310 select VERSATILE_FPGA_IRQ
312 Support for ARM's Integrator platform.
315 bool "ARM Ltd. RealView family"
316 select ARCH_WANT_OPTIONAL_GPIOLIB
318 select ARM_TIMER_SP804
320 select COMMON_CLK_VERSATILE
321 select GENERIC_CLOCKEVENTS
322 select GPIO_PL061 if GPIOLIB
324 select NEED_MACH_MEMORY_H
325 select PLAT_VERSATILE
326 select PLAT_VERSATILE_CLCD
328 This enables support for ARM Ltd RealView boards.
330 config ARCH_VERSATILE
331 bool "ARM Ltd. Versatile family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
338 select HAVE_MACH_CLKDEV
340 select PLAT_VERSATILE
341 select PLAT_VERSATILE_CLCD
342 select PLAT_VERSATILE_CLOCK
343 select VERSATILE_FPGA_IRQ
345 This enables support for ARM Ltd Versatile board.
349 select ARCH_REQUIRE_GPIOLIB
353 select NEED_MACH_GPIO_H
354 select NEED_MACH_IO_H if PCCARD
356 select PINCTRL_AT91 if USE_OF
358 This enables support for systems based on Atmel
359 AT91RM9200 and AT91SAM9* processors.
362 bool "Broadcom BCM2835 family"
363 select ARCH_REQUIRE_GPIOLIB
365 select ARM_ERRATA_411920
366 select ARM_TIMER_SP804
370 select GENERIC_CLOCKEVENTS
372 select MULTI_IRQ_HANDLER
374 select PINCTRL_BCM2835
378 This enables support for the Broadcom BCM2835 SoC. This SoC is
379 use in the Raspberry Pi, and Roku 2 devices.
382 bool "Cavium Networks CNS3XXX family"
385 select GENERIC_CLOCKEVENTS
386 select MIGHT_HAVE_CACHE_L2X0
387 select MIGHT_HAVE_PCI
388 select PCI_DOMAINS if PCI
390 Support for Cavium Networks CNS3XXX platform.
393 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
394 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
400 select MULTI_IRQ_HANDLER
401 select NEED_MACH_MEMORY_H
404 Support for Cirrus Logic 711x/721x/731x based boards.
407 bool "Cortina Systems Gemini"
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_USES_GETTIMEOFFSET
412 Support for the Cortina Systems Gemini family SoCs
416 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_CLOCKEVENTS
419 select GENERIC_IRQ_CHIP
420 select MIGHT_HAVE_CACHE_L2X0
426 Support for CSR SiRFprimaII/Marco/Polo platforms
430 select ARCH_USES_GETTIMEOFFSET
433 select NEED_MACH_IO_H
434 select NEED_MACH_MEMORY_H
437 This is an evaluation board for the StrongARM processor available
438 from Digital. It has limited hardware on-board, including an
439 Ethernet interface, two PCMCIA sockets, two serial ports and a
444 select ARCH_HAS_HOLES_MEMORYMODEL
445 select ARCH_REQUIRE_GPIOLIB
446 select ARCH_USES_GETTIMEOFFSET
451 select NEED_MACH_MEMORY_H
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Freescale MXS-based"
469 select ARCH_REQUIRE_GPIOLIB
473 select GENERIC_CLOCKEVENTS
474 select HAVE_CLK_PREPARE
475 select MULTI_IRQ_HANDLER
480 Support for Freescale MXS-based family of processors
483 bool "Hilscher NetX based"
487 select GENERIC_CLOCKEVENTS
489 This enables support for systems based on the Hilscher NetX Soc
492 bool "Hynix HMS720x-based"
493 select ARCH_USES_GETTIMEOFFSET
497 This enables support for systems based on the Hynix HMS720x
502 select ARCH_SUPPORTS_MSI
504 select NEED_MACH_MEMORY_H
505 select NEED_RET_TO_USER
510 Support for Intel's IOP13XX (XScale) family of processors.
515 select ARCH_REQUIRE_GPIOLIB
517 select NEED_MACH_GPIO_H
518 select NEED_RET_TO_USER
522 Support for Intel's 80219 and IOP32X (XScale) family of
528 select ARCH_REQUIRE_GPIOLIB
530 select NEED_MACH_GPIO_H
531 select NEED_RET_TO_USER
535 Support for Intel's IOP33X (XScale) family of processors.
540 select ARCH_HAS_DMA_SET_COHERENT_MASK
541 select ARCH_REQUIRE_GPIOLIB
544 select DMABOUNCE if PCI
545 select GENERIC_CLOCKEVENTS
546 select MIGHT_HAVE_PCI
547 select NEED_MACH_IO_H
549 Support for Intel's IXP4XX (XScale) family of processors.
553 select ARCH_REQUIRE_GPIOLIB
554 select COMMON_CLK_DOVE
556 select GENERIC_CLOCKEVENTS
557 select MIGHT_HAVE_PCI
560 select PLAT_ORION_LEGACY
561 select USB_ARCH_HAS_EHCI
563 Support for the Marvell Dove SoC 88AP510
566 bool "Marvell Kirkwood"
567 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
573 select PINCTRL_KIRKWOOD
574 select PLAT_ORION_LEGACY
576 Support for the following Marvell Kirkwood series SoCs:
577 88F6180, 88F6192 and 88F6281.
580 bool "Marvell MV78xx0"
581 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
585 select PLAT_ORION_LEGACY
587 Support for the following Marvell MV78xx0 series SoCs:
593 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
597 select PLAT_ORION_LEGACY
599 Support for the following Marvell Orion 5x series SoCs:
600 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
601 Orion-2 (5281), Orion-1-90 (6183).
604 bool "Marvell PXA168/910/MMP2"
606 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_ALLOCATOR
609 select GENERIC_CLOCKEVENTS
612 select NEED_MACH_GPIO_H
617 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
620 bool "Micrel/Kendin KS8695"
621 select ARCH_REQUIRE_GPIOLIB
624 select GENERIC_CLOCKEVENTS
625 select NEED_MACH_MEMORY_H
627 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
628 System-on-Chip devices.
631 bool "Nuvoton W90X900 CPU"
632 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
638 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
639 At present, the w90x900 has been renamed nuc900, regarding
640 the ARM series product line, you can login the following
641 link address to know more.
643 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
644 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
648 select ARCH_REQUIRE_GPIOLIB
653 select GENERIC_CLOCKEVENTS
656 select USB_ARCH_HAS_OHCI
659 Support for the NXP LPC32XX family of processors
663 select ARCH_HAS_CPUFREQ
667 select GENERIC_CLOCKEVENTS
671 select MIGHT_HAVE_CACHE_L2X0
675 This enables support for NVIDIA Tegra based systems (Tegra APX,
676 Tegra 6xx and Tegra 2 series).
679 bool "PXA2xx/PXA3xx-based"
681 select ARCH_HAS_CPUFREQ
683 select ARCH_REQUIRE_GPIOLIB
684 select ARM_CPU_SUSPEND if PM
688 select GENERIC_CLOCKEVENTS
691 select MULTI_IRQ_HANDLER
692 select NEED_MACH_GPIO_H
696 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
700 select ARCH_REQUIRE_GPIOLIB
702 select GENERIC_CLOCKEVENTS
705 Support for Qualcomm MSM/QSD based systems. This runs on the
706 apps processor of the MSM/QSD and depends on a shared memory
707 interface to the modem processor which runs the baseband
708 stack and controls some vital subsystems
709 (clock and power control, etc).
712 bool "Renesas SH-Mobile / R-Mobile"
714 select GENERIC_CLOCKEVENTS
716 select HAVE_MACH_CLKDEV
718 select MIGHT_HAVE_CACHE_L2X0
719 select MULTI_IRQ_HANDLER
720 select NEED_MACH_MEMORY_H
722 select PM_GENERIC_DOMAINS if PM
725 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
730 select ARCH_MAY_HAVE_PC_FDC
731 select ARCH_SPARSEMEM_ENABLE
732 select ARCH_USES_GETTIMEOFFSET
735 select HAVE_PATA_PLATFORM
737 select NEED_MACH_IO_H
738 select NEED_MACH_MEMORY_H
741 On the Acorn Risc-PC, Linux can support the internal IDE disk and
742 CD-ROM interface, serial and parallel port, and the floppy drive.
746 select ARCH_HAS_CPUFREQ
748 select ARCH_REQUIRE_GPIOLIB
749 select ARCH_SPARSEMEM_ENABLE
754 select GENERIC_CLOCKEVENTS
757 select NEED_MACH_GPIO_H
758 select NEED_MACH_MEMORY_H
761 Support for StrongARM 11x0 based boards.
764 bool "Samsung S3C24XX SoCs"
765 select ARCH_HAS_CPUFREQ
766 select ARCH_USES_GETTIMEOFFSET
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
774 select NEED_MACH_IO_H
776 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
777 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
778 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
779 Samsung SMDK2410 development board (and derivatives).
782 bool "Samsung S3C64XX"
783 select ARCH_HAS_CPUFREQ
784 select ARCH_REQUIRE_GPIOLIB
785 select ARCH_USES_GETTIMEOFFSET
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 select NEED_MACH_GPIO_H
797 select S3C_GPIO_TRACK
798 select SAMSUNG_CLKSRC
799 select SAMSUNG_GPIOLIB_4BIT
800 select SAMSUNG_IRQ_VIC_TIMER
801 select USB_ARCH_HAS_OHCI
803 Samsung S3C64XX series based systems
806 bool "Samsung S5P6440 S5P6450"
810 select GENERIC_CLOCKEVENTS
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select HAVE_S3C_RTC if RTC_CLASS
816 select NEED_MACH_GPIO_H
818 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
822 bool "Samsung S5PC100"
823 select ARCH_USES_GETTIMEOFFSET
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C2410_WATCHDOG if WATCHDOG
830 select HAVE_S3C_RTC if RTC_CLASS
831 select NEED_MACH_GPIO_H
833 Samsung S5PC100 series based systems
836 bool "Samsung S5PV210/S5PC110"
837 select ARCH_HAS_CPUFREQ
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_SPARSEMEM_ENABLE
843 select GENERIC_CLOCKEVENTS
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select HAVE_S3C_RTC if RTC_CLASS
849 select NEED_MACH_GPIO_H
850 select NEED_MACH_MEMORY_H
852 Samsung S5PV210/S5PC110 series based systems
855 bool "Samsung EXYNOS"
856 select ARCH_HAS_CPUFREQ
857 select ARCH_HAS_HOLES_MEMORYMODEL
858 select ARCH_SPARSEMEM_ENABLE
861 select GENERIC_CLOCKEVENTS
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 select HAVE_S3C_RTC if RTC_CLASS
867 select NEED_MACH_GPIO_H
868 select NEED_MACH_MEMORY_H
870 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
874 select ARCH_USES_GETTIMEOFFSET
878 select NEED_MACH_MEMORY_H
882 Support for the StrongARM based Digital DNARD machine, also known
883 as "Shark" (<http://www.shark-linux.de/shark.html>).
886 bool "ST-Ericsson U300 Series"
888 select ARCH_REQUIRE_GPIOLIB
890 select ARM_PATCH_PHYS_VIRT
896 select GENERIC_CLOCKEVENTS
901 Support for ST-Ericsson U300 series mobile platforms.
904 bool "ST-Ericsson U8500 Series"
906 select ARCH_HAS_CPUFREQ
907 select ARCH_REQUIRE_GPIOLIB
911 select GENERIC_CLOCKEVENTS
913 select MIGHT_HAVE_CACHE_L2X0
916 Support for ST-Ericsson's Ux500 architecture
919 bool "STMicroelectronics Nomadik"
920 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_CLOCKEVENTS
926 select MIGHT_HAVE_CACHE_L2X0
928 select PINCTRL_STN8815
931 Support for the Nomadik platform by ST-Ericsson
935 select ARCH_HAS_CPUFREQ
936 select ARCH_REQUIRE_GPIOLIB
941 select GENERIC_CLOCKEVENTS
944 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
948 select ARCH_HAS_HOLES_MEMORYMODEL
949 select ARCH_REQUIRE_GPIOLIB
951 select GENERIC_ALLOCATOR
952 select GENERIC_CLOCKEVENTS
953 select GENERIC_IRQ_CHIP
955 select NEED_MACH_GPIO_H
959 Support for TI's DaVinci platform.
964 select ARCH_HAS_CPUFREQ
965 select ARCH_HAS_HOLES_MEMORYMODEL
966 select ARCH_REQUIRE_GPIOLIB
968 select GENERIC_CLOCKEVENTS
971 Support for TI's OMAP platform (OMAP1/2/3/4).
973 config ARCH_VT8500_SINGLE
974 bool "VIA/WonderMedia 85xx"
975 select ARCH_HAS_CPUFREQ
976 select ARCH_REQUIRE_GPIOLIB
980 select GENERIC_CLOCKEVENTS
983 select MULTI_IRQ_HANDLER
987 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
991 menu "Multiple platform selection"
992 depends on ARCH_MULTIPLATFORM
994 comment "CPU Core family selection"
997 bool "ARMv4 based platforms (FA526, StrongARM)"
998 depends on !ARCH_MULTI_V6_V7
999 select ARCH_MULTI_V4_V5
1001 config ARCH_MULTI_V4T
1002 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1003 depends on !ARCH_MULTI_V6_V7
1004 select ARCH_MULTI_V4_V5
1006 config ARCH_MULTI_V5
1007 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1008 depends on !ARCH_MULTI_V6_V7
1009 select ARCH_MULTI_V4_V5
1011 config ARCH_MULTI_V4_V5
1014 config ARCH_MULTI_V6
1015 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1016 select ARCH_MULTI_V6_V7
1019 config ARCH_MULTI_V7
1020 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1022 select ARCH_MULTI_V6_V7
1023 select ARCH_VEXPRESS
1026 config ARCH_MULTI_V6_V7
1029 config ARCH_MULTI_CPU_AUTO
1030 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1031 select ARCH_MULTI_V5
1036 # This is sorted alphabetically by mach-* pathname. However, plat-*
1037 # Kconfigs may be included either alphabetically (according to the
1038 # plat- suffix) or along side the corresponding mach-* source.
1040 source "arch/arm/mach-mvebu/Kconfig"
1042 source "arch/arm/mach-at91/Kconfig"
1044 source "arch/arm/mach-bcm/Kconfig"
1046 source "arch/arm/mach-clps711x/Kconfig"
1048 source "arch/arm/mach-cns3xxx/Kconfig"
1050 source "arch/arm/mach-davinci/Kconfig"
1052 source "arch/arm/mach-dove/Kconfig"
1054 source "arch/arm/mach-ep93xx/Kconfig"
1056 source "arch/arm/mach-footbridge/Kconfig"
1058 source "arch/arm/mach-gemini/Kconfig"
1060 source "arch/arm/mach-h720x/Kconfig"
1062 source "arch/arm/mach-highbank/Kconfig"
1064 source "arch/arm/mach-integrator/Kconfig"
1066 source "arch/arm/mach-iop32x/Kconfig"
1068 source "arch/arm/mach-iop33x/Kconfig"
1070 source "arch/arm/mach-iop13xx/Kconfig"
1072 source "arch/arm/mach-ixp4xx/Kconfig"
1074 source "arch/arm/mach-kirkwood/Kconfig"
1076 source "arch/arm/mach-ks8695/Kconfig"
1078 source "arch/arm/mach-msm/Kconfig"
1080 source "arch/arm/mach-mv78xx0/Kconfig"
1082 source "arch/arm/mach-imx/Kconfig"
1084 source "arch/arm/mach-mxs/Kconfig"
1086 source "arch/arm/mach-netx/Kconfig"
1088 source "arch/arm/mach-nomadik/Kconfig"
1090 source "arch/arm/plat-omap/Kconfig"
1092 source "arch/arm/mach-omap1/Kconfig"
1094 source "arch/arm/mach-omap2/Kconfig"
1096 source "arch/arm/mach-orion5x/Kconfig"
1098 source "arch/arm/mach-picoxcell/Kconfig"
1100 source "arch/arm/mach-pxa/Kconfig"
1101 source "arch/arm/plat-pxa/Kconfig"
1103 source "arch/arm/mach-mmp/Kconfig"
1105 source "arch/arm/mach-realview/Kconfig"
1107 source "arch/arm/mach-sa1100/Kconfig"
1109 source "arch/arm/plat-samsung/Kconfig"
1110 source "arch/arm/plat-s3c24xx/Kconfig"
1112 source "arch/arm/mach-socfpga/Kconfig"
1114 source "arch/arm/plat-spear/Kconfig"
1116 source "arch/arm/mach-s3c24xx/Kconfig"
1118 source "arch/arm/mach-s3c2412/Kconfig"
1119 source "arch/arm/mach-s3c2440/Kconfig"
1123 source "arch/arm/mach-s3c64xx/Kconfig"
1126 source "arch/arm/mach-s5p64x0/Kconfig"
1128 source "arch/arm/mach-s5pc100/Kconfig"
1130 source "arch/arm/mach-s5pv210/Kconfig"
1132 source "arch/arm/mach-exynos/Kconfig"
1134 source "arch/arm/mach-shmobile/Kconfig"
1136 source "arch/arm/mach-sunxi/Kconfig"
1138 source "arch/arm/mach-prima2/Kconfig"
1140 source "arch/arm/mach-tegra/Kconfig"
1142 source "arch/arm/mach-u300/Kconfig"
1144 source "arch/arm/mach-ux500/Kconfig"
1146 source "arch/arm/mach-versatile/Kconfig"
1148 source "arch/arm/mach-vexpress/Kconfig"
1149 source "arch/arm/plat-versatile/Kconfig"
1151 source "arch/arm/mach-vt8500/Kconfig"
1153 source "arch/arm/mach-w90x900/Kconfig"
1155 source "arch/arm/mach-zynq/Kconfig"
1157 # Definitions to make life easier
1163 select GENERIC_CLOCKEVENTS
1169 select GENERIC_IRQ_CHIP
1172 config PLAT_ORION_LEGACY
1179 config PLAT_VERSATILE
1182 config ARM_TIMER_SP804
1185 select HAVE_SCHED_CLOCK
1187 source arch/arm/mm/Kconfig
1191 default 16 if ARCH_EP93XX
1195 bool "Enable iWMMXt support"
1196 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1197 default y if PXA27x || PXA3xx || ARCH_MMP
1199 Enable support for iWMMXt context switching at run time if
1200 running on a CPU that supports it.
1204 depends on CPU_XSCALE
1207 config MULTI_IRQ_HANDLER
1210 Allow each machine to specify it's own IRQ handler at run time.
1213 source "arch/arm/Kconfig-nommu"
1216 config ARM_ERRATA_326103
1217 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1220 Executing a SWP instruction to read-only memory does not set bit 11
1221 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1222 treat the access as a read, preventing a COW from occurring and
1223 causing the faulting task to livelock.
1225 config ARM_ERRATA_411920
1226 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1227 depends on CPU_V6 || CPU_V6K
1229 Invalidation of the Instruction Cache operation can
1230 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1231 It does not affect the MPCore. This option enables the ARM Ltd.
1232 recommended workaround.
1234 config ARM_ERRATA_430973
1235 bool "ARM errata: Stale prediction on replaced interworking branch"
1238 This option enables the workaround for the 430973 Cortex-A8
1239 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1240 interworking branch is replaced with another code sequence at the
1241 same virtual address, whether due to self-modifying code or virtual
1242 to physical address re-mapping, Cortex-A8 does not recover from the
1243 stale interworking branch prediction. This results in Cortex-A8
1244 executing the new code sequence in the incorrect ARM or Thumb state.
1245 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1246 and also flushes the branch target cache at every context switch.
1247 Note that setting specific bits in the ACTLR register may not be
1248 available in non-secure mode.
1250 config ARM_ERRATA_458693
1251 bool "ARM errata: Processor deadlock when a false hazard is created"
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1256 erratum. For very specific sequences of memory operations, it is
1257 possible for a hazard condition intended for a cache line to instead
1258 be incorrectly associated with a different cache line. This false
1259 hazard might then cause a processor deadlock. The workaround enables
1260 the L1 caching of the NEON accesses and disables the PLD instruction
1261 in the ACTLR register. Note that setting specific bits in the ACTLR
1262 register may not be available in non-secure mode.
1264 config ARM_ERRATA_460075
1265 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1267 depends on !ARCH_MULTIPLATFORM
1269 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1270 erratum. Any asynchronous access to the L2 cache may encounter a
1271 situation in which recent store transactions to the L2 cache are lost
1272 and overwritten with stale memory contents from external memory. The
1273 workaround disables the write-allocate mode for the L2 cache via the
1274 ACTLR register. Note that setting specific bits in the ACTLR register
1275 may not be available in non-secure mode.
1277 config ARM_ERRATA_742230
1278 bool "ARM errata: DMB operation may be faulty"
1279 depends on CPU_V7 && SMP
1280 depends on !ARCH_MULTIPLATFORM
1282 This option enables the workaround for the 742230 Cortex-A9
1283 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1284 between two write operations may not ensure the correct visibility
1285 ordering of the two writes. This workaround sets a specific bit in
1286 the diagnostic register of the Cortex-A9 which causes the DMB
1287 instruction to behave as a DSB, ensuring the correct behaviour of
1290 config ARM_ERRATA_742231
1291 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1292 depends on CPU_V7 && SMP
1293 depends on !ARCH_MULTIPLATFORM
1295 This option enables the workaround for the 742231 Cortex-A9
1296 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1297 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1298 accessing some data located in the same cache line, may get corrupted
1299 data due to bad handling of the address hazard when the line gets
1300 replaced from one of the CPUs at the same time as another CPU is
1301 accessing it. This workaround sets specific bits in the diagnostic
1302 register of the Cortex-A9 which reduces the linefill issuing
1303 capabilities of the processor.
1305 config PL310_ERRATA_588369
1306 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1307 depends on CACHE_L2X0
1309 The PL310 L2 cache controller implements three types of Clean &
1310 Invalidate maintenance operations: by Physical Address
1311 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1312 They are architecturally defined to behave as the execution of a
1313 clean operation followed immediately by an invalidate operation,
1314 both performing to the same memory location. This functionality
1315 is not correctly implemented in PL310 as clean lines are not
1316 invalidated as a result of these operations.
1318 config ARM_ERRATA_720789
1319 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1322 This option enables the workaround for the 720789 Cortex-A9 (prior to
1323 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1324 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1325 As a consequence of this erratum, some TLB entries which should be
1326 invalidated are not, resulting in an incoherency in the system page
1327 tables. The workaround changes the TLB flushing routines to invalidate
1328 entries regardless of the ASID.
1330 config PL310_ERRATA_727915
1331 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1332 depends on CACHE_L2X0
1334 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1335 operation (offset 0x7FC). This operation runs in background so that
1336 PL310 can handle normal accesses while it is in progress. Under very
1337 rare circumstances, due to this erratum, write data can be lost when
1338 PL310 treats a cacheable write transaction during a Clean &
1339 Invalidate by Way operation.
1341 config ARM_ERRATA_743622
1342 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1344 depends on !ARCH_MULTIPLATFORM
1346 This option enables the workaround for the 743622 Cortex-A9
1347 (r2p*) erratum. Under very rare conditions, a faulty
1348 optimisation in the Cortex-A9 Store Buffer may lead to data
1349 corruption. This workaround sets a specific bit in the diagnostic
1350 register of the Cortex-A9 which disables the Store Buffer
1351 optimisation, preventing the defect from occurring. This has no
1352 visible impact on the overall performance or power consumption of the
1355 config ARM_ERRATA_751472
1356 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1358 depends on !ARCH_MULTIPLATFORM
1360 This option enables the workaround for the 751472 Cortex-A9 (prior
1361 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1362 completion of a following broadcasted operation if the second
1363 operation is received by a CPU before the ICIALLUIS has completed,
1364 potentially leading to corrupted entries in the cache or TLB.
1366 config PL310_ERRATA_753970
1367 bool "PL310 errata: cache sync operation may be faulty"
1368 depends on CACHE_PL310
1370 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1372 Under some condition the effect of cache sync operation on
1373 the store buffer still remains when the operation completes.
1374 This means that the store buffer is always asked to drain and
1375 this prevents it from merging any further writes. The workaround
1376 is to replace the normal offset of cache sync operation (0x730)
1377 by another offset targeting an unmapped PL310 register 0x740.
1378 This has the same effect as the cache sync operation: store buffer
1379 drain and waiting for all buffers empty.
1381 config ARM_ERRATA_754322
1382 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1385 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1386 r3p*) erratum. A speculative memory access may cause a page table walk
1387 which starts prior to an ASID switch but completes afterwards. This
1388 can populate the micro-TLB with a stale entry which may be hit with
1389 the new ASID. This workaround places two dsb instructions in the mm
1390 switching code so that no page table walks can cross the ASID switch.
1392 config ARM_ERRATA_754327
1393 bool "ARM errata: no automatic Store Buffer drain"
1394 depends on CPU_V7 && SMP
1396 This option enables the workaround for the 754327 Cortex-A9 (prior to
1397 r2p0) erratum. The Store Buffer does not have any automatic draining
1398 mechanism and therefore a livelock may occur if an external agent
1399 continuously polls a memory location waiting to observe an update.
1400 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1401 written polling loops from denying visibility of updates to memory.
1403 config ARM_ERRATA_364296
1404 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1405 depends on CPU_V6 && !SMP
1407 This options enables the workaround for the 364296 ARM1136
1408 r0p2 erratum (possible cache data corruption with
1409 hit-under-miss enabled). It sets the undocumented bit 31 in
1410 the auxiliary control register and the FI bit in the control
1411 register, thus disabling hit-under-miss without putting the
1412 processor into full low interrupt latency mode. ARM11MPCore
1415 config ARM_ERRATA_764369
1416 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1417 depends on CPU_V7 && SMP
1419 This option enables the workaround for erratum 764369
1420 affecting Cortex-A9 MPCore with two or more processors (all
1421 current revisions). Under certain timing circumstances, a data
1422 cache line maintenance operation by MVA targeting an Inner
1423 Shareable memory region may fail to proceed up to either the
1424 Point of Coherency or to the Point of Unification of the
1425 system. This workaround adds a DSB instruction before the
1426 relevant cache maintenance functions and sets a specific bit
1427 in the diagnostic control register of the SCU.
1429 config PL310_ERRATA_769419
1430 bool "PL310 errata: no automatic Store Buffer drain"
1431 depends on CACHE_L2X0
1433 On revisions of the PL310 prior to r3p2, the Store Buffer does
1434 not automatically drain. This can cause normal, non-cacheable
1435 writes to be retained when the memory system is idle, leading
1436 to suboptimal I/O performance for drivers using coherent DMA.
1437 This option adds a write barrier to the cpu_idle loop so that,
1438 on systems with an outer cache, the store buffer is drained
1441 config ARM_ERRATA_775420
1442 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1445 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1446 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1447 operation aborts with MMU exception, it might cause the processor
1448 to deadlock. This workaround puts DSB before executing ISB if
1449 an abort may occur on cache maintenance.
1453 source "arch/arm/common/Kconfig"
1463 Find out whether you have ISA slots on your motherboard. ISA is the
1464 name of a bus system, i.e. the way the CPU talks to the other stuff
1465 inside your box. Other bus systems are PCI, EISA, MicroChannel
1466 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1467 newer boards don't support it. If you have ISA, say Y, otherwise N.
1469 # Select ISA DMA controller support
1474 # Select ISA DMA interface
1479 bool "PCI support" if MIGHT_HAVE_PCI
1481 Find out whether you have a PCI motherboard. PCI is the name of a
1482 bus system, i.e. the way the CPU talks to the other stuff inside
1483 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1484 VESA. If you have PCI, say Y, otherwise N.
1490 config PCI_NANOENGINE
1491 bool "BSE nanoEngine PCI support"
1492 depends on SA1100_NANOENGINE
1494 Enable PCI on the BSE nanoEngine board.
1499 # Select the host bridge type
1500 config PCI_HOST_VIA82C505
1502 depends on PCI && ARCH_SHARK
1505 config PCI_HOST_ITE8152
1507 depends on PCI && MACH_ARMCORE
1511 source "drivers/pci/Kconfig"
1513 source "drivers/pcmcia/Kconfig"
1517 menu "Kernel Features"
1522 This option should be selected by machines which have an SMP-
1525 The only effect of this option is to make the SMP-related
1526 options available to the user for configuration.
1529 bool "Symmetric Multi-Processing"
1530 depends on CPU_V6K || CPU_V7
1531 depends on GENERIC_CLOCKEVENTS
1534 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1535 select USE_GENERIC_SMP_HELPERS
1537 This enables support for systems with more than one CPU. If you have
1538 a system with only one CPU, like most personal computers, say N. If
1539 you have a system with more than one CPU, say Y.
1541 If you say N here, the kernel will run on single and multiprocessor
1542 machines, but will use only one CPU of a multiprocessor machine. If
1543 you say Y here, the kernel will run on many, but not all, single
1544 processor machines. On a single processor machine, the kernel will
1545 run faster if you say N here.
1547 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1548 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1549 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1551 If you don't know what to do here, say N.
1554 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1555 depends on EXPERIMENTAL
1556 depends on SMP && !XIP_KERNEL
1559 SMP kernels contain instructions which fail on non-SMP processors.
1560 Enabling this option allows the kernel to modify itself to make
1561 these instructions safe. Disabling it allows about 1K of space
1564 If you don't know what to do here, say Y.
1566 config ARM_CPU_TOPOLOGY
1567 bool "Support cpu topology definition"
1568 depends on SMP && CPU_V7
1571 Support ARM cpu topology definition. The MPIDR register defines
1572 affinity between processors which is then used to describe the cpu
1573 topology of an ARM System.
1576 bool "Multi-core scheduler support"
1577 depends on ARM_CPU_TOPOLOGY
1579 Multi-core scheduler support improves the CPU scheduler's decision
1580 making when dealing with multi-core CPU chips at a cost of slightly
1581 increased overhead in some places. If unsure say N here.
1584 bool "SMT scheduler support"
1585 depends on ARM_CPU_TOPOLOGY
1587 Improves the CPU scheduler's decision making when dealing with
1588 MultiThreading at a cost of slightly increased overhead in some
1589 places. If unsure say N here.
1594 This option enables support for the ARM system coherency unit
1596 config ARM_ARCH_TIMER
1597 bool "Architected timer support"
1600 This option enables support for the ARM architected timer
1606 This options enables support for the ARM timer and watchdog unit
1609 prompt "Memory split"
1612 Select the desired split between kernel and user memory.
1614 If you are not absolutely sure what you are doing, leave this
1618 bool "3G/1G user/kernel split"
1620 bool "2G/2G user/kernel split"
1622 bool "1G/3G user/kernel split"
1627 default 0x40000000 if VMSPLIT_1G
1628 default 0x80000000 if VMSPLIT_2G
1632 int "Maximum number of CPUs (2-32)"
1638 bool "Support for hot-pluggable CPUs"
1639 depends on SMP && HOTPLUG
1641 Say Y here to experiment with turning CPUs off and on. CPUs
1642 can be controlled through /sys/devices/system/cpu.
1645 bool "Use local timer interrupts"
1648 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1650 Enable support for local timers on SMP platforms, rather then the
1651 legacy IPI broadcast method. Local timers allows the system
1652 accounting to be spread across the timer interval, preventing a
1653 "thundering herd" at every timer tick.
1657 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1658 default 355 if ARCH_U8500
1659 default 264 if MACH_H4700
1660 default 512 if SOC_OMAP5
1661 default 288 if ARCH_VT8500
1664 Maximum number of GPIOs in the system.
1666 If unsure, leave the default value.
1668 source kernel/Kconfig.preempt
1672 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1673 ARCH_S5PV210 || ARCH_EXYNOS4
1674 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1675 default AT91_TIMER_HZ if ARCH_AT91
1676 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1679 config THUMB2_KERNEL
1680 bool "Compile the kernel in Thumb-2 mode"
1681 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1683 select ARM_ASM_UNIFIED
1686 By enabling this option, the kernel will be compiled in
1687 Thumb-2 mode. A compiler/assembler that understand the unified
1688 ARM-Thumb syntax is needed.
1692 config THUMB2_AVOID_R_ARM_THM_JUMP11
1693 bool "Work around buggy Thumb-2 short branch relocations in gas"
1694 depends on THUMB2_KERNEL && MODULES
1697 Various binutils versions can resolve Thumb-2 branches to
1698 locally-defined, preemptible global symbols as short-range "b.n"
1699 branch instructions.
1701 This is a problem, because there's no guarantee the final
1702 destination of the symbol, or any candidate locations for a
1703 trampoline, are within range of the branch. For this reason, the
1704 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1705 relocation in modules at all, and it makes little sense to add
1708 The symptom is that the kernel fails with an "unsupported
1709 relocation" error when loading some modules.
1711 Until fixed tools are available, passing
1712 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1713 code which hits this problem, at the cost of a bit of extra runtime
1714 stack usage in some cases.
1716 The problem is described in more detail at:
1717 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1719 Only Thumb-2 kernels are affected.
1721 Unless you are sure your tools don't have this problem, say Y.
1723 config ARM_ASM_UNIFIED
1727 bool "Use the ARM EABI to compile the kernel"
1729 This option allows for the kernel to be compiled using the latest
1730 ARM ABI (aka EABI). This is only useful if you are using a user
1731 space environment that is also compiled with EABI.
1733 Since there are major incompatibilities between the legacy ABI and
1734 EABI, especially with regard to structure member alignment, this
1735 option also changes the kernel syscall calling convention to
1736 disambiguate both ABIs and allow for backward compatibility support
1737 (selected with CONFIG_OABI_COMPAT).
1739 To use this you need GCC version 4.0.0 or later.
1742 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1743 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1746 This option preserves the old syscall interface along with the
1747 new (ARM EABI) one. It also provides a compatibility layer to
1748 intercept syscalls that have structure arguments which layout
1749 in memory differs between the legacy ABI and the new ARM EABI
1750 (only for non "thumb" binaries). This option adds a tiny
1751 overhead to all syscalls and produces a slightly larger kernel.
1752 If you know you'll be using only pure EABI user space then you
1753 can say N here. If this option is not selected and you attempt
1754 to execute a legacy ABI binary then the result will be
1755 UNPREDICTABLE (in fact it can be predicted that it won't work
1756 at all). If in doubt say Y.
1758 config ARCH_HAS_HOLES_MEMORYMODEL
1761 config ARCH_SPARSEMEM_ENABLE
1764 config ARCH_SPARSEMEM_DEFAULT
1765 def_bool ARCH_SPARSEMEM_ENABLE
1767 config ARCH_SELECT_MEMORY_MODEL
1768 def_bool ARCH_SPARSEMEM_ENABLE
1770 config HAVE_ARCH_PFN_VALID
1771 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1774 bool "High Memory Support"
1777 The address space of ARM processors is only 4 Gigabytes large
1778 and it has to accommodate user address space, kernel address
1779 space as well as some memory mapped IO. That means that, if you
1780 have a large amount of physical memory and/or IO, not all of the
1781 memory can be "permanently mapped" by the kernel. The physical
1782 memory that is not permanently mapped is called "high memory".
1784 Depending on the selected kernel/user memory split, minimum
1785 vmalloc space and actual amount of RAM, you may not need this
1786 option which should result in a slightly faster kernel.
1791 bool "Allocate 2nd-level pagetables from highmem"
1794 config HW_PERF_EVENTS
1795 bool "Enable hardware performance counter support for perf events"
1796 depends on PERF_EVENTS
1799 Enable hardware performance counter support for perf events. If
1800 disabled, perf events will use software events only.
1804 config FORCE_MAX_ZONEORDER
1805 int "Maximum zone order" if ARCH_SHMOBILE
1806 range 11 64 if ARCH_SHMOBILE
1807 default "12" if SOC_AM33XX
1808 default "9" if SA1111
1811 The kernel memory allocator divides physically contiguous memory
1812 blocks into "zones", where each zone is a power of two number of
1813 pages. This option selects the largest power of two that the kernel
1814 keeps in the memory allocator. If you need to allocate very large
1815 blocks of physically contiguous memory, then you may need to
1816 increase this value.
1818 This config option is actually maximum order plus one. For example,
1819 a value of 11 means that the largest free memory block is 2^10 pages.
1821 config ALIGNMENT_TRAP
1823 depends on CPU_CP15_MMU
1824 default y if !ARCH_EBSA110
1825 select HAVE_PROC_CPU if PROC_FS
1827 ARM processors cannot fetch/store information which is not
1828 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1829 address divisible by 4. On 32-bit ARM processors, these non-aligned
1830 fetch/store instructions will be emulated in software if you say
1831 here, which has a severe performance impact. This is necessary for
1832 correct operation of some network protocols. With an IP-only
1833 configuration it is safe to say N, otherwise say Y.
1835 config UACCESS_WITH_MEMCPY
1836 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1838 default y if CPU_FEROCEON
1840 Implement faster copy_to_user and clear_user methods for CPU
1841 cores where a 8-word STM instruction give significantly higher
1842 memory write throughput than a sequence of individual 32bit stores.
1844 A possible side effect is a slight increase in scheduling latency
1845 between threads sharing the same address space if they invoke
1846 such copy operations with large buffers.
1848 However, if the CPU data cache is using a write-allocate mode,
1849 this option is unlikely to provide any performance gain.
1853 prompt "Enable seccomp to safely compute untrusted bytecode"
1855 This kernel feature is useful for number crunching applications
1856 that may need to compute untrusted bytecode during their
1857 execution. By using pipes or other transports made available to
1858 the process as file descriptors supporting the read/write
1859 syscalls, it's possible to isolate those applications in
1860 their own address space using seccomp. Once seccomp is
1861 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1862 and the task is only allowed to execute a few safe syscalls
1863 defined by each seccomp mode.
1865 config CC_STACKPROTECTOR
1866 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1867 depends on EXPERIMENTAL
1869 This option turns on the -fstack-protector GCC feature. This
1870 feature puts, at the beginning of functions, a canary value on
1871 the stack just before the return address, and validates
1872 the value just before actually returning. Stack based buffer
1873 overflows (that need to overwrite this return address) now also
1874 overwrite the canary, which gets detected and the attack is then
1875 neutralized via a kernel panic.
1876 This feature requires gcc version 4.2 or above.
1883 bool "Xen guest support on ARM (EXPERIMENTAL)"
1884 depends on EXPERIMENTAL && ARM && OF
1885 depends on CPU_V7 && !CPU_V6
1887 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1894 bool "Flattened Device Tree support"
1897 select OF_EARLY_FLATTREE
1899 Include support for flattened device tree machine descriptions.
1902 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1905 This is the traditional way of passing data to the kernel at boot
1906 time. If you are solely relying on the flattened device tree (or
1907 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1908 to remove ATAGS support from your kernel binary. If unsure,
1911 config DEPRECATED_PARAM_STRUCT
1912 bool "Provide old way to pass kernel parameters"
1915 This was deprecated in 2001 and announced to live on for 5 years.
1916 Some old boot loaders still use this way.
1918 # Compressed boot loader in ROM. Yes, we really want to ask about
1919 # TEXT and BSS so we preserve their values in the config files.
1920 config ZBOOT_ROM_TEXT
1921 hex "Compressed ROM boot loader base address"
1924 The physical address at which the ROM-able zImage is to be
1925 placed in the target. Platforms which normally make use of
1926 ROM-able zImage formats normally set this to a suitable
1927 value in their defconfig file.
1929 If ZBOOT_ROM is not enabled, this has no effect.
1931 config ZBOOT_ROM_BSS
1932 hex "Compressed ROM boot loader BSS address"
1935 The base address of an area of read/write memory in the target
1936 for the ROM-able zImage which must be available while the
1937 decompressor is running. It must be large enough to hold the
1938 entire decompressed kernel plus an additional 128 KiB.
1939 Platforms which normally make use of ROM-able zImage formats
1940 normally set this to a suitable value in their defconfig file.
1942 If ZBOOT_ROM is not enabled, this has no effect.
1945 bool "Compressed boot loader in ROM/flash"
1946 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1948 Say Y here if you intend to execute your compressed kernel image
1949 (zImage) directly from ROM or flash. If unsure, say N.
1952 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1953 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1954 default ZBOOT_ROM_NONE
1956 Include experimental SD/MMC loading code in the ROM-able zImage.
1957 With this enabled it is possible to write the ROM-able zImage
1958 kernel image to an MMC or SD card and boot the kernel straight
1959 from the reset vector. At reset the processor Mask ROM will load
1960 the first part of the ROM-able zImage which in turn loads the
1961 rest the kernel image to RAM.
1963 config ZBOOT_ROM_NONE
1964 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1966 Do not load image from SD or MMC
1968 config ZBOOT_ROM_MMCIF
1969 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1971 Load image from MMCIF hardware block.
1973 config ZBOOT_ROM_SH_MOBILE_SDHI
1974 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1976 Load image from SDHI hardware block
1980 config ARM_APPENDED_DTB
1981 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1982 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1984 With this option, the boot code will look for a device tree binary
1985 (DTB) appended to zImage
1986 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1988 This is meant as a backward compatibility convenience for those
1989 systems with a bootloader that can't be upgraded to accommodate
1990 the documented boot protocol using a device tree.
1992 Beware that there is very little in terms of protection against
1993 this option being confused by leftover garbage in memory that might
1994 look like a DTB header after a reboot if no actual DTB is appended
1995 to zImage. Do not leave this option active in a production kernel
1996 if you don't intend to always append a DTB. Proper passing of the
1997 location into r2 of a bootloader provided DTB is always preferable
2000 config ARM_ATAG_DTB_COMPAT
2001 bool "Supplement the appended DTB with traditional ATAG information"
2002 depends on ARM_APPENDED_DTB
2004 Some old bootloaders can't be updated to a DTB capable one, yet
2005 they provide ATAGs with memory configuration, the ramdisk address,
2006 the kernel cmdline string, etc. Such information is dynamically
2007 provided by the bootloader and can't always be stored in a static
2008 DTB. To allow a device tree enabled kernel to be used with such
2009 bootloaders, this option allows zImage to extract the information
2010 from the ATAG list and store it at run time into the appended DTB.
2013 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2014 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2016 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017 bool "Use bootloader kernel arguments if available"
2019 Uses the command-line options passed by the boot loader instead of
2020 the device tree bootargs property. If the boot loader doesn't provide
2021 any, the device tree bootargs property will be used.
2023 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2024 bool "Extend with bootloader kernel arguments"
2026 The command-line arguments provided by the boot loader will be
2027 appended to the the device tree bootargs property.
2032 string "Default kernel command string"
2035 On some architectures (EBSA110 and CATS), there is currently no way
2036 for the boot loader to pass arguments to the kernel. For these
2037 architectures, you should supply some command-line options at build
2038 time by entering them here. As a minimum, you should specify the
2039 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2042 prompt "Kernel command line type" if CMDLINE != ""
2043 default CMDLINE_FROM_BOOTLOADER
2046 config CMDLINE_FROM_BOOTLOADER
2047 bool "Use bootloader kernel arguments if available"
2049 Uses the command-line options passed by the boot loader. If
2050 the boot loader doesn't provide any, the default kernel command
2051 string provided in CMDLINE will be used.
2053 config CMDLINE_EXTEND
2054 bool "Extend bootloader kernel arguments"
2056 The command-line arguments provided by the boot loader will be
2057 appended to the default kernel command string.
2059 config CMDLINE_FORCE
2060 bool "Always use the default kernel command string"
2062 Always use the default kernel command string, even if the boot
2063 loader passes other arguments to the kernel.
2064 This is useful if you cannot or don't want to change the
2065 command-line options your boot loader passes to the kernel.
2069 bool "Kernel Execute-In-Place from ROM"
2070 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2072 Execute-In-Place allows the kernel to run from non-volatile storage
2073 directly addressable by the CPU, such as NOR flash. This saves RAM
2074 space since the text section of the kernel is not loaded from flash
2075 to RAM. Read-write sections, such as the data section and stack,
2076 are still copied to RAM. The XIP kernel is not compressed since
2077 it has to run directly from flash, so it will take more space to
2078 store it. The flash address used to link the kernel object files,
2079 and for storing it, is configuration dependent. Therefore, if you
2080 say Y here, you must know the proper physical address where to
2081 store the kernel image depending on your own flash memory usage.
2083 Also note that the make target becomes "make xipImage" rather than
2084 "make zImage" or "make Image". The final kernel binary to put in
2085 ROM memory will be arch/arm/boot/xipImage.
2089 config XIP_PHYS_ADDR
2090 hex "XIP Kernel Physical Location"
2091 depends on XIP_KERNEL
2092 default "0x00080000"
2094 This is the physical address in your flash memory the kernel will
2095 be linked for and stored to. This address is dependent on your
2099 bool "Kexec system call (EXPERIMENTAL)"
2100 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2102 kexec is a system call that implements the ability to shutdown your
2103 current kernel, and to start another kernel. It is like a reboot
2104 but it is independent of the system firmware. And like a reboot
2105 you can start any kernel with it, not just Linux.
2107 It is an ongoing process to be certain the hardware in a machine
2108 is properly shutdown, so do not be surprised if this code does not
2109 initially work for you. It may help to enable device hotplugging
2113 bool "Export atags in procfs"
2114 depends on ATAGS && KEXEC
2117 Should the atags used to boot the kernel be exported in an "atags"
2118 file in procfs. Useful with kexec.
2121 bool "Build kdump crash kernel (EXPERIMENTAL)"
2122 depends on EXPERIMENTAL
2124 Generate crash dump after being started by kexec. This should
2125 be normally only set in special crash dump kernels which are
2126 loaded in the main kernel with kexec-tools into a specially
2127 reserved region and then later executed after a crash by
2128 kdump/kexec. The crash dump kernel must be compiled to a
2129 memory address not used by the main kernel
2131 For more details see Documentation/kdump/kdump.txt
2133 config AUTO_ZRELADDR
2134 bool "Auto calculation of the decompressed kernel image address"
2135 depends on !ZBOOT_ROM && !ARCH_U300
2137 ZRELADDR is the physical address where the decompressed kernel
2138 image will be placed. If AUTO_ZRELADDR is selected, the address
2139 will be determined at run-time by masking the current IP with
2140 0xf8000000. This assumes the zImage being placed in the first 128MB
2141 from start of memory.
2145 menu "CPU Power Management"
2149 source "drivers/cpufreq/Kconfig"
2152 tristate "CPUfreq driver for i.MX CPUs"
2153 depends on ARCH_MXC && CPU_FREQ
2154 select CPU_FREQ_TABLE
2156 This enables the CPUfreq driver for i.MX CPUs.
2158 config CPU_FREQ_SA1100
2161 config CPU_FREQ_SA1110
2164 config CPU_FREQ_INTEGRATOR
2165 tristate "CPUfreq driver for ARM Integrator CPUs"
2166 depends on ARCH_INTEGRATOR && CPU_FREQ
2169 This enables the CPUfreq driver for ARM Integrator CPUs.
2171 For details, take a look at <file:Documentation/cpu-freq>.
2177 depends on CPU_FREQ && ARCH_PXA && PXA25x
2179 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2180 select CPU_FREQ_TABLE
2185 Internal configuration node for common cpufreq on Samsung SoC
2187 config CPU_FREQ_S3C24XX
2188 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2189 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2192 This enables the CPUfreq driver for the Samsung S3C24XX family
2195 For details, take a look at <file:Documentation/cpu-freq>.
2199 config CPU_FREQ_S3C24XX_PLL
2200 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2201 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2203 Compile in support for changing the PLL frequency from the
2204 S3C24XX series CPUfreq driver. The PLL takes time to settle
2205 after a frequency change, so by default it is not enabled.
2207 This also means that the PLL tables for the selected CPU(s) will
2208 be built which may increase the size of the kernel image.
2210 config CPU_FREQ_S3C24XX_DEBUG
2211 bool "Debug CPUfreq Samsung driver core"
2212 depends on CPU_FREQ_S3C24XX
2214 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2216 config CPU_FREQ_S3C24XX_IODEBUG
2217 bool "Debug CPUfreq Samsung driver IO timing"
2218 depends on CPU_FREQ_S3C24XX
2220 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2222 config CPU_FREQ_S3C24XX_DEBUGFS
2223 bool "Export debugfs for CPUFreq"
2224 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2226 Export status information via debugfs.
2230 source "drivers/cpuidle/Kconfig"
2234 menu "Floating point emulation"
2236 comment "At least one emulation must be selected"
2239 bool "NWFPE math emulation"
2240 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2242 Say Y to include the NWFPE floating point emulator in the kernel.
2243 This is necessary to run most binaries. Linux does not currently
2244 support floating point hardware so you need to say Y here even if
2245 your machine has an FPA or floating point co-processor podule.
2247 You may say N here if you are going to load the Acorn FPEmulator
2248 early in the bootup.
2251 bool "Support extended precision"
2252 depends on FPE_NWFPE
2254 Say Y to include 80-bit support in the kernel floating-point
2255 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2256 Note that gcc does not generate 80-bit operations by default,
2257 so in most cases this option only enlarges the size of the
2258 floating point emulator without any good reason.
2260 You almost surely want to say N here.
2263 bool "FastFPE math emulation (EXPERIMENTAL)"
2264 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2266 Say Y here to include the FAST floating point emulator in the kernel.
2267 This is an experimental much faster emulator which now also has full
2268 precision for the mantissa. It does not support any exceptions.
2269 It is very simple, and approximately 3-6 times faster than NWFPE.
2271 It should be sufficient for most programs. It may be not suitable
2272 for scientific calculations, but you have to check this for yourself.
2273 If you do not feel you need a faster FP emulation you should better
2277 bool "VFP-format floating point maths"
2278 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2280 Say Y to include VFP support code in the kernel. This is needed
2281 if your hardware includes a VFP unit.
2283 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2284 release notes and additional status information.
2286 Say N if your target does not have VFP hardware.
2294 bool "Advanced SIMD (NEON) Extension support"
2295 depends on VFPv3 && CPU_V7
2297 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2302 menu "Userspace binary formats"
2304 source "fs/Kconfig.binfmt"
2307 tristate "RISC OS personality"
2310 Say Y here to include the kernel code necessary if you want to run
2311 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2312 experimental; if this sounds frightening, say N and sleep in peace.
2313 You can also say M here to compile this support as a module (which
2314 will be called arthur).
2318 menu "Power management options"
2320 source "kernel/power/Kconfig"
2322 config ARCH_SUSPEND_POSSIBLE
2323 depends on !ARCH_S5PC100
2324 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2325 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2328 config ARM_CPU_SUSPEND
2333 source "net/Kconfig"
2335 source "drivers/Kconfig"
2339 source "arch/arm/Kconfig.debug"
2341 source "security/Kconfig"
2343 source "crypto/Kconfig"
2345 source "lib/Kconfig"