arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  41         select HAVE_ARCH_TRACEHOOK
  42         select HAVE_ARM_SMCCC if CPU_V7
  43         select HAVE_BPF_JIT
  44         select HAVE_CC_STACKPROTECTOR
  45         select HAVE_CONTEXT_TRACKING
  46         select HAVE_C_RECORDMCOUNT
  47         select HAVE_DEBUG_KMEMLEAK
  48         select HAVE_DMA_API_DEBUG
  49         select HAVE_DMA_ATTRS
  50         select HAVE_DMA_CONTIGUOUS if MMU
  51         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  53         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  54         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  55         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  56         select HAVE_GENERIC_DMA_COHERENT
  57         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  58         select HAVE_IDE if PCI || ISA || PCMCIA
  59         select HAVE_IRQ_TIME_ACCOUNTING
  60         select HAVE_KERNEL_GZIP
  61         select HAVE_KERNEL_LZ4
  62         select HAVE_KERNEL_LZMA
  63         select HAVE_KERNEL_LZO
  64         select HAVE_KERNEL_XZ
  65         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  66         select HAVE_KRETPROBES if (HAVE_KPROBES)
  67         select HAVE_MEMBLOCK
  68         select HAVE_MOD_ARCH_SPECIFIC
  69         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  70         select HAVE_OPTPROBES if !THUMB2_KERNEL
  71         select HAVE_PERF_EVENTS
  72         select HAVE_PERF_REGS
  73         select HAVE_PERF_USER_STACK_DUMP
  74         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  75         select HAVE_REGS_AND_STACK_ACCESS_API
  76         select HAVE_SYSCALL_TRACEPOINTS
  77         select HAVE_UID16
  78         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  79         select IRQ_FORCED_THREADING
  80         select MODULES_USE_ELF_REL
  81         select NO_BOOTMEM
  82         select OF_EARLY_FLATTREE if OF
  83         select OF_RESERVED_MEM if OF
  84         select OLD_SIGACTION
  85         select OLD_SIGSUSPEND3
  86         select PERF_USE_VMALLOC
  87         select RTC_LIB
  88         select SYS_SUPPORTS_APM_EMULATION
  89         # Above selects are sorted alphabetically; please add new ones
  90         # according to that.  Thanks.
  91         help
  92           The ARM series is a line of low-power-consumption RISC chip designs
  93           licensed by ARM Ltd and targeted at embedded applications and
  94           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  95           manufactured, but legacy ARM-based PC hardware remains popular in
  96           Europe.  There is an ARM Linux project with a web page at
  97           <http://www.arm.linux.org.uk/>.
  98
  99 config ARM_HAS_SG_CHAIN
 100         select ARCH_HAS_SG_CHAIN
 101         bool
 102
 103 config NEED_SG_DMA_LENGTH
 104         bool
 105
 106 config ARM_DMA_USE_IOMMU
 107         bool
 108         select ARM_HAS_SG_CHAIN
 109         select NEED_SG_DMA_LENGTH
 110
 111 if ARM_DMA_USE_IOMMU
 112
 113 config ARM_DMA_IOMMU_ALIGNMENT
 114         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 115         range 4 9
 116         default 8
 117         help
 118           DMA mapping framework by default aligns all buffers to the smallest
 119           PAGE_SIZE order which is greater than or equal to the requested buffer
 120           size. This works well for buffers up to a few hundreds kilobytes, but
 121           for larger buffers it just a waste of address space. Drivers which has
 122           relatively small addressing window (like 64Mib) might run out of
 123           virtual space with just a few allocations.
 124
 125           With this parameter you can specify the maximum PAGE_SIZE order for
 126           DMA IOMMU buffers. Larger buffers will be aligned only to this
 127           specified order. The order is expressed as a power of two multiplied
 128           by the PAGE_SIZE.
 129
 130 endif
 131
 132 config MIGHT_HAVE_PCI
 133         bool
 134
 135 config SYS_SUPPORTS_APM_EMULATION
 136         bool
 137
 138 config HAVE_TCM
 139         bool
 140         select GENERIC_ALLOCATOR
 141
 142 config HAVE_PROC_CPU
 143         bool
 144
 145 config NO_IOPORT_MAP
 146         bool
 147
 148 config EISA
 149         bool
 150         ---help---
 151           The Extended Industry Standard Architecture (EISA) bus was
 152           developed as an open alternative to the IBM MicroChannel bus.
 153
 154           The EISA bus provided some of the features of the IBM MicroChannel
 155           bus while maintaining backward compatibility with cards made for
 156           the older ISA bus.  The EISA bus saw limited use between 1988 and
 157           1995 when it was made obsolete by the PCI bus.
 158
 159           Say Y here if you are building a kernel for an EISA-based machine.
 160
 161           Otherwise, say N.
 162
 163 config SBUS
 164         bool
 165
 166 config STACKTRACE_SUPPORT
 167         bool
 168         default y
 169
 170 config HAVE_LATENCYTOP_SUPPORT
 171         bool
 172         depends on !SMP
 173         default y
 174
 175 config LOCKDEP_SUPPORT
 176         bool
 177         default y
 178
 179 config TRACE_IRQFLAGS_SUPPORT
 180         bool
 181         default !CPU_V7M
 182
 183 config RWSEM_XCHGADD_ALGORITHM
 184         bool
 185         default y
 186
 187 config ARCH_HAS_ILOG2_U32
 188         bool
 189
 190 config ARCH_HAS_ILOG2_U64
 191         bool
 192
 193 config ARCH_HAS_BANDGAP
 194         bool
 195
 196 config FIX_EARLYCON_MEM
 197         def_bool y if MMU
 198
 199 config GENERIC_HWEIGHT
 200         bool
 201         default y
 202
 203 config GENERIC_CALIBRATE_DELAY
 204         bool
 205         default y
 206
 207 config ARCH_MAY_HAVE_PC_FDC
 208         bool
 209
 210 config ZONE_DMA
 211         bool
 212
 213 config NEED_DMA_MAP_STATE
 214        def_bool y
 215
 216 config ARCH_SUPPORTS_UPROBES
 217         def_bool y
 218
 219 config ARCH_HAS_DMA_SET_COHERENT_MASK
 220         bool
 221
 222 config GENERIC_ISA_DMA
 223         bool
 224
 225 config FIQ
 226         bool
 227
 228 config NEED_RET_TO_USER
 229         bool
 230
 231 config ARCH_MTD_XIP
 232         bool
 233
 234 config VECTORS_BASE
 235         hex
 236         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 237         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 238         default 0x00000000
 239         help
 240           The base address of exception vectors.  This must be two pages
 241           in size.
 242
 243 config ARM_PATCH_PHYS_VIRT
 244         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 245         default y
 246         depends on !XIP_KERNEL && MMU
 247         depends on !ARCH_REALVIEW || !SPARSEMEM
 248         help
 249           Patch phys-to-virt and virt-to-phys translation functions at
 250           boot and module load time according to the position of the
 251           kernel in system memory.
 252
 253           This can only be used with non-XIP MMU kernels where the base
 254           of physical memory is at a 16MB boundary.
 255
 256           Only disable this option if you know that you do not require
 257           this feature (eg, building a kernel for a single machine) and
 258           you need to shrink the kernel to the minimal size.
 259
 260 config NEED_MACH_IO_H
 261         bool
 262         help
 263           Select this when mach/io.h is required to provide special
 264           definitions for this platform.  The need for mach/io.h should
 265           be avoided when possible.
 266
 267 config NEED_MACH_MEMORY_H
 268         bool
 269         help
 270           Select this when mach/memory.h is required to provide special
 271           definitions for this platform.  The need for mach/memory.h should
 272           be avoided when possible.
 273
 274 config PHYS_OFFSET
 275         hex "Physical address of main memory" if MMU
 276         depends on !ARM_PATCH_PHYS_VIRT
 277         default DRAM_BASE if !MMU
 278         default 0x00000000 if ARCH_EBSA110 || \
 279                         ARCH_FOOTBRIDGE || \
 280                         ARCH_INTEGRATOR || \
 281                         ARCH_IOP13XX || \
 282                         ARCH_KS8695 || \
 283                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 284         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 285         default 0x20000000 if ARCH_S5PV210
 286         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 287         default 0xc0000000 if ARCH_SA1100
 288         help
 289           Please provide the physical address corresponding to the
 290           location of main memory in your system.
 291
 292 config GENERIC_BUG
 293         def_bool y
 294         depends on BUG
 295
 296 config PGTABLE_LEVELS
 297         int
 298         default 3 if ARM_LPAE
 299         default 2
 300
 301 source "init/Kconfig"
 302
 303 source "kernel/Kconfig.freezer"
 304
 305 menu "System Type"
 306
 307 config MMU
 308         bool "MMU-based Paged Memory Management Support"
 309         default y
 310         help
 311           Select if you want MMU-based virtualised addressing space
 312           support by paged memory management. If unsure, say 'Y'.
 313
 314 #
 315 # The "ARM system type" choice list is ordered alphabetically by option
 316 # text.  Please add new entries in the option alphabetic order.
 317 #
 318 choice
 319         prompt "ARM system type"
 320         default ARCH_VERSATILE if !MMU
 321         default ARCH_MULTIPLATFORM if MMU
 322
 323 config ARCH_MULTIPLATFORM
 324         bool "Allow multiple platforms to be selected"
 325         depends on MMU
 326         select ARCH_WANT_OPTIONAL_GPIOLIB
 327         select ARM_HAS_SG_CHAIN
 328         select ARM_PATCH_PHYS_VIRT
 329         select AUTO_ZRELADDR
 330         select CLKSRC_OF
 331         select COMMON_CLK
 332         select GENERIC_CLOCKEVENTS
 333         select MIGHT_HAVE_PCI
 334         select MULTI_IRQ_HANDLER
 335         select SPARSE_IRQ
 336         select USE_OF
 337
 338 config ARM_SINGLE_ARMV7M
 339         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 340         depends on !MMU
 341         select ARCH_WANT_OPTIONAL_GPIOLIB
 342         select ARM_NVIC
 343         select AUTO_ZRELADDR
 344         select CLKSRC_OF
 345         select COMMON_CLK
 346         select CPU_V7M
 347         select GENERIC_CLOCKEVENTS
 348         select NO_IOPORT_MAP
 349         select SPARSE_IRQ
 350         select USE_OF
 351
 352 config ARCH_REALVIEW
 353         bool "ARM Ltd. RealView family"
 354         select ARCH_WANT_OPTIONAL_GPIOLIB
 355         select ARM_AMBA
 356         select ARM_TIMER_SP804
 357         select COMMON_CLK
 358         select COMMON_CLK_VERSATILE
 359         select GENERIC_CLOCKEVENTS
 360         select GPIO_PL061 if GPIOLIB
 361         select ICST
 362         select NEED_MACH_MEMORY_H
 363         select PLAT_VERSATILE
 364         select PLAT_VERSATILE_SCHED_CLOCK
 365         help
 366           This enables support for ARM Ltd RealView boards.
 367
 368 config ARCH_VERSATILE
 369         bool "ARM Ltd. Versatile family"
 370         select ARCH_WANT_OPTIONAL_GPIOLIB
 371         select ARM_AMBA
 372         select ARM_TIMER_SP804
 373         select ARM_VIC
 374         select CLKDEV_LOOKUP
 375         select GENERIC_CLOCKEVENTS
 376         select HAVE_MACH_CLKDEV
 377         select ICST
 378         select PLAT_VERSATILE
 379         select PLAT_VERSATILE_CLOCK
 380         select PLAT_VERSATILE_SCHED_CLOCK
 381         select VERSATILE_FPGA_IRQ
 382         help
 383           This enables support for ARM Ltd Versatile board.
 384
 385 config ARCH_CLPS711X
 386         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select AUTO_ZRELADDR
 389         select CLKSRC_MMIO
 390         select COMMON_CLK
 391         select CPU_ARM720T
 392         select GENERIC_CLOCKEVENTS
 393         select MFD_SYSCON
 394         select SOC_BUS
 395         help
 396           Support for Cirrus Logic 711x/721x/731x based boards.
 397
 398 config ARCH_GEMINI
 399         bool "Cortina Systems Gemini"
 400         select ARCH_REQUIRE_GPIOLIB
 401         select CLKSRC_MMIO
 402         select CPU_FA526
 403         select GENERIC_CLOCKEVENTS
 404         help
 405           Support for the Cortina Systems Gemini family SoCs
 406
 407 config ARCH_EBSA110
 408         bool "EBSA-110"
 409         select ARCH_USES_GETTIMEOFFSET
 410         select CPU_SA110
 411         select ISA
 412         select NEED_MACH_IO_H
 413         select NEED_MACH_MEMORY_H
 414         select NO_IOPORT_MAP
 415         help
 416           This is an evaluation board for the StrongARM processor available
 417           from Digital. It has limited hardware on-board, including an
 418           Ethernet interface, two PCMCIA sockets, two serial ports and a
 419           parallel port.
 420
 421 config ARCH_EP93XX
 422         bool "EP93xx-based"
 423         select ARCH_HAS_HOLES_MEMORYMODEL
 424         select ARCH_REQUIRE_GPIOLIB
 425         select ARM_AMBA
 426         select ARM_PATCH_PHYS_VIRT
 427         select ARM_VIC
 428         select AUTO_ZRELADDR
 429         select CLKDEV_LOOKUP
 430         select CLKSRC_MMIO
 431         select CPU_ARM920T
 432         select GENERIC_CLOCKEVENTS
 433         help
 434           This enables support for the Cirrus EP93xx series of CPUs.
 435
 436 config ARCH_FOOTBRIDGE
 437         bool "FootBridge"
 438         select CPU_SA110
 439         select FOOTBRIDGE
 440         select GENERIC_CLOCKEVENTS
 441         select HAVE_IDE
 442         select NEED_MACH_IO_H if !MMU
 443         select NEED_MACH_MEMORY_H
 444         help
 445           Support for systems based on the DC21285 companion chip
 446           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 447
 448 config ARCH_NETX
 449         bool "Hilscher NetX based"
 450         select ARM_VIC
 451         select CLKSRC_MMIO
 452         select CPU_ARM926T
 453         select GENERIC_CLOCKEVENTS
 454         help
 455           This enables support for systems based on the Hilscher NetX Soc
 456
 457 config ARCH_IOP13XX
 458         bool "IOP13xx-based"
 459         depends on MMU
 460         select CPU_XSC3
 461         select NEED_MACH_MEMORY_H
 462         select NEED_RET_TO_USER
 463         select PCI
 464         select PLAT_IOP
 465         select VMSPLIT_1G
 466         select SPARSE_IRQ
 467         help
 468           Support for Intel's IOP13XX (XScale) family of processors.
 469
 470 config ARCH_IOP32X
 471         bool "IOP32x-based"
 472         depends on MMU
 473         select ARCH_REQUIRE_GPIOLIB
 474         select CPU_XSCALE
 475         select GPIO_IOP
 476         select NEED_RET_TO_USER
 477         select PCI
 478         select PLAT_IOP
 479         help
 480           Support for Intel's 80219 and IOP32X (XScale) family of
 481           processors.
 482
 483 config ARCH_IOP33X
 484         bool "IOP33x-based"
 485         depends on MMU
 486         select ARCH_REQUIRE_GPIOLIB
 487         select CPU_XSCALE
 488         select GPIO_IOP
 489         select NEED_RET_TO_USER
 490         select PCI
 491         select PLAT_IOP
 492         help
 493           Support for Intel's IOP33X (XScale) family of processors.
 494
 495 config ARCH_IXP4XX
 496         bool "IXP4xx-based"
 497         depends on MMU
 498         select ARCH_HAS_DMA_SET_COHERENT_MASK
 499         select ARCH_REQUIRE_GPIOLIB
 500         select ARCH_SUPPORTS_BIG_ENDIAN
 501         select CLKSRC_MMIO
 502         select CPU_XSCALE
 503         select DMABOUNCE if PCI
 504         select GENERIC_CLOCKEVENTS
 505         select MIGHT_HAVE_PCI
 506         select NEED_MACH_IO_H
 507         select USB_EHCI_BIG_ENDIAN_DESC
 508         select USB_EHCI_BIG_ENDIAN_MMIO
 509         help
 510           Support for Intel's IXP4XX (XScale) family of processors.
 511
 512 config ARCH_DOVE
 513         bool "Marvell Dove"
 514         select ARCH_REQUIRE_GPIOLIB
 515         select CPU_PJ4
 516         select GENERIC_CLOCKEVENTS
 517         select MIGHT_HAVE_PCI
 518         select MVEBU_MBUS
 519         select PINCTRL
 520         select PINCTRL_DOVE
 521         select PLAT_ORION_LEGACY
 522         help
 523           Support for the Marvell Dove SoC 88AP510
 524
 525 config ARCH_MV78XX0
 526         bool "Marvell MV78xx0"
 527         select ARCH_REQUIRE_GPIOLIB
 528         select CPU_FEROCEON
 529         select GENERIC_CLOCKEVENTS
 530         select MVEBU_MBUS
 531         select PCI
 532         select PLAT_ORION_LEGACY
 533         help
 534           Support for the following Marvell MV78xx0 series SoCs:
 535           MV781x0, MV782x0.
 536
 537 config ARCH_ORION5X
 538         bool "Marvell Orion"
 539         depends on MMU
 540         select ARCH_REQUIRE_GPIOLIB
 541         select CPU_FEROCEON
 542         select GENERIC_CLOCKEVENTS
 543         select MVEBU_MBUS
 544         select PCI
 545         select PLAT_ORION_LEGACY
 546         select MULTI_IRQ_HANDLER
 547         help
 548           Support for the following Marvell Orion 5x series SoCs:
 549           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 550           Orion-2 (5281), Orion-1-90 (6183).
 551
 552 config ARCH_MMP
 553         bool "Marvell PXA168/910/MMP2"
 554         depends on MMU
 555         select ARCH_REQUIRE_GPIOLIB
 556         select CLKDEV_LOOKUP
 557         select GENERIC_ALLOCATOR
 558         select GENERIC_CLOCKEVENTS
 559         select GPIO_PXA
 560         select IRQ_DOMAIN
 561         select MULTI_IRQ_HANDLER
 562         select PINCTRL
 563         select PLAT_PXA
 564         select SPARSE_IRQ
 565         help
 566           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 567
 568 config ARCH_KS8695
 569         bool "Micrel/Kendin KS8695"
 570         select ARCH_REQUIRE_GPIOLIB
 571         select CLKSRC_MMIO
 572         select CPU_ARM922T
 573         select GENERIC_CLOCKEVENTS
 574         select NEED_MACH_MEMORY_H
 575         help
 576           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 577           System-on-Chip devices.
 578
 579 config ARCH_W90X900
 580         bool "Nuvoton W90X900 CPU"
 581         select ARCH_REQUIRE_GPIOLIB
 582         select CLKDEV_LOOKUP
 583         select CLKSRC_MMIO
 584         select CPU_ARM926T
 585         select GENERIC_CLOCKEVENTS
 586         help
 587           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 588           At present, the w90x900 has been renamed nuc900, regarding
 589           the ARM series product line, you can login the following
 590           link address to know more.
 591
 592           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 593                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 594
 595 config ARCH_LPC32XX
 596         bool "NXP LPC32XX"
 597         select ARCH_REQUIRE_GPIOLIB
 598         select ARM_AMBA
 599         select CLKDEV_LOOKUP
 600         select CLKSRC_MMIO
 601         select CPU_ARM926T
 602         select GENERIC_CLOCKEVENTS
 603         select HAVE_IDE
 604         select USE_OF
 605         help
 606           Support for the NXP LPC32XX family of processors
 607
 608 config ARCH_PXA
 609         bool "PXA2xx/PXA3xx-based"
 610         depends on MMU
 611         select ARCH_MTD_XIP
 612         select ARCH_REQUIRE_GPIOLIB
 613         select ARM_CPU_SUSPEND if PM
 614         select AUTO_ZRELADDR
 615         select COMMON_CLK
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_PXA
 618         select CLKSRC_MMIO
 619         select CLKSRC_OF
 620         select GENERIC_CLOCKEVENTS
 621         select GPIO_PXA
 622         select HAVE_IDE
 623         select IRQ_DOMAIN
 624         select MULTI_IRQ_HANDLER
 625         select PLAT_PXA
 626         select SPARSE_IRQ
 627         help
 628           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 629
 630 config ARCH_RPC
 631         bool "RiscPC"
 632         depends on MMU
 633         select ARCH_ACORN
 634         select ARCH_MAY_HAVE_PC_FDC
 635         select ARCH_SPARSEMEM_ENABLE
 636         select ARCH_USES_GETTIMEOFFSET
 637         select CPU_SA110
 638         select FIQ
 639         select HAVE_IDE
 640         select HAVE_PATA_PLATFORM
 641         select ISA_DMA_API
 642         select NEED_MACH_IO_H
 643         select NEED_MACH_MEMORY_H
 644         select NO_IOPORT_MAP
 645         select VIRT_TO_BUS
 646         help
 647           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 648           CD-ROM interface, serial and parallel port, and the floppy drive.
 649
 650 config ARCH_SA1100
 651         bool "SA1100-based"
 652         select ARCH_MTD_XIP
 653         select ARCH_REQUIRE_GPIOLIB
 654         select ARCH_SPARSEMEM_ENABLE
 655         select CLKDEV_LOOKUP
 656         select CLKSRC_MMIO
 657         select CLKSRC_PXA
 658         select CLKSRC_OF if OF
 659         select CPU_FREQ
 660         select CPU_SA1100
 661         select GENERIC_CLOCKEVENTS
 662         select HAVE_IDE
 663         select IRQ_DOMAIN
 664         select ISA
 665         select MULTI_IRQ_HANDLER
 666         select NEED_MACH_MEMORY_H
 667         select SPARSE_IRQ
 668         help
 669           Support for StrongARM 11x0 based boards.
 670
 671 config ARCH_S3C24XX
 672         bool "Samsung S3C24XX SoCs"
 673         select ARCH_REQUIRE_GPIOLIB
 674         select ATAGS
 675         select CLKDEV_LOOKUP
 676         select CLKSRC_SAMSUNG_PWM
 677         select GENERIC_CLOCKEVENTS
 678         select GPIO_SAMSUNG
 679         select HAVE_S3C2410_I2C if I2C
 680         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 681         select HAVE_S3C_RTC if RTC_CLASS
 682         select MULTI_IRQ_HANDLER
 683         select NEED_MACH_IO_H
 684         select SAMSUNG_ATAGS
 685         help
 686           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 687           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 688           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 689           Samsung SMDK2410 development board (and derivatives).
 690
 691 config ARCH_S3C64XX
 692         bool "Samsung S3C64XX"
 693         select ARCH_REQUIRE_GPIOLIB
 694         select ARM_AMBA
 695         select ARM_VIC
 696         select ATAGS
 697         select CLKDEV_LOOKUP
 698         select CLKSRC_SAMSUNG_PWM
 699         select COMMON_CLK_SAMSUNG
 700         select CPU_V6K
 701         select GENERIC_CLOCKEVENTS
 702         select GPIO_SAMSUNG
 703         select HAVE_S3C2410_I2C if I2C
 704         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 705         select HAVE_TCM
 706         select NO_IOPORT_MAP
 707         select PLAT_SAMSUNG
 708         select PM_GENERIC_DOMAINS if PM
 709         select S3C_DEV_NAND
 710         select S3C_GPIO_TRACK
 711         select SAMSUNG_ATAGS
 712         select SAMSUNG_WAKEMASK
 713         select SAMSUNG_WDT_RESET
 714         help
 715           Samsung S3C64XX series based systems
 716
 717 config ARCH_DAVINCI
 718         bool "TI DaVinci"
 719         select ARCH_HAS_HOLES_MEMORYMODEL
 720         select ARCH_REQUIRE_GPIOLIB
 721         select CLKDEV_LOOKUP
 722         select GENERIC_ALLOCATOR
 723         select GENERIC_CLOCKEVENTS
 724         select GENERIC_IRQ_CHIP
 725         select HAVE_IDE
 726         select USE_OF
 727         select ZONE_DMA
 728         help
 729           Support for TI's DaVinci platform.
 730
 731 config ARCH_OMAP1
 732         bool "TI OMAP1"
 733         depends on MMU
 734         select ARCH_HAS_HOLES_MEMORYMODEL
 735         select ARCH_OMAP
 736         select ARCH_REQUIRE_GPIOLIB
 737         select CLKDEV_LOOKUP
 738         select CLKSRC_MMIO
 739         select GENERIC_CLOCKEVENTS
 740         select GENERIC_IRQ_CHIP
 741         select HAVE_IDE
 742         select IRQ_DOMAIN
 743         select MULTI_IRQ_HANDLER
 744         select NEED_MACH_IO_H if PCCARD
 745         select NEED_MACH_MEMORY_H
 746         select SPARSE_IRQ
 747         help
 748           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 749
 750 endchoice
 751
 752 menu "Multiple platform selection"
 753         depends on ARCH_MULTIPLATFORM
 754
 755 comment "CPU Core family selection"
 756
 757 config ARCH_MULTI_V4
 758         bool "ARMv4 based platforms (FA526)"
 759         depends on !ARCH_MULTI_V6_V7
 760         select ARCH_MULTI_V4_V5
 761         select CPU_FA526
 762
 763 config ARCH_MULTI_V4T
 764         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 765         depends on !ARCH_MULTI_V6_V7
 766         select ARCH_MULTI_V4_V5
 767         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 768                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 769                 CPU_ARM925T || CPU_ARM940T)
 770
 771 config ARCH_MULTI_V5
 772         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 773         depends on !ARCH_MULTI_V6_V7
 774         select ARCH_MULTI_V4_V5
 775         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 776                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 777                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 778
 779 config ARCH_MULTI_V4_V5
 780         bool
 781
 782 config ARCH_MULTI_V6
 783         bool "ARMv6 based platforms (ARM11)"
 784         select ARCH_MULTI_V6_V7
 785         select CPU_V6K
 786
 787 config ARCH_MULTI_V7
 788         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 789         default y
 790         select ARCH_MULTI_V6_V7
 791         select CPU_V7
 792         select HAVE_SMP
 793
 794 config ARCH_MULTI_V6_V7
 795         bool
 796         select MIGHT_HAVE_CACHE_L2X0
 797
 798 config ARCH_MULTI_CPU_AUTO
 799         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 800         select ARCH_MULTI_V5
 801
 802 endmenu
 803
 804 config ARCH_VIRT
 805         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 806         select ARM_AMBA
 807         select ARM_GIC
 808         select ARM_GIC_V2M if PCI_MSI
 809         select ARM_GIC_V3
 810         select ARM_PSCI
 811         select HAVE_ARM_ARCH_TIMER
 812
 813 #
 814 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 815 # Kconfigs may be included either alphabetically (according to the
 816 # plat- suffix) or along side the corresponding mach-* source.
 817 #
 818 source "arch/arm/mach-mvebu/Kconfig"
 819
 820 source "arch/arm/mach-alpine/Kconfig"
 821
 822 source "arch/arm/mach-asm9260/Kconfig"
 823
 824 source "arch/arm/mach-at91/Kconfig"
 825
 826 source "arch/arm/mach-axxia/Kconfig"
 827
 828 source "arch/arm/mach-bcm/Kconfig"
 829
 830 source "arch/arm/mach-berlin/Kconfig"
 831
 832 source "arch/arm/mach-clps711x/Kconfig"
 833
 834 source "arch/arm/mach-cns3xxx/Kconfig"
 835
 836 source "arch/arm/mach-davinci/Kconfig"
 837
 838 source "arch/arm/mach-digicolor/Kconfig"
 839
 840 source "arch/arm/mach-dove/Kconfig"
 841
 842 source "arch/arm/mach-ep93xx/Kconfig"
 843
 844 source "arch/arm/mach-footbridge/Kconfig"
 845
 846 source "arch/arm/mach-gemini/Kconfig"
 847
 848 source "arch/arm/mach-highbank/Kconfig"
 849
 850 source "arch/arm/mach-hisi/Kconfig"
 851
 852 source "arch/arm/mach-integrator/Kconfig"
 853
 854 source "arch/arm/mach-iop32x/Kconfig"
 855
 856 source "arch/arm/mach-iop33x/Kconfig"
 857
 858 source "arch/arm/mach-iop13xx/Kconfig"
 859
 860 source "arch/arm/mach-ixp4xx/Kconfig"
 861
 862 source "arch/arm/mach-keystone/Kconfig"
 863
 864 source "arch/arm/mach-ks8695/Kconfig"
 865
 866 source "arch/arm/mach-meson/Kconfig"
 867
 868 source "arch/arm/mach-moxart/Kconfig"
 869
 870 source "arch/arm/mach-mv78xx0/Kconfig"
 871
 872 source "arch/arm/mach-imx/Kconfig"
 873
 874 source "arch/arm/mach-mediatek/Kconfig"
 875
 876 source "arch/arm/mach-mxs/Kconfig"
 877
 878 source "arch/arm/mach-netx/Kconfig"
 879
 880 source "arch/arm/mach-nomadik/Kconfig"
 881
 882 source "arch/arm/mach-nspire/Kconfig"
 883
 884 source "arch/arm/plat-omap/Kconfig"
 885
 886 source "arch/arm/mach-omap1/Kconfig"
 887
 888 source "arch/arm/mach-omap2/Kconfig"
 889
 890 source "arch/arm/mach-orion5x/Kconfig"
 891
 892 source "arch/arm/mach-picoxcell/Kconfig"
 893
 894 source "arch/arm/mach-pxa/Kconfig"
 895 source "arch/arm/plat-pxa/Kconfig"
 896
 897 source "arch/arm/mach-mmp/Kconfig"
 898
 899 source "arch/arm/mach-qcom/Kconfig"
 900
 901 source "arch/arm/mach-realview/Kconfig"
 902
 903 source "arch/arm/mach-rockchip/Kconfig"
 904
 905 source "arch/arm/mach-sa1100/Kconfig"
 906
 907 source "arch/arm/mach-socfpga/Kconfig"
 908
 909 source "arch/arm/mach-spear/Kconfig"
 910
 911 source "arch/arm/mach-sti/Kconfig"
 912
 913 source "arch/arm/mach-s3c24xx/Kconfig"
 914
 915 source "arch/arm/mach-s3c64xx/Kconfig"
 916
 917 source "arch/arm/mach-s5pv210/Kconfig"
 918
 919 source "arch/arm/mach-exynos/Kconfig"
 920 source "arch/arm/plat-samsung/Kconfig"
 921
 922 source "arch/arm/mach-shmobile/Kconfig"
 923
 924 source "arch/arm/mach-sunxi/Kconfig"
 925
 926 source "arch/arm/mach-prima2/Kconfig"
 927
 928 source "arch/arm/mach-tegra/Kconfig"
 929
 930 source "arch/arm/mach-u300/Kconfig"
 931
 932 source "arch/arm/mach-uniphier/Kconfig"
 933
 934 source "arch/arm/mach-ux500/Kconfig"
 935
 936 source "arch/arm/mach-versatile/Kconfig"
 937
 938 source "arch/arm/mach-vexpress/Kconfig"
 939 source "arch/arm/plat-versatile/Kconfig"
 940
 941 source "arch/arm/mach-vt8500/Kconfig"
 942
 943 source "arch/arm/mach-w90x900/Kconfig"
 944
 945 source "arch/arm/mach-zx/Kconfig"
 946
 947 source "arch/arm/mach-zynq/Kconfig"
 948
 949 # ARMv7-M architecture
 950 config ARCH_EFM32
 951         bool "Energy Micro efm32"
 952         depends on ARM_SINGLE_ARMV7M
 953         select ARCH_REQUIRE_GPIOLIB
 954         help
 955           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 956           processors.
 957
 958 config ARCH_LPC18XX
 959         bool "NXP LPC18xx/LPC43xx"
 960         depends on ARM_SINGLE_ARMV7M
 961         select ARCH_HAS_RESET_CONTROLLER
 962         select ARM_AMBA
 963         select CLKSRC_LPC32XX
 964         select PINCTRL
 965         help
 966           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 967           high performance microcontrollers.
 968
 969 config ARCH_STM32
 970         bool "STMicrolectronics STM32"
 971         depends on ARM_SINGLE_ARMV7M
 972         select ARCH_HAS_RESET_CONTROLLER
 973         select ARMV7M_SYSTICK
 974         select CLKSRC_STM32
 975         select RESET_CONTROLLER
 976         help
 977           Support for STMicroelectronics STM32 processors.
 978
 979 # Definitions to make life easier
 980 config ARCH_ACORN
 981         bool
 982
 983 config PLAT_IOP
 984         bool
 985         select GENERIC_CLOCKEVENTS
 986
 987 config PLAT_ORION
 988         bool
 989         select CLKSRC_MMIO
 990         select COMMON_CLK
 991         select GENERIC_IRQ_CHIP
 992         select IRQ_DOMAIN
 993
 994 config PLAT_ORION_LEGACY
 995         bool
 996         select PLAT_ORION
 997
 998 config PLAT_PXA
 999         bool
1000
1001 config PLAT_VERSATILE
1002         bool
1003
1004 source "arch/arm/firmware/Kconfig"
1005
1006 source arch/arm/mm/Kconfig
1007
1008 config IWMMXT
1009         bool "Enable iWMMXt support"
1010         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1011         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1012         help
1013           Enable support for iWMMXt context switching at run time if
1014           running on a CPU that supports it.
1015
1016 config MULTI_IRQ_HANDLER
1017         bool
1018         help
1019           Allow each machine to specify it's own IRQ handler at run time.
1020
1021 if !MMU
1022 source "arch/arm/Kconfig-nommu"
1023 endif
1024
1025 config PJ4B_ERRATA_4742
1026         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1027         depends on CPU_PJ4B && MACH_ARMADA_370
1028         default y
1029         help
1030           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1031           Event (WFE) IDLE states, a specific timing sensitivity exists between
1032           the retiring WFI/WFE instructions and the newly issued subsequent
1033           instructions.  This sensitivity can result in a CPU hang scenario.
1034           Workaround:
1035           The software must insert either a Data Synchronization Barrier (DSB)
1036           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1037           instruction
1038
1039 config ARM_ERRATA_326103
1040         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1041         depends on CPU_V6
1042         help
1043           Executing a SWP instruction to read-only memory does not set bit 11
1044           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1045           treat the access as a read, preventing a COW from occurring and
1046           causing the faulting task to livelock.
1047
1048 config ARM_ERRATA_411920
1049         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1050         depends on CPU_V6 || CPU_V6K
1051         help
1052           Invalidation of the Instruction Cache operation can
1053           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1054           It does not affect the MPCore. This option enables the ARM Ltd.
1055           recommended workaround.
1056
1057 config ARM_ERRATA_430973
1058         bool "ARM errata: Stale prediction on replaced interworking branch"
1059         depends on CPU_V7
1060         help
1061           This option enables the workaround for the 430973 Cortex-A8
1062           r1p* erratum. If a code sequence containing an ARM/Thumb
1063           interworking branch is replaced with another code sequence at the
1064           same virtual address, whether due to self-modifying code or virtual
1065           to physical address re-mapping, Cortex-A8 does not recover from the
1066           stale interworking branch prediction. This results in Cortex-A8
1067           executing the new code sequence in the incorrect ARM or Thumb state.
1068           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1069           and also flushes the branch target cache at every context switch.
1070           Note that setting specific bits in the ACTLR register may not be
1071           available in non-secure mode.
1072
1073 config ARM_ERRATA_458693
1074         bool "ARM errata: Processor deadlock when a false hazard is created"
1075         depends on CPU_V7
1076         depends on !ARCH_MULTIPLATFORM
1077         help
1078           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1079           erratum. For very specific sequences of memory operations, it is
1080           possible for a hazard condition intended for a cache line to instead
1081           be incorrectly associated with a different cache line. This false
1082           hazard might then cause a processor deadlock. The workaround enables
1083           the L1 caching of the NEON accesses and disables the PLD instruction
1084           in the ACTLR register. Note that setting specific bits in the ACTLR
1085           register may not be available in non-secure mode.
1086
1087 config ARM_ERRATA_460075
1088         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1089         depends on CPU_V7
1090         depends on !ARCH_MULTIPLATFORM
1091         help
1092           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1093           erratum. Any asynchronous access to the L2 cache may encounter a
1094           situation in which recent store transactions to the L2 cache are lost
1095           and overwritten with stale memory contents from external memory. The
1096           workaround disables the write-allocate mode for the L2 cache via the
1097           ACTLR register. Note that setting specific bits in the ACTLR register
1098           may not be available in non-secure mode.
1099
1100 config ARM_ERRATA_742230
1101         bool "ARM errata: DMB operation may be faulty"
1102         depends on CPU_V7 && SMP
1103         depends on !ARCH_MULTIPLATFORM
1104         help
1105           This option enables the workaround for the 742230 Cortex-A9
1106           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1107           between two write operations may not ensure the correct visibility
1108           ordering of the two writes. This workaround sets a specific bit in
1109           the diagnostic register of the Cortex-A9 which causes the DMB
1110           instruction to behave as a DSB, ensuring the correct behaviour of
1111           the two writes.
1112
1113 config ARM_ERRATA_742231
1114         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1115         depends on CPU_V7 && SMP
1116         depends on !ARCH_MULTIPLATFORM
1117         help
1118           This option enables the workaround for the 742231 Cortex-A9
1119           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1120           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1121           accessing some data located in the same cache line, may get corrupted
1122           data due to bad handling of the address hazard when the line gets
1123           replaced from one of the CPUs at the same time as another CPU is
1124           accessing it. This workaround sets specific bits in the diagnostic
1125           register of the Cortex-A9 which reduces the linefill issuing
1126           capabilities of the processor.
1127
1128 config ARM_ERRATA_643719
1129         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1130         depends on CPU_V7 && SMP
1131         default y
1132         help
1133           This option enables the workaround for the 643719 Cortex-A9 (prior to
1134           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1135           register returns zero when it should return one. The workaround
1136           corrects this value, ensuring cache maintenance operations which use
1137           it behave as intended and avoiding data corruption.
1138
1139 config ARM_ERRATA_720789
1140         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1141         depends on CPU_V7
1142         help
1143           This option enables the workaround for the 720789 Cortex-A9 (prior to
1144           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1145           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1146           As a consequence of this erratum, some TLB entries which should be
1147           invalidated are not, resulting in an incoherency in the system page
1148           tables. The workaround changes the TLB flushing routines to invalidate
1149           entries regardless of the ASID.
1150
1151 config ARM_ERRATA_743622
1152         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1153         depends on CPU_V7
1154         depends on !ARCH_MULTIPLATFORM
1155         help
1156           This option enables the workaround for the 743622 Cortex-A9
1157           (r2p*) erratum. Under very rare conditions, a faulty
1158           optimisation in the Cortex-A9 Store Buffer may lead to data
1159           corruption. This workaround sets a specific bit in the diagnostic
1160           register of the Cortex-A9 which disables the Store Buffer
1161           optimisation, preventing the defect from occurring. This has no
1162           visible impact on the overall performance or power consumption of the
1163           processor.
1164
1165 config ARM_ERRATA_751472
1166         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1167         depends on CPU_V7
1168         depends on !ARCH_MULTIPLATFORM
1169         help
1170           This option enables the workaround for the 751472 Cortex-A9 (prior
1171           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1172           completion of a following broadcasted operation if the second
1173           operation is received by a CPU before the ICIALLUIS has completed,
1174           potentially leading to corrupted entries in the cache or TLB.
1175
1176 config ARM_ERRATA_754322
1177         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1178         depends on CPU_V7
1179         help
1180           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1181           r3p*) erratum. A speculative memory access may cause a page table walk
1182           which starts prior to an ASID switch but completes afterwards. This
1183           can populate the micro-TLB with a stale entry which may be hit with
1184           the new ASID. This workaround places two dsb instructions in the mm
1185           switching code so that no page table walks can cross the ASID switch.
1186
1187 config ARM_ERRATA_754327
1188         bool "ARM errata: no automatic Store Buffer drain"
1189         depends on CPU_V7 && SMP
1190         help
1191           This option enables the workaround for the 754327 Cortex-A9 (prior to
1192           r2p0) erratum. The Store Buffer does not have any automatic draining
1193           mechanism and therefore a livelock may occur if an external agent
1194           continuously polls a memory location waiting to observe an update.
1195           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1196           written polling loops from denying visibility of updates to memory.
1197
1198 config ARM_ERRATA_364296
1199         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1200         depends on CPU_V6
1201         help
1202           This options enables the workaround for the 364296 ARM1136
1203           r0p2 erratum (possible cache data corruption with
1204           hit-under-miss enabled). It sets the undocumented bit 31 in
1205           the auxiliary control register and the FI bit in the control
1206           register, thus disabling hit-under-miss without putting the
1207           processor into full low interrupt latency mode. ARM11MPCore
1208           is not affected.
1209
1210 config ARM_ERRATA_764369
1211         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1212         depends on CPU_V7 && SMP
1213         help
1214           This option enables the workaround for erratum 764369
1215           affecting Cortex-A9 MPCore with two or more processors (all
1216           current revisions). Under certain timing circumstances, a data
1217           cache line maintenance operation by MVA targeting an Inner
1218           Shareable memory region may fail to proceed up to either the
1219           Point of Coherency or to the Point of Unification of the
1220           system. This workaround adds a DSB instruction before the
1221           relevant cache maintenance functions and sets a specific bit
1222           in the diagnostic control register of the SCU.
1223
1224 config ARM_ERRATA_775420
1225        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1226        depends on CPU_V7
1227        help
1228          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1229          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1230          operation aborts with MMU exception, it might cause the processor
1231          to deadlock. This workaround puts DSB before executing ISB if
1232          an abort may occur on cache maintenance.
1233
1234 config ARM_ERRATA_798181
1235         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1236         depends on CPU_V7 && SMP
1237         help
1238           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1239           adequately shooting down all use of the old entries. This
1240           option enables the Linux kernel workaround for this erratum
1241           which sends an IPI to the CPUs that are running the same ASID
1242           as the one being invalidated.
1243
1244 config ARM_ERRATA_773022
1245         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1246         depends on CPU_V7
1247         help
1248           This option enables the workaround for the 773022 Cortex-A15
1249           (up to r0p4) erratum. In certain rare sequences of code, the
1250           loop buffer may deliver incorrect instructions. This
1251           workaround disables the loop buffer to avoid the erratum.
1252
1253 endmenu
1254
1255 source "arch/arm/common/Kconfig"
1256
1257 menu "Bus support"
1258
1259 config ISA
1260         bool
1261         help
1262           Find out whether you have ISA slots on your motherboard.  ISA is the
1263           name of a bus system, i.e. the way the CPU talks to the other stuff
1264           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1265           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1266           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1267
1268 # Select ISA DMA controller support
1269 config ISA_DMA
1270         bool
1271         select ISA_DMA_API
1272
1273 # Select ISA DMA interface
1274 config ISA_DMA_API
1275         bool
1276
1277 config PCI
1278         bool "PCI support" if MIGHT_HAVE_PCI
1279         help
1280           Find out whether you have a PCI motherboard. PCI is the name of a
1281           bus system, i.e. the way the CPU talks to the other stuff inside
1282           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1283           VESA. If you have PCI, say Y, otherwise N.
1284
1285 config PCI_DOMAINS
1286         bool
1287         depends on PCI
1288
1289 config PCI_DOMAINS_GENERIC
1290         def_bool PCI_DOMAINS
1291
1292 config PCI_NANOENGINE
1293         bool "BSE nanoEngine PCI support"
1294         depends on SA1100_NANOENGINE
1295         help
1296           Enable PCI on the BSE nanoEngine board.
1297
1298 config PCI_SYSCALL
1299         def_bool PCI
1300
1301 config PCI_HOST_ITE8152
1302         bool
1303         depends on PCI && MACH_ARMCORE
1304         default y
1305         select DMABOUNCE
1306
1307 source "drivers/pci/Kconfig"
1308 source "drivers/pci/pcie/Kconfig"
1309
1310 source "drivers/pcmcia/Kconfig"
1311
1312 endmenu
1313
1314 menu "Kernel Features"
1315
1316 config HAVE_SMP
1317         bool
1318         help
1319           This option should be selected by machines which have an SMP-
1320           capable CPU.
1321
1322           The only effect of this option is to make the SMP-related
1323           options available to the user for configuration.
1324
1325 config SMP
1326         bool "Symmetric Multi-Processing"
1327         depends on CPU_V6K || CPU_V7
1328         depends on GENERIC_CLOCKEVENTS
1329         depends on HAVE_SMP
1330         depends on MMU || ARM_MPU
1331         select IRQ_WORK
1332         help
1333           This enables support for systems with more than one CPU. If you have
1334           a system with only one CPU, say N. If you have a system with more
1335           than one CPU, say Y.
1336
1337           If you say N here, the kernel will run on uni- and multiprocessor
1338           machines, but will use only one CPU of a multiprocessor machine. If
1339           you say Y here, the kernel will run on many, but not all,
1340           uniprocessor machines. On a uniprocessor machine, the kernel
1341           will run faster if you say N here.
1342
1343           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1344           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1345           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1346
1347           If you don't know what to do here, say N.
1348
1349 config SMP_ON_UP
1350         bool "Allow booting SMP kernel on uniprocessor systems"
1351         depends on SMP && !XIP_KERNEL && MMU
1352         default y
1353         help
1354           SMP kernels contain instructions which fail on non-SMP processors.
1355           Enabling this option allows the kernel to modify itself to make
1356           these instructions safe.  Disabling it allows about 1K of space
1357           savings.
1358
1359           If you don't know what to do here, say Y.
1360
1361 config ARM_CPU_TOPOLOGY
1362         bool "Support cpu topology definition"
1363         depends on SMP && CPU_V7
1364         default y
1365         help
1366           Support ARM cpu topology definition. The MPIDR register defines
1367           affinity between processors which is then used to describe the cpu
1368           topology of an ARM System.
1369
1370 config SCHED_MC
1371         bool "Multi-core scheduler support"
1372         depends on ARM_CPU_TOPOLOGY
1373         help
1374           Multi-core scheduler support improves the CPU scheduler's decision
1375           making when dealing with multi-core CPU chips at a cost of slightly
1376           increased overhead in some places. If unsure say N here.
1377
1378 config SCHED_SMT
1379         bool "SMT scheduler support"
1380         depends on ARM_CPU_TOPOLOGY
1381         help
1382           Improves the CPU scheduler's decision making when dealing with
1383           MultiThreading at a cost of slightly increased overhead in some
1384           places. If unsure say N here.
1385
1386 config HAVE_ARM_SCU
1387         bool
1388         help
1389           This option enables support for the ARM system coherency unit
1390
1391 config HAVE_ARM_ARCH_TIMER
1392         bool "Architected timer support"
1393         depends on CPU_V7
1394         select ARM_ARCH_TIMER
1395         select GENERIC_CLOCKEVENTS
1396         help
1397           This option enables support for the ARM architected timer
1398
1399 config HAVE_ARM_TWD
1400         bool
1401         select CLKSRC_OF if OF
1402         help
1403           This options enables support for the ARM timer and watchdog unit
1404
1405 config MCPM
1406         bool "Multi-Cluster Power Management"
1407         depends on CPU_V7 && SMP
1408         help
1409           This option provides the common power management infrastructure
1410           for (multi-)cluster based systems, such as big.LITTLE based
1411           systems.
1412
1413 config MCPM_QUAD_CLUSTER
1414         bool
1415         depends on MCPM
1416         help
1417           To avoid wasting resources unnecessarily, MCPM only supports up
1418           to 2 clusters by default.
1419           Platforms with 3 or 4 clusters that use MCPM must select this
1420           option to allow the additional clusters to be managed.
1421
1422 config BIG_LITTLE
1423         bool "big.LITTLE support (Experimental)"
1424         depends on CPU_V7 && SMP
1425         select MCPM
1426         help
1427           This option enables support selections for the big.LITTLE
1428           system architecture.
1429
1430 config BL_SWITCHER
1431         bool "big.LITTLE switcher support"
1432         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1433         select ARM_CPU_SUSPEND
1434         select CPU_PM
1435         help
1436           The big.LITTLE "switcher" provides the core functionality to
1437           transparently handle transition between a cluster of A15's
1438           and a cluster of A7's in a big.LITTLE system.
1439
1440 config BL_SWITCHER_DUMMY_IF
1441         tristate "Simple big.LITTLE switcher user interface"
1442         depends on BL_SWITCHER && DEBUG_KERNEL
1443         help
1444           This is a simple and dummy char dev interface to control
1445           the big.LITTLE switcher core code.  It is meant for
1446           debugging purposes only.
1447
1448 choice
1449         prompt "Memory split"
1450         depends on MMU
1451         default VMSPLIT_3G
1452         help
1453           Select the desired split between kernel and user memory.
1454
1455           If you are not absolutely sure what you are doing, leave this
1456           option alone!
1457
1458         config VMSPLIT_3G
1459                 bool "3G/1G user/kernel split"
1460         config VMSPLIT_3G_OPT
1461                 bool "3G/1G user/kernel split (for full 1G low memory)"
1462         config VMSPLIT_2G
1463                 bool "2G/2G user/kernel split"
1464         config VMSPLIT_1G
1465                 bool "1G/3G user/kernel split"
1466 endchoice
1467
1468 config PAGE_OFFSET
1469         hex
1470         default PHYS_OFFSET if !MMU
1471         default 0x40000000 if VMSPLIT_1G
1472         default 0x80000000 if VMSPLIT_2G
1473         default 0xB0000000 if VMSPLIT_3G_OPT
1474         default 0xC0000000
1475
1476 config NR_CPUS
1477         int "Maximum number of CPUs (2-32)"
1478         range 2 32
1479         depends on SMP
1480         default "4"
1481
1482 config HOTPLUG_CPU
1483         bool "Support for hot-pluggable CPUs"
1484         depends on SMP
1485         help
1486           Say Y here to experiment with turning CPUs off and on.  CPUs
1487           can be controlled through /sys/devices/system/cpu.
1488
1489 config ARM_PSCI
1490         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1491         depends on HAVE_ARM_SMCCC
1492         select ARM_PSCI_FW
1493         help
1494           Say Y here if you want Linux to communicate with system firmware
1495           implementing the PSCI specification for CPU-centric power
1496           management operations described in ARM document number ARM DEN
1497           0022A ("Power State Coordination Interface System Software on
1498           ARM processors").
1499
1500 # The GPIO number here must be sorted by descending number. In case of
1501 # a multiplatform kernel, we just want the highest value required by the
1502 # selected platforms.
1503 config ARCH_NR_GPIO
1504         int
1505         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1506                 ARCH_ZYNQ
1507         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1508                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1509         default 416 if ARCH_SUNXI
1510         default 392 if ARCH_U8500
1511         default 352 if ARCH_VT8500
1512         default 288 if ARCH_ROCKCHIP
1513         default 264 if MACH_H4700
1514         default 0
1515         help
1516           Maximum number of GPIOs in the system.
1517
1518           If unsure, leave the default value.
1519
1520 source kernel/Kconfig.preempt
1521
1522 config HZ_FIXED
1523         int
1524         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1525                 ARCH_S5PV210 || ARCH_EXYNOS4
1526         default 128 if SOC_AT91RM9200
1527         default 0
1528
1529 choice
1530         depends on HZ_FIXED = 0
1531         prompt "Timer frequency"
1532
1533 config HZ_100
1534         bool "100 Hz"
1535
1536 config HZ_200
1537         bool "200 Hz"
1538
1539 config HZ_250
1540         bool "250 Hz"
1541
1542 config HZ_300
1543         bool "300 Hz"
1544
1545 config HZ_500
1546         bool "500 Hz"
1547
1548 config HZ_1000
1549         bool "1000 Hz"
1550
1551 endchoice
1552
1553 config HZ
1554         int
1555         default HZ_FIXED if HZ_FIXED != 0
1556         default 100 if HZ_100
1557         default 200 if HZ_200
1558         default 250 if HZ_250
1559         default 300 if HZ_300
1560         default 500 if HZ_500
1561         default 1000
1562
1563 config SCHED_HRTICK
1564         def_bool HIGH_RES_TIMERS
1565
1566 config THUMB2_KERNEL
1567         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1568         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1569         default y if CPU_THUMBONLY
1570         select AEABI
1571         select ARM_ASM_UNIFIED
1572         select ARM_UNWIND
1573         help
1574           By enabling this option, the kernel will be compiled in
1575           Thumb-2 mode. A compiler/assembler that understand the unified
1576           ARM-Thumb syntax is needed.
1577
1578           If unsure, say N.
1579
1580 config THUMB2_AVOID_R_ARM_THM_JUMP11
1581         bool "Work around buggy Thumb-2 short branch relocations in gas"
1582         depends on THUMB2_KERNEL && MODULES
1583         default y
1584         help
1585           Various binutils versions can resolve Thumb-2 branches to
1586           locally-defined, preemptible global symbols as short-range "b.n"
1587           branch instructions.
1588
1589           This is a problem, because there's no guarantee the final
1590           destination of the symbol, or any candidate locations for a
1591           trampoline, are within range of the branch.  For this reason, the
1592           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1593           relocation in modules at all, and it makes little sense to add
1594           support.
1595
1596           The symptom is that the kernel fails with an "unsupported
1597           relocation" error when loading some modules.
1598
1599           Until fixed tools are available, passing
1600           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1601           code which hits this problem, at the cost of a bit of extra runtime
1602           stack usage in some cases.
1603
1604           The problem is described in more detail at:
1605               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1606
1607           Only Thumb-2 kernels are affected.
1608
1609           Unless you are sure your tools don't have this problem, say Y.
1610
1611 config ARM_ASM_UNIFIED
1612         bool
1613
1614 config ARM_PATCH_IDIV
1615         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1616         depends on CPU_32v7 && !XIP_KERNEL
1617         default y
1618         help
1619           The ARM compiler inserts calls to __aeabi_idiv() and
1620           __aeabi_uidiv() when it needs to perform division on signed
1621           and unsigned integers. Some v7 CPUs have support for the sdiv
1622           and udiv instructions that can be used to implement those
1623           functions.
1624
1625           Enabling this option allows the kernel to modify itself to
1626           replace the first two instructions of these library functions
1627           with the sdiv or udiv plus "bx lr" instructions when the CPU
1628           it is running on supports them. Typically this will be faster
1629           and less power intensive than running the original library
1630           code to do integer division.
1631
1632 config AEABI
1633         bool "Use the ARM EABI to compile the kernel"
1634         help
1635           This option allows for the kernel to be compiled using the latest
1636           ARM ABI (aka EABI).  This is only useful if you are using a user
1637           space environment that is also compiled with EABI.
1638
1639           Since there are major incompatibilities between the legacy ABI and
1640           EABI, especially with regard to structure member alignment, this
1641           option also changes the kernel syscall calling convention to
1642           disambiguate both ABIs and allow for backward compatibility support
1643           (selected with CONFIG_OABI_COMPAT).
1644
1645           To use this you need GCC version 4.0.0 or later.
1646
1647 config OABI_COMPAT
1648         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1649         depends on AEABI && !THUMB2_KERNEL
1650         help
1651           This option preserves the old syscall interface along with the
1652           new (ARM EABI) one. It also provides a compatibility layer to
1653           intercept syscalls that have structure arguments which layout
1654           in memory differs between the legacy ABI and the new ARM EABI
1655           (only for non "thumb" binaries). This option adds a tiny
1656           overhead to all syscalls and produces a slightly larger kernel.
1657
1658           The seccomp filter system will not be available when this is
1659           selected, since there is no way yet to sensibly distinguish
1660           between calling conventions during filtering.
1661
1662           If you know you'll be using only pure EABI user space then you
1663           can say N here. If this option is not selected and you attempt
1664           to execute a legacy ABI binary then the result will be
1665           UNPREDICTABLE (in fact it can be predicted that it won't work
1666           at all). If in doubt say N.
1667
1668 config ARCH_HAS_HOLES_MEMORYMODEL
1669         bool
1670
1671 config ARCH_SPARSEMEM_ENABLE
1672         bool
1673
1674 config ARCH_SPARSEMEM_DEFAULT
1675         def_bool ARCH_SPARSEMEM_ENABLE
1676
1677 config ARCH_SELECT_MEMORY_MODEL
1678         def_bool ARCH_SPARSEMEM_ENABLE
1679
1680 config HAVE_ARCH_PFN_VALID
1681         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1682
1683 config HAVE_GENERIC_RCU_GUP
1684         def_bool y
1685         depends on ARM_LPAE
1686
1687 config HIGHMEM
1688         bool "High Memory Support"
1689         depends on MMU
1690         help
1691           The address space of ARM processors is only 4 Gigabytes large
1692           and it has to accommodate user address space, kernel address
1693           space as well as some memory mapped IO. That means that, if you
1694           have a large amount of physical memory and/or IO, not all of the
1695           memory can be "permanently mapped" by the kernel. The physical
1696           memory that is not permanently mapped is called "high memory".
1697
1698           Depending on the selected kernel/user memory split, minimum
1699           vmalloc space and actual amount of RAM, you may not need this
1700           option which should result in a slightly faster kernel.
1701
1702           If unsure, say n.
1703
1704 config HIGHPTE
1705         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1706         depends on HIGHMEM
1707         default y
1708         help
1709           The VM uses one page of physical memory for each page table.
1710           For systems with a lot of processes, this can use a lot of
1711           precious low memory, eventually leading to low memory being
1712           consumed by page tables.  Setting this option will allow
1713           user-space 2nd level page tables to reside in high memory.
1714
1715 config CPU_SW_DOMAIN_PAN
1716         bool "Enable use of CPU domains to implement privileged no-access"
1717         depends on MMU && !ARM_LPAE
1718         default y
1719         help
1720           Increase kernel security by ensuring that normal kernel accesses
1721           are unable to access userspace addresses.  This can help prevent
1722           use-after-free bugs becoming an exploitable privilege escalation
1723           by ensuring that magic values (such as LIST_POISON) will always
1724           fault when dereferenced.
1725
1726           CPUs with low-vector mappings use a best-efforts implementation.
1727           Their lower 1MB needs to remain accessible for the vectors, but
1728           the remainder of userspace will become appropriately inaccessible.
1729
1730 config HW_PERF_EVENTS
1731         def_bool y
1732         depends on ARM_PMU
1733
1734 config SYS_SUPPORTS_HUGETLBFS
1735        def_bool y
1736        depends on ARM_LPAE
1737
1738 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1739        def_bool y
1740        depends on ARM_LPAE
1741
1742 config ARCH_WANT_GENERAL_HUGETLB
1743         def_bool y
1744
1745 config ARM_MODULE_PLTS
1746         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1747         depends on MODULES
1748         help
1749           Allocate PLTs when loading modules so that jumps and calls whose
1750           targets are too far away for their relative offsets to be encoded
1751           in the instructions themselves can be bounced via veneers in the
1752           module's PLT. This allows modules to be allocated in the generic
1753           vmalloc area after the dedicated module memory area has been
1754           exhausted. The modules will use slightly more memory, but after
1755           rounding up to page size, the actual memory footprint is usually
1756           the same.
1757
1758           Say y if you are getting out of memory errors while loading modules
1759
1760 source "mm/Kconfig"
1761
1762 config FORCE_MAX_ZONEORDER
1763         int "Maximum zone order"
1764         default "12" if SOC_AM33XX
1765         default "9" if SA1111 || ARCH_EFM32
1766         default "11"
1767         help
1768           The kernel memory allocator divides physically contiguous memory
1769           blocks into "zones", where each zone is a power of two number of
1770           pages.  This option selects the largest power of two that the kernel
1771           keeps in the memory allocator.  If you need to allocate very large
1772           blocks of physically contiguous memory, then you may need to
1773           increase this value.
1774
1775           This config option is actually maximum order plus one. For example,
1776           a value of 11 means that the largest free memory block is 2^10 pages.
1777
1778 config ALIGNMENT_TRAP
1779         bool
1780         depends on CPU_CP15_MMU
1781         default y if !ARCH_EBSA110
1782         select HAVE_PROC_CPU if PROC_FS
1783         help
1784           ARM processors cannot fetch/store information which is not
1785           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1786           address divisible by 4. On 32-bit ARM processors, these non-aligned
1787           fetch/store instructions will be emulated in software if you say
1788           here, which has a severe performance impact. This is necessary for
1789           correct operation of some network protocols. With an IP-only
1790           configuration it is safe to say N, otherwise say Y.
1791
1792 config UACCESS_WITH_MEMCPY
1793         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1794         depends on MMU
1795         default y if CPU_FEROCEON
1796         help
1797           Implement faster copy_to_user and clear_user methods for CPU
1798           cores where a 8-word STM instruction give significantly higher
1799           memory write throughput than a sequence of individual 32bit stores.
1800
1801           A possible side effect is a slight increase in scheduling latency
1802           between threads sharing the same address space if they invoke
1803           such copy operations with large buffers.
1804
1805           However, if the CPU data cache is using a write-allocate mode,
1806           this option is unlikely to provide any performance gain.
1807
1808 config SECCOMP
1809         bool
1810         prompt "Enable seccomp to safely compute untrusted bytecode"
1811         ---help---
1812           This kernel feature is useful for number crunching applications
1813           that may need to compute untrusted bytecode during their
1814           execution. By using pipes or other transports made available to
1815           the process as file descriptors supporting the read/write
1816           syscalls, it's possible to isolate those applications in
1817           their own address space using seccomp. Once seccomp is
1818           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1819           and the task is only allowed to execute a few safe syscalls
1820           defined by each seccomp mode.
1821
1822 config SWIOTLB
1823         def_bool y
1824
1825 config IOMMU_HELPER
1826         def_bool SWIOTLB
1827
1828 config PARAVIRT
1829         bool "Enable paravirtualization code"
1830         help
1831           This changes the kernel so it can modify itself when it is run
1832           under a hypervisor, potentially improving performance significantly
1833           over full virtualization.
1834
1835 config PARAVIRT_TIME_ACCOUNTING
1836         bool "Paravirtual steal time accounting"
1837         select PARAVIRT
1838         default n
1839         help
1840           Select this option to enable fine granularity task steal time
1841           accounting. Time spent executing other tasks in parallel with
1842           the current vCPU is discounted from the vCPU power. To account for
1843           that, there can be a small performance impact.
1844
1845           If in doubt, say N here.
1846
1847 config XEN_DOM0
1848         def_bool y
1849         depends on XEN
1850
1851 config XEN
1852         bool "Xen guest support on ARM"
1853         depends on ARM && AEABI && OF
1854         depends on CPU_V7 && !CPU_V6
1855         depends on !GENERIC_ATOMIC64
1856         depends on MMU
1857         select ARCH_DMA_ADDR_T_64BIT
1858         select ARM_PSCI
1859         select SWIOTLB_XEN
1860         select PARAVIRT
1861         help
1862           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1863
1864 endmenu
1865
1866 menu "Boot options"
1867
1868 config USE_OF
1869         bool "Flattened Device Tree support"
1870         select IRQ_DOMAIN
1871         select OF
1872         help
1873           Include support for flattened device tree machine descriptions.
1874
1875 config ATAGS
1876         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1877         default y
1878         help
1879           This is the traditional way of passing data to the kernel at boot
1880           time. If you are solely relying on the flattened device tree (or
1881           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1882           to remove ATAGS support from your kernel binary.  If unsure,
1883           leave this to y.
1884
1885 config DEPRECATED_PARAM_STRUCT
1886         bool "Provide old way to pass kernel parameters"
1887         depends on ATAGS
1888         help
1889           This was deprecated in 2001 and announced to live on for 5 years.
1890           Some old boot loaders still use this way.
1891
1892 # Compressed boot loader in ROM.  Yes, we really want to ask about
1893 # TEXT and BSS so we preserve their values in the config files.
1894 config ZBOOT_ROM_TEXT
1895         hex "Compressed ROM boot loader base address"
1896         default "0"
1897         help
1898           The physical address at which the ROM-able zImage is to be
1899           placed in the target.  Platforms which normally make use of
1900           ROM-able zImage formats normally set this to a suitable
1901           value in their defconfig file.
1902
1903           If ZBOOT_ROM is not enabled, this has no effect.
1904
1905 config ZBOOT_ROM_BSS
1906         hex "Compressed ROM boot loader BSS address"
1907         default "0"
1908         help
1909           The base address of an area of read/write memory in the target
1910           for the ROM-able zImage which must be available while the
1911           decompressor is running. It must be large enough to hold the
1912           entire decompressed kernel plus an additional 128 KiB.
1913           Platforms which normally make use of ROM-able zImage formats
1914           normally set this to a suitable value in their defconfig file.
1915
1916           If ZBOOT_ROM is not enabled, this has no effect.
1917
1918 config ZBOOT_ROM
1919         bool "Compressed boot loader in ROM/flash"
1920         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1921         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1922         help
1923           Say Y here if you intend to execute your compressed kernel image
1924           (zImage) directly from ROM or flash.  If unsure, say N.
1925
1926 config ARM_APPENDED_DTB
1927         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1928         depends on OF
1929         help
1930           With this option, the boot code will look for a device tree binary
1931           (DTB) appended to zImage
1932           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1933
1934           This is meant as a backward compatibility convenience for those
1935           systems with a bootloader that can't be upgraded to accommodate
1936           the documented boot protocol using a device tree.
1937
1938           Beware that there is very little in terms of protection against
1939           this option being confused by leftover garbage in memory that might
1940           look like a DTB header after a reboot if no actual DTB is appended
1941           to zImage.  Do not leave this option active in a production kernel
1942           if you don't intend to always append a DTB.  Proper passing of the
1943           location into r2 of a bootloader provided DTB is always preferable
1944           to this option.
1945
1946 config ARM_ATAG_DTB_COMPAT
1947         bool "Supplement the appended DTB with traditional ATAG information"
1948         depends on ARM_APPENDED_DTB
1949         help
1950           Some old bootloaders can't be updated to a DTB capable one, yet
1951           they provide ATAGs with memory configuration, the ramdisk address,
1952           the kernel cmdline string, etc.  Such information is dynamically
1953           provided by the bootloader and can't always be stored in a static
1954           DTB.  To allow a device tree enabled kernel to be used with such
1955           bootloaders, this option allows zImage to extract the information
1956           from the ATAG list and store it at run time into the appended DTB.
1957
1958 choice
1959         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1960         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1961
1962 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1963         bool "Use bootloader kernel arguments if available"
1964         help
1965           Uses the command-line options passed by the boot loader instead of
1966           the device tree bootargs property. If the boot loader doesn't provide
1967           any, the device tree bootargs property will be used.
1968
1969 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1970         bool "Extend with bootloader kernel arguments"
1971         help
1972           The command-line arguments provided by the boot loader will be
1973           appended to the the device tree bootargs property.
1974
1975 endchoice
1976
1977 config CMDLINE
1978         string "Default kernel command string"
1979         default ""
1980         help
1981           On some architectures (EBSA110 and CATS), there is currently no way
1982           for the boot loader to pass arguments to the kernel. For these
1983           architectures, you should supply some command-line options at build
1984           time by entering them here. As a minimum, you should specify the
1985           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1986
1987 choice
1988         prompt "Kernel command line type" if CMDLINE != ""
1989         default CMDLINE_FROM_BOOTLOADER
1990         depends on ATAGS
1991
1992 config CMDLINE_FROM_BOOTLOADER
1993         bool "Use bootloader kernel arguments if available"
1994         help
1995           Uses the command-line options passed by the boot loader. If
1996           the boot loader doesn't provide any, the default kernel command
1997           string provided in CMDLINE will be used.
1998
1999 config CMDLINE_EXTEND
2000         bool "Extend bootloader kernel arguments"
2001         help
2002           The command-line arguments provided by the boot loader will be
2003           appended to the default kernel command string.
2004
2005 config CMDLINE_FORCE
2006         bool "Always use the default kernel command string"
2007         help
2008           Always use the default kernel command string, even if the boot
2009           loader passes other arguments to the kernel.
2010           This is useful if you cannot or don't want to change the
2011           command-line options your boot loader passes to the kernel.
2012 endchoice
2013
2014 config XIP_KERNEL
2015         bool "Kernel Execute-In-Place from ROM"
2016         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2017         help
2018           Execute-In-Place allows the kernel to run from non-volatile storage
2019           directly addressable by the CPU, such as NOR flash. This saves RAM
2020           space since the text section of the kernel is not loaded from flash
2021           to RAM.  Read-write sections, such as the data section and stack,
2022           are still copied to RAM.  The XIP kernel is not compressed since
2023           it has to run directly from flash, so it will take more space to
2024           store it.  The flash address used to link the kernel object files,
2025           and for storing it, is configuration dependent. Therefore, if you
2026           say Y here, you must know the proper physical address where to
2027           store the kernel image depending on your own flash memory usage.
2028
2029           Also note that the make target becomes "make xipImage" rather than
2030           "make zImage" or "make Image".  The final kernel binary to put in
2031           ROM memory will be arch/arm/boot/xipImage.
2032
2033           If unsure, say N.
2034
2035 config XIP_PHYS_ADDR
2036         hex "XIP Kernel Physical Location"
2037         depends on XIP_KERNEL
2038         default "0x00080000"
2039         help
2040           This is the physical address in your flash memory the kernel will
2041           be linked for and stored to.  This address is dependent on your
2042           own flash usage.
2043
2044 config KEXEC
2045         bool "Kexec system call (EXPERIMENTAL)"
2046         depends on (!SMP || PM_SLEEP_SMP)
2047         depends on !CPU_V7M
2048         select KEXEC_CORE
2049         help
2050           kexec is a system call that implements the ability to shutdown your
2051           current kernel, and to start another kernel.  It is like a reboot
2052           but it is independent of the system firmware.   And like a reboot
2053           you can start any kernel with it, not just Linux.
2054
2055           It is an ongoing process to be certain the hardware in a machine
2056           is properly shutdown, so do not be surprised if this code does not
2057           initially work for you.
2058
2059 config ATAGS_PROC
2060         bool "Export atags in procfs"
2061         depends on ATAGS && KEXEC
2062         default y
2063         help
2064           Should the atags used to boot the kernel be exported in an "atags"
2065           file in procfs. Useful with kexec.
2066
2067 config CRASH_DUMP
2068         bool "Build kdump crash kernel (EXPERIMENTAL)"
2069         help
2070           Generate crash dump after being started by kexec. This should
2071           be normally only set in special crash dump kernels which are
2072           loaded in the main kernel with kexec-tools into a specially
2073           reserved region and then later executed after a crash by
2074           kdump/kexec. The crash dump kernel must be compiled to a
2075           memory address not used by the main kernel
2076
2077           For more details see Documentation/kdump/kdump.txt
2078
2079 config AUTO_ZRELADDR
2080         bool "Auto calculation of the decompressed kernel image address"
2081         help
2082           ZRELADDR is the physical address where the decompressed kernel
2083           image will be placed. If AUTO_ZRELADDR is selected, the address
2084           will be determined at run-time by masking the current IP with
2085           0xf8000000. This assumes the zImage being placed in the first 128MB
2086           from start of memory.
2087
2088 config EFI_STUB
2089         bool
2090
2091 config EFI
2092         bool "UEFI runtime support"
2093         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2094         select UCS2_STRING
2095         select EFI_PARAMS_FROM_FDT
2096         select EFI_STUB
2097         select EFI_ARMSTUB
2098         select EFI_RUNTIME_WRAPPERS
2099         ---help---
2100           This option provides support for runtime services provided
2101           by UEFI firmware (such as non-volatile variables, realtime
2102           clock, and platform reset). A UEFI stub is also provided to
2103           allow the kernel to be booted as an EFI application. This
2104           is only useful for kernels that may run on systems that have
2105           UEFI firmware.
2106
2107 endmenu
2108
2109 menu "CPU Power Management"
2110
2111 source "drivers/cpufreq/Kconfig"
2112
2113 source "drivers/cpuidle/Kconfig"
2114
2115 endmenu
2116
2117 menu "Floating point emulation"
2118
2119 comment "At least one emulation must be selected"
2120
2121 config FPE_NWFPE
2122         bool "NWFPE math emulation"
2123         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2124         ---help---
2125           Say Y to include the NWFPE floating point emulator in the kernel.
2126           This is necessary to run most binaries. Linux does not currently
2127           support floating point hardware so you need to say Y here even if
2128           your machine has an FPA or floating point co-processor podule.
2129
2130           You may say N here if you are going to load the Acorn FPEmulator
2131           early in the bootup.
2132
2133 config FPE_NWFPE_XP
2134         bool "Support extended precision"
2135         depends on FPE_NWFPE
2136         help
2137           Say Y to include 80-bit support in the kernel floating-point
2138           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2139           Note that gcc does not generate 80-bit operations by default,
2140           so in most cases this option only enlarges the size of the
2141           floating point emulator without any good reason.
2142
2143           You almost surely want to say N here.
2144
2145 config FPE_FASTFPE
2146         bool "FastFPE math emulation (EXPERIMENTAL)"
2147         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2148         ---help---
2149           Say Y here to include the FAST floating point emulator in the kernel.
2150           This is an experimental much faster emulator which now also has full
2151           precision for the mantissa.  It does not support any exceptions.
2152           It is very simple, and approximately 3-6 times faster than NWFPE.
2153
2154           It should be sufficient for most programs.  It may be not suitable
2155           for scientific calculations, but you have to check this for yourself.
2156           If you do not feel you need a faster FP emulation you should better
2157           choose NWFPE.
2158
2159 config VFP
2160         bool "VFP-format floating point maths"
2161         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2162         help
2163           Say Y to include VFP support code in the kernel. This is needed
2164           if your hardware includes a VFP unit.
2165
2166           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2167           release notes and additional status information.
2168
2169           Say N if your target does not have VFP hardware.
2170
2171 config VFPv3
2172         bool
2173         depends on VFP
2174         default y if CPU_V7
2175
2176 config NEON
2177         bool "Advanced SIMD (NEON) Extension support"
2178         depends on VFPv3 && CPU_V7
2179         help
2180           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2181           Extension.
2182
2183 config KERNEL_MODE_NEON
2184         bool "Support for NEON in kernel mode"
2185         depends on NEON && AEABI
2186         help
2187           Say Y to include support for NEON in kernel mode.
2188
2189 endmenu
2190
2191 menu "Userspace binary formats"
2192
2193 source "fs/Kconfig.binfmt"
2194
2195 endmenu
2196
2197 menu "Power management options"
2198
2199 source "kernel/power/Kconfig"
2200
2201 config ARCH_SUSPEND_POSSIBLE
2202         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2203                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2204         def_bool y
2205
2206 config ARM_CPU_SUSPEND
2207         def_bool PM_SLEEP
2208
2209 config ARCH_HIBERNATION_POSSIBLE
2210         bool
2211         depends on MMU
2212         default y if ARCH_SUSPEND_POSSIBLE
2213
2214 endmenu
2215
2216 source "net/Kconfig"
2217
2218 source "drivers/Kconfig"
2219
2220 source "drivers/firmware/Kconfig"
2221
2222 source "fs/Kconfig"
2223
2224 source "arch/arm/Kconfig.debug"
2225
2226 source "security/Kconfig"
2227
2228 source "crypto/Kconfig"
2229 if CRYPTO
2230 source "arch/arm/crypto/Kconfig"
2231 endif
2232
2233 source "lib/Kconfig"
2234
2235 source "arch/arm/kvm/Kconfig"