4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_CPUFREQ
181 Internal node to signify that the ARCH has CPUFREQ support
182 and that the relevant menu configurations are displayed for
185 config ARCH_HAS_BANDGAP
188 config GENERIC_HWEIGHT
192 config GENERIC_CALIBRATE_DELAY
196 config ARCH_MAY_HAVE_PC_FDC
202 config NEED_DMA_MAP_STATE
205 config ARCH_SUPPORTS_UPROBES
208 config ARCH_HAS_DMA_SET_COHERENT_MASK
211 config GENERIC_ISA_DMA
217 config NEED_RET_TO_USER
225 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
226 default DRAM_BASE if REMAP_VECTORS_TO_RAM
229 The base address of exception vectors. This must be two pages
232 config ARM_PATCH_PHYS_VIRT
233 bool "Patch physical to virtual translations at runtime" if EMBEDDED
235 depends on !XIP_KERNEL && MMU
236 depends on !ARCH_REALVIEW || !SPARSEMEM
238 Patch phys-to-virt and virt-to-phys translation functions at
239 boot and module load time according to the position of the
240 kernel in system memory.
242 This can only be used with non-XIP MMU kernels where the base
243 of physical memory is at a 16MB boundary.
245 Only disable this option if you know that you do not require
246 this feature (eg, building a kernel for a single machine) and
247 you need to shrink the kernel to the minimal size.
249 config NEED_MACH_GPIO_H
252 Select this when mach/gpio.h is required to provide special
253 definitions for this platform. The need for mach/gpio.h should
254 be avoided when possible.
256 config NEED_MACH_IO_H
259 Select this when mach/io.h is required to provide special
260 definitions for this platform. The need for mach/io.h should
261 be avoided when possible.
263 config NEED_MACH_MEMORY_H
266 Select this when mach/memory.h is required to provide special
267 definitions for this platform. The need for mach/memory.h should
268 be avoided when possible.
271 hex "Physical address of main memory" if MMU
272 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
273 default DRAM_BASE if !MMU
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 source "init/Kconfig"
284 source "kernel/Kconfig.freezer"
289 bool "MMU-based Paged Memory Management Support"
292 Select if you want MMU-based virtualised addressing space
293 support by paged memory management. If unsure, say 'Y'.
296 # The "ARM system type" choice list is ordered alphabetically by option
297 # text. Please add new entries in the option alphabetic order.
300 prompt "ARM system type"
301 default ARCH_VERSATILE if !MMU
302 default ARCH_MULTIPLATFORM if MMU
304 config ARCH_MULTIPLATFORM
305 bool "Allow multiple platforms to be selected"
307 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_HAS_SG_CHAIN
309 select ARM_PATCH_PHYS_VIRT
313 select GENERIC_CLOCKEVENTS
314 select MULTI_IRQ_HANDLER
318 config ARCH_INTEGRATOR
319 bool "ARM Ltd. Integrator family"
320 select ARCH_HAS_CPUFREQ
322 select ARM_PATCH_PHYS_VIRT
325 select COMMON_CLK_VERSATILE
326 select GENERIC_CLOCKEVENTS
329 select MULTI_IRQ_HANDLER
330 select NEED_MACH_MEMORY_H
331 select PLAT_VERSATILE
334 select VERSATILE_FPGA_IRQ
336 Support for ARM's Integrator platform.
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_CLCD
352 This enables support for ARM Ltd RealView boards.
354 config ARCH_VERSATILE
355 bool "ARM Ltd. Versatile family"
356 select ARCH_WANT_OPTIONAL_GPIOLIB
358 select ARM_TIMER_SP804
361 select GENERIC_CLOCKEVENTS
362 select HAVE_MACH_CLKDEV
364 select PLAT_VERSATILE
365 select PLAT_VERSATILE_CLCD
366 select PLAT_VERSATILE_CLOCK
367 select VERSATILE_FPGA_IRQ
369 This enables support for ARM Ltd Versatile board.
373 select ARCH_REQUIRE_GPIOLIB
376 select NEED_MACH_GPIO_H
377 select NEED_MACH_IO_H if PCCARD
379 select PINCTRL_AT91 if USE_OF
381 This enables support for systems based on Atmel
382 AT91RM9200 and AT91SAM9* processors.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
394 Support for Cirrus Logic 711x/721x/731x based boards.
397 bool "Cortina Systems Gemini"
398 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
403 Support for the Cortina Systems Gemini family SoCs
407 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_IO_H
411 select NEED_MACH_MEMORY_H
414 This is an evaluation board for the StrongARM processor available
415 from Digital. It has limited hardware on-board, including an
416 Ethernet interface, two PCMCIA sockets, two serial ports and a
420 bool "Energy Micro efm32"
422 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_CLOCKEVENTS
434 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
439 select ARCH_HAS_HOLES_MEMORYMODEL
440 select ARCH_REQUIRE_GPIOLIB
441 select ARCH_USES_GETTIMEOFFSET
446 select NEED_MACH_MEMORY_H
448 This enables support for the Cirrus EP93xx series of CPUs.
450 config ARCH_FOOTBRIDGE
454 select GENERIC_CLOCKEVENTS
456 select NEED_MACH_IO_H if !MMU
457 select NEED_MACH_MEMORY_H
459 Support for systems based on the DC21285 companion chip
460 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
463 bool "Hilscher NetX based"
467 select GENERIC_CLOCKEVENTS
469 This enables support for systems based on the Hilscher NetX Soc
475 select NEED_MACH_MEMORY_H
476 select NEED_RET_TO_USER
481 Support for Intel's IOP13XX (XScale) family of processors.
486 select ARCH_REQUIRE_GPIOLIB
489 select NEED_RET_TO_USER
493 Support for Intel's 80219 and IOP32X (XScale) family of
499 select ARCH_REQUIRE_GPIOLIB
502 select NEED_RET_TO_USER
506 Support for Intel's IOP33X (XScale) family of processors.
511 select ARCH_HAS_DMA_SET_COHERENT_MASK
512 select ARCH_REQUIRE_GPIOLIB
513 select ARCH_SUPPORTS_BIG_ENDIAN
516 select DMABOUNCE if PCI
517 select GENERIC_CLOCKEVENTS
518 select MIGHT_HAVE_PCI
519 select NEED_MACH_IO_H
520 select USB_EHCI_BIG_ENDIAN_DESC
521 select USB_EHCI_BIG_ENDIAN_MMIO
523 Support for Intel's IXP4XX (XScale) family of processors.
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
530 select MIGHT_HAVE_PCI
534 select PLAT_ORION_LEGACY
536 Support for the Marvell Dove SoC 88AP510
539 bool "Marvell Kirkwood"
540 select ARCH_HAS_CPUFREQ
541 select ARCH_REQUIRE_GPIOLIB
543 select GENERIC_CLOCKEVENTS
548 select PINCTRL_KIRKWOOD
549 select PLAT_ORION_LEGACY
551 Support for the following Marvell Kirkwood series SoCs:
552 88F6180, 88F6192 and 88F6281.
555 bool "Marvell MV78xx0"
556 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_CLOCKEVENTS
561 select PLAT_ORION_LEGACY
563 Support for the following Marvell MV78xx0 series SoCs:
569 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
574 select PLAT_ORION_LEGACY
576 Support for the following Marvell Orion 5x series SoCs:
577 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
578 Orion-2 (5281), Orion-1-90 (6183).
581 bool "Marvell PXA168/910/MMP2"
583 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_ALLOCATOR
586 select GENERIC_CLOCKEVENTS
589 select MULTI_IRQ_HANDLER
594 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
597 bool "Micrel/Kendin KS8695"
598 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
602 select NEED_MACH_MEMORY_H
604 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
605 System-on-Chip devices.
608 bool "Nuvoton W90X900 CPU"
609 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_CLOCKEVENTS
615 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
616 At present, the w90x900 has been renamed nuc900, regarding
617 the ARM series product line, you can login the following
618 link address to know more.
620 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
621 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
634 Support for the NXP LPC32XX family of processors
637 bool "PXA2xx/PXA3xx-based"
639 select ARCH_HAS_CPUFREQ
641 select ARCH_REQUIRE_GPIOLIB
642 select ARM_CPU_SUSPEND if PM
646 select GENERIC_CLOCKEVENTS
649 select MULTI_IRQ_HANDLER
653 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
656 bool "Qualcomm MSM (non-multiplatform)"
657 select ARCH_REQUIRE_GPIOLIB
659 select GENERIC_CLOCKEVENTS
661 Support for Qualcomm MSM/QSD based systems. This runs on the
662 apps processor of the MSM/QSD and depends on a shared memory
663 interface to the modem processor which runs the baseband
664 stack and controls some vital subsystems
665 (clock and power control, etc).
667 config ARCH_SHMOBILE_LEGACY
668 bool "Renesas ARM SoCs (non-multiplatform)"
670 select ARM_PATCH_PHYS_VIRT
672 select GENERIC_CLOCKEVENTS
673 select HAVE_ARM_SCU if SMP
674 select HAVE_ARM_TWD if SMP
675 select HAVE_MACH_CLKDEV
677 select MIGHT_HAVE_CACHE_L2X0
678 select MULTI_IRQ_HANDLER
681 select PM_GENERIC_DOMAINS if PM
684 Support for Renesas ARM SoC platforms using a non-multiplatform
685 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
691 select ARCH_MAY_HAVE_PC_FDC
692 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_USES_GETTIMEOFFSET
697 select HAVE_PATA_PLATFORM
699 select NEED_MACH_IO_H
700 select NEED_MACH_MEMORY_H
704 On the Acorn Risc-PC, Linux can support the internal IDE disk and
705 CD-ROM interface, serial and parallel port, and the floppy drive.
709 select ARCH_HAS_CPUFREQ
711 select ARCH_REQUIRE_GPIOLIB
712 select ARCH_SPARSEMEM_ENABLE
717 select GENERIC_CLOCKEVENTS
720 select NEED_MACH_MEMORY_H
723 Support for StrongARM 11x0 based boards.
726 bool "Samsung S3C24XX SoCs"
727 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
731 select CLKSRC_SAMSUNG_PWM
732 select GENERIC_CLOCKEVENTS
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
736 select HAVE_S3C_RTC if RTC_CLASS
737 select MULTI_IRQ_HANDLER
738 select NEED_MACH_IO_H
741 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
742 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
743 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
744 Samsung SMDK2410 development board (and derivatives).
747 bool "Samsung S3C64XX"
748 select ARCH_HAS_CPUFREQ
749 select ARCH_REQUIRE_GPIOLIB
754 select CLKSRC_SAMSUNG_PWM
757 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select PM_GENERIC_DOMAINS if PM
766 select S3C_GPIO_TRACK
768 select SAMSUNG_WAKEMASK
769 select SAMSUNG_WDT_RESET
771 Samsung S3C64XX series based systems
774 bool "Samsung S5P6440 S5P6450"
777 select CLKSRC_SAMSUNG_PWM
779 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select HAVE_S3C_RTC if RTC_CLASS
784 select NEED_MACH_GPIO_H
786 select SAMSUNG_WDT_RESET
788 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
792 bool "Samsung S5PC100"
793 select ARCH_REQUIRE_GPIOLIB
796 select CLKSRC_SAMSUNG_PWM
798 select GENERIC_CLOCKEVENTS
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 select HAVE_S3C_RTC if RTC_CLASS
803 select NEED_MACH_GPIO_H
805 select SAMSUNG_WDT_RESET
807 Samsung S5PC100 series based systems
810 bool "Samsung S5PV210/S5PC110"
811 select ARCH_HAS_CPUFREQ
812 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_SPARSEMEM_ENABLE
816 select CLKSRC_SAMSUNG_PWM
818 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_GPIO_H
824 select NEED_MACH_MEMORY_H
827 Samsung S5PV210/S5PC110 series based systems
830 bool "Samsung EXYNOS"
831 select ARCH_HAS_CPUFREQ
832 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_REQUIRE_GPIOLIB
834 select ARCH_SPARSEMEM_ENABLE
838 select GENERIC_CLOCKEVENTS
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select HAVE_S3C_RTC if RTC_CLASS
842 select NEED_MACH_MEMORY_H
846 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
850 select ARCH_HAS_HOLES_MEMORYMODEL
851 select ARCH_REQUIRE_GPIOLIB
853 select GENERIC_ALLOCATOR
854 select GENERIC_CLOCKEVENTS
855 select GENERIC_IRQ_CHIP
861 Support for TI's DaVinci platform.
866 select ARCH_HAS_CPUFREQ
867 select ARCH_HAS_HOLES_MEMORYMODEL
869 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
873 select GENERIC_IRQ_CHIP
876 select NEED_MACH_IO_H if PCCARD
877 select NEED_MACH_MEMORY_H
879 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
883 menu "Multiple platform selection"
884 depends on ARCH_MULTIPLATFORM
886 comment "CPU Core family selection"
889 bool "ARMv4 based platforms (FA526)"
890 depends on !ARCH_MULTI_V6_V7
891 select ARCH_MULTI_V4_V5
894 config ARCH_MULTI_V4T
895 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
896 depends on !ARCH_MULTI_V6_V7
897 select ARCH_MULTI_V4_V5
898 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
899 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
900 CPU_ARM925T || CPU_ARM940T)
903 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
904 depends on !ARCH_MULTI_V6_V7
905 select ARCH_MULTI_V4_V5
906 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
907 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
908 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
910 config ARCH_MULTI_V4_V5
914 bool "ARMv6 based platforms (ARM11)"
915 select ARCH_MULTI_V6_V7
919 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
921 select ARCH_MULTI_V6_V7
925 config ARCH_MULTI_V6_V7
927 select MIGHT_HAVE_CACHE_L2X0
929 config ARCH_MULTI_CPU_AUTO
930 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
936 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
940 select HAVE_ARM_ARCH_TIMER
943 # This is sorted alphabetically by mach-* pathname. However, plat-*
944 # Kconfigs may be included either alphabetically (according to the
945 # plat- suffix) or along side the corresponding mach-* source.
947 source "arch/arm/mach-mvebu/Kconfig"
949 source "arch/arm/mach-at91/Kconfig"
951 source "arch/arm/mach-bcm/Kconfig"
953 source "arch/arm/mach-berlin/Kconfig"
955 source "arch/arm/mach-clps711x/Kconfig"
957 source "arch/arm/mach-cns3xxx/Kconfig"
959 source "arch/arm/mach-davinci/Kconfig"
961 source "arch/arm/mach-dove/Kconfig"
963 source "arch/arm/mach-ep93xx/Kconfig"
965 source "arch/arm/mach-footbridge/Kconfig"
967 source "arch/arm/mach-gemini/Kconfig"
969 source "arch/arm/mach-highbank/Kconfig"
971 source "arch/arm/mach-hisi/Kconfig"
973 source "arch/arm/mach-integrator/Kconfig"
975 source "arch/arm/mach-iop32x/Kconfig"
977 source "arch/arm/mach-iop33x/Kconfig"
979 source "arch/arm/mach-iop13xx/Kconfig"
981 source "arch/arm/mach-ixp4xx/Kconfig"
983 source "arch/arm/mach-keystone/Kconfig"
985 source "arch/arm/mach-kirkwood/Kconfig"
987 source "arch/arm/mach-ks8695/Kconfig"
989 source "arch/arm/mach-msm/Kconfig"
991 source "arch/arm/mach-moxart/Kconfig"
993 source "arch/arm/mach-mv78xx0/Kconfig"
995 source "arch/arm/mach-imx/Kconfig"
997 source "arch/arm/mach-mxs/Kconfig"
999 source "arch/arm/mach-netx/Kconfig"
1001 source "arch/arm/mach-nomadik/Kconfig"
1003 source "arch/arm/mach-nspire/Kconfig"
1005 source "arch/arm/plat-omap/Kconfig"
1007 source "arch/arm/mach-omap1/Kconfig"
1009 source "arch/arm/mach-omap2/Kconfig"
1011 source "arch/arm/mach-orion5x/Kconfig"
1013 source "arch/arm/mach-picoxcell/Kconfig"
1015 source "arch/arm/mach-pxa/Kconfig"
1016 source "arch/arm/plat-pxa/Kconfig"
1018 source "arch/arm/mach-mmp/Kconfig"
1020 source "arch/arm/mach-qcom/Kconfig"
1022 source "arch/arm/mach-realview/Kconfig"
1024 source "arch/arm/mach-rockchip/Kconfig"
1026 source "arch/arm/mach-sa1100/Kconfig"
1028 source "arch/arm/plat-samsung/Kconfig"
1030 source "arch/arm/mach-socfpga/Kconfig"
1032 source "arch/arm/mach-spear/Kconfig"
1034 source "arch/arm/mach-sti/Kconfig"
1036 source "arch/arm/mach-s3c24xx/Kconfig"
1038 source "arch/arm/mach-s3c64xx/Kconfig"
1040 source "arch/arm/mach-s5p64x0/Kconfig"
1042 source "arch/arm/mach-s5pc100/Kconfig"
1044 source "arch/arm/mach-s5pv210/Kconfig"
1046 source "arch/arm/mach-exynos/Kconfig"
1048 source "arch/arm/mach-shmobile/Kconfig"
1050 source "arch/arm/mach-sunxi/Kconfig"
1052 source "arch/arm/mach-prima2/Kconfig"
1054 source "arch/arm/mach-tegra/Kconfig"
1056 source "arch/arm/mach-u300/Kconfig"
1058 source "arch/arm/mach-ux500/Kconfig"
1060 source "arch/arm/mach-versatile/Kconfig"
1062 source "arch/arm/mach-vexpress/Kconfig"
1063 source "arch/arm/plat-versatile/Kconfig"
1065 source "arch/arm/mach-vt8500/Kconfig"
1067 source "arch/arm/mach-w90x900/Kconfig"
1069 source "arch/arm/mach-zynq/Kconfig"
1071 # Definitions to make life easier
1077 select GENERIC_CLOCKEVENTS
1083 select GENERIC_IRQ_CHIP
1086 config PLAT_ORION_LEGACY
1093 config PLAT_VERSATILE
1096 config ARM_TIMER_SP804
1099 select CLKSRC_OF if OF
1101 source "arch/arm/firmware/Kconfig"
1103 source arch/arm/mm/Kconfig
1106 bool "Enable iWMMXt support"
1107 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1108 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1110 Enable support for iWMMXt context switching at run time if
1111 running on a CPU that supports it.
1113 config MULTI_IRQ_HANDLER
1116 Allow each machine to specify it's own IRQ handler at run time.
1119 source "arch/arm/Kconfig-nommu"
1122 config PJ4B_ERRATA_4742
1123 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1124 depends on CPU_PJ4B && MACH_ARMADA_370
1127 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1128 Event (WFE) IDLE states, a specific timing sensitivity exists between
1129 the retiring WFI/WFE instructions and the newly issued subsequent
1130 instructions. This sensitivity can result in a CPU hang scenario.
1132 The software must insert either a Data Synchronization Barrier (DSB)
1133 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1136 config ARM_ERRATA_326103
1137 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1140 Executing a SWP instruction to read-only memory does not set bit 11
1141 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1142 treat the access as a read, preventing a COW from occurring and
1143 causing the faulting task to livelock.
1145 config ARM_ERRATA_411920
1146 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1147 depends on CPU_V6 || CPU_V6K
1149 Invalidation of the Instruction Cache operation can
1150 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1151 It does not affect the MPCore. This option enables the ARM Ltd.
1152 recommended workaround.
1154 config ARM_ERRATA_430973
1155 bool "ARM errata: Stale prediction on replaced interworking branch"
1158 This option enables the workaround for the 430973 Cortex-A8
1159 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1160 interworking branch is replaced with another code sequence at the
1161 same virtual address, whether due to self-modifying code or virtual
1162 to physical address re-mapping, Cortex-A8 does not recover from the
1163 stale interworking branch prediction. This results in Cortex-A8
1164 executing the new code sequence in the incorrect ARM or Thumb state.
1165 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1166 and also flushes the branch target cache at every context switch.
1167 Note that setting specific bits in the ACTLR register may not be
1168 available in non-secure mode.
1170 config ARM_ERRATA_458693
1171 bool "ARM errata: Processor deadlock when a false hazard is created"
1173 depends on !ARCH_MULTIPLATFORM
1175 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1176 erratum. For very specific sequences of memory operations, it is
1177 possible for a hazard condition intended for a cache line to instead
1178 be incorrectly associated with a different cache line. This false
1179 hazard might then cause a processor deadlock. The workaround enables
1180 the L1 caching of the NEON accesses and disables the PLD instruction
1181 in the ACTLR register. Note that setting specific bits in the ACTLR
1182 register may not be available in non-secure mode.
1184 config ARM_ERRATA_460075
1185 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1187 depends on !ARCH_MULTIPLATFORM
1189 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1190 erratum. Any asynchronous access to the L2 cache may encounter a
1191 situation in which recent store transactions to the L2 cache are lost
1192 and overwritten with stale memory contents from external memory. The
1193 workaround disables the write-allocate mode for the L2 cache via the
1194 ACTLR register. Note that setting specific bits in the ACTLR register
1195 may not be available in non-secure mode.
1197 config ARM_ERRATA_742230
1198 bool "ARM errata: DMB operation may be faulty"
1199 depends on CPU_V7 && SMP
1200 depends on !ARCH_MULTIPLATFORM
1202 This option enables the workaround for the 742230 Cortex-A9
1203 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1204 between two write operations may not ensure the correct visibility
1205 ordering of the two writes. This workaround sets a specific bit in
1206 the diagnostic register of the Cortex-A9 which causes the DMB
1207 instruction to behave as a DSB, ensuring the correct behaviour of
1210 config ARM_ERRATA_742231
1211 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1212 depends on CPU_V7 && SMP
1213 depends on !ARCH_MULTIPLATFORM
1215 This option enables the workaround for the 742231 Cortex-A9
1216 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1217 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1218 accessing some data located in the same cache line, may get corrupted
1219 data due to bad handling of the address hazard when the line gets
1220 replaced from one of the CPUs at the same time as another CPU is
1221 accessing it. This workaround sets specific bits in the diagnostic
1222 register of the Cortex-A9 which reduces the linefill issuing
1223 capabilities of the processor.
1225 config ARM_ERRATA_643719
1226 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 643719 Cortex-A9 (prior to
1230 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1231 register returns zero when it should return one. The workaround
1232 corrects this value, ensuring cache maintenance operations which use
1233 it behave as intended and avoiding data corruption.
1235 config ARM_ERRATA_720789
1236 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1239 This option enables the workaround for the 720789 Cortex-A9 (prior to
1240 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1241 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1242 As a consequence of this erratum, some TLB entries which should be
1243 invalidated are not, resulting in an incoherency in the system page
1244 tables. The workaround changes the TLB flushing routines to invalidate
1245 entries regardless of the ASID.
1247 config ARM_ERRATA_743622
1248 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1250 depends on !ARCH_MULTIPLATFORM
1252 This option enables the workaround for the 743622 Cortex-A9
1253 (r2p*) erratum. Under very rare conditions, a faulty
1254 optimisation in the Cortex-A9 Store Buffer may lead to data
1255 corruption. This workaround sets a specific bit in the diagnostic
1256 register of the Cortex-A9 which disables the Store Buffer
1257 optimisation, preventing the defect from occurring. This has no
1258 visible impact on the overall performance or power consumption of the
1261 config ARM_ERRATA_751472
1262 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1264 depends on !ARCH_MULTIPLATFORM
1266 This option enables the workaround for the 751472 Cortex-A9 (prior
1267 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1268 completion of a following broadcasted operation if the second
1269 operation is received by a CPU before the ICIALLUIS has completed,
1270 potentially leading to corrupted entries in the cache or TLB.
1272 config ARM_ERRATA_754322
1273 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1276 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1277 r3p*) erratum. A speculative memory access may cause a page table walk
1278 which starts prior to an ASID switch but completes afterwards. This
1279 can populate the micro-TLB with a stale entry which may be hit with
1280 the new ASID. This workaround places two dsb instructions in the mm
1281 switching code so that no page table walks can cross the ASID switch.
1283 config ARM_ERRATA_754327
1284 bool "ARM errata: no automatic Store Buffer drain"
1285 depends on CPU_V7 && SMP
1287 This option enables the workaround for the 754327 Cortex-A9 (prior to
1288 r2p0) erratum. The Store Buffer does not have any automatic draining
1289 mechanism and therefore a livelock may occur if an external agent
1290 continuously polls a memory location waiting to observe an update.
1291 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1292 written polling loops from denying visibility of updates to memory.
1294 config ARM_ERRATA_364296
1295 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1298 This options enables the workaround for the 364296 ARM1136
1299 r0p2 erratum (possible cache data corruption with
1300 hit-under-miss enabled). It sets the undocumented bit 31 in
1301 the auxiliary control register and the FI bit in the control
1302 register, thus disabling hit-under-miss without putting the
1303 processor into full low interrupt latency mode. ARM11MPCore
1306 config ARM_ERRATA_764369
1307 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for erratum 764369
1311 affecting Cortex-A9 MPCore with two or more processors (all
1312 current revisions). Under certain timing circumstances, a data
1313 cache line maintenance operation by MVA targeting an Inner
1314 Shareable memory region may fail to proceed up to either the
1315 Point of Coherency or to the Point of Unification of the
1316 system. This workaround adds a DSB instruction before the
1317 relevant cache maintenance functions and sets a specific bit
1318 in the diagnostic control register of the SCU.
1320 config ARM_ERRATA_775420
1321 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1324 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1325 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1326 operation aborts with MMU exception, it might cause the processor
1327 to deadlock. This workaround puts DSB before executing ISB if
1328 an abort may occur on cache maintenance.
1330 config ARM_ERRATA_798181
1331 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1332 depends on CPU_V7 && SMP
1334 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1335 adequately shooting down all use of the old entries. This
1336 option enables the Linux kernel workaround for this erratum
1337 which sends an IPI to the CPUs that are running the same ASID
1338 as the one being invalidated.
1340 config ARM_ERRATA_773022
1341 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1344 This option enables the workaround for the 773022 Cortex-A15
1345 (up to r0p4) erratum. In certain rare sequences of code, the
1346 loop buffer may deliver incorrect instructions. This
1347 workaround disables the loop buffer to avoid the erratum.
1351 source "arch/arm/common/Kconfig"
1361 Find out whether you have ISA slots on your motherboard. ISA is the
1362 name of a bus system, i.e. the way the CPU talks to the other stuff
1363 inside your box. Other bus systems are PCI, EISA, MicroChannel
1364 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1365 newer boards don't support it. If you have ISA, say Y, otherwise N.
1367 # Select ISA DMA controller support
1372 # Select ISA DMA interface
1377 bool "PCI support" if MIGHT_HAVE_PCI
1379 Find out whether you have a PCI motherboard. PCI is the name of a
1380 bus system, i.e. the way the CPU talks to the other stuff inside
1381 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1382 VESA. If you have PCI, say Y, otherwise N.
1388 config PCI_NANOENGINE
1389 bool "BSE nanoEngine PCI support"
1390 depends on SA1100_NANOENGINE
1392 Enable PCI on the BSE nanoEngine board.
1397 config PCI_HOST_ITE8152
1399 depends on PCI && MACH_ARMCORE
1403 source "drivers/pci/Kconfig"
1404 source "drivers/pci/pcie/Kconfig"
1406 source "drivers/pcmcia/Kconfig"
1410 menu "Kernel Features"
1415 This option should be selected by machines which have an SMP-
1418 The only effect of this option is to make the SMP-related
1419 options available to the user for configuration.
1422 bool "Symmetric Multi-Processing"
1423 depends on CPU_V6K || CPU_V7
1424 depends on GENERIC_CLOCKEVENTS
1426 depends on MMU || ARM_MPU
1428 This enables support for systems with more than one CPU. If you have
1429 a system with only one CPU, say N. If you have a system with more
1430 than one CPU, say Y.
1432 If you say N here, the kernel will run on uni- and multiprocessor
1433 machines, but will use only one CPU of a multiprocessor machine. If
1434 you say Y here, the kernel will run on many, but not all,
1435 uniprocessor machines. On a uniprocessor machine, the kernel
1436 will run faster if you say N here.
1438 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1439 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1440 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1442 If you don't know what to do here, say N.
1445 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1446 depends on SMP && !XIP_KERNEL && MMU
1449 SMP kernels contain instructions which fail on non-SMP processors.
1450 Enabling this option allows the kernel to modify itself to make
1451 these instructions safe. Disabling it allows about 1K of space
1454 If you don't know what to do here, say Y.
1456 config ARM_CPU_TOPOLOGY
1457 bool "Support cpu topology definition"
1458 depends on SMP && CPU_V7
1461 Support ARM cpu topology definition. The MPIDR register defines
1462 affinity between processors which is then used to describe the cpu
1463 topology of an ARM System.
1466 bool "Multi-core scheduler support"
1467 depends on ARM_CPU_TOPOLOGY
1469 Multi-core scheduler support improves the CPU scheduler's decision
1470 making when dealing with multi-core CPU chips at a cost of slightly
1471 increased overhead in some places. If unsure say N here.
1474 bool "SMT scheduler support"
1475 depends on ARM_CPU_TOPOLOGY
1477 Improves the CPU scheduler's decision making when dealing with
1478 MultiThreading at a cost of slightly increased overhead in some
1479 places. If unsure say N here.
1484 This option enables support for the ARM system coherency unit
1486 config HAVE_ARM_ARCH_TIMER
1487 bool "Architected timer support"
1489 select ARM_ARCH_TIMER
1490 select GENERIC_CLOCKEVENTS
1492 This option enables support for the ARM architected timer
1497 select CLKSRC_OF if OF
1499 This options enables support for the ARM timer and watchdog unit
1502 bool "Multi-Cluster Power Management"
1503 depends on CPU_V7 && SMP
1505 This option provides the common power management infrastructure
1506 for (multi-)cluster based systems, such as big.LITTLE based
1510 bool "big.LITTLE support (Experimental)"
1511 depends on CPU_V7 && SMP
1514 This option enables support selections for the big.LITTLE
1515 system architecture.
1518 bool "big.LITTLE switcher support"
1519 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1520 select ARM_CPU_SUSPEND
1523 The big.LITTLE "switcher" provides the core functionality to
1524 transparently handle transition between a cluster of A15's
1525 and a cluster of A7's in a big.LITTLE system.
1527 config BL_SWITCHER_DUMMY_IF
1528 tristate "Simple big.LITTLE switcher user interface"
1529 depends on BL_SWITCHER && DEBUG_KERNEL
1531 This is a simple and dummy char dev interface to control
1532 the big.LITTLE switcher core code. It is meant for
1533 debugging purposes only.
1536 prompt "Memory split"
1540 Select the desired split between kernel and user memory.
1542 If you are not absolutely sure what you are doing, leave this
1546 bool "3G/1G user/kernel split"
1548 bool "2G/2G user/kernel split"
1550 bool "1G/3G user/kernel split"
1555 default PHYS_OFFSET if !MMU
1556 default 0x40000000 if VMSPLIT_1G
1557 default 0x80000000 if VMSPLIT_2G
1561 int "Maximum number of CPUs (2-32)"
1567 bool "Support for hot-pluggable CPUs"
1570 Say Y here to experiment with turning CPUs off and on. CPUs
1571 can be controlled through /sys/devices/system/cpu.
1574 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1577 Say Y here if you want Linux to communicate with system firmware
1578 implementing the PSCI specification for CPU-centric power
1579 management operations described in ARM document number ARM DEN
1580 0022A ("Power State Coordination Interface System Software on
1583 # The GPIO number here must be sorted by descending number. In case of
1584 # a multiplatform kernel, we just want the highest value required by the
1585 # selected platforms.
1588 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1589 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1590 default 392 if ARCH_U8500
1591 default 352 if ARCH_VT8500
1592 default 288 if ARCH_SUNXI
1593 default 264 if MACH_H4700
1596 Maximum number of GPIOs in the system.
1598 If unsure, leave the default value.
1600 source kernel/Kconfig.preempt
1604 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1605 ARCH_S5PV210 || ARCH_EXYNOS4
1606 default AT91_TIMER_HZ if ARCH_AT91
1607 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1611 depends on HZ_FIXED = 0
1612 prompt "Timer frequency"
1636 default HZ_FIXED if HZ_FIXED != 0
1637 default 100 if HZ_100
1638 default 200 if HZ_200
1639 default 250 if HZ_250
1640 default 300 if HZ_300
1641 default 500 if HZ_500
1645 def_bool HIGH_RES_TIMERS
1647 config THUMB2_KERNEL
1648 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1649 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1650 default y if CPU_THUMBONLY
1652 select ARM_ASM_UNIFIED
1655 By enabling this option, the kernel will be compiled in
1656 Thumb-2 mode. A compiler/assembler that understand the unified
1657 ARM-Thumb syntax is needed.
1661 config THUMB2_AVOID_R_ARM_THM_JUMP11
1662 bool "Work around buggy Thumb-2 short branch relocations in gas"
1663 depends on THUMB2_KERNEL && MODULES
1666 Various binutils versions can resolve Thumb-2 branches to
1667 locally-defined, preemptible global symbols as short-range "b.n"
1668 branch instructions.
1670 This is a problem, because there's no guarantee the final
1671 destination of the symbol, or any candidate locations for a
1672 trampoline, are within range of the branch. For this reason, the
1673 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1674 relocation in modules at all, and it makes little sense to add
1677 The symptom is that the kernel fails with an "unsupported
1678 relocation" error when loading some modules.
1680 Until fixed tools are available, passing
1681 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1682 code which hits this problem, at the cost of a bit of extra runtime
1683 stack usage in some cases.
1685 The problem is described in more detail at:
1686 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1688 Only Thumb-2 kernels are affected.
1690 Unless you are sure your tools don't have this problem, say Y.
1692 config ARM_ASM_UNIFIED
1696 bool "Use the ARM EABI to compile the kernel"
1698 This option allows for the kernel to be compiled using the latest
1699 ARM ABI (aka EABI). This is only useful if you are using a user
1700 space environment that is also compiled with EABI.
1702 Since there are major incompatibilities between the legacy ABI and
1703 EABI, especially with regard to structure member alignment, this
1704 option also changes the kernel syscall calling convention to
1705 disambiguate both ABIs and allow for backward compatibility support
1706 (selected with CONFIG_OABI_COMPAT).
1708 To use this you need GCC version 4.0.0 or later.
1711 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1712 depends on AEABI && !THUMB2_KERNEL
1714 This option preserves the old syscall interface along with the
1715 new (ARM EABI) one. It also provides a compatibility layer to
1716 intercept syscalls that have structure arguments which layout
1717 in memory differs between the legacy ABI and the new ARM EABI
1718 (only for non "thumb" binaries). This option adds a tiny
1719 overhead to all syscalls and produces a slightly larger kernel.
1721 The seccomp filter system will not be available when this is
1722 selected, since there is no way yet to sensibly distinguish
1723 between calling conventions during filtering.
1725 If you know you'll be using only pure EABI user space then you
1726 can say N here. If this option is not selected and you attempt
1727 to execute a legacy ABI binary then the result will be
1728 UNPREDICTABLE (in fact it can be predicted that it won't work
1729 at all). If in doubt say N.
1731 config ARCH_HAS_HOLES_MEMORYMODEL
1734 config ARCH_SPARSEMEM_ENABLE
1737 config ARCH_SPARSEMEM_DEFAULT
1738 def_bool ARCH_SPARSEMEM_ENABLE
1740 config ARCH_SELECT_MEMORY_MODEL
1741 def_bool ARCH_SPARSEMEM_ENABLE
1743 config HAVE_ARCH_PFN_VALID
1744 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1747 bool "High Memory Support"
1750 The address space of ARM processors is only 4 Gigabytes large
1751 and it has to accommodate user address space, kernel address
1752 space as well as some memory mapped IO. That means that, if you
1753 have a large amount of physical memory and/or IO, not all of the
1754 memory can be "permanently mapped" by the kernel. The physical
1755 memory that is not permanently mapped is called "high memory".
1757 Depending on the selected kernel/user memory split, minimum
1758 vmalloc space and actual amount of RAM, you may not need this
1759 option which should result in a slightly faster kernel.
1764 bool "Allocate 2nd-level pagetables from highmem"
1767 config HW_PERF_EVENTS
1768 bool "Enable hardware performance counter support for perf events"
1769 depends on PERF_EVENTS
1772 Enable hardware performance counter support for perf events. If
1773 disabled, perf events will use software events only.
1775 config SYS_SUPPORTS_HUGETLBFS
1779 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1783 config ARCH_WANT_GENERAL_HUGETLB
1788 config FORCE_MAX_ZONEORDER
1789 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1790 range 11 64 if ARCH_SHMOBILE_LEGACY
1791 default "12" if SOC_AM33XX
1792 default "9" if SA1111 || ARCH_EFM32
1795 The kernel memory allocator divides physically contiguous memory
1796 blocks into "zones", where each zone is a power of two number of
1797 pages. This option selects the largest power of two that the kernel
1798 keeps in the memory allocator. If you need to allocate very large
1799 blocks of physically contiguous memory, then you may need to
1800 increase this value.
1802 This config option is actually maximum order plus one. For example,
1803 a value of 11 means that the largest free memory block is 2^10 pages.
1805 config ALIGNMENT_TRAP
1807 depends on CPU_CP15_MMU
1808 default y if !ARCH_EBSA110
1809 select HAVE_PROC_CPU if PROC_FS
1811 ARM processors cannot fetch/store information which is not
1812 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1813 address divisible by 4. On 32-bit ARM processors, these non-aligned
1814 fetch/store instructions will be emulated in software if you say
1815 here, which has a severe performance impact. This is necessary for
1816 correct operation of some network protocols. With an IP-only
1817 configuration it is safe to say N, otherwise say Y.
1819 config UACCESS_WITH_MEMCPY
1820 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1822 default y if CPU_FEROCEON
1824 Implement faster copy_to_user and clear_user methods for CPU
1825 cores where a 8-word STM instruction give significantly higher
1826 memory write throughput than a sequence of individual 32bit stores.
1828 A possible side effect is a slight increase in scheduling latency
1829 between threads sharing the same address space if they invoke
1830 such copy operations with large buffers.
1832 However, if the CPU data cache is using a write-allocate mode,
1833 this option is unlikely to provide any performance gain.
1837 prompt "Enable seccomp to safely compute untrusted bytecode"
1839 This kernel feature is useful for number crunching applications
1840 that may need to compute untrusted bytecode during their
1841 execution. By using pipes or other transports made available to
1842 the process as file descriptors supporting the read/write
1843 syscalls, it's possible to isolate those applications in
1844 their own address space using seccomp. Once seccomp is
1845 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1846 and the task is only allowed to execute a few safe syscalls
1847 defined by each seccomp mode.
1860 bool "Xen guest support on ARM (EXPERIMENTAL)"
1861 depends on ARM && AEABI && OF
1862 depends on CPU_V7 && !CPU_V6
1863 depends on !GENERIC_ATOMIC64
1865 select ARCH_DMA_ADDR_T_64BIT
1869 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1876 bool "Flattened Device Tree support"
1879 select OF_EARLY_FLATTREE
1880 select OF_RESERVED_MEM
1882 Include support for flattened device tree machine descriptions.
1885 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1888 This is the traditional way of passing data to the kernel at boot
1889 time. If you are solely relying on the flattened device tree (or
1890 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1891 to remove ATAGS support from your kernel binary. If unsure,
1894 config DEPRECATED_PARAM_STRUCT
1895 bool "Provide old way to pass kernel parameters"
1898 This was deprecated in 2001 and announced to live on for 5 years.
1899 Some old boot loaders still use this way.
1901 # Compressed boot loader in ROM. Yes, we really want to ask about
1902 # TEXT and BSS so we preserve their values in the config files.
1903 config ZBOOT_ROM_TEXT
1904 hex "Compressed ROM boot loader base address"
1907 The physical address at which the ROM-able zImage is to be
1908 placed in the target. Platforms which normally make use of
1909 ROM-able zImage formats normally set this to a suitable
1910 value in their defconfig file.
1912 If ZBOOT_ROM is not enabled, this has no effect.
1914 config ZBOOT_ROM_BSS
1915 hex "Compressed ROM boot loader BSS address"
1918 The base address of an area of read/write memory in the target
1919 for the ROM-able zImage which must be available while the
1920 decompressor is running. It must be large enough to hold the
1921 entire decompressed kernel plus an additional 128 KiB.
1922 Platforms which normally make use of ROM-able zImage formats
1923 normally set this to a suitable value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1928 bool "Compressed boot loader in ROM/flash"
1929 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1930 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1932 Say Y here if you intend to execute your compressed kernel image
1933 (zImage) directly from ROM or flash. If unsure, say N.
1936 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1937 depends on ZBOOT_ROM && ARCH_SH7372
1938 default ZBOOT_ROM_NONE
1940 Include experimental SD/MMC loading code in the ROM-able zImage.
1941 With this enabled it is possible to write the ROM-able zImage
1942 kernel image to an MMC or SD card and boot the kernel straight
1943 from the reset vector. At reset the processor Mask ROM will load
1944 the first part of the ROM-able zImage which in turn loads the
1945 rest the kernel image to RAM.
1947 config ZBOOT_ROM_NONE
1948 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1950 Do not load image from SD or MMC
1952 config ZBOOT_ROM_MMCIF
1953 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1955 Load image from MMCIF hardware block.
1957 config ZBOOT_ROM_SH_MOBILE_SDHI
1958 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1960 Load image from SDHI hardware block
1964 config ARM_APPENDED_DTB
1965 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968 With this option, the boot code will look for a device tree binary
1969 (DTB) appended to zImage
1970 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1972 This is meant as a backward compatibility convenience for those
1973 systems with a bootloader that can't be upgraded to accommodate
1974 the documented boot protocol using a device tree.
1976 Beware that there is very little in terms of protection against
1977 this option being confused by leftover garbage in memory that might
1978 look like a DTB header after a reboot if no actual DTB is appended
1979 to zImage. Do not leave this option active in a production kernel
1980 if you don't intend to always append a DTB. Proper passing of the
1981 location into r2 of a bootloader provided DTB is always preferable
1984 config ARM_ATAG_DTB_COMPAT
1985 bool "Supplement the appended DTB with traditional ATAG information"
1986 depends on ARM_APPENDED_DTB
1988 Some old bootloaders can't be updated to a DTB capable one, yet
1989 they provide ATAGs with memory configuration, the ramdisk address,
1990 the kernel cmdline string, etc. Such information is dynamically
1991 provided by the bootloader and can't always be stored in a static
1992 DTB. To allow a device tree enabled kernel to be used with such
1993 bootloaders, this option allows zImage to extract the information
1994 from the ATAG list and store it at run time into the appended DTB.
1997 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1998 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2000 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2001 bool "Use bootloader kernel arguments if available"
2003 Uses the command-line options passed by the boot loader instead of
2004 the device tree bootargs property. If the boot loader doesn't provide
2005 any, the device tree bootargs property will be used.
2007 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2008 bool "Extend with bootloader kernel arguments"
2010 The command-line arguments provided by the boot loader will be
2011 appended to the the device tree bootargs property.
2016 string "Default kernel command string"
2019 On some architectures (EBSA110 and CATS), there is currently no way
2020 for the boot loader to pass arguments to the kernel. For these
2021 architectures, you should supply some command-line options at build
2022 time by entering them here. As a minimum, you should specify the
2023 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2026 prompt "Kernel command line type" if CMDLINE != ""
2027 default CMDLINE_FROM_BOOTLOADER
2030 config CMDLINE_FROM_BOOTLOADER
2031 bool "Use bootloader kernel arguments if available"
2033 Uses the command-line options passed by the boot loader. If
2034 the boot loader doesn't provide any, the default kernel command
2035 string provided in CMDLINE will be used.
2037 config CMDLINE_EXTEND
2038 bool "Extend bootloader kernel arguments"
2040 The command-line arguments provided by the boot loader will be
2041 appended to the default kernel command string.
2043 config CMDLINE_FORCE
2044 bool "Always use the default kernel command string"
2046 Always use the default kernel command string, even if the boot
2047 loader passes other arguments to the kernel.
2048 This is useful if you cannot or don't want to change the
2049 command-line options your boot loader passes to the kernel.
2053 bool "Kernel Execute-In-Place from ROM"
2054 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2056 Execute-In-Place allows the kernel to run from non-volatile storage
2057 directly addressable by the CPU, such as NOR flash. This saves RAM
2058 space since the text section of the kernel is not loaded from flash
2059 to RAM. Read-write sections, such as the data section and stack,
2060 are still copied to RAM. The XIP kernel is not compressed since
2061 it has to run directly from flash, so it will take more space to
2062 store it. The flash address used to link the kernel object files,
2063 and for storing it, is configuration dependent. Therefore, if you
2064 say Y here, you must know the proper physical address where to
2065 store the kernel image depending on your own flash memory usage.
2067 Also note that the make target becomes "make xipImage" rather than
2068 "make zImage" or "make Image". The final kernel binary to put in
2069 ROM memory will be arch/arm/boot/xipImage.
2073 config XIP_PHYS_ADDR
2074 hex "XIP Kernel Physical Location"
2075 depends on XIP_KERNEL
2076 default "0x00080000"
2078 This is the physical address in your flash memory the kernel will
2079 be linked for and stored to. This address is dependent on your
2083 bool "Kexec system call (EXPERIMENTAL)"
2084 depends on (!SMP || PM_SLEEP_SMP)
2086 kexec is a system call that implements the ability to shutdown your
2087 current kernel, and to start another kernel. It is like a reboot
2088 but it is independent of the system firmware. And like a reboot
2089 you can start any kernel with it, not just Linux.
2091 It is an ongoing process to be certain the hardware in a machine
2092 is properly shutdown, so do not be surprised if this code does not
2093 initially work for you.
2096 bool "Export atags in procfs"
2097 depends on ATAGS && KEXEC
2100 Should the atags used to boot the kernel be exported in an "atags"
2101 file in procfs. Useful with kexec.
2104 bool "Build kdump crash kernel (EXPERIMENTAL)"
2106 Generate crash dump after being started by kexec. This should
2107 be normally only set in special crash dump kernels which are
2108 loaded in the main kernel with kexec-tools into a specially
2109 reserved region and then later executed after a crash by
2110 kdump/kexec. The crash dump kernel must be compiled to a
2111 memory address not used by the main kernel
2113 For more details see Documentation/kdump/kdump.txt
2115 config AUTO_ZRELADDR
2116 bool "Auto calculation of the decompressed kernel image address"
2118 ZRELADDR is the physical address where the decompressed kernel
2119 image will be placed. If AUTO_ZRELADDR is selected, the address
2120 will be determined at run-time by masking the current IP with
2121 0xf8000000. This assumes the zImage being placed in the first 128MB
2122 from start of memory.
2126 menu "CPU Power Management"
2129 source "drivers/cpufreq/Kconfig"
2132 source "drivers/cpuidle/Kconfig"
2136 menu "Floating point emulation"
2138 comment "At least one emulation must be selected"
2141 bool "NWFPE math emulation"
2142 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2144 Say Y to include the NWFPE floating point emulator in the kernel.
2145 This is necessary to run most binaries. Linux does not currently
2146 support floating point hardware so you need to say Y here even if
2147 your machine has an FPA or floating point co-processor podule.
2149 You may say N here if you are going to load the Acorn FPEmulator
2150 early in the bootup.
2153 bool "Support extended precision"
2154 depends on FPE_NWFPE
2156 Say Y to include 80-bit support in the kernel floating-point
2157 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2158 Note that gcc does not generate 80-bit operations by default,
2159 so in most cases this option only enlarges the size of the
2160 floating point emulator without any good reason.
2162 You almost surely want to say N here.
2165 bool "FastFPE math emulation (EXPERIMENTAL)"
2166 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2168 Say Y here to include the FAST floating point emulator in the kernel.
2169 This is an experimental much faster emulator which now also has full
2170 precision for the mantissa. It does not support any exceptions.
2171 It is very simple, and approximately 3-6 times faster than NWFPE.
2173 It should be sufficient for most programs. It may be not suitable
2174 for scientific calculations, but you have to check this for yourself.
2175 If you do not feel you need a faster FP emulation you should better
2179 bool "VFP-format floating point maths"
2180 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2182 Say Y to include VFP support code in the kernel. This is needed
2183 if your hardware includes a VFP unit.
2185 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2186 release notes and additional status information.
2188 Say N if your target does not have VFP hardware.
2196 bool "Advanced SIMD (NEON) Extension support"
2197 depends on VFPv3 && CPU_V7
2199 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2202 config KERNEL_MODE_NEON
2203 bool "Support for NEON in kernel mode"
2204 depends on NEON && AEABI
2206 Say Y to include support for NEON in kernel mode.
2210 menu "Userspace binary formats"
2212 source "fs/Kconfig.binfmt"
2215 tristate "RISC OS personality"
2218 Say Y here to include the kernel code necessary if you want to run
2219 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2220 experimental; if this sounds frightening, say N and sleep in peace.
2221 You can also say M here to compile this support as a module (which
2222 will be called arthur).
2226 menu "Power management options"
2228 source "kernel/power/Kconfig"
2230 config ARCH_SUSPEND_POSSIBLE
2231 depends on !ARCH_S5PC100
2232 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2233 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2236 config ARM_CPU_SUSPEND
2239 config ARCH_HIBERNATION_POSSIBLE
2242 default y if ARCH_SUSPEND_POSSIBLE
2246 source "net/Kconfig"
2248 source "drivers/Kconfig"
2252 source "arch/arm/Kconfig.debug"
2254 source "security/Kconfig"
2256 source "crypto/Kconfig"
2258 source "lib/Kconfig"
2260 source "arch/arm/kvm/Kconfig"