4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT
266 default DRAM_BASE if !MMU
267 default 0x00000000 if ARCH_EBSA110 || \
268 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
273 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
275 default 0x20000000 if ARCH_S5PV210
276 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
277 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
278 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
279 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
280 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
282 Please provide the physical address corresponding to the
283 location of main memory in your system.
289 source "init/Kconfig"
291 source "kernel/Kconfig.freezer"
296 bool "MMU-based Paged Memory Management Support"
299 Select if you want MMU-based virtualised addressing space
300 support by paged memory management. If unsure, say 'Y'.
303 # The "ARM system type" choice list is ordered alphabetically by option
304 # text. Please add new entries in the option alphabetic order.
307 prompt "ARM system type"
308 default ARCH_VERSATILE if !MMU
309 default ARCH_MULTIPLATFORM if MMU
311 config ARCH_MULTIPLATFORM
312 bool "Allow multiple platforms to be selected"
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_HAS_SG_CHAIN
316 select ARM_PATCH_PHYS_VIRT
320 select GENERIC_CLOCKEVENTS
321 select MIGHT_HAVE_PCI
322 select MULTI_IRQ_HANDLER
326 config ARCH_INTEGRATOR
327 bool "ARM Ltd. Integrator family"
329 select ARM_PATCH_PHYS_VIRT if MMU
332 select COMMON_CLK_VERSATILE
333 select GENERIC_CLOCKEVENTS
336 select MULTI_IRQ_HANDLER
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
341 select VERSATILE_FPGA_IRQ
343 Support for ARM's Integrator platform.
346 bool "ARM Ltd. RealView family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
351 select COMMON_CLK_VERSATILE
352 select GENERIC_CLOCKEVENTS
353 select GPIO_PL061 if GPIOLIB
355 select NEED_MACH_MEMORY_H
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
359 This enables support for ARM Ltd RealView boards.
361 config ARCH_VERSATILE
362 bool "ARM Ltd. Versatile family"
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 select ARM_TIMER_SP804
368 select GENERIC_CLOCKEVENTS
369 select HAVE_MACH_CLKDEV
371 select PLAT_VERSATILE
372 select PLAT_VERSATILE_CLCD
373 select PLAT_VERSATILE_CLOCK
374 select VERSATILE_FPGA_IRQ
376 This enables support for ARM Ltd Versatile board.
380 select ARCH_REQUIRE_GPIOLIB
383 select NEED_MACH_IO_H if PCCARD
385 select PINCTRL_AT91 if USE_OF
387 This enables support for systems based on Atmel
388 AT91RM9200 and AT91SAM9* processors.
391 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
392 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
400 Support for Cirrus Logic 711x/721x/731x based boards.
403 bool "Cortina Systems Gemini"
404 select ARCH_REQUIRE_GPIOLIB
407 select GENERIC_CLOCKEVENTS
409 Support for the Cortina Systems Gemini family SoCs
413 select ARCH_USES_GETTIMEOFFSET
416 select NEED_MACH_IO_H
417 select NEED_MACH_MEMORY_H
420 This is an evaluation board for the StrongARM processor available
421 from Digital. It has limited hardware on-board, including an
422 Ethernet interface, two PCMCIA sockets, two serial ports and a
426 bool "Energy Micro efm32"
428 select ARCH_REQUIRE_GPIOLIB
434 select GENERIC_CLOCKEVENTS
440 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
445 select ARCH_HAS_HOLES_MEMORYMODEL
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_USES_GETTIMEOFFSET
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
480 select NEED_MACH_MEMORY_H
481 select NEED_RET_TO_USER
487 Support for Intel's IOP13XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
495 select NEED_RET_TO_USER
499 Support for Intel's 80219 and IOP32X (XScale) family of
505 select ARCH_REQUIRE_GPIOLIB
508 select NEED_RET_TO_USER
512 Support for Intel's IOP33X (XScale) family of processors.
517 select ARCH_HAS_DMA_SET_COHERENT_MASK
518 select ARCH_REQUIRE_GPIOLIB
519 select ARCH_SUPPORTS_BIG_ENDIAN
522 select DMABOUNCE if PCI
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
525 select NEED_MACH_IO_H
526 select USB_EHCI_BIG_ENDIAN_DESC
527 select USB_EHCI_BIG_ENDIAN_MMIO
529 Support for Intel's IXP4XX (XScale) family of processors.
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
540 select PLAT_ORION_LEGACY
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
553 select PINCTRL_KIRKWOOD
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
560 bool "Marvell MV78xx0"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
594 select MULTI_IRQ_HANDLER
599 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
602 bool "Micrel/Kendin KS8695"
603 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_MEMORY_H
609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
610 System-on-Chip devices.
613 bool "Nuvoton W90X900 CPU"
614 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
620 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
621 At present, the w90x900 has been renamed nuc900, regarding
622 the ARM series product line, you can login the following
623 link address to know more.
625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
630 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
639 Support for the NXP LPC32XX family of processors
642 bool "PXA2xx/PXA3xx-based"
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_CPU_SUSPEND if PM
650 select GENERIC_CLOCKEVENTS
653 select MULTI_IRQ_HANDLER
657 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
660 bool "Qualcomm MSM (non-multiplatform)"
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas ARM SoCs (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT if MMU
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas ARM SoC platforms using a non-multiplatform
689 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
701 select HAVE_PATA_PLATFORM
703 select NEED_MACH_IO_H
704 select NEED_MACH_MEMORY_H
708 On the Acorn Risc-PC, Linux can support the internal IDE disk and
709 CD-ROM interface, serial and parallel port, and the floppy drive.
714 select ARCH_REQUIRE_GPIOLIB
715 select ARCH_SPARSEMEM_ENABLE
720 select GENERIC_CLOCKEVENTS
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_REQUIRE_GPIOLIB
755 select CLKSRC_SAMSUNG_PWM
756 select COMMON_CLK_SAMSUNG
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select PM_GENERIC_DOMAINS if PM
767 select S3C_GPIO_TRACK
769 select SAMSUNG_WAKEMASK
770 select SAMSUNG_WDT_RESET
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
778 select CLKSRC_SAMSUNG_PWM
780 select GENERIC_CLOCKEVENTS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 select SAMSUNG_WDT_RESET
789 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 bool "Samsung S5PC100"
794 select ARCH_REQUIRE_GPIOLIB
797 select CLKSRC_SAMSUNG_PWM
799 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
806 select SAMSUNG_WDT_RESET
808 Samsung S5PC100 series based systems
811 bool "Samsung S5PV210/S5PC110"
812 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_SPARSEMEM_ENABLE
816 select CLKSRC_SAMSUNG_PWM
818 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_GPIO_H
824 select NEED_MACH_MEMORY_H
827 Samsung S5PV210/S5PC110 series based systems
831 select ARCH_HAS_HOLES_MEMORYMODEL
832 select ARCH_REQUIRE_GPIOLIB
834 select GENERIC_ALLOCATOR
835 select GENERIC_CLOCKEVENTS
836 select GENERIC_IRQ_CHIP
842 Support for TI's DaVinci platform.
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_CLOCKEVENTS
853 select GENERIC_IRQ_CHIP
856 select NEED_MACH_IO_H if PCCARD
857 select NEED_MACH_MEMORY_H
859 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
863 menu "Multiple platform selection"
864 depends on ARCH_MULTIPLATFORM
866 comment "CPU Core family selection"
869 bool "ARMv4 based platforms (FA526)"
870 depends on !ARCH_MULTI_V6_V7
871 select ARCH_MULTI_V4_V5
874 config ARCH_MULTI_V4T
875 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
876 depends on !ARCH_MULTI_V6_V7
877 select ARCH_MULTI_V4_V5
878 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
879 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
880 CPU_ARM925T || CPU_ARM940T)
883 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
884 depends on !ARCH_MULTI_V6_V7
885 select ARCH_MULTI_V4_V5
886 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
887 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
888 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
890 config ARCH_MULTI_V4_V5
894 bool "ARMv6 based platforms (ARM11)"
895 select ARCH_MULTI_V6_V7
899 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
901 select ARCH_MULTI_V6_V7
905 config ARCH_MULTI_V6_V7
907 select MIGHT_HAVE_CACHE_L2X0
909 config ARCH_MULTI_CPU_AUTO
910 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
916 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
920 select HAVE_ARM_ARCH_TIMER
923 # This is sorted alphabetically by mach-* pathname. However, plat-*
924 # Kconfigs may be included either alphabetically (according to the
925 # plat- suffix) or along side the corresponding mach-* source.
927 source "arch/arm/mach-mvebu/Kconfig"
929 source "arch/arm/mach-at91/Kconfig"
931 source "arch/arm/mach-axxia/Kconfig"
933 source "arch/arm/mach-bcm/Kconfig"
935 source "arch/arm/mach-berlin/Kconfig"
937 source "arch/arm/mach-clps711x/Kconfig"
939 source "arch/arm/mach-cns3xxx/Kconfig"
941 source "arch/arm/mach-davinci/Kconfig"
943 source "arch/arm/mach-dove/Kconfig"
945 source "arch/arm/mach-ep93xx/Kconfig"
947 source "arch/arm/mach-footbridge/Kconfig"
949 source "arch/arm/mach-gemini/Kconfig"
951 source "arch/arm/mach-highbank/Kconfig"
953 source "arch/arm/mach-hisi/Kconfig"
955 source "arch/arm/mach-integrator/Kconfig"
957 source "arch/arm/mach-iop32x/Kconfig"
959 source "arch/arm/mach-iop33x/Kconfig"
961 source "arch/arm/mach-iop13xx/Kconfig"
963 source "arch/arm/mach-ixp4xx/Kconfig"
965 source "arch/arm/mach-keystone/Kconfig"
967 source "arch/arm/mach-kirkwood/Kconfig"
969 source "arch/arm/mach-ks8695/Kconfig"
971 source "arch/arm/mach-msm/Kconfig"
973 source "arch/arm/mach-moxart/Kconfig"
975 source "arch/arm/mach-mv78xx0/Kconfig"
977 source "arch/arm/mach-imx/Kconfig"
979 source "arch/arm/mach-mxs/Kconfig"
981 source "arch/arm/mach-netx/Kconfig"
983 source "arch/arm/mach-nomadik/Kconfig"
985 source "arch/arm/mach-nspire/Kconfig"
987 source "arch/arm/plat-omap/Kconfig"
989 source "arch/arm/mach-omap1/Kconfig"
991 source "arch/arm/mach-omap2/Kconfig"
993 source "arch/arm/mach-orion5x/Kconfig"
995 source "arch/arm/mach-picoxcell/Kconfig"
997 source "arch/arm/mach-pxa/Kconfig"
998 source "arch/arm/plat-pxa/Kconfig"
1000 source "arch/arm/mach-mmp/Kconfig"
1002 source "arch/arm/mach-qcom/Kconfig"
1004 source "arch/arm/mach-realview/Kconfig"
1006 source "arch/arm/mach-rockchip/Kconfig"
1008 source "arch/arm/mach-sa1100/Kconfig"
1010 source "arch/arm/mach-socfpga/Kconfig"
1012 source "arch/arm/mach-spear/Kconfig"
1014 source "arch/arm/mach-sti/Kconfig"
1016 source "arch/arm/mach-s3c24xx/Kconfig"
1018 source "arch/arm/mach-s3c64xx/Kconfig"
1020 source "arch/arm/mach-s5p64x0/Kconfig"
1022 source "arch/arm/mach-s5pc100/Kconfig"
1024 source "arch/arm/mach-s5pv210/Kconfig"
1026 source "arch/arm/mach-exynos/Kconfig"
1027 source "arch/arm/plat-samsung/Kconfig"
1029 source "arch/arm/mach-shmobile/Kconfig"
1031 source "arch/arm/mach-sunxi/Kconfig"
1033 source "arch/arm/mach-prima2/Kconfig"
1035 source "arch/arm/mach-tegra/Kconfig"
1037 source "arch/arm/mach-u300/Kconfig"
1039 source "arch/arm/mach-ux500/Kconfig"
1041 source "arch/arm/mach-versatile/Kconfig"
1043 source "arch/arm/mach-vexpress/Kconfig"
1044 source "arch/arm/plat-versatile/Kconfig"
1046 source "arch/arm/mach-vt8500/Kconfig"
1048 source "arch/arm/mach-w90x900/Kconfig"
1050 source "arch/arm/mach-zynq/Kconfig"
1052 # Definitions to make life easier
1058 select GENERIC_CLOCKEVENTS
1064 select GENERIC_IRQ_CHIP
1067 config PLAT_ORION_LEGACY
1074 config PLAT_VERSATILE
1077 config ARM_TIMER_SP804
1080 select CLKSRC_OF if OF
1082 source "arch/arm/firmware/Kconfig"
1084 source arch/arm/mm/Kconfig
1087 bool "Enable iWMMXt support"
1088 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1089 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1091 Enable support for iWMMXt context switching at run time if
1092 running on a CPU that supports it.
1094 config MULTI_IRQ_HANDLER
1097 Allow each machine to specify it's own IRQ handler at run time.
1100 source "arch/arm/Kconfig-nommu"
1103 config PJ4B_ERRATA_4742
1104 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1105 depends on CPU_PJ4B && MACH_ARMADA_370
1108 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1109 Event (WFE) IDLE states, a specific timing sensitivity exists between
1110 the retiring WFI/WFE instructions and the newly issued subsequent
1111 instructions. This sensitivity can result in a CPU hang scenario.
1113 The software must insert either a Data Synchronization Barrier (DSB)
1114 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1117 config ARM_ERRATA_326103
1118 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1121 Executing a SWP instruction to read-only memory does not set bit 11
1122 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1123 treat the access as a read, preventing a COW from occurring and
1124 causing the faulting task to livelock.
1126 config ARM_ERRATA_411920
1127 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1128 depends on CPU_V6 || CPU_V6K
1130 Invalidation of the Instruction Cache operation can
1131 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1132 It does not affect the MPCore. This option enables the ARM Ltd.
1133 recommended workaround.
1135 config ARM_ERRATA_430973
1136 bool "ARM errata: Stale prediction on replaced interworking branch"
1139 This option enables the workaround for the 430973 Cortex-A8
1140 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1141 interworking branch is replaced with another code sequence at the
1142 same virtual address, whether due to self-modifying code or virtual
1143 to physical address re-mapping, Cortex-A8 does not recover from the
1144 stale interworking branch prediction. This results in Cortex-A8
1145 executing the new code sequence in the incorrect ARM or Thumb state.
1146 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1147 and also flushes the branch target cache at every context switch.
1148 Note that setting specific bits in the ACTLR register may not be
1149 available in non-secure mode.
1151 config ARM_ERRATA_458693
1152 bool "ARM errata: Processor deadlock when a false hazard is created"
1154 depends on !ARCH_MULTIPLATFORM
1156 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1157 erratum. For very specific sequences of memory operations, it is
1158 possible for a hazard condition intended for a cache line to instead
1159 be incorrectly associated with a different cache line. This false
1160 hazard might then cause a processor deadlock. The workaround enables
1161 the L1 caching of the NEON accesses and disables the PLD instruction
1162 in the ACTLR register. Note that setting specific bits in the ACTLR
1163 register may not be available in non-secure mode.
1165 config ARM_ERRATA_460075
1166 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1168 depends on !ARCH_MULTIPLATFORM
1170 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1171 erratum. Any asynchronous access to the L2 cache may encounter a
1172 situation in which recent store transactions to the L2 cache are lost
1173 and overwritten with stale memory contents from external memory. The
1174 workaround disables the write-allocate mode for the L2 cache via the
1175 ACTLR register. Note that setting specific bits in the ACTLR register
1176 may not be available in non-secure mode.
1178 config ARM_ERRATA_742230
1179 bool "ARM errata: DMB operation may be faulty"
1180 depends on CPU_V7 && SMP
1181 depends on !ARCH_MULTIPLATFORM
1183 This option enables the workaround for the 742230 Cortex-A9
1184 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1185 between two write operations may not ensure the correct visibility
1186 ordering of the two writes. This workaround sets a specific bit in
1187 the diagnostic register of the Cortex-A9 which causes the DMB
1188 instruction to behave as a DSB, ensuring the correct behaviour of
1191 config ARM_ERRATA_742231
1192 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1193 depends on CPU_V7 && SMP
1194 depends on !ARCH_MULTIPLATFORM
1196 This option enables the workaround for the 742231 Cortex-A9
1197 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1198 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1199 accessing some data located in the same cache line, may get corrupted
1200 data due to bad handling of the address hazard when the line gets
1201 replaced from one of the CPUs at the same time as another CPU is
1202 accessing it. This workaround sets specific bits in the diagnostic
1203 register of the Cortex-A9 which reduces the linefill issuing
1204 capabilities of the processor.
1206 config ARM_ERRATA_643719
1207 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for the 643719 Cortex-A9 (prior to
1211 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1212 register returns zero when it should return one. The workaround
1213 corrects this value, ensuring cache maintenance operations which use
1214 it behave as intended and avoiding data corruption.
1216 config ARM_ERRATA_720789
1217 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1220 This option enables the workaround for the 720789 Cortex-A9 (prior to
1221 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1222 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1223 As a consequence of this erratum, some TLB entries which should be
1224 invalidated are not, resulting in an incoherency in the system page
1225 tables. The workaround changes the TLB flushing routines to invalidate
1226 entries regardless of the ASID.
1228 config ARM_ERRATA_743622
1229 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231 depends on !ARCH_MULTIPLATFORM
1233 This option enables the workaround for the 743622 Cortex-A9
1234 (r2p*) erratum. Under very rare conditions, a faulty
1235 optimisation in the Cortex-A9 Store Buffer may lead to data
1236 corruption. This workaround sets a specific bit in the diagnostic
1237 register of the Cortex-A9 which disables the Store Buffer
1238 optimisation, preventing the defect from occurring. This has no
1239 visible impact on the overall performance or power consumption of the
1242 config ARM_ERRATA_751472
1243 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 751472 Cortex-A9 (prior
1248 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1249 completion of a following broadcasted operation if the second
1250 operation is received by a CPU before the ICIALLUIS has completed,
1251 potentially leading to corrupted entries in the cache or TLB.
1253 config ARM_ERRATA_754322
1254 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1257 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1258 r3p*) erratum. A speculative memory access may cause a page table walk
1259 which starts prior to an ASID switch but completes afterwards. This
1260 can populate the micro-TLB with a stale entry which may be hit with
1261 the new ASID. This workaround places two dsb instructions in the mm
1262 switching code so that no page table walks can cross the ASID switch.
1264 config ARM_ERRATA_754327
1265 bool "ARM errata: no automatic Store Buffer drain"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 754327 Cortex-A9 (prior to
1269 r2p0) erratum. The Store Buffer does not have any automatic draining
1270 mechanism and therefore a livelock may occur if an external agent
1271 continuously polls a memory location waiting to observe an update.
1272 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1273 written polling loops from denying visibility of updates to memory.
1275 config ARM_ERRATA_364296
1276 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1279 This options enables the workaround for the 364296 ARM1136
1280 r0p2 erratum (possible cache data corruption with
1281 hit-under-miss enabled). It sets the undocumented bit 31 in
1282 the auxiliary control register and the FI bit in the control
1283 register, thus disabling hit-under-miss without putting the
1284 processor into full low interrupt latency mode. ARM11MPCore
1287 config ARM_ERRATA_764369
1288 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1289 depends on CPU_V7 && SMP
1291 This option enables the workaround for erratum 764369
1292 affecting Cortex-A9 MPCore with two or more processors (all
1293 current revisions). Under certain timing circumstances, a data
1294 cache line maintenance operation by MVA targeting an Inner
1295 Shareable memory region may fail to proceed up to either the
1296 Point of Coherency or to the Point of Unification of the
1297 system. This workaround adds a DSB instruction before the
1298 relevant cache maintenance functions and sets a specific bit
1299 in the diagnostic control register of the SCU.
1301 config ARM_ERRATA_775420
1302 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1305 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1306 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1307 operation aborts with MMU exception, it might cause the processor
1308 to deadlock. This workaround puts DSB before executing ISB if
1309 an abort may occur on cache maintenance.
1311 config ARM_ERRATA_798181
1312 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1313 depends on CPU_V7 && SMP
1315 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1316 adequately shooting down all use of the old entries. This
1317 option enables the Linux kernel workaround for this erratum
1318 which sends an IPI to the CPUs that are running the same ASID
1319 as the one being invalidated.
1321 config ARM_ERRATA_773022
1322 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1325 This option enables the workaround for the 773022 Cortex-A15
1326 (up to r0p4) erratum. In certain rare sequences of code, the
1327 loop buffer may deliver incorrect instructions. This
1328 workaround disables the loop buffer to avoid the erratum.
1332 source "arch/arm/common/Kconfig"
1342 Find out whether you have ISA slots on your motherboard. ISA is the
1343 name of a bus system, i.e. the way the CPU talks to the other stuff
1344 inside your box. Other bus systems are PCI, EISA, MicroChannel
1345 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1346 newer boards don't support it. If you have ISA, say Y, otherwise N.
1348 # Select ISA DMA controller support
1353 # Select ISA DMA interface
1358 bool "PCI support" if MIGHT_HAVE_PCI
1360 Find out whether you have a PCI motherboard. PCI is the name of a
1361 bus system, i.e. the way the CPU talks to the other stuff inside
1362 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1363 VESA. If you have PCI, say Y, otherwise N.
1369 config PCI_NANOENGINE
1370 bool "BSE nanoEngine PCI support"
1371 depends on SA1100_NANOENGINE
1373 Enable PCI on the BSE nanoEngine board.
1378 config PCI_HOST_ITE8152
1380 depends on PCI && MACH_ARMCORE
1384 source "drivers/pci/Kconfig"
1385 source "drivers/pci/pcie/Kconfig"
1387 source "drivers/pcmcia/Kconfig"
1391 menu "Kernel Features"
1396 This option should be selected by machines which have an SMP-
1399 The only effect of this option is to make the SMP-related
1400 options available to the user for configuration.
1403 bool "Symmetric Multi-Processing"
1404 depends on CPU_V6K || CPU_V7
1405 depends on GENERIC_CLOCKEVENTS
1407 depends on MMU || ARM_MPU
1409 This enables support for systems with more than one CPU. If you have
1410 a system with only one CPU, say N. If you have a system with more
1411 than one CPU, say Y.
1413 If you say N here, the kernel will run on uni- and multiprocessor
1414 machines, but will use only one CPU of a multiprocessor machine. If
1415 you say Y here, the kernel will run on many, but not all,
1416 uniprocessor machines. On a uniprocessor machine, the kernel
1417 will run faster if you say N here.
1419 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1420 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1421 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1423 If you don't know what to do here, say N.
1426 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1427 depends on SMP && !XIP_KERNEL && MMU
1430 SMP kernels contain instructions which fail on non-SMP processors.
1431 Enabling this option allows the kernel to modify itself to make
1432 these instructions safe. Disabling it allows about 1K of space
1435 If you don't know what to do here, say Y.
1437 config ARM_CPU_TOPOLOGY
1438 bool "Support cpu topology definition"
1439 depends on SMP && CPU_V7
1442 Support ARM cpu topology definition. The MPIDR register defines
1443 affinity between processors which is then used to describe the cpu
1444 topology of an ARM System.
1447 bool "Multi-core scheduler support"
1448 depends on ARM_CPU_TOPOLOGY
1450 Multi-core scheduler support improves the CPU scheduler's decision
1451 making when dealing with multi-core CPU chips at a cost of slightly
1452 increased overhead in some places. If unsure say N here.
1455 bool "SMT scheduler support"
1456 depends on ARM_CPU_TOPOLOGY
1458 Improves the CPU scheduler's decision making when dealing with
1459 MultiThreading at a cost of slightly increased overhead in some
1460 places. If unsure say N here.
1465 This option enables support for the ARM system coherency unit
1467 config HAVE_ARM_ARCH_TIMER
1468 bool "Architected timer support"
1470 select ARM_ARCH_TIMER
1471 select GENERIC_CLOCKEVENTS
1473 This option enables support for the ARM architected timer
1478 select CLKSRC_OF if OF
1480 This options enables support for the ARM timer and watchdog unit
1483 bool "Multi-Cluster Power Management"
1484 depends on CPU_V7 && SMP
1486 This option provides the common power management infrastructure
1487 for (multi-)cluster based systems, such as big.LITTLE based
1491 bool "big.LITTLE support (Experimental)"
1492 depends on CPU_V7 && SMP
1495 This option enables support selections for the big.LITTLE
1496 system architecture.
1499 bool "big.LITTLE switcher support"
1500 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1501 select ARM_CPU_SUSPEND
1504 The big.LITTLE "switcher" provides the core functionality to
1505 transparently handle transition between a cluster of A15's
1506 and a cluster of A7's in a big.LITTLE system.
1508 config BL_SWITCHER_DUMMY_IF
1509 tristate "Simple big.LITTLE switcher user interface"
1510 depends on BL_SWITCHER && DEBUG_KERNEL
1512 This is a simple and dummy char dev interface to control
1513 the big.LITTLE switcher core code. It is meant for
1514 debugging purposes only.
1517 prompt "Memory split"
1521 Select the desired split between kernel and user memory.
1523 If you are not absolutely sure what you are doing, leave this
1527 bool "3G/1G user/kernel split"
1529 bool "2G/2G user/kernel split"
1531 bool "1G/3G user/kernel split"
1536 default PHYS_OFFSET if !MMU
1537 default 0x40000000 if VMSPLIT_1G
1538 default 0x80000000 if VMSPLIT_2G
1542 int "Maximum number of CPUs (2-32)"
1548 bool "Support for hot-pluggable CPUs"
1551 Say Y here to experiment with turning CPUs off and on. CPUs
1552 can be controlled through /sys/devices/system/cpu.
1555 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1558 Say Y here if you want Linux to communicate with system firmware
1559 implementing the PSCI specification for CPU-centric power
1560 management operations described in ARM document number ARM DEN
1561 0022A ("Power State Coordination Interface System Software on
1564 # The GPIO number here must be sorted by descending number. In case of
1565 # a multiplatform kernel, we just want the highest value required by the
1566 # selected platforms.
1569 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1570 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1571 default 416 if ARCH_SUNXI
1572 default 392 if ARCH_U8500
1573 default 352 if ARCH_VT8500
1574 default 264 if MACH_H4700
1577 Maximum number of GPIOs in the system.
1579 If unsure, leave the default value.
1581 source kernel/Kconfig.preempt
1585 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1586 ARCH_S5PV210 || ARCH_EXYNOS4
1587 default AT91_TIMER_HZ if ARCH_AT91
1588 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1592 depends on HZ_FIXED = 0
1593 prompt "Timer frequency"
1617 default HZ_FIXED if HZ_FIXED != 0
1618 default 100 if HZ_100
1619 default 200 if HZ_200
1620 default 250 if HZ_250
1621 default 300 if HZ_300
1622 default 500 if HZ_500
1626 def_bool HIGH_RES_TIMERS
1628 config THUMB2_KERNEL
1629 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1630 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1631 default y if CPU_THUMBONLY
1633 select ARM_ASM_UNIFIED
1636 By enabling this option, the kernel will be compiled in
1637 Thumb-2 mode. A compiler/assembler that understand the unified
1638 ARM-Thumb syntax is needed.
1642 config THUMB2_AVOID_R_ARM_THM_JUMP11
1643 bool "Work around buggy Thumb-2 short branch relocations in gas"
1644 depends on THUMB2_KERNEL && MODULES
1647 Various binutils versions can resolve Thumb-2 branches to
1648 locally-defined, preemptible global symbols as short-range "b.n"
1649 branch instructions.
1651 This is a problem, because there's no guarantee the final
1652 destination of the symbol, or any candidate locations for a
1653 trampoline, are within range of the branch. For this reason, the
1654 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1655 relocation in modules at all, and it makes little sense to add
1658 The symptom is that the kernel fails with an "unsupported
1659 relocation" error when loading some modules.
1661 Until fixed tools are available, passing
1662 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1663 code which hits this problem, at the cost of a bit of extra runtime
1664 stack usage in some cases.
1666 The problem is described in more detail at:
1667 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1669 Only Thumb-2 kernels are affected.
1671 Unless you are sure your tools don't have this problem, say Y.
1673 config ARM_ASM_UNIFIED
1677 bool "Use the ARM EABI to compile the kernel"
1679 This option allows for the kernel to be compiled using the latest
1680 ARM ABI (aka EABI). This is only useful if you are using a user
1681 space environment that is also compiled with EABI.
1683 Since there are major incompatibilities between the legacy ABI and
1684 EABI, especially with regard to structure member alignment, this
1685 option also changes the kernel syscall calling convention to
1686 disambiguate both ABIs and allow for backward compatibility support
1687 (selected with CONFIG_OABI_COMPAT).
1689 To use this you need GCC version 4.0.0 or later.
1692 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1693 depends on AEABI && !THUMB2_KERNEL
1695 This option preserves the old syscall interface along with the
1696 new (ARM EABI) one. It also provides a compatibility layer to
1697 intercept syscalls that have structure arguments which layout
1698 in memory differs between the legacy ABI and the new ARM EABI
1699 (only for non "thumb" binaries). This option adds a tiny
1700 overhead to all syscalls and produces a slightly larger kernel.
1702 The seccomp filter system will not be available when this is
1703 selected, since there is no way yet to sensibly distinguish
1704 between calling conventions during filtering.
1706 If you know you'll be using only pure EABI user space then you
1707 can say N here. If this option is not selected and you attempt
1708 to execute a legacy ABI binary then the result will be
1709 UNPREDICTABLE (in fact it can be predicted that it won't work
1710 at all). If in doubt say N.
1712 config ARCH_HAS_HOLES_MEMORYMODEL
1715 config ARCH_SPARSEMEM_ENABLE
1718 config ARCH_SPARSEMEM_DEFAULT
1719 def_bool ARCH_SPARSEMEM_ENABLE
1721 config ARCH_SELECT_MEMORY_MODEL
1722 def_bool ARCH_SPARSEMEM_ENABLE
1724 config HAVE_ARCH_PFN_VALID
1725 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1728 bool "High Memory Support"
1731 The address space of ARM processors is only 4 Gigabytes large
1732 and it has to accommodate user address space, kernel address
1733 space as well as some memory mapped IO. That means that, if you
1734 have a large amount of physical memory and/or IO, not all of the
1735 memory can be "permanently mapped" by the kernel. The physical
1736 memory that is not permanently mapped is called "high memory".
1738 Depending on the selected kernel/user memory split, minimum
1739 vmalloc space and actual amount of RAM, you may not need this
1740 option which should result in a slightly faster kernel.
1745 bool "Allocate 2nd-level pagetables from highmem"
1748 config HW_PERF_EVENTS
1749 bool "Enable hardware performance counter support for perf events"
1750 depends on PERF_EVENTS
1753 Enable hardware performance counter support for perf events. If
1754 disabled, perf events will use software events only.
1756 config SYS_SUPPORTS_HUGETLBFS
1760 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1764 config ARCH_WANT_GENERAL_HUGETLB
1769 config FORCE_MAX_ZONEORDER
1770 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1771 range 11 64 if ARCH_SHMOBILE_LEGACY
1772 default "12" if SOC_AM33XX
1773 default "9" if SA1111 || ARCH_EFM32
1776 The kernel memory allocator divides physically contiguous memory
1777 blocks into "zones", where each zone is a power of two number of
1778 pages. This option selects the largest power of two that the kernel
1779 keeps in the memory allocator. If you need to allocate very large
1780 blocks of physically contiguous memory, then you may need to
1781 increase this value.
1783 This config option is actually maximum order plus one. For example,
1784 a value of 11 means that the largest free memory block is 2^10 pages.
1786 config ALIGNMENT_TRAP
1788 depends on CPU_CP15_MMU
1789 default y if !ARCH_EBSA110
1790 select HAVE_PROC_CPU if PROC_FS
1792 ARM processors cannot fetch/store information which is not
1793 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1794 address divisible by 4. On 32-bit ARM processors, these non-aligned
1795 fetch/store instructions will be emulated in software if you say
1796 here, which has a severe performance impact. This is necessary for
1797 correct operation of some network protocols. With an IP-only
1798 configuration it is safe to say N, otherwise say Y.
1800 config UACCESS_WITH_MEMCPY
1801 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1803 default y if CPU_FEROCEON
1805 Implement faster copy_to_user and clear_user methods for CPU
1806 cores where a 8-word STM instruction give significantly higher
1807 memory write throughput than a sequence of individual 32bit stores.
1809 A possible side effect is a slight increase in scheduling latency
1810 between threads sharing the same address space if they invoke
1811 such copy operations with large buffers.
1813 However, if the CPU data cache is using a write-allocate mode,
1814 this option is unlikely to provide any performance gain.
1818 prompt "Enable seccomp to safely compute untrusted bytecode"
1820 This kernel feature is useful for number crunching applications
1821 that may need to compute untrusted bytecode during their
1822 execution. By using pipes or other transports made available to
1823 the process as file descriptors supporting the read/write
1824 syscalls, it's possible to isolate those applications in
1825 their own address space using seccomp. Once seccomp is
1826 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1827 and the task is only allowed to execute a few safe syscalls
1828 defined by each seccomp mode.
1841 bool "Xen guest support on ARM (EXPERIMENTAL)"
1842 depends on ARM && AEABI && OF
1843 depends on CPU_V7 && !CPU_V6
1844 depends on !GENERIC_ATOMIC64
1846 select ARCH_DMA_ADDR_T_64BIT
1850 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1857 bool "Flattened Device Tree support"
1860 select OF_EARLY_FLATTREE
1861 select OF_RESERVED_MEM
1863 Include support for flattened device tree machine descriptions.
1866 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1869 This is the traditional way of passing data to the kernel at boot
1870 time. If you are solely relying on the flattened device tree (or
1871 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1872 to remove ATAGS support from your kernel binary. If unsure,
1875 config DEPRECATED_PARAM_STRUCT
1876 bool "Provide old way to pass kernel parameters"
1879 This was deprecated in 2001 and announced to live on for 5 years.
1880 Some old boot loaders still use this way.
1882 # Compressed boot loader in ROM. Yes, we really want to ask about
1883 # TEXT and BSS so we preserve their values in the config files.
1884 config ZBOOT_ROM_TEXT
1885 hex "Compressed ROM boot loader base address"
1888 The physical address at which the ROM-able zImage is to be
1889 placed in the target. Platforms which normally make use of
1890 ROM-able zImage formats normally set this to a suitable
1891 value in their defconfig file.
1893 If ZBOOT_ROM is not enabled, this has no effect.
1895 config ZBOOT_ROM_BSS
1896 hex "Compressed ROM boot loader BSS address"
1899 The base address of an area of read/write memory in the target
1900 for the ROM-able zImage which must be available while the
1901 decompressor is running. It must be large enough to hold the
1902 entire decompressed kernel plus an additional 128 KiB.
1903 Platforms which normally make use of ROM-able zImage formats
1904 normally set this to a suitable value in their defconfig file.
1906 If ZBOOT_ROM is not enabled, this has no effect.
1909 bool "Compressed boot loader in ROM/flash"
1910 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1911 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1913 Say Y here if you intend to execute your compressed kernel image
1914 (zImage) directly from ROM or flash. If unsure, say N.
1917 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1918 depends on ZBOOT_ROM && ARCH_SH7372
1919 default ZBOOT_ROM_NONE
1921 Include experimental SD/MMC loading code in the ROM-able zImage.
1922 With this enabled it is possible to write the ROM-able zImage
1923 kernel image to an MMC or SD card and boot the kernel straight
1924 from the reset vector. At reset the processor Mask ROM will load
1925 the first part of the ROM-able zImage which in turn loads the
1926 rest the kernel image to RAM.
1928 config ZBOOT_ROM_NONE
1929 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1931 Do not load image from SD or MMC
1933 config ZBOOT_ROM_MMCIF
1934 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1936 Load image from MMCIF hardware block.
1938 config ZBOOT_ROM_SH_MOBILE_SDHI
1939 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1941 Load image from SDHI hardware block
1945 config ARM_APPENDED_DTB
1946 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1949 With this option, the boot code will look for a device tree binary
1950 (DTB) appended to zImage
1951 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1953 This is meant as a backward compatibility convenience for those
1954 systems with a bootloader that can't be upgraded to accommodate
1955 the documented boot protocol using a device tree.
1957 Beware that there is very little in terms of protection against
1958 this option being confused by leftover garbage in memory that might
1959 look like a DTB header after a reboot if no actual DTB is appended
1960 to zImage. Do not leave this option active in a production kernel
1961 if you don't intend to always append a DTB. Proper passing of the
1962 location into r2 of a bootloader provided DTB is always preferable
1965 config ARM_ATAG_DTB_COMPAT
1966 bool "Supplement the appended DTB with traditional ATAG information"
1967 depends on ARM_APPENDED_DTB
1969 Some old bootloaders can't be updated to a DTB capable one, yet
1970 they provide ATAGs with memory configuration, the ramdisk address,
1971 the kernel cmdline string, etc. Such information is dynamically
1972 provided by the bootloader and can't always be stored in a static
1973 DTB. To allow a device tree enabled kernel to be used with such
1974 bootloaders, this option allows zImage to extract the information
1975 from the ATAG list and store it at run time into the appended DTB.
1978 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1979 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1981 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1982 bool "Use bootloader kernel arguments if available"
1984 Uses the command-line options passed by the boot loader instead of
1985 the device tree bootargs property. If the boot loader doesn't provide
1986 any, the device tree bootargs property will be used.
1988 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1989 bool "Extend with bootloader kernel arguments"
1991 The command-line arguments provided by the boot loader will be
1992 appended to the the device tree bootargs property.
1997 string "Default kernel command string"
2000 On some architectures (EBSA110 and CATS), there is currently no way
2001 for the boot loader to pass arguments to the kernel. For these
2002 architectures, you should supply some command-line options at build
2003 time by entering them here. As a minimum, you should specify the
2004 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2007 prompt "Kernel command line type" if CMDLINE != ""
2008 default CMDLINE_FROM_BOOTLOADER
2011 config CMDLINE_FROM_BOOTLOADER
2012 bool "Use bootloader kernel arguments if available"
2014 Uses the command-line options passed by the boot loader. If
2015 the boot loader doesn't provide any, the default kernel command
2016 string provided in CMDLINE will be used.
2018 config CMDLINE_EXTEND
2019 bool "Extend bootloader kernel arguments"
2021 The command-line arguments provided by the boot loader will be
2022 appended to the default kernel command string.
2024 config CMDLINE_FORCE
2025 bool "Always use the default kernel command string"
2027 Always use the default kernel command string, even if the boot
2028 loader passes other arguments to the kernel.
2029 This is useful if you cannot or don't want to change the
2030 command-line options your boot loader passes to the kernel.
2034 bool "Kernel Execute-In-Place from ROM"
2035 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2037 Execute-In-Place allows the kernel to run from non-volatile storage
2038 directly addressable by the CPU, such as NOR flash. This saves RAM
2039 space since the text section of the kernel is not loaded from flash
2040 to RAM. Read-write sections, such as the data section and stack,
2041 are still copied to RAM. The XIP kernel is not compressed since
2042 it has to run directly from flash, so it will take more space to
2043 store it. The flash address used to link the kernel object files,
2044 and for storing it, is configuration dependent. Therefore, if you
2045 say Y here, you must know the proper physical address where to
2046 store the kernel image depending on your own flash memory usage.
2048 Also note that the make target becomes "make xipImage" rather than
2049 "make zImage" or "make Image". The final kernel binary to put in
2050 ROM memory will be arch/arm/boot/xipImage.
2054 config XIP_PHYS_ADDR
2055 hex "XIP Kernel Physical Location"
2056 depends on XIP_KERNEL
2057 default "0x00080000"
2059 This is the physical address in your flash memory the kernel will
2060 be linked for and stored to. This address is dependent on your
2064 bool "Kexec system call (EXPERIMENTAL)"
2065 depends on (!SMP || PM_SLEEP_SMP)
2067 kexec is a system call that implements the ability to shutdown your
2068 current kernel, and to start another kernel. It is like a reboot
2069 but it is independent of the system firmware. And like a reboot
2070 you can start any kernel with it, not just Linux.
2072 It is an ongoing process to be certain the hardware in a machine
2073 is properly shutdown, so do not be surprised if this code does not
2074 initially work for you.
2077 bool "Export atags in procfs"
2078 depends on ATAGS && KEXEC
2081 Should the atags used to boot the kernel be exported in an "atags"
2082 file in procfs. Useful with kexec.
2085 bool "Build kdump crash kernel (EXPERIMENTAL)"
2087 Generate crash dump after being started by kexec. This should
2088 be normally only set in special crash dump kernels which are
2089 loaded in the main kernel with kexec-tools into a specially
2090 reserved region and then later executed after a crash by
2091 kdump/kexec. The crash dump kernel must be compiled to a
2092 memory address not used by the main kernel
2094 For more details see Documentation/kdump/kdump.txt
2096 config AUTO_ZRELADDR
2097 bool "Auto calculation of the decompressed kernel image address"
2099 ZRELADDR is the physical address where the decompressed kernel
2100 image will be placed. If AUTO_ZRELADDR is selected, the address
2101 will be determined at run-time by masking the current IP with
2102 0xf8000000. This assumes the zImage being placed in the first 128MB
2103 from start of memory.
2107 menu "CPU Power Management"
2109 source "drivers/cpufreq/Kconfig"
2111 source "drivers/cpuidle/Kconfig"
2115 menu "Floating point emulation"
2117 comment "At least one emulation must be selected"
2120 bool "NWFPE math emulation"
2121 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2123 Say Y to include the NWFPE floating point emulator in the kernel.
2124 This is necessary to run most binaries. Linux does not currently
2125 support floating point hardware so you need to say Y here even if
2126 your machine has an FPA or floating point co-processor podule.
2128 You may say N here if you are going to load the Acorn FPEmulator
2129 early in the bootup.
2132 bool "Support extended precision"
2133 depends on FPE_NWFPE
2135 Say Y to include 80-bit support in the kernel floating-point
2136 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2137 Note that gcc does not generate 80-bit operations by default,
2138 so in most cases this option only enlarges the size of the
2139 floating point emulator without any good reason.
2141 You almost surely want to say N here.
2144 bool "FastFPE math emulation (EXPERIMENTAL)"
2145 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2147 Say Y here to include the FAST floating point emulator in the kernel.
2148 This is an experimental much faster emulator which now also has full
2149 precision for the mantissa. It does not support any exceptions.
2150 It is very simple, and approximately 3-6 times faster than NWFPE.
2152 It should be sufficient for most programs. It may be not suitable
2153 for scientific calculations, but you have to check this for yourself.
2154 If you do not feel you need a faster FP emulation you should better
2158 bool "VFP-format floating point maths"
2159 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2161 Say Y to include VFP support code in the kernel. This is needed
2162 if your hardware includes a VFP unit.
2164 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2165 release notes and additional status information.
2167 Say N if your target does not have VFP hardware.
2175 bool "Advanced SIMD (NEON) Extension support"
2176 depends on VFPv3 && CPU_V7
2178 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2181 config KERNEL_MODE_NEON
2182 bool "Support for NEON in kernel mode"
2183 depends on NEON && AEABI
2185 Say Y to include support for NEON in kernel mode.
2189 menu "Userspace binary formats"
2191 source "fs/Kconfig.binfmt"
2194 tristate "RISC OS personality"
2197 Say Y here to include the kernel code necessary if you want to run
2198 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2199 experimental; if this sounds frightening, say N and sleep in peace.
2200 You can also say M here to compile this support as a module (which
2201 will be called arthur).
2205 menu "Power management options"
2207 source "kernel/power/Kconfig"
2209 config ARCH_SUSPEND_POSSIBLE
2210 depends on !ARCH_S5PC100
2211 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2212 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2215 config ARM_CPU_SUSPEND
2218 config ARCH_HIBERNATION_POSSIBLE
2221 default y if ARCH_SUSPEND_POSSIBLE
2225 source "net/Kconfig"
2227 source "drivers/Kconfig"
2231 source "arch/arm/Kconfig.debug"
2233 source "security/Kconfig"
2235 source "crypto/Kconfig"
2237 source "lib/Kconfig"
2239 source "arch/arm/kvm/Kconfig"