arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_MIGHT_HAVE_PC_PARPORT
   9         select ARCH_SUPPORTS_ATOMIC_RMW
  10         select ARCH_USE_BUILTIN_BSWAP
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_WANT_IPC_PARSE_VERSION
  13         select BUILDTIME_EXTABLE_SORT if MMU
  14         select CLONE_BACKWARDS
  15         select CPU_PM if (SUSPEND || CPU_IDLE)
  16         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  17         select GENERIC_ALLOCATOR
  18         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  19         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  20         select GENERIC_IDLE_POLL_SETUP
  21         select GENERIC_IRQ_PROBE
  22         select GENERIC_IRQ_SHOW
  23         select GENERIC_PCI_IOMAP
  24         select GENERIC_SCHED_CLOCK
  25         select GENERIC_SMP_IDLE_THREAD
  26         select GENERIC_STRNCPY_FROM_USER
  27         select GENERIC_STRNLEN_USER
  28         select HANDLE_DOMAIN_IRQ
  29         select HARDIRQS_SW_RESEND
  30         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  31         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  32         select HAVE_ARCH_KGDB
  33         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  34         select HAVE_ARCH_TRACEHOOK
  35         select HAVE_BPF_JIT
  36         select HAVE_CC_STACKPROTECTOR
  37         select HAVE_CONTEXT_TRACKING
  38         select HAVE_C_RECORDMCOUNT
  39         select HAVE_DEBUG_KMEMLEAK
  40         select HAVE_DMA_API_DEBUG
  41         select HAVE_DMA_ATTRS
  42         select HAVE_DMA_CONTIGUOUS if MMU
  43         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  44         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  45         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  46         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  47         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  48         select HAVE_GENERIC_DMA_COHERENT
  49         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  50         select HAVE_IDE if PCI || ISA || PCMCIA
  51         select HAVE_IRQ_TIME_ACCOUNTING
  52         select HAVE_KERNEL_GZIP
  53         select HAVE_KERNEL_LZ4
  54         select HAVE_KERNEL_LZMA
  55         select HAVE_KERNEL_LZO
  56         select HAVE_KERNEL_XZ
  57         select HAVE_KPROBES if !XIP_KERNEL
  58         select HAVE_KRETPROBES if (HAVE_KPROBES)
  59         select HAVE_MEMBLOCK
  60         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  61         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  62         select HAVE_PERF_EVENTS
  63         select HAVE_PERF_REGS
  64         select HAVE_PERF_USER_STACK_DUMP
  65         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  66         select HAVE_REGS_AND_STACK_ACCESS_API
  67         select HAVE_SYSCALL_TRACEPOINTS
  68         select HAVE_UID16
  69         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  70         select IRQ_FORCED_THREADING
  71         select MODULES_USE_ELF_REL
  72         select NO_BOOTMEM
  73         select OLD_SIGACTION
  74         select OLD_SIGSUSPEND3
  75         select PERF_USE_VMALLOC
  76         select RTC_LIB
  77         select SYS_SUPPORTS_APM_EMULATION
  78         # Above selects are sorted alphabetically; please add new ones
  79         # according to that.  Thanks.
  80         help
  81           The ARM series is a line of low-power-consumption RISC chip designs
  82           licensed by ARM Ltd and targeted at embedded applications and
  83           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  84           manufactured, but legacy ARM-based PC hardware remains popular in
  85           Europe.  There is an ARM Linux project with a web page at
  86           <http://www.arm.linux.org.uk/>.
  87
  88 config ARM_HAS_SG_CHAIN
  89         select ARCH_HAS_SG_CHAIN
  90         bool
  91
  92 config NEED_SG_DMA_LENGTH
  93         bool
  94
  95 config ARM_DMA_USE_IOMMU
  96         bool
  97         select ARM_HAS_SG_CHAIN
  98         select NEED_SG_DMA_LENGTH
  99
 100 if ARM_DMA_USE_IOMMU
 101
 102 config ARM_DMA_IOMMU_ALIGNMENT
 103         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 104         range 4 9
 105         default 8
 106         help
 107           DMA mapping framework by default aligns all buffers to the smallest
 108           PAGE_SIZE order which is greater than or equal to the requested buffer
 109           size. This works well for buffers up to a few hundreds kilobytes, but
 110           for larger buffers it just a waste of address space. Drivers which has
 111           relatively small addressing window (like 64Mib) might run out of
 112           virtual space with just a few allocations.
 113
 114           With this parameter you can specify the maximum PAGE_SIZE order for
 115           DMA IOMMU buffers. Larger buffers will be aligned only to this
 116           specified order. The order is expressed as a power of two multiplied
 117           by the PAGE_SIZE.
 118
 119 endif
 120
 121 config MIGHT_HAVE_PCI
 122         bool
 123
 124 config SYS_SUPPORTS_APM_EMULATION
 125         bool
 126
 127 config HAVE_TCM
 128         bool
 129         select GENERIC_ALLOCATOR
 130
 131 config HAVE_PROC_CPU
 132         bool
 133
 134 config NO_IOPORT_MAP
 135         bool
 136
 137 config EISA
 138         bool
 139         ---help---
 140           The Extended Industry Standard Architecture (EISA) bus was
 141           developed as an open alternative to the IBM MicroChannel bus.
 142
 143           The EISA bus provided some of the features of the IBM MicroChannel
 144           bus while maintaining backward compatibility with cards made for
 145           the older ISA bus.  The EISA bus saw limited use between 1988 and
 146           1995 when it was made obsolete by the PCI bus.
 147
 148           Say Y here if you are building a kernel for an EISA-based machine.
 149
 150           Otherwise, say N.
 151
 152 config SBUS
 153         bool
 154
 155 config STACKTRACE_SUPPORT
 156         bool
 157         default y
 158
 159 config HAVE_LATENCYTOP_SUPPORT
 160         bool
 161         depends on !SMP
 162         default y
 163
 164 config LOCKDEP_SUPPORT
 165         bool
 166         default y
 167
 168 config TRACE_IRQFLAGS_SUPPORT
 169         bool
 170         default y
 171
 172 config RWSEM_XCHGADD_ALGORITHM
 173         bool
 174         default y
 175
 176 config ARCH_HAS_ILOG2_U32
 177         bool
 178
 179 config ARCH_HAS_ILOG2_U64
 180         bool
 181
 182 config ARCH_HAS_BANDGAP
 183         bool
 184
 185 config GENERIC_HWEIGHT
 186         bool
 187         default y
 188
 189 config GENERIC_CALIBRATE_DELAY
 190         bool
 191         default y
 192
 193 config ARCH_MAY_HAVE_PC_FDC
 194         bool
 195
 196 config ZONE_DMA
 197         bool
 198
 199 config NEED_DMA_MAP_STATE
 200        def_bool y
 201
 202 config ARCH_SUPPORTS_UPROBES
 203         def_bool y
 204
 205 config ARCH_HAS_DMA_SET_COHERENT_MASK
 206         bool
 207
 208 config GENERIC_ISA_DMA
 209         bool
 210
 211 config FIQ
 212         bool
 213
 214 config NEED_RET_TO_USER
 215         bool
 216
 217 config ARCH_MTD_XIP
 218         bool
 219
 220 config VECTORS_BASE
 221         hex
 222         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 223         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 224         default 0x00000000
 225         help
 226           The base address of exception vectors.  This must be two pages
 227           in size.
 228
 229 config ARM_PATCH_PHYS_VIRT
 230         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 231         default y
 232         depends on !XIP_KERNEL && MMU
 233         depends on !ARCH_REALVIEW || !SPARSEMEM
 234         help
 235           Patch phys-to-virt and virt-to-phys translation functions at
 236           boot and module load time according to the position of the
 237           kernel in system memory.
 238
 239           This can only be used with non-XIP MMU kernels where the base
 240           of physical memory is at a 16MB boundary.
 241
 242           Only disable this option if you know that you do not require
 243           this feature (eg, building a kernel for a single machine) and
 244           you need to shrink the kernel to the minimal size.
 245
 246 config NEED_MACH_IO_H
 247         bool
 248         help
 249           Select this when mach/io.h is required to provide special
 250           definitions for this platform.  The need for mach/io.h should
 251           be avoided when possible.
 252
 253 config NEED_MACH_MEMORY_H
 254         bool
 255         help
 256           Select this when mach/memory.h is required to provide special
 257           definitions for this platform.  The need for mach/memory.h should
 258           be avoided when possible.
 259
 260 config PHYS_OFFSET
 261         hex "Physical address of main memory" if MMU
 262         depends on !ARM_PATCH_PHYS_VIRT
 263         default DRAM_BASE if !MMU
 264         default 0x00000000 if ARCH_EBSA110 || \
 265                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 266                         ARCH_FOOTBRIDGE || \
 267                         ARCH_INTEGRATOR || \
 268                         ARCH_IOP13XX || \
 269                         ARCH_KS8695 || \
 270                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 271         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 272         default 0x20000000 if ARCH_S5PV210
 273         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 274         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 275         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 276         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 277         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 278         help
 279           Please provide the physical address corresponding to the
 280           location of main memory in your system.
 281
 282 config GENERIC_BUG
 283         def_bool y
 284         depends on BUG
 285
 286 source "init/Kconfig"
 287
 288 source "kernel/Kconfig.freezer"
 289
 290 menu "System Type"
 291
 292 config MMU
 293         bool "MMU-based Paged Memory Management Support"
 294         default y
 295         help
 296           Select if you want MMU-based virtualised addressing space
 297           support by paged memory management. If unsure, say 'Y'.
 298
 299 #
 300 # The "ARM system type" choice list is ordered alphabetically by option
 301 # text.  Please add new entries in the option alphabetic order.
 302 #
 303 choice
 304         prompt "ARM system type"
 305         default ARCH_VERSATILE if !MMU
 306         default ARCH_MULTIPLATFORM if MMU
 307
 308 config ARCH_MULTIPLATFORM
 309         bool "Allow multiple platforms to be selected"
 310         depends on MMU
 311         select ARCH_WANT_OPTIONAL_GPIOLIB
 312         select ARM_HAS_SG_CHAIN
 313         select ARM_PATCH_PHYS_VIRT
 314         select AUTO_ZRELADDR
 315         select CLKSRC_OF
 316         select COMMON_CLK
 317         select GENERIC_CLOCKEVENTS
 318         select MIGHT_HAVE_PCI
 319         select MULTI_IRQ_HANDLER
 320         select SPARSE_IRQ
 321         select USE_OF
 322
 323 config ARCH_REALVIEW
 324         bool "ARM Ltd. RealView family"
 325         select ARCH_WANT_OPTIONAL_GPIOLIB
 326         select ARM_AMBA
 327         select ARM_TIMER_SP804
 328         select COMMON_CLK
 329         select COMMON_CLK_VERSATILE
 330         select GENERIC_CLOCKEVENTS
 331         select GPIO_PL061 if GPIOLIB
 332         select ICST
 333         select NEED_MACH_MEMORY_H
 334         select PLAT_VERSATILE
 335         select PLAT_VERSATILE_SCHED_CLOCK
 336         help
 337           This enables support for ARM Ltd RealView boards.
 338
 339 config ARCH_VERSATILE
 340         bool "ARM Ltd. Versatile family"
 341         select ARCH_WANT_OPTIONAL_GPIOLIB
 342         select ARM_AMBA
 343         select ARM_TIMER_SP804
 344         select ARM_VIC
 345         select CLKDEV_LOOKUP
 346         select GENERIC_CLOCKEVENTS
 347         select HAVE_MACH_CLKDEV
 348         select ICST
 349         select PLAT_VERSATILE
 350         select PLAT_VERSATILE_CLOCK
 351         select PLAT_VERSATILE_SCHED_CLOCK
 352         select VERSATILE_FPGA_IRQ
 353         help
 354           This enables support for ARM Ltd Versatile board.
 355
 356 config ARCH_AT91
 357         bool "Atmel AT91"
 358         select ARCH_REQUIRE_GPIOLIB
 359         select CLKDEV_LOOKUP
 360         select IRQ_DOMAIN
 361         select NEED_MACH_IO_H if PCCARD
 362         select PINCTRL
 363         select PINCTRL_AT91
 364         select USE_OF
 365         help
 366           This enables support for systems based on Atmel
 367           AT91RM9200, AT91SAM9 and SAMA5 processors.
 368
 369 config ARCH_CLPS711X
 370         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 371         select ARCH_REQUIRE_GPIOLIB
 372         select AUTO_ZRELADDR
 373         select CLKSRC_MMIO
 374         select COMMON_CLK
 375         select CPU_ARM720T
 376         select GENERIC_CLOCKEVENTS
 377         select MFD_SYSCON
 378         select SOC_BUS
 379         help
 380           Support for Cirrus Logic 711x/721x/731x based boards.
 381
 382 config ARCH_GEMINI
 383         bool "Cortina Systems Gemini"
 384         select ARCH_REQUIRE_GPIOLIB
 385         select CLKSRC_MMIO
 386         select CPU_FA526
 387         select GENERIC_CLOCKEVENTS
 388         help
 389           Support for the Cortina Systems Gemini family SoCs
 390
 391 config ARCH_EBSA110
 392         bool "EBSA-110"
 393         select ARCH_USES_GETTIMEOFFSET
 394         select CPU_SA110
 395         select ISA
 396         select NEED_MACH_IO_H
 397         select NEED_MACH_MEMORY_H
 398         select NO_IOPORT_MAP
 399         help
 400           This is an evaluation board for the StrongARM processor available
 401           from Digital. It has limited hardware on-board, including an
 402           Ethernet interface, two PCMCIA sockets, two serial ports and a
 403           parallel port.
 404
 405 config ARCH_EFM32
 406         bool "Energy Micro efm32"
 407         depends on !MMU
 408         select ARCH_REQUIRE_GPIOLIB
 409         select ARM_NVIC
 410         select AUTO_ZRELADDR
 411         select CLKSRC_OF
 412         select COMMON_CLK
 413         select CPU_V7M
 414         select GENERIC_CLOCKEVENTS
 415         select NO_DMA
 416         select NO_IOPORT_MAP
 417         select SPARSE_IRQ
 418         select USE_OF
 419         help
 420           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 421           processors.
 422
 423 config ARCH_EP93XX
 424         bool "EP93xx-based"
 425         select ARCH_HAS_HOLES_MEMORYMODEL
 426         select ARCH_REQUIRE_GPIOLIB
 427         select ARCH_USES_GETTIMEOFFSET
 428         select ARM_AMBA
 429         select ARM_VIC
 430         select CLKDEV_LOOKUP
 431         select CPU_ARM920T
 432         help
 433           This enables support for the Cirrus EP93xx series of CPUs.
 434
 435 config ARCH_FOOTBRIDGE
 436         bool "FootBridge"
 437         select CPU_SA110
 438         select FOOTBRIDGE
 439         select GENERIC_CLOCKEVENTS
 440         select HAVE_IDE
 441         select NEED_MACH_IO_H if !MMU
 442         select NEED_MACH_MEMORY_H
 443         help
 444           Support for systems based on the DC21285 companion chip
 445           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 446
 447 config ARCH_NETX
 448         bool "Hilscher NetX based"
 449         select ARM_VIC
 450         select CLKSRC_MMIO
 451         select CPU_ARM926T
 452         select GENERIC_CLOCKEVENTS
 453         help
 454           This enables support for systems based on the Hilscher NetX Soc
 455
 456 config ARCH_IOP13XX
 457         bool "IOP13xx-based"
 458         depends on MMU
 459         select CPU_XSC3
 460         select NEED_MACH_MEMORY_H
 461         select NEED_RET_TO_USER
 462         select PCI
 463         select PLAT_IOP
 464         select VMSPLIT_1G
 465         select SPARSE_IRQ
 466         help
 467           Support for Intel's IOP13XX (XScale) family of processors.
 468
 469 config ARCH_IOP32X
 470         bool "IOP32x-based"
 471         depends on MMU
 472         select ARCH_REQUIRE_GPIOLIB
 473         select CPU_XSCALE
 474         select GPIO_IOP
 475         select NEED_RET_TO_USER
 476         select PCI
 477         select PLAT_IOP
 478         help
 479           Support for Intel's 80219 and IOP32X (XScale) family of
 480           processors.
 481
 482 config ARCH_IOP33X
 483         bool "IOP33x-based"
 484         depends on MMU
 485         select ARCH_REQUIRE_GPIOLIB
 486         select CPU_XSCALE
 487         select GPIO_IOP
 488         select NEED_RET_TO_USER
 489         select PCI
 490         select PLAT_IOP
 491         help
 492           Support for Intel's IOP33X (XScale) family of processors.
 493
 494 config ARCH_IXP4XX
 495         bool "IXP4xx-based"
 496         depends on MMU
 497         select ARCH_HAS_DMA_SET_COHERENT_MASK
 498         select ARCH_REQUIRE_GPIOLIB
 499         select ARCH_SUPPORTS_BIG_ENDIAN
 500         select CLKSRC_MMIO
 501         select CPU_XSCALE
 502         select DMABOUNCE if PCI
 503         select GENERIC_CLOCKEVENTS
 504         select MIGHT_HAVE_PCI
 505         select NEED_MACH_IO_H
 506         select USB_EHCI_BIG_ENDIAN_DESC
 507         select USB_EHCI_BIG_ENDIAN_MMIO
 508         help
 509           Support for Intel's IXP4XX (XScale) family of processors.
 510
 511 config ARCH_DOVE
 512         bool "Marvell Dove"
 513         select ARCH_REQUIRE_GPIOLIB
 514         select CPU_PJ4
 515         select GENERIC_CLOCKEVENTS
 516         select MIGHT_HAVE_PCI
 517         select MVEBU_MBUS
 518         select PINCTRL
 519         select PINCTRL_DOVE
 520         select PLAT_ORION_LEGACY
 521         help
 522           Support for the Marvell Dove SoC 88AP510
 523
 524 config ARCH_MV78XX0
 525         bool "Marvell MV78xx0"
 526         select ARCH_REQUIRE_GPIOLIB
 527         select CPU_FEROCEON
 528         select GENERIC_CLOCKEVENTS
 529         select MVEBU_MBUS
 530         select PCI
 531         select PLAT_ORION_LEGACY
 532         help
 533           Support for the following Marvell MV78xx0 series SoCs:
 534           MV781x0, MV782x0.
 535
 536 config ARCH_ORION5X
 537         bool "Marvell Orion"
 538         depends on MMU
 539         select ARCH_REQUIRE_GPIOLIB
 540         select CPU_FEROCEON
 541         select GENERIC_CLOCKEVENTS
 542         select MVEBU_MBUS
 543         select PCI
 544         select PLAT_ORION_LEGACY
 545         help
 546           Support for the following Marvell Orion 5x series SoCs:
 547           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 548           Orion-2 (5281), Orion-1-90 (6183).
 549
 550 config ARCH_MMP
 551         bool "Marvell PXA168/910/MMP2"
 552         depends on MMU
 553         select ARCH_REQUIRE_GPIOLIB
 554         select CLKDEV_LOOKUP
 555         select GENERIC_ALLOCATOR
 556         select GENERIC_CLOCKEVENTS
 557         select GPIO_PXA
 558         select IRQ_DOMAIN
 559         select MULTI_IRQ_HANDLER
 560         select PINCTRL
 561         select PLAT_PXA
 562         select SPARSE_IRQ
 563         help
 564           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 565
 566 config ARCH_KS8695
 567         bool "Micrel/Kendin KS8695"
 568         select ARCH_REQUIRE_GPIOLIB
 569         select CLKSRC_MMIO
 570         select CPU_ARM922T
 571         select GENERIC_CLOCKEVENTS
 572         select NEED_MACH_MEMORY_H
 573         help
 574           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 575           System-on-Chip devices.
 576
 577 config ARCH_W90X900
 578         bool "Nuvoton W90X900 CPU"
 579         select ARCH_REQUIRE_GPIOLIB
 580         select CLKDEV_LOOKUP
 581         select CLKSRC_MMIO
 582         select CPU_ARM926T
 583         select GENERIC_CLOCKEVENTS
 584         help
 585           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 586           At present, the w90x900 has been renamed nuc900, regarding
 587           the ARM series product line, you can login the following
 588           link address to know more.
 589
 590           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 591                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 592
 593 config ARCH_LPC32XX
 594         bool "NXP LPC32XX"
 595         select ARCH_REQUIRE_GPIOLIB
 596         select ARM_AMBA
 597         select CLKDEV_LOOKUP
 598         select CLKSRC_MMIO
 599         select CPU_ARM926T
 600         select GENERIC_CLOCKEVENTS
 601         select HAVE_IDE
 602         select USE_OF
 603         help
 604           Support for the NXP LPC32XX family of processors
 605
 606 config ARCH_PXA
 607         bool "PXA2xx/PXA3xx-based"
 608         depends on MMU
 609         select ARCH_MTD_XIP
 610         select ARCH_REQUIRE_GPIOLIB
 611         select ARM_CPU_SUSPEND if PM
 612         select AUTO_ZRELADDR
 613         select CLKDEV_LOOKUP
 614         select CLKSRC_MMIO
 615         select CLKSRC_OF
 616         select GENERIC_CLOCKEVENTS
 617         select GPIO_PXA
 618         select HAVE_IDE
 619         select MULTI_IRQ_HANDLER
 620         select PLAT_PXA
 621         select SPARSE_IRQ
 622         help
 623           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 624
 625 config ARCH_MSM
 626         bool "Qualcomm MSM (non-multiplatform)"
 627         select ARCH_REQUIRE_GPIOLIB
 628         select COMMON_CLK
 629         select GENERIC_CLOCKEVENTS
 630         help
 631           Support for Qualcomm MSM/QSD based systems.  This runs on the
 632           apps processor of the MSM/QSD and depends on a shared memory
 633           interface to the modem processor which runs the baseband
 634           stack and controls some vital subsystems
 635           (clock and power control, etc).
 636
 637 config ARCH_SHMOBILE_LEGACY
 638         bool "Renesas ARM SoCs (non-multiplatform)"
 639         select ARCH_SHMOBILE
 640         select ARM_PATCH_PHYS_VIRT if MMU
 641         select CLKDEV_LOOKUP
 642         select CPU_V7
 643         select GENERIC_CLOCKEVENTS
 644         select HAVE_ARM_SCU if SMP
 645         select HAVE_ARM_TWD if SMP
 646         select HAVE_MACH_CLKDEV
 647         select HAVE_SMP
 648         select MIGHT_HAVE_CACHE_L2X0
 649         select MULTI_IRQ_HANDLER
 650         select NO_IOPORT_MAP
 651         select PINCTRL
 652         select PM_GENERIC_DOMAINS if PM
 653         select SH_CLK_CPG
 654         select SPARSE_IRQ
 655         help
 656           Support for Renesas ARM SoC platforms using a non-multiplatform
 657           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 658           and RZ families.
 659
 660 config ARCH_RPC
 661         bool "RiscPC"
 662         select ARCH_ACORN
 663         select ARCH_MAY_HAVE_PC_FDC
 664         select ARCH_SPARSEMEM_ENABLE
 665         select ARCH_USES_GETTIMEOFFSET
 666         select CPU_SA110
 667         select FIQ
 668         select HAVE_IDE
 669         select HAVE_PATA_PLATFORM
 670         select ISA_DMA_API
 671         select NEED_MACH_IO_H
 672         select NEED_MACH_MEMORY_H
 673         select NO_IOPORT_MAP
 674         select VIRT_TO_BUS
 675         help
 676           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 677           CD-ROM interface, serial and parallel port, and the floppy drive.
 678
 679 config ARCH_SA1100
 680         bool "SA1100-based"
 681         select ARCH_MTD_XIP
 682         select ARCH_REQUIRE_GPIOLIB
 683         select ARCH_SPARSEMEM_ENABLE
 684         select CLKDEV_LOOKUP
 685         select CLKSRC_MMIO
 686         select CPU_FREQ
 687         select CPU_SA1100
 688         select GENERIC_CLOCKEVENTS
 689         select HAVE_IDE
 690         select ISA
 691         select NEED_MACH_MEMORY_H
 692         select SPARSE_IRQ
 693         help
 694           Support for StrongARM 11x0 based boards.
 695
 696 config ARCH_S3C24XX
 697         bool "Samsung S3C24XX SoCs"
 698         select ARCH_REQUIRE_GPIOLIB
 699         select ATAGS
 700         select CLKDEV_LOOKUP
 701         select CLKSRC_SAMSUNG_PWM
 702         select GENERIC_CLOCKEVENTS
 703         select GPIO_SAMSUNG
 704         select HAVE_S3C2410_I2C if I2C
 705         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 706         select HAVE_S3C_RTC if RTC_CLASS
 707         select MULTI_IRQ_HANDLER
 708         select NEED_MACH_IO_H
 709         select SAMSUNG_ATAGS
 710         help
 711           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 712           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 713           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 714           Samsung SMDK2410 development board (and derivatives).
 715
 716 config ARCH_S3C64XX
 717         bool "Samsung S3C64XX"
 718         select ARCH_REQUIRE_GPIOLIB
 719         select ARM_AMBA
 720         select ARM_VIC
 721         select ATAGS
 722         select CLKDEV_LOOKUP
 723         select CLKSRC_SAMSUNG_PWM
 724         select COMMON_CLK_SAMSUNG
 725         select CPU_V6K
 726         select GENERIC_CLOCKEVENTS
 727         select GPIO_SAMSUNG
 728         select HAVE_S3C2410_I2C if I2C
 729         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 730         select HAVE_TCM
 731         select NO_IOPORT_MAP
 732         select PLAT_SAMSUNG
 733         select PM_GENERIC_DOMAINS if PM
 734         select S3C_DEV_NAND
 735         select S3C_GPIO_TRACK
 736         select SAMSUNG_ATAGS
 737         select SAMSUNG_WAKEMASK
 738         select SAMSUNG_WDT_RESET
 739         help
 740           Samsung S3C64XX series based systems
 741
 742 config ARCH_DAVINCI
 743         bool "TI DaVinci"
 744         select ARCH_HAS_HOLES_MEMORYMODEL
 745         select ARCH_REQUIRE_GPIOLIB
 746         select CLKDEV_LOOKUP
 747         select GENERIC_ALLOCATOR
 748         select GENERIC_CLOCKEVENTS
 749         select GENERIC_IRQ_CHIP
 750         select HAVE_IDE
 751         select TI_PRIV_EDMA
 752         select USE_OF
 753         select ZONE_DMA
 754         help
 755           Support for TI's DaVinci platform.
 756
 757 config ARCH_OMAP1
 758         bool "TI OMAP1"
 759         depends on MMU
 760         select ARCH_HAS_HOLES_MEMORYMODEL
 761         select ARCH_OMAP
 762         select ARCH_REQUIRE_GPIOLIB
 763         select CLKDEV_LOOKUP
 764         select CLKSRC_MMIO
 765         select GENERIC_CLOCKEVENTS
 766         select GENERIC_IRQ_CHIP
 767         select HAVE_IDE
 768         select IRQ_DOMAIN
 769         select NEED_MACH_IO_H if PCCARD
 770         select NEED_MACH_MEMORY_H
 771         help
 772           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 773
 774 endchoice
 775
 776 menu "Multiple platform selection"
 777         depends on ARCH_MULTIPLATFORM
 778
 779 comment "CPU Core family selection"
 780
 781 config ARCH_MULTI_V4
 782         bool "ARMv4 based platforms (FA526)"
 783         depends on !ARCH_MULTI_V6_V7
 784         select ARCH_MULTI_V4_V5
 785         select CPU_FA526
 786
 787 config ARCH_MULTI_V4T
 788         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 789         depends on !ARCH_MULTI_V6_V7
 790         select ARCH_MULTI_V4_V5
 791         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 792                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 793                 CPU_ARM925T || CPU_ARM940T)
 794
 795 config ARCH_MULTI_V5
 796         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 797         depends on !ARCH_MULTI_V6_V7
 798         select ARCH_MULTI_V4_V5
 799         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 800                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 801                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 802
 803 config ARCH_MULTI_V4_V5
 804         bool
 805
 806 config ARCH_MULTI_V6
 807         bool "ARMv6 based platforms (ARM11)"
 808         select ARCH_MULTI_V6_V7
 809         select CPU_V6K
 810
 811 config ARCH_MULTI_V7
 812         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 813         default y
 814         select ARCH_MULTI_V6_V7
 815         select CPU_V7
 816         select HAVE_SMP
 817
 818 config ARCH_MULTI_V6_V7
 819         bool
 820         select MIGHT_HAVE_CACHE_L2X0
 821
 822 config ARCH_MULTI_CPU_AUTO
 823         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 824         select ARCH_MULTI_V5
 825
 826 endmenu
 827
 828 config ARCH_VIRT
 829         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 830         select ARM_AMBA
 831         select ARM_GIC
 832         select ARM_PSCI
 833         select HAVE_ARM_ARCH_TIMER
 834
 835 #
 836 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 837 # Kconfigs may be included either alphabetically (according to the
 838 # plat- suffix) or along side the corresponding mach-* source.
 839 #
 840 source "arch/arm/mach-mvebu/Kconfig"
 841
 842 source "arch/arm/mach-asm9260/Kconfig"
 843
 844 source "arch/arm/mach-at91/Kconfig"
 845
 846 source "arch/arm/mach-axxia/Kconfig"
 847
 848 source "arch/arm/mach-bcm/Kconfig"
 849
 850 source "arch/arm/mach-berlin/Kconfig"
 851
 852 source "arch/arm/mach-clps711x/Kconfig"
 853
 854 source "arch/arm/mach-cns3xxx/Kconfig"
 855
 856 source "arch/arm/mach-davinci/Kconfig"
 857
 858 source "arch/arm/mach-dove/Kconfig"
 859
 860 source "arch/arm/mach-ep93xx/Kconfig"
 861
 862 source "arch/arm/mach-footbridge/Kconfig"
 863
 864 source "arch/arm/mach-gemini/Kconfig"
 865
 866 source "arch/arm/mach-highbank/Kconfig"
 867
 868 source "arch/arm/mach-hisi/Kconfig"
 869
 870 source "arch/arm/mach-integrator/Kconfig"
 871
 872 source "arch/arm/mach-iop32x/Kconfig"
 873
 874 source "arch/arm/mach-iop33x/Kconfig"
 875
 876 source "arch/arm/mach-iop13xx/Kconfig"
 877
 878 source "arch/arm/mach-ixp4xx/Kconfig"
 879
 880 source "arch/arm/mach-keystone/Kconfig"
 881
 882 source "arch/arm/mach-ks8695/Kconfig"
 883
 884 source "arch/arm/mach-meson/Kconfig"
 885
 886 source "arch/arm/mach-msm/Kconfig"
 887
 888 source "arch/arm/mach-moxart/Kconfig"
 889
 890 source "arch/arm/mach-mv78xx0/Kconfig"
 891
 892 source "arch/arm/mach-imx/Kconfig"
 893
 894 source "arch/arm/mach-mediatek/Kconfig"
 895
 896 source "arch/arm/mach-mxs/Kconfig"
 897
 898 source "arch/arm/mach-netx/Kconfig"
 899
 900 source "arch/arm/mach-nomadik/Kconfig"
 901
 902 source "arch/arm/mach-nspire/Kconfig"
 903
 904 source "arch/arm/plat-omap/Kconfig"
 905
 906 source "arch/arm/mach-omap1/Kconfig"
 907
 908 source "arch/arm/mach-omap2/Kconfig"
 909
 910 source "arch/arm/mach-orion5x/Kconfig"
 911
 912 source "arch/arm/mach-picoxcell/Kconfig"
 913
 914 source "arch/arm/mach-pxa/Kconfig"
 915 source "arch/arm/plat-pxa/Kconfig"
 916
 917 source "arch/arm/mach-mmp/Kconfig"
 918
 919 source "arch/arm/mach-qcom/Kconfig"
 920
 921 source "arch/arm/mach-realview/Kconfig"
 922
 923 source "arch/arm/mach-rockchip/Kconfig"
 924
 925 source "arch/arm/mach-sa1100/Kconfig"
 926
 927 source "arch/arm/mach-socfpga/Kconfig"
 928
 929 source "arch/arm/mach-spear/Kconfig"
 930
 931 source "arch/arm/mach-sti/Kconfig"
 932
 933 source "arch/arm/mach-s3c24xx/Kconfig"
 934
 935 source "arch/arm/mach-s3c64xx/Kconfig"
 936
 937 source "arch/arm/mach-s5pv210/Kconfig"
 938
 939 source "arch/arm/mach-exynos/Kconfig"
 940 source "arch/arm/plat-samsung/Kconfig"
 941
 942 source "arch/arm/mach-shmobile/Kconfig"
 943
 944 source "arch/arm/mach-sunxi/Kconfig"
 945
 946 source "arch/arm/mach-prima2/Kconfig"
 947
 948 source "arch/arm/mach-tegra/Kconfig"
 949
 950 source "arch/arm/mach-u300/Kconfig"
 951
 952 source "arch/arm/mach-ux500/Kconfig"
 953
 954 source "arch/arm/mach-versatile/Kconfig"
 955
 956 source "arch/arm/mach-vexpress/Kconfig"
 957 source "arch/arm/plat-versatile/Kconfig"
 958
 959 source "arch/arm/mach-vt8500/Kconfig"
 960
 961 source "arch/arm/mach-w90x900/Kconfig"
 962
 963 source "arch/arm/mach-zynq/Kconfig"
 964
 965 # Definitions to make life easier
 966 config ARCH_ACORN
 967         bool
 968
 969 config PLAT_IOP
 970         bool
 971         select GENERIC_CLOCKEVENTS
 972
 973 config PLAT_ORION
 974         bool
 975         select CLKSRC_MMIO
 976         select COMMON_CLK
 977         select GENERIC_IRQ_CHIP
 978         select IRQ_DOMAIN
 979
 980 config PLAT_ORION_LEGACY
 981         bool
 982         select PLAT_ORION
 983
 984 config PLAT_PXA
 985         bool
 986
 987 config PLAT_VERSATILE
 988         bool
 989
 990 config ARM_TIMER_SP804
 991         bool
 992         select CLKSRC_MMIO
 993         select CLKSRC_OF if OF
 994
 995 source "arch/arm/firmware/Kconfig"
 996
 997 source arch/arm/mm/Kconfig
 998
 999 config IWMMXT
1000         bool "Enable iWMMXt support"
1001         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1002         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1003         help
1004           Enable support for iWMMXt context switching at run time if
1005           running on a CPU that supports it.
1006
1007 config MULTI_IRQ_HANDLER
1008         bool
1009         help
1010           Allow each machine to specify it's own IRQ handler at run time.
1011
1012 if !MMU
1013 source "arch/arm/Kconfig-nommu"
1014 endif
1015
1016 config PJ4B_ERRATA_4742
1017         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1018         depends on CPU_PJ4B && MACH_ARMADA_370
1019         default y
1020         help
1021           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1022           Event (WFE) IDLE states, a specific timing sensitivity exists between
1023           the retiring WFI/WFE instructions and the newly issued subsequent
1024           instructions.  This sensitivity can result in a CPU hang scenario.
1025           Workaround:
1026           The software must insert either a Data Synchronization Barrier (DSB)
1027           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1028           instruction
1029
1030 config ARM_ERRATA_326103
1031         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1032         depends on CPU_V6
1033         help
1034           Executing a SWP instruction to read-only memory does not set bit 11
1035           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1036           treat the access as a read, preventing a COW from occurring and
1037           causing the faulting task to livelock.
1038
1039 config ARM_ERRATA_411920
1040         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1041         depends on CPU_V6 || CPU_V6K
1042         help
1043           Invalidation of the Instruction Cache operation can
1044           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1045           It does not affect the MPCore. This option enables the ARM Ltd.
1046           recommended workaround.
1047
1048 config ARM_ERRATA_430973
1049         bool "ARM errata: Stale prediction on replaced interworking branch"
1050         depends on CPU_V7
1051         help
1052           This option enables the workaround for the 430973 Cortex-A8
1053           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1054           interworking branch is replaced with another code sequence at the
1055           same virtual address, whether due to self-modifying code or virtual
1056           to physical address re-mapping, Cortex-A8 does not recover from the
1057           stale interworking branch prediction. This results in Cortex-A8
1058           executing the new code sequence in the incorrect ARM or Thumb state.
1059           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1060           and also flushes the branch target cache at every context switch.
1061           Note that setting specific bits in the ACTLR register may not be
1062           available in non-secure mode.
1063
1064 config ARM_ERRATA_458693
1065         bool "ARM errata: Processor deadlock when a false hazard is created"
1066         depends on CPU_V7
1067         depends on !ARCH_MULTIPLATFORM
1068         help
1069           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1070           erratum. For very specific sequences of memory operations, it is
1071           possible for a hazard condition intended for a cache line to instead
1072           be incorrectly associated with a different cache line. This false
1073           hazard might then cause a processor deadlock. The workaround enables
1074           the L1 caching of the NEON accesses and disables the PLD instruction
1075           in the ACTLR register. Note that setting specific bits in the ACTLR
1076           register may not be available in non-secure mode.
1077
1078 config ARM_ERRATA_460075
1079         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1080         depends on CPU_V7
1081         depends on !ARCH_MULTIPLATFORM
1082         help
1083           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1084           erratum. Any asynchronous access to the L2 cache may encounter a
1085           situation in which recent store transactions to the L2 cache are lost
1086           and overwritten with stale memory contents from external memory. The
1087           workaround disables the write-allocate mode for the L2 cache via the
1088           ACTLR register. Note that setting specific bits in the ACTLR register
1089           may not be available in non-secure mode.
1090
1091 config ARM_ERRATA_742230
1092         bool "ARM errata: DMB operation may be faulty"
1093         depends on CPU_V7 && SMP
1094         depends on !ARCH_MULTIPLATFORM
1095         help
1096           This option enables the workaround for the 742230 Cortex-A9
1097           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1098           between two write operations may not ensure the correct visibility
1099           ordering of the two writes. This workaround sets a specific bit in
1100           the diagnostic register of the Cortex-A9 which causes the DMB
1101           instruction to behave as a DSB, ensuring the correct behaviour of
1102           the two writes.
1103
1104 config ARM_ERRATA_742231
1105         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1106         depends on CPU_V7 && SMP
1107         depends on !ARCH_MULTIPLATFORM
1108         help
1109           This option enables the workaround for the 742231 Cortex-A9
1110           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1111           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1112           accessing some data located in the same cache line, may get corrupted
1113           data due to bad handling of the address hazard when the line gets
1114           replaced from one of the CPUs at the same time as another CPU is
1115           accessing it. This workaround sets specific bits in the diagnostic
1116           register of the Cortex-A9 which reduces the linefill issuing
1117           capabilities of the processor.
1118
1119 config ARM_ERRATA_643719
1120         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1121         depends on CPU_V7 && SMP
1122         help
1123           This option enables the workaround for the 643719 Cortex-A9 (prior to
1124           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1125           register returns zero when it should return one. The workaround
1126           corrects this value, ensuring cache maintenance operations which use
1127           it behave as intended and avoiding data corruption.
1128
1129 config ARM_ERRATA_720789
1130         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1131         depends on CPU_V7
1132         help
1133           This option enables the workaround for the 720789 Cortex-A9 (prior to
1134           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1135           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1136           As a consequence of this erratum, some TLB entries which should be
1137           invalidated are not, resulting in an incoherency in the system page
1138           tables. The workaround changes the TLB flushing routines to invalidate
1139           entries regardless of the ASID.
1140
1141 config ARM_ERRATA_743622
1142         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1143         depends on CPU_V7
1144         depends on !ARCH_MULTIPLATFORM
1145         help
1146           This option enables the workaround for the 743622 Cortex-A9
1147           (r2p*) erratum. Under very rare conditions, a faulty
1148           optimisation in the Cortex-A9 Store Buffer may lead to data
1149           corruption. This workaround sets a specific bit in the diagnostic
1150           register of the Cortex-A9 which disables the Store Buffer
1151           optimisation, preventing the defect from occurring. This has no
1152           visible impact on the overall performance or power consumption of the
1153           processor.
1154
1155 config ARM_ERRATA_751472
1156         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1157         depends on CPU_V7
1158         depends on !ARCH_MULTIPLATFORM
1159         help
1160           This option enables the workaround for the 751472 Cortex-A9 (prior
1161           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1162           completion of a following broadcasted operation if the second
1163           operation is received by a CPU before the ICIALLUIS has completed,
1164           potentially leading to corrupted entries in the cache or TLB.
1165
1166 config ARM_ERRATA_754322
1167         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1168         depends on CPU_V7
1169         help
1170           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1171           r3p*) erratum. A speculative memory access may cause a page table walk
1172           which starts prior to an ASID switch but completes afterwards. This
1173           can populate the micro-TLB with a stale entry which may be hit with
1174           the new ASID. This workaround places two dsb instructions in the mm
1175           switching code so that no page table walks can cross the ASID switch.
1176
1177 config ARM_ERRATA_754327
1178         bool "ARM errata: no automatic Store Buffer drain"
1179         depends on CPU_V7 && SMP
1180         help
1181           This option enables the workaround for the 754327 Cortex-A9 (prior to
1182           r2p0) erratum. The Store Buffer does not have any automatic draining
1183           mechanism and therefore a livelock may occur if an external agent
1184           continuously polls a memory location waiting to observe an update.
1185           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1186           written polling loops from denying visibility of updates to memory.
1187
1188 config ARM_ERRATA_364296
1189         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1190         depends on CPU_V6
1191         help
1192           This options enables the workaround for the 364296 ARM1136
1193           r0p2 erratum (possible cache data corruption with
1194           hit-under-miss enabled). It sets the undocumented bit 31 in
1195           the auxiliary control register and the FI bit in the control
1196           register, thus disabling hit-under-miss without putting the
1197           processor into full low interrupt latency mode. ARM11MPCore
1198           is not affected.
1199
1200 config ARM_ERRATA_764369
1201         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1202         depends on CPU_V7 && SMP
1203         help
1204           This option enables the workaround for erratum 764369
1205           affecting Cortex-A9 MPCore with two or more processors (all
1206           current revisions). Under certain timing circumstances, a data
1207           cache line maintenance operation by MVA targeting an Inner
1208           Shareable memory region may fail to proceed up to either the
1209           Point of Coherency or to the Point of Unification of the
1210           system. This workaround adds a DSB instruction before the
1211           relevant cache maintenance functions and sets a specific bit
1212           in the diagnostic control register of the SCU.
1213
1214 config ARM_ERRATA_775420
1215        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1216        depends on CPU_V7
1217        help
1218          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1219          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1220          operation aborts with MMU exception, it might cause the processor
1221          to deadlock. This workaround puts DSB before executing ISB if
1222          an abort may occur on cache maintenance.
1223
1224 config ARM_ERRATA_798181
1225         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1226         depends on CPU_V7 && SMP
1227         help
1228           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1229           adequately shooting down all use of the old entries. This
1230           option enables the Linux kernel workaround for this erratum
1231           which sends an IPI to the CPUs that are running the same ASID
1232           as the one being invalidated.
1233
1234 config ARM_ERRATA_773022
1235         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1236         depends on CPU_V7
1237         help
1238           This option enables the workaround for the 773022 Cortex-A15
1239           (up to r0p4) erratum. In certain rare sequences of code, the
1240           loop buffer may deliver incorrect instructions. This
1241           workaround disables the loop buffer to avoid the erratum.
1242
1243 endmenu
1244
1245 source "arch/arm/common/Kconfig"
1246
1247 menu "Bus support"
1248
1249 config ISA
1250         bool
1251         help
1252           Find out whether you have ISA slots on your motherboard.  ISA is the
1253           name of a bus system, i.e. the way the CPU talks to the other stuff
1254           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1255           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1256           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1257
1258 # Select ISA DMA controller support
1259 config ISA_DMA
1260         bool
1261         select ISA_DMA_API
1262
1263 # Select ISA DMA interface
1264 config ISA_DMA_API
1265         bool
1266
1267 config PCI
1268         bool "PCI support" if MIGHT_HAVE_PCI
1269         help
1270           Find out whether you have a PCI motherboard. PCI is the name of a
1271           bus system, i.e. the way the CPU talks to the other stuff inside
1272           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1273           VESA. If you have PCI, say Y, otherwise N.
1274
1275 config PCI_DOMAINS
1276         bool
1277         depends on PCI
1278
1279 config PCI_NANOENGINE
1280         bool "BSE nanoEngine PCI support"
1281         depends on SA1100_NANOENGINE
1282         help
1283           Enable PCI on the BSE nanoEngine board.
1284
1285 config PCI_SYSCALL
1286         def_bool PCI
1287
1288 config PCI_HOST_ITE8152
1289         bool
1290         depends on PCI && MACH_ARMCORE
1291         default y
1292         select DMABOUNCE
1293
1294 source "drivers/pci/Kconfig"
1295 source "drivers/pci/pcie/Kconfig"
1296
1297 source "drivers/pcmcia/Kconfig"
1298
1299 endmenu
1300
1301 menu "Kernel Features"
1302
1303 config HAVE_SMP
1304         bool
1305         help
1306           This option should be selected by machines which have an SMP-
1307           capable CPU.
1308
1309           The only effect of this option is to make the SMP-related
1310           options available to the user for configuration.
1311
1312 config SMP
1313         bool "Symmetric Multi-Processing"
1314         depends on CPU_V6K || CPU_V7
1315         depends on GENERIC_CLOCKEVENTS
1316         depends on HAVE_SMP
1317         depends on MMU || ARM_MPU
1318         help
1319           This enables support for systems with more than one CPU. If you have
1320           a system with only one CPU, say N. If you have a system with more
1321           than one CPU, say Y.
1322
1323           If you say N here, the kernel will run on uni- and multiprocessor
1324           machines, but will use only one CPU of a multiprocessor machine. If
1325           you say Y here, the kernel will run on many, but not all,
1326           uniprocessor machines. On a uniprocessor machine, the kernel
1327           will run faster if you say N here.
1328
1329           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1330           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1331           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1332
1333           If you don't know what to do here, say N.
1334
1335 config SMP_ON_UP
1336         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1337         depends on SMP && !XIP_KERNEL && MMU
1338         default y
1339         help
1340           SMP kernels contain instructions which fail on non-SMP processors.
1341           Enabling this option allows the kernel to modify itself to make
1342           these instructions safe.  Disabling it allows about 1K of space
1343           savings.
1344
1345           If you don't know what to do here, say Y.
1346
1347 config ARM_CPU_TOPOLOGY
1348         bool "Support cpu topology definition"
1349         depends on SMP && CPU_V7
1350         default y
1351         help
1352           Support ARM cpu topology definition. The MPIDR register defines
1353           affinity between processors which is then used to describe the cpu
1354           topology of an ARM System.
1355
1356 config SCHED_MC
1357         bool "Multi-core scheduler support"
1358         depends on ARM_CPU_TOPOLOGY
1359         help
1360           Multi-core scheduler support improves the CPU scheduler's decision
1361           making when dealing with multi-core CPU chips at a cost of slightly
1362           increased overhead in some places. If unsure say N here.
1363
1364 config SCHED_SMT
1365         bool "SMT scheduler support"
1366         depends on ARM_CPU_TOPOLOGY
1367         help
1368           Improves the CPU scheduler's decision making when dealing with
1369           MultiThreading at a cost of slightly increased overhead in some
1370           places. If unsure say N here.
1371
1372 config HAVE_ARM_SCU
1373         bool
1374         help
1375           This option enables support for the ARM system coherency unit
1376
1377 config HAVE_ARM_ARCH_TIMER
1378         bool "Architected timer support"
1379         depends on CPU_V7
1380         select ARM_ARCH_TIMER
1381         select GENERIC_CLOCKEVENTS
1382         help
1383           This option enables support for the ARM architected timer
1384
1385 config HAVE_ARM_TWD
1386         bool
1387         depends on SMP
1388         select CLKSRC_OF if OF
1389         help
1390           This options enables support for the ARM timer and watchdog unit
1391
1392 config MCPM
1393         bool "Multi-Cluster Power Management"
1394         depends on CPU_V7 && SMP
1395         help
1396           This option provides the common power management infrastructure
1397           for (multi-)cluster based systems, such as big.LITTLE based
1398           systems.
1399
1400 config MCPM_QUAD_CLUSTER
1401         bool
1402         depends on MCPM
1403         help
1404           To avoid wasting resources unnecessarily, MCPM only supports up
1405           to 2 clusters by default.
1406           Platforms with 3 or 4 clusters that use MCPM must select this
1407           option to allow the additional clusters to be managed.
1408
1409 config BIG_LITTLE
1410         bool "big.LITTLE support (Experimental)"
1411         depends on CPU_V7 && SMP
1412         select MCPM
1413         help
1414           This option enables support selections for the big.LITTLE
1415           system architecture.
1416
1417 config BL_SWITCHER
1418         bool "big.LITTLE switcher support"
1419         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1420         select ARM_CPU_SUSPEND
1421         select CPU_PM
1422         help
1423           The big.LITTLE "switcher" provides the core functionality to
1424           transparently handle transition between a cluster of A15's
1425           and a cluster of A7's in a big.LITTLE system.
1426
1427 config BL_SWITCHER_DUMMY_IF
1428         tristate "Simple big.LITTLE switcher user interface"
1429         depends on BL_SWITCHER && DEBUG_KERNEL
1430         help
1431           This is a simple and dummy char dev interface to control
1432           the big.LITTLE switcher core code.  It is meant for
1433           debugging purposes only.
1434
1435 choice
1436         prompt "Memory split"
1437         depends on MMU
1438         default VMSPLIT_3G
1439         help
1440           Select the desired split between kernel and user memory.
1441
1442           If you are not absolutely sure what you are doing, leave this
1443           option alone!
1444
1445         config VMSPLIT_3G
1446                 bool "3G/1G user/kernel split"
1447         config VMSPLIT_2G
1448                 bool "2G/2G user/kernel split"
1449         config VMSPLIT_1G
1450                 bool "1G/3G user/kernel split"
1451 endchoice
1452
1453 config PAGE_OFFSET
1454         hex
1455         default PHYS_OFFSET if !MMU
1456         default 0x40000000 if VMSPLIT_1G
1457         default 0x80000000 if VMSPLIT_2G
1458         default 0xC0000000
1459
1460 config NR_CPUS
1461         int "Maximum number of CPUs (2-32)"
1462         range 2 32
1463         depends on SMP
1464         default "4"
1465
1466 config HOTPLUG_CPU
1467         bool "Support for hot-pluggable CPUs"
1468         depends on SMP
1469         help
1470           Say Y here to experiment with turning CPUs off and on.  CPUs
1471           can be controlled through /sys/devices/system/cpu.
1472
1473 config ARM_PSCI
1474         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1475         depends on CPU_V7
1476         help
1477           Say Y here if you want Linux to communicate with system firmware
1478           implementing the PSCI specification for CPU-centric power
1479           management operations described in ARM document number ARM DEN
1480           0022A ("Power State Coordination Interface System Software on
1481           ARM processors").
1482
1483 # The GPIO number here must be sorted by descending number. In case of
1484 # a multiplatform kernel, we just want the highest value required by the
1485 # selected platforms.
1486 config ARCH_NR_GPIO
1487         int
1488         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1489         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1490                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1491         default 416 if ARCH_SUNXI
1492         default 392 if ARCH_U8500
1493         default 352 if ARCH_VT8500
1494         default 288 if ARCH_ROCKCHIP
1495         default 264 if MACH_H4700
1496         default 0
1497         help
1498           Maximum number of GPIOs in the system.
1499
1500           If unsure, leave the default value.
1501
1502 source kernel/Kconfig.preempt
1503
1504 config HZ_FIXED
1505         int
1506         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1507                 ARCH_S5PV210 || ARCH_EXYNOS4
1508         default AT91_TIMER_HZ if ARCH_AT91
1509         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1510         default 0
1511
1512 choice
1513         depends on HZ_FIXED = 0
1514         prompt "Timer frequency"
1515
1516 config HZ_100
1517         bool "100 Hz"
1518
1519 config HZ_200
1520         bool "200 Hz"
1521
1522 config HZ_250
1523         bool "250 Hz"
1524
1525 config HZ_300
1526         bool "300 Hz"
1527
1528 config HZ_500
1529         bool "500 Hz"
1530
1531 config HZ_1000
1532         bool "1000 Hz"
1533
1534 endchoice
1535
1536 config HZ
1537         int
1538         default HZ_FIXED if HZ_FIXED != 0
1539         default 100 if HZ_100
1540         default 200 if HZ_200
1541         default 250 if HZ_250
1542         default 300 if HZ_300
1543         default 500 if HZ_500
1544         default 1000
1545
1546 config SCHED_HRTICK
1547         def_bool HIGH_RES_TIMERS
1548
1549 config THUMB2_KERNEL
1550         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1551         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1552         default y if CPU_THUMBONLY
1553         select AEABI
1554         select ARM_ASM_UNIFIED
1555         select ARM_UNWIND
1556         help
1557           By enabling this option, the kernel will be compiled in
1558           Thumb-2 mode. A compiler/assembler that understand the unified
1559           ARM-Thumb syntax is needed.
1560
1561           If unsure, say N.
1562
1563 config THUMB2_AVOID_R_ARM_THM_JUMP11
1564         bool "Work around buggy Thumb-2 short branch relocations in gas"
1565         depends on THUMB2_KERNEL && MODULES
1566         default y
1567         help
1568           Various binutils versions can resolve Thumb-2 branches to
1569           locally-defined, preemptible global symbols as short-range "b.n"
1570           branch instructions.
1571
1572           This is a problem, because there's no guarantee the final
1573           destination of the symbol, or any candidate locations for a
1574           trampoline, are within range of the branch.  For this reason, the
1575           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1576           relocation in modules at all, and it makes little sense to add
1577           support.
1578
1579           The symptom is that the kernel fails with an "unsupported
1580           relocation" error when loading some modules.
1581
1582           Until fixed tools are available, passing
1583           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1584           code which hits this problem, at the cost of a bit of extra runtime
1585           stack usage in some cases.
1586
1587           The problem is described in more detail at:
1588               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1589
1590           Only Thumb-2 kernels are affected.
1591
1592           Unless you are sure your tools don't have this problem, say Y.
1593
1594 config ARM_ASM_UNIFIED
1595         bool
1596
1597 config AEABI
1598         bool "Use the ARM EABI to compile the kernel"
1599         help
1600           This option allows for the kernel to be compiled using the latest
1601           ARM ABI (aka EABI).  This is only useful if you are using a user
1602           space environment that is also compiled with EABI.
1603
1604           Since there are major incompatibilities between the legacy ABI and
1605           EABI, especially with regard to structure member alignment, this
1606           option also changes the kernel syscall calling convention to
1607           disambiguate both ABIs and allow for backward compatibility support
1608           (selected with CONFIG_OABI_COMPAT).
1609
1610           To use this you need GCC version 4.0.0 or later.
1611
1612 config OABI_COMPAT
1613         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1614         depends on AEABI && !THUMB2_KERNEL
1615         help
1616           This option preserves the old syscall interface along with the
1617           new (ARM EABI) one. It also provides a compatibility layer to
1618           intercept syscalls that have structure arguments which layout
1619           in memory differs between the legacy ABI and the new ARM EABI
1620           (only for non "thumb" binaries). This option adds a tiny
1621           overhead to all syscalls and produces a slightly larger kernel.
1622
1623           The seccomp filter system will not be available when this is
1624           selected, since there is no way yet to sensibly distinguish
1625           between calling conventions during filtering.
1626
1627           If you know you'll be using only pure EABI user space then you
1628           can say N here. If this option is not selected and you attempt
1629           to execute a legacy ABI binary then the result will be
1630           UNPREDICTABLE (in fact it can be predicted that it won't work
1631           at all). If in doubt say N.
1632
1633 config ARCH_HAS_HOLES_MEMORYMODEL
1634         bool
1635
1636 config ARCH_SPARSEMEM_ENABLE
1637         bool
1638
1639 config ARCH_SPARSEMEM_DEFAULT
1640         def_bool ARCH_SPARSEMEM_ENABLE
1641
1642 config ARCH_SELECT_MEMORY_MODEL
1643         def_bool ARCH_SPARSEMEM_ENABLE
1644
1645 config HAVE_ARCH_PFN_VALID
1646         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1647
1648 config HAVE_GENERIC_RCU_GUP
1649         def_bool y
1650         depends on ARM_LPAE
1651
1652 config HIGHMEM
1653         bool "High Memory Support"
1654         depends on MMU
1655         help
1656           The address space of ARM processors is only 4 Gigabytes large
1657           and it has to accommodate user address space, kernel address
1658           space as well as some memory mapped IO. That means that, if you
1659           have a large amount of physical memory and/or IO, not all of the
1660           memory can be "permanently mapped" by the kernel. The physical
1661           memory that is not permanently mapped is called "high memory".
1662
1663           Depending on the selected kernel/user memory split, minimum
1664           vmalloc space and actual amount of RAM, you may not need this
1665           option which should result in a slightly faster kernel.
1666
1667           If unsure, say n.
1668
1669 config HIGHPTE
1670         bool "Allocate 2nd-level pagetables from highmem"
1671         depends on HIGHMEM
1672
1673 config HW_PERF_EVENTS
1674         bool "Enable hardware performance counter support for perf events"
1675         depends on PERF_EVENTS
1676         default y
1677         help
1678           Enable hardware performance counter support for perf events. If
1679           disabled, perf events will use software events only.
1680
1681 config SYS_SUPPORTS_HUGETLBFS
1682        def_bool y
1683        depends on ARM_LPAE
1684
1685 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1686        def_bool y
1687        depends on ARM_LPAE
1688
1689 config ARCH_WANT_GENERAL_HUGETLB
1690         def_bool y
1691
1692 source "mm/Kconfig"
1693
1694 config FORCE_MAX_ZONEORDER
1695         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1696         range 11 64 if ARCH_SHMOBILE_LEGACY
1697         default "12" if SOC_AM33XX
1698         default "9" if SA1111 || ARCH_EFM32
1699         default "11"
1700         help
1701           The kernel memory allocator divides physically contiguous memory
1702           blocks into "zones", where each zone is a power of two number of
1703           pages.  This option selects the largest power of two that the kernel
1704           keeps in the memory allocator.  If you need to allocate very large
1705           blocks of physically contiguous memory, then you may need to
1706           increase this value.
1707
1708           This config option is actually maximum order plus one. For example,
1709           a value of 11 means that the largest free memory block is 2^10 pages.
1710
1711 config ALIGNMENT_TRAP
1712         bool
1713         depends on CPU_CP15_MMU
1714         default y if !ARCH_EBSA110
1715         select HAVE_PROC_CPU if PROC_FS
1716         help
1717           ARM processors cannot fetch/store information which is not
1718           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1719           address divisible by 4. On 32-bit ARM processors, these non-aligned
1720           fetch/store instructions will be emulated in software if you say
1721           here, which has a severe performance impact. This is necessary for
1722           correct operation of some network protocols. With an IP-only
1723           configuration it is safe to say N, otherwise say Y.
1724
1725 config UACCESS_WITH_MEMCPY
1726         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1727         depends on MMU
1728         default y if CPU_FEROCEON
1729         help
1730           Implement faster copy_to_user and clear_user methods for CPU
1731           cores where a 8-word STM instruction give significantly higher
1732           memory write throughput than a sequence of individual 32bit stores.
1733
1734           A possible side effect is a slight increase in scheduling latency
1735           between threads sharing the same address space if they invoke
1736           such copy operations with large buffers.
1737
1738           However, if the CPU data cache is using a write-allocate mode,
1739           this option is unlikely to provide any performance gain.
1740
1741 config SECCOMP
1742         bool
1743         prompt "Enable seccomp to safely compute untrusted bytecode"
1744         ---help---
1745           This kernel feature is useful for number crunching applications
1746           that may need to compute untrusted bytecode during their
1747           execution. By using pipes or other transports made available to
1748           the process as file descriptors supporting the read/write
1749           syscalls, it's possible to isolate those applications in
1750           their own address space using seccomp. Once seccomp is
1751           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1752           and the task is only allowed to execute a few safe syscalls
1753           defined by each seccomp mode.
1754
1755 config SWIOTLB
1756         def_bool y
1757
1758 config IOMMU_HELPER
1759         def_bool SWIOTLB
1760
1761 config XEN_DOM0
1762         def_bool y
1763         depends on XEN
1764
1765 config XEN
1766         bool "Xen guest support on ARM"
1767         depends on ARM && AEABI && OF
1768         depends on CPU_V7 && !CPU_V6
1769         depends on !GENERIC_ATOMIC64
1770         depends on MMU
1771         select ARCH_DMA_ADDR_T_64BIT
1772         select ARM_PSCI
1773         select SWIOTLB_XEN
1774         help
1775           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1776
1777 endmenu
1778
1779 menu "Boot options"
1780
1781 config USE_OF
1782         bool "Flattened Device Tree support"
1783         select IRQ_DOMAIN
1784         select OF
1785         select OF_EARLY_FLATTREE
1786         select OF_RESERVED_MEM
1787         help
1788           Include support for flattened device tree machine descriptions.
1789
1790 config ATAGS
1791         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1792         default y
1793         help
1794           This is the traditional way of passing data to the kernel at boot
1795           time. If you are solely relying on the flattened device tree (or
1796           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1797           to remove ATAGS support from your kernel binary.  If unsure,
1798           leave this to y.
1799
1800 config DEPRECATED_PARAM_STRUCT
1801         bool "Provide old way to pass kernel parameters"
1802         depends on ATAGS
1803         help
1804           This was deprecated in 2001 and announced to live on for 5 years.
1805           Some old boot loaders still use this way.
1806
1807 # Compressed boot loader in ROM.  Yes, we really want to ask about
1808 # TEXT and BSS so we preserve their values in the config files.
1809 config ZBOOT_ROM_TEXT
1810         hex "Compressed ROM boot loader base address"
1811         default "0"
1812         help
1813           The physical address at which the ROM-able zImage is to be
1814           placed in the target.  Platforms which normally make use of
1815           ROM-able zImage formats normally set this to a suitable
1816           value in their defconfig file.
1817
1818           If ZBOOT_ROM is not enabled, this has no effect.
1819
1820 config ZBOOT_ROM_BSS
1821         hex "Compressed ROM boot loader BSS address"
1822         default "0"
1823         help
1824           The base address of an area of read/write memory in the target
1825           for the ROM-able zImage which must be available while the
1826           decompressor is running. It must be large enough to hold the
1827           entire decompressed kernel plus an additional 128 KiB.
1828           Platforms which normally make use of ROM-able zImage formats
1829           normally set this to a suitable value in their defconfig file.
1830
1831           If ZBOOT_ROM is not enabled, this has no effect.
1832
1833 config ZBOOT_ROM
1834         bool "Compressed boot loader in ROM/flash"
1835         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1836         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1837         help
1838           Say Y here if you intend to execute your compressed kernel image
1839           (zImage) directly from ROM or flash.  If unsure, say N.
1840
1841 choice
1842         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1843         depends on ZBOOT_ROM && ARCH_SH7372
1844         default ZBOOT_ROM_NONE
1845         help
1846           Include experimental SD/MMC loading code in the ROM-able zImage.
1847           With this enabled it is possible to write the ROM-able zImage
1848           kernel image to an MMC or SD card and boot the kernel straight
1849           from the reset vector. At reset the processor Mask ROM will load
1850           the first part of the ROM-able zImage which in turn loads the
1851           rest the kernel image to RAM.
1852
1853 config ZBOOT_ROM_NONE
1854         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1855         help
1856           Do not load image from SD or MMC
1857
1858 config ZBOOT_ROM_MMCIF
1859         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1860         help
1861           Load image from MMCIF hardware block.
1862
1863 config ZBOOT_ROM_SH_MOBILE_SDHI
1864         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1865         help
1866           Load image from SDHI hardware block
1867
1868 endchoice
1869
1870 config ARM_APPENDED_DTB
1871         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1872         depends on OF
1873         help
1874           With this option, the boot code will look for a device tree binary
1875           (DTB) appended to zImage
1876           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1877
1878           This is meant as a backward compatibility convenience for those
1879           systems with a bootloader that can't be upgraded to accommodate
1880           the documented boot protocol using a device tree.
1881
1882           Beware that there is very little in terms of protection against
1883           this option being confused by leftover garbage in memory that might
1884           look like a DTB header after a reboot if no actual DTB is appended
1885           to zImage.  Do not leave this option active in a production kernel
1886           if you don't intend to always append a DTB.  Proper passing of the
1887           location into r2 of a bootloader provided DTB is always preferable
1888           to this option.
1889
1890 config ARM_ATAG_DTB_COMPAT
1891         bool "Supplement the appended DTB with traditional ATAG information"
1892         depends on ARM_APPENDED_DTB
1893         help
1894           Some old bootloaders can't be updated to a DTB capable one, yet
1895           they provide ATAGs with memory configuration, the ramdisk address,
1896           the kernel cmdline string, etc.  Such information is dynamically
1897           provided by the bootloader and can't always be stored in a static
1898           DTB.  To allow a device tree enabled kernel to be used with such
1899           bootloaders, this option allows zImage to extract the information
1900           from the ATAG list and store it at run time into the appended DTB.
1901
1902 choice
1903         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1904         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1905
1906 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1907         bool "Use bootloader kernel arguments if available"
1908         help
1909           Uses the command-line options passed by the boot loader instead of
1910           the device tree bootargs property. If the boot loader doesn't provide
1911           any, the device tree bootargs property will be used.
1912
1913 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1914         bool "Extend with bootloader kernel arguments"
1915         help
1916           The command-line arguments provided by the boot loader will be
1917           appended to the the device tree bootargs property.
1918
1919 endchoice
1920
1921 config CMDLINE
1922         string "Default kernel command string"
1923         default ""
1924         help
1925           On some architectures (EBSA110 and CATS), there is currently no way
1926           for the boot loader to pass arguments to the kernel. For these
1927           architectures, you should supply some command-line options at build
1928           time by entering them here. As a minimum, you should specify the
1929           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1930
1931 choice
1932         prompt "Kernel command line type" if CMDLINE != ""
1933         default CMDLINE_FROM_BOOTLOADER
1934         depends on ATAGS
1935
1936 config CMDLINE_FROM_BOOTLOADER
1937         bool "Use bootloader kernel arguments if available"
1938         help
1939           Uses the command-line options passed by the boot loader. If
1940           the boot loader doesn't provide any, the default kernel command
1941           string provided in CMDLINE will be used.
1942
1943 config CMDLINE_EXTEND
1944         bool "Extend bootloader kernel arguments"
1945         help
1946           The command-line arguments provided by the boot loader will be
1947           appended to the default kernel command string.
1948
1949 config CMDLINE_FORCE
1950         bool "Always use the default kernel command string"
1951         help
1952           Always use the default kernel command string, even if the boot
1953           loader passes other arguments to the kernel.
1954           This is useful if you cannot or don't want to change the
1955           command-line options your boot loader passes to the kernel.
1956 endchoice
1957
1958 config XIP_KERNEL
1959         bool "Kernel Execute-In-Place from ROM"
1960         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1961         help
1962           Execute-In-Place allows the kernel to run from non-volatile storage
1963           directly addressable by the CPU, such as NOR flash. This saves RAM
1964           space since the text section of the kernel is not loaded from flash
1965           to RAM.  Read-write sections, such as the data section and stack,
1966           are still copied to RAM.  The XIP kernel is not compressed since
1967           it has to run directly from flash, so it will take more space to
1968           store it.  The flash address used to link the kernel object files,
1969           and for storing it, is configuration dependent. Therefore, if you
1970           say Y here, you must know the proper physical address where to
1971           store the kernel image depending on your own flash memory usage.
1972
1973           Also note that the make target becomes "make xipImage" rather than
1974           "make zImage" or "make Image".  The final kernel binary to put in
1975           ROM memory will be arch/arm/boot/xipImage.
1976
1977           If unsure, say N.
1978
1979 config XIP_PHYS_ADDR
1980         hex "XIP Kernel Physical Location"
1981         depends on XIP_KERNEL
1982         default "0x00080000"
1983         help
1984           This is the physical address in your flash memory the kernel will
1985           be linked for and stored to.  This address is dependent on your
1986           own flash usage.
1987
1988 config KEXEC
1989         bool "Kexec system call (EXPERIMENTAL)"
1990         depends on (!SMP || PM_SLEEP_SMP)
1991         help
1992           kexec is a system call that implements the ability to shutdown your
1993           current kernel, and to start another kernel.  It is like a reboot
1994           but it is independent of the system firmware.   And like a reboot
1995           you can start any kernel with it, not just Linux.
1996
1997           It is an ongoing process to be certain the hardware in a machine
1998           is properly shutdown, so do not be surprised if this code does not
1999           initially work for you.
2000
2001 config ATAGS_PROC
2002         bool "Export atags in procfs"
2003         depends on ATAGS && KEXEC
2004         default y
2005         help
2006           Should the atags used to boot the kernel be exported in an "atags"
2007           file in procfs. Useful with kexec.
2008
2009 config CRASH_DUMP
2010         bool "Build kdump crash kernel (EXPERIMENTAL)"
2011         help
2012           Generate crash dump after being started by kexec. This should
2013           be normally only set in special crash dump kernels which are
2014           loaded in the main kernel with kexec-tools into a specially
2015           reserved region and then later executed after a crash by
2016           kdump/kexec. The crash dump kernel must be compiled to a
2017           memory address not used by the main kernel
2018
2019           For more details see Documentation/kdump/kdump.txt
2020
2021 config AUTO_ZRELADDR
2022         bool "Auto calculation of the decompressed kernel image address"
2023         help
2024           ZRELADDR is the physical address where the decompressed kernel
2025           image will be placed. If AUTO_ZRELADDR is selected, the address
2026           will be determined at run-time by masking the current IP with
2027           0xf8000000. This assumes the zImage being placed in the first 128MB
2028           from start of memory.
2029
2030 endmenu
2031
2032 menu "CPU Power Management"
2033
2034 source "drivers/cpufreq/Kconfig"
2035
2036 source "drivers/cpuidle/Kconfig"
2037
2038 endmenu
2039
2040 menu "Floating point emulation"
2041
2042 comment "At least one emulation must be selected"
2043
2044 config FPE_NWFPE
2045         bool "NWFPE math emulation"
2046         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2047         ---help---
2048           Say Y to include the NWFPE floating point emulator in the kernel.
2049           This is necessary to run most binaries. Linux does not currently
2050           support floating point hardware so you need to say Y here even if
2051           your machine has an FPA or floating point co-processor podule.
2052
2053           You may say N here if you are going to load the Acorn FPEmulator
2054           early in the bootup.
2055
2056 config FPE_NWFPE_XP
2057         bool "Support extended precision"
2058         depends on FPE_NWFPE
2059         help
2060           Say Y to include 80-bit support in the kernel floating-point
2061           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2062           Note that gcc does not generate 80-bit operations by default,
2063           so in most cases this option only enlarges the size of the
2064           floating point emulator without any good reason.
2065
2066           You almost surely want to say N here.
2067
2068 config FPE_FASTFPE
2069         bool "FastFPE math emulation (EXPERIMENTAL)"
2070         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2071         ---help---
2072           Say Y here to include the FAST floating point emulator in the kernel.
2073           This is an experimental much faster emulator which now also has full
2074           precision for the mantissa.  It does not support any exceptions.
2075           It is very simple, and approximately 3-6 times faster than NWFPE.
2076
2077           It should be sufficient for most programs.  It may be not suitable
2078           for scientific calculations, but you have to check this for yourself.
2079           If you do not feel you need a faster FP emulation you should better
2080           choose NWFPE.
2081
2082 config VFP
2083         bool "VFP-format floating point maths"
2084         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2085         help
2086           Say Y to include VFP support code in the kernel. This is needed
2087           if your hardware includes a VFP unit.
2088
2089           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2090           release notes and additional status information.
2091
2092           Say N if your target does not have VFP hardware.
2093
2094 config VFPv3
2095         bool
2096         depends on VFP
2097         default y if CPU_V7
2098
2099 config NEON
2100         bool "Advanced SIMD (NEON) Extension support"
2101         depends on VFPv3 && CPU_V7
2102         help
2103           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2104           Extension.
2105
2106 config KERNEL_MODE_NEON
2107         bool "Support for NEON in kernel mode"
2108         depends on NEON && AEABI
2109         help
2110           Say Y to include support for NEON in kernel mode.
2111
2112 endmenu
2113
2114 menu "Userspace binary formats"
2115
2116 source "fs/Kconfig.binfmt"
2117
2118 config ARTHUR
2119         tristate "RISC OS personality"
2120         depends on !AEABI
2121         help
2122           Say Y here to include the kernel code necessary if you want to run
2123           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2124           experimental; if this sounds frightening, say N and sleep in peace.
2125           You can also say M here to compile this support as a module (which
2126           will be called arthur).
2127
2128 endmenu
2129
2130 menu "Power management options"
2131
2132 source "kernel/power/Kconfig"
2133
2134 config ARCH_SUSPEND_POSSIBLE
2135         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2136                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2137         def_bool y
2138
2139 config ARM_CPU_SUSPEND
2140         def_bool PM_SLEEP
2141
2142 config ARCH_HIBERNATION_POSSIBLE
2143         bool
2144         depends on MMU
2145         default y if ARCH_SUSPEND_POSSIBLE
2146
2147 endmenu
2148
2149 source "net/Kconfig"
2150
2151 source "drivers/Kconfig"
2152
2153 source "fs/Kconfig"
2154
2155 source "arch/arm/Kconfig.debug"
2156
2157 source "security/Kconfig"
2158
2159 source "crypto/Kconfig"
2160
2161 source "lib/Kconfig"
2162
2163 source "arch/arm/kvm/Kconfig"