arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_MIGHT_HAVE_PC_PARPORT
   9         select ARCH_SUPPORTS_ATOMIC_RMW
  10         select ARCH_USE_BUILTIN_BSWAP
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_WANT_IPC_PARSE_VERSION
  13         select BUILDTIME_EXTABLE_SORT if MMU
  14         select CLONE_BACKWARDS
  15         select CPU_PM if (SUSPEND || CPU_IDLE)
  16         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  17         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  18         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  19         select GENERIC_IDLE_POLL_SETUP
  20         select GENERIC_IRQ_PROBE
  21         select GENERIC_IRQ_SHOW
  22         select GENERIC_PCI_IOMAP
  23         select GENERIC_SCHED_CLOCK
  24         select GENERIC_SMP_IDLE_THREAD
  25         select GENERIC_STRNCPY_FROM_USER
  26         select GENERIC_STRNLEN_USER
  27         select HARDIRQS_SW_RESEND
  28         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  29         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  30         select HAVE_ARCH_KGDB
  31         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_TRACEHOOK
  33         select HAVE_BPF_JIT
  34         select HAVE_CC_STACKPROTECTOR
  35         select HAVE_CONTEXT_TRACKING
  36         select HAVE_C_RECORDMCOUNT
  37         select HAVE_DEBUG_KMEMLEAK
  38         select HAVE_DMA_API_DEBUG
  39         select HAVE_DMA_ATTRS
  40         select HAVE_DMA_CONTIGUOUS if MMU
  41         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  42         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  43         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  44         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  45         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  46         select HAVE_GENERIC_DMA_COHERENT
  47         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  48         select HAVE_IDE if PCI || ISA || PCMCIA
  49         select HAVE_IRQ_TIME_ACCOUNTING
  50         select HAVE_KERNEL_GZIP
  51         select HAVE_KERNEL_LZ4
  52         select HAVE_KERNEL_LZMA
  53         select HAVE_KERNEL_LZO
  54         select HAVE_KERNEL_XZ
  55         select HAVE_KPROBES if !XIP_KERNEL
  56         select HAVE_KRETPROBES if (HAVE_KPROBES)
  57         select HAVE_MEMBLOCK
  58         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  59         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  60         select HAVE_PERF_EVENTS
  61         select HAVE_PERF_REGS
  62         select HAVE_PERF_USER_STACK_DUMP
  63         select HAVE_REGS_AND_STACK_ACCESS_API
  64         select HAVE_SYSCALL_TRACEPOINTS
  65         select HAVE_UID16
  66         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  67         select IRQ_FORCED_THREADING
  68         select MODULES_USE_ELF_REL
  69         select NO_BOOTMEM
  70         select OLD_SIGACTION
  71         select OLD_SIGSUSPEND3
  72         select PERF_USE_VMALLOC
  73         select RTC_LIB
  74         select SYS_SUPPORTS_APM_EMULATION
  75         # Above selects are sorted alphabetically; please add new ones
  76         # according to that.  Thanks.
  77         help
  78           The ARM series is a line of low-power-consumption RISC chip designs
  79           licensed by ARM Ltd and targeted at embedded applications and
  80           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  81           manufactured, but legacy ARM-based PC hardware remains popular in
  82           Europe.  There is an ARM Linux project with a web page at
  83           <http://www.arm.linux.org.uk/>.
  84
  85 config ARM_HAS_SG_CHAIN
  86         select ARCH_HAS_SG_CHAIN
  87         bool
  88
  89 config NEED_SG_DMA_LENGTH
  90         bool
  91
  92 config ARM_DMA_USE_IOMMU
  93         bool
  94         select ARM_HAS_SG_CHAIN
  95         select NEED_SG_DMA_LENGTH
  96
  97 if ARM_DMA_USE_IOMMU
  98
  99 config ARM_DMA_IOMMU_ALIGNMENT
 100         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 101         range 4 9
 102         default 8
 103         help
 104           DMA mapping framework by default aligns all buffers to the smallest
 105           PAGE_SIZE order which is greater than or equal to the requested buffer
 106           size. This works well for buffers up to a few hundreds kilobytes, but
 107           for larger buffers it just a waste of address space. Drivers which has
 108           relatively small addressing window (like 64Mib) might run out of
 109           virtual space with just a few allocations.
 110
 111           With this parameter you can specify the maximum PAGE_SIZE order for
 112           DMA IOMMU buffers. Larger buffers will be aligned only to this
 113           specified order. The order is expressed as a power of two multiplied
 114           by the PAGE_SIZE.
 115
 116 endif
 117
 118 config MIGHT_HAVE_PCI
 119         bool
 120
 121 config SYS_SUPPORTS_APM_EMULATION
 122         bool
 123
 124 config HAVE_TCM
 125         bool
 126         select GENERIC_ALLOCATOR
 127
 128 config HAVE_PROC_CPU
 129         bool
 130
 131 config NO_IOPORT_MAP
 132         bool
 133
 134 config EISA
 135         bool
 136         ---help---
 137           The Extended Industry Standard Architecture (EISA) bus was
 138           developed as an open alternative to the IBM MicroChannel bus.
 139
 140           The EISA bus provided some of the features of the IBM MicroChannel
 141           bus while maintaining backward compatibility with cards made for
 142           the older ISA bus.  The EISA bus saw limited use between 1988 and
 143           1995 when it was made obsolete by the PCI bus.
 144
 145           Say Y here if you are building a kernel for an EISA-based machine.
 146
 147           Otherwise, say N.
 148
 149 config SBUS
 150         bool
 151
 152 config STACKTRACE_SUPPORT
 153         bool
 154         default y
 155
 156 config HAVE_LATENCYTOP_SUPPORT
 157         bool
 158         depends on !SMP
 159         default y
 160
 161 config LOCKDEP_SUPPORT
 162         bool
 163         default y
 164
 165 config TRACE_IRQFLAGS_SUPPORT
 166         bool
 167         default y
 168
 169 config RWSEM_XCHGADD_ALGORITHM
 170         bool
 171         default y
 172
 173 config ARCH_HAS_ILOG2_U32
 174         bool
 175
 176 config ARCH_HAS_ILOG2_U64
 177         bool
 178
 179 config ARCH_HAS_BANDGAP
 180         bool
 181
 182 config GENERIC_HWEIGHT
 183         bool
 184         default y
 185
 186 config GENERIC_CALIBRATE_DELAY
 187         bool
 188         default y
 189
 190 config ARCH_MAY_HAVE_PC_FDC
 191         bool
 192
 193 config ZONE_DMA
 194         bool
 195
 196 config NEED_DMA_MAP_STATE
 197        def_bool y
 198
 199 config ARCH_SUPPORTS_UPROBES
 200         def_bool y
 201
 202 config ARCH_HAS_DMA_SET_COHERENT_MASK
 203         bool
 204
 205 config GENERIC_ISA_DMA
 206         bool
 207
 208 config FIQ
 209         bool
 210
 211 config NEED_RET_TO_USER
 212         bool
 213
 214 config ARCH_MTD_XIP
 215         bool
 216
 217 config VECTORS_BASE
 218         hex
 219         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 220         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 221         default 0x00000000
 222         help
 223           The base address of exception vectors.  This must be two pages
 224           in size.
 225
 226 config ARM_PATCH_PHYS_VIRT
 227         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 228         default y
 229         depends on !XIP_KERNEL && MMU
 230         depends on !ARCH_REALVIEW || !SPARSEMEM
 231         help
 232           Patch phys-to-virt and virt-to-phys translation functions at
 233           boot and module load time according to the position of the
 234           kernel in system memory.
 235
 236           This can only be used with non-XIP MMU kernels where the base
 237           of physical memory is at a 16MB boundary.
 238
 239           Only disable this option if you know that you do not require
 240           this feature (eg, building a kernel for a single machine) and
 241           you need to shrink the kernel to the minimal size.
 242
 243 config NEED_MACH_IO_H
 244         bool
 245         help
 246           Select this when mach/io.h is required to provide special
 247           definitions for this platform.  The need for mach/io.h should
 248           be avoided when possible.
 249
 250 config NEED_MACH_MEMORY_H
 251         bool
 252         help
 253           Select this when mach/memory.h is required to provide special
 254           definitions for this platform.  The need for mach/memory.h should
 255           be avoided when possible.
 256
 257 config PHYS_OFFSET
 258         hex "Physical address of main memory" if MMU
 259         depends on !ARM_PATCH_PHYS_VIRT
 260         default DRAM_BASE if !MMU
 261         default 0x00000000 if ARCH_EBSA110 || \
 262                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 263                         ARCH_FOOTBRIDGE || \
 264                         ARCH_INTEGRATOR || \
 265                         ARCH_IOP13XX || \
 266                         ARCH_KS8695 || \
 267                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 268         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 269         default 0x20000000 if ARCH_S5PV210
 270         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 271         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 272         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 273         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 274         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 275         help
 276           Please provide the physical address corresponding to the
 277           location of main memory in your system.
 278
 279 config GENERIC_BUG
 280         def_bool y
 281         depends on BUG
 282
 283 source "init/Kconfig"
 284
 285 source "kernel/Kconfig.freezer"
 286
 287 menu "System Type"
 288
 289 config MMU
 290         bool "MMU-based Paged Memory Management Support"
 291         default y
 292         help
 293           Select if you want MMU-based virtualised addressing space
 294           support by paged memory management. If unsure, say 'Y'.
 295
 296 #
 297 # The "ARM system type" choice list is ordered alphabetically by option
 298 # text.  Please add new entries in the option alphabetic order.
 299 #
 300 choice
 301         prompt "ARM system type"
 302         default ARCH_VERSATILE if !MMU
 303         default ARCH_MULTIPLATFORM if MMU
 304
 305 config ARCH_MULTIPLATFORM
 306         bool "Allow multiple platforms to be selected"
 307         depends on MMU
 308         select ARCH_WANT_OPTIONAL_GPIOLIB
 309         select ARM_HAS_SG_CHAIN
 310         select ARM_PATCH_PHYS_VIRT
 311         select AUTO_ZRELADDR
 312         select CLKSRC_OF
 313         select COMMON_CLK
 314         select GENERIC_CLOCKEVENTS
 315         select MIGHT_HAVE_PCI
 316         select MULTI_IRQ_HANDLER
 317         select SPARSE_IRQ
 318         select USE_OF
 319
 320 config ARCH_INTEGRATOR
 321         bool "ARM Ltd. Integrator family"
 322         select ARM_AMBA
 323         select ARM_PATCH_PHYS_VIRT if MMU
 324         select AUTO_ZRELADDR
 325         select COMMON_CLK
 326         select COMMON_CLK_VERSATILE
 327         select GENERIC_CLOCKEVENTS
 328         select HAVE_TCM
 329         select ICST
 330         select MULTI_IRQ_HANDLER
 331         select PLAT_VERSATILE
 332         select SPARSE_IRQ
 333         select USE_OF
 334         select VERSATILE_FPGA_IRQ
 335         help
 336           Support for ARM's Integrator platform.
 337
 338 config ARCH_REALVIEW
 339         bool "ARM Ltd. RealView family"
 340         select ARCH_WANT_OPTIONAL_GPIOLIB
 341         select ARM_AMBA
 342         select ARM_TIMER_SP804
 343         select COMMON_CLK
 344         select COMMON_CLK_VERSATILE
 345         select GENERIC_CLOCKEVENTS
 346         select GPIO_PL061 if GPIOLIB
 347         select ICST
 348         select NEED_MACH_MEMORY_H
 349         select PLAT_VERSATILE
 350         help
 351           This enables support for ARM Ltd RealView boards.
 352
 353 config ARCH_VERSATILE
 354         bool "ARM Ltd. Versatile family"
 355         select ARCH_WANT_OPTIONAL_GPIOLIB
 356         select ARM_AMBA
 357         select ARM_TIMER_SP804
 358         select ARM_VIC
 359         select CLKDEV_LOOKUP
 360         select GENERIC_CLOCKEVENTS
 361         select HAVE_MACH_CLKDEV
 362         select ICST
 363         select PLAT_VERSATILE
 364         select PLAT_VERSATILE_CLOCK
 365         select VERSATILE_FPGA_IRQ
 366         help
 367           This enables support for ARM Ltd Versatile board.
 368
 369 config ARCH_AT91
 370         bool "Atmel AT91"
 371         select ARCH_REQUIRE_GPIOLIB
 372         select CLKDEV_LOOKUP
 373         select IRQ_DOMAIN
 374         select NEED_MACH_IO_H if PCCARD
 375         select PINCTRL
 376         select PINCTRL_AT91 if USE_OF
 377         help
 378           This enables support for systems based on Atmel
 379           AT91RM9200 and AT91SAM9* processors.
 380
 381 config ARCH_CLPS711X
 382         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 383         select ARCH_REQUIRE_GPIOLIB
 384         select AUTO_ZRELADDR
 385         select CLKSRC_MMIO
 386         select COMMON_CLK
 387         select CPU_ARM720T
 388         select GENERIC_CLOCKEVENTS
 389         select MFD_SYSCON
 390         select SOC_BUS
 391         help
 392           Support for Cirrus Logic 711x/721x/731x based boards.
 393
 394 config ARCH_GEMINI
 395         bool "Cortina Systems Gemini"
 396         select ARCH_REQUIRE_GPIOLIB
 397         select CLKSRC_MMIO
 398         select CPU_FA526
 399         select GENERIC_CLOCKEVENTS
 400         help
 401           Support for the Cortina Systems Gemini family SoCs
 402
 403 config ARCH_EBSA110
 404         bool "EBSA-110"
 405         select ARCH_USES_GETTIMEOFFSET
 406         select CPU_SA110
 407         select ISA
 408         select NEED_MACH_IO_H
 409         select NEED_MACH_MEMORY_H
 410         select NO_IOPORT_MAP
 411         help
 412           This is an evaluation board for the StrongARM processor available
 413           from Digital. It has limited hardware on-board, including an
 414           Ethernet interface, two PCMCIA sockets, two serial ports and a
 415           parallel port.
 416
 417 config ARCH_EFM32
 418         bool "Energy Micro efm32"
 419         depends on !MMU
 420         select ARCH_REQUIRE_GPIOLIB
 421         select ARM_NVIC
 422         select AUTO_ZRELADDR
 423         select CLKSRC_OF
 424         select COMMON_CLK
 425         select CPU_V7M
 426         select GENERIC_CLOCKEVENTS
 427         select NO_DMA
 428         select NO_IOPORT_MAP
 429         select SPARSE_IRQ
 430         select USE_OF
 431         help
 432           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 433           processors.
 434
 435 config ARCH_EP93XX
 436         bool "EP93xx-based"
 437         select ARCH_HAS_HOLES_MEMORYMODEL
 438         select ARCH_REQUIRE_GPIOLIB
 439         select ARCH_USES_GETTIMEOFFSET
 440         select ARM_AMBA
 441         select ARM_VIC
 442         select CLKDEV_LOOKUP
 443         select CPU_ARM920T
 444         help
 445           This enables support for the Cirrus EP93xx series of CPUs.
 446
 447 config ARCH_FOOTBRIDGE
 448         bool "FootBridge"
 449         select CPU_SA110
 450         select FOOTBRIDGE
 451         select GENERIC_CLOCKEVENTS
 452         select HAVE_IDE
 453         select NEED_MACH_IO_H if !MMU
 454         select NEED_MACH_MEMORY_H
 455         help
 456           Support for systems based on the DC21285 companion chip
 457           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 458
 459 config ARCH_NETX
 460         bool "Hilscher NetX based"
 461         select ARM_VIC
 462         select CLKSRC_MMIO
 463         select CPU_ARM926T
 464         select GENERIC_CLOCKEVENTS
 465         help
 466           This enables support for systems based on the Hilscher NetX Soc
 467
 468 config ARCH_IOP13XX
 469         bool "IOP13xx-based"
 470         depends on MMU
 471         select CPU_XSC3
 472         select NEED_MACH_MEMORY_H
 473         select NEED_RET_TO_USER
 474         select PCI
 475         select PLAT_IOP
 476         select VMSPLIT_1G
 477         select SPARSE_IRQ
 478         help
 479           Support for Intel's IOP13XX (XScale) family of processors.
 480
 481 config ARCH_IOP32X
 482         bool "IOP32x-based"
 483         depends on MMU
 484         select ARCH_REQUIRE_GPIOLIB
 485         select CPU_XSCALE
 486         select GPIO_IOP
 487         select NEED_RET_TO_USER
 488         select PCI
 489         select PLAT_IOP
 490         help
 491           Support for Intel's 80219 and IOP32X (XScale) family of
 492           processors.
 493
 494 config ARCH_IOP33X
 495         bool "IOP33x-based"
 496         depends on MMU
 497         select ARCH_REQUIRE_GPIOLIB
 498         select CPU_XSCALE
 499         select GPIO_IOP
 500         select NEED_RET_TO_USER
 501         select PCI
 502         select PLAT_IOP
 503         help
 504           Support for Intel's IOP33X (XScale) family of processors.
 505
 506 config ARCH_IXP4XX
 507         bool "IXP4xx-based"
 508         depends on MMU
 509         select ARCH_HAS_DMA_SET_COHERENT_MASK
 510         select ARCH_REQUIRE_GPIOLIB
 511         select ARCH_SUPPORTS_BIG_ENDIAN
 512         select CLKSRC_MMIO
 513         select CPU_XSCALE
 514         select DMABOUNCE if PCI
 515         select GENERIC_CLOCKEVENTS
 516         select MIGHT_HAVE_PCI
 517         select NEED_MACH_IO_H
 518         select USB_EHCI_BIG_ENDIAN_DESC
 519         select USB_EHCI_BIG_ENDIAN_MMIO
 520         help
 521           Support for Intel's IXP4XX (XScale) family of processors.
 522
 523 config ARCH_DOVE
 524         bool "Marvell Dove"
 525         select ARCH_REQUIRE_GPIOLIB
 526         select CPU_PJ4
 527         select GENERIC_CLOCKEVENTS
 528         select MIGHT_HAVE_PCI
 529         select MVEBU_MBUS
 530         select PINCTRL
 531         select PINCTRL_DOVE
 532         select PLAT_ORION_LEGACY
 533         help
 534           Support for the Marvell Dove SoC 88AP510
 535
 536 config ARCH_MV78XX0
 537         bool "Marvell MV78xx0"
 538         select ARCH_REQUIRE_GPIOLIB
 539         select CPU_FEROCEON
 540         select GENERIC_CLOCKEVENTS
 541         select MVEBU_MBUS
 542         select PCI
 543         select PLAT_ORION_LEGACY
 544         help
 545           Support for the following Marvell MV78xx0 series SoCs:
 546           MV781x0, MV782x0.
 547
 548 config ARCH_ORION5X
 549         bool "Marvell Orion"
 550         depends on MMU
 551         select ARCH_REQUIRE_GPIOLIB
 552         select CPU_FEROCEON
 553         select GENERIC_CLOCKEVENTS
 554         select MVEBU_MBUS
 555         select PCI
 556         select PLAT_ORION_LEGACY
 557         help
 558           Support for the following Marvell Orion 5x series SoCs:
 559           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 560           Orion-2 (5281), Orion-1-90 (6183).
 561
 562 config ARCH_MMP
 563         bool "Marvell PXA168/910/MMP2"
 564         depends on MMU
 565         select ARCH_REQUIRE_GPIOLIB
 566         select CLKDEV_LOOKUP
 567         select GENERIC_ALLOCATOR
 568         select GENERIC_CLOCKEVENTS
 569         select GPIO_PXA
 570         select IRQ_DOMAIN
 571         select MULTI_IRQ_HANDLER
 572         select PINCTRL
 573         select PLAT_PXA
 574         select SPARSE_IRQ
 575         help
 576           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 577
 578 config ARCH_KS8695
 579         bool "Micrel/Kendin KS8695"
 580         select ARCH_REQUIRE_GPIOLIB
 581         select CLKSRC_MMIO
 582         select CPU_ARM922T
 583         select GENERIC_CLOCKEVENTS
 584         select NEED_MACH_MEMORY_H
 585         help
 586           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 587           System-on-Chip devices.
 588
 589 config ARCH_W90X900
 590         bool "Nuvoton W90X900 CPU"
 591         select ARCH_REQUIRE_GPIOLIB
 592         select CLKDEV_LOOKUP
 593         select CLKSRC_MMIO
 594         select CPU_ARM926T
 595         select GENERIC_CLOCKEVENTS
 596         help
 597           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 598           At present, the w90x900 has been renamed nuc900, regarding
 599           the ARM series product line, you can login the following
 600           link address to know more.
 601
 602           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 603                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 604
 605 config ARCH_LPC32XX
 606         bool "NXP LPC32XX"
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_AMBA
 609         select CLKDEV_LOOKUP
 610         select CLKSRC_MMIO
 611         select CPU_ARM926T
 612         select GENERIC_CLOCKEVENTS
 613         select HAVE_IDE
 614         select USE_OF
 615         help
 616           Support for the NXP LPC32XX family of processors
 617
 618 config ARCH_PXA
 619         bool "PXA2xx/PXA3xx-based"
 620         depends on MMU
 621         select ARCH_MTD_XIP
 622         select ARCH_REQUIRE_GPIOLIB
 623         select ARM_CPU_SUSPEND if PM
 624         select AUTO_ZRELADDR
 625         select CLKDEV_LOOKUP
 626         select CLKSRC_MMIO
 627         select CLKSRC_OF
 628         select GENERIC_CLOCKEVENTS
 629         select GPIO_PXA
 630         select HAVE_IDE
 631         select MULTI_IRQ_HANDLER
 632         select PLAT_PXA
 633         select SPARSE_IRQ
 634         help
 635           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 636
 637 config ARCH_MSM
 638         bool "Qualcomm MSM (non-multiplatform)"
 639         select ARCH_REQUIRE_GPIOLIB
 640         select COMMON_CLK
 641         select GENERIC_CLOCKEVENTS
 642         help
 643           Support for Qualcomm MSM/QSD based systems.  This runs on the
 644           apps processor of the MSM/QSD and depends on a shared memory
 645           interface to the modem processor which runs the baseband
 646           stack and controls some vital subsystems
 647           (clock and power control, etc).
 648
 649 config ARCH_SHMOBILE_LEGACY
 650         bool "Renesas ARM SoCs (non-multiplatform)"
 651         select ARCH_SHMOBILE
 652         select ARM_PATCH_PHYS_VIRT if MMU
 653         select CLKDEV_LOOKUP
 654         select GENERIC_CLOCKEVENTS
 655         select HAVE_ARM_SCU if SMP
 656         select HAVE_ARM_TWD if SMP
 657         select HAVE_MACH_CLKDEV
 658         select HAVE_SMP
 659         select MIGHT_HAVE_CACHE_L2X0
 660         select MULTI_IRQ_HANDLER
 661         select NO_IOPORT_MAP
 662         select PINCTRL
 663         select PM_GENERIC_DOMAINS if PM
 664         select SPARSE_IRQ
 665         help
 666           Support for Renesas ARM SoC platforms using a non-multiplatform
 667           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 668           and RZ families.
 669
 670 config ARCH_RPC
 671         bool "RiscPC"
 672         select ARCH_ACORN
 673         select ARCH_MAY_HAVE_PC_FDC
 674         select ARCH_SPARSEMEM_ENABLE
 675         select ARCH_USES_GETTIMEOFFSET
 676         select CPU_SA110
 677         select FIQ
 678         select HAVE_IDE
 679         select HAVE_PATA_PLATFORM
 680         select ISA_DMA_API
 681         select NEED_MACH_IO_H
 682         select NEED_MACH_MEMORY_H
 683         select NO_IOPORT_MAP
 684         select VIRT_TO_BUS
 685         help
 686           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 687           CD-ROM interface, serial and parallel port, and the floppy drive.
 688
 689 config ARCH_SA1100
 690         bool "SA1100-based"
 691         select ARCH_MTD_XIP
 692         select ARCH_REQUIRE_GPIOLIB
 693         select ARCH_SPARSEMEM_ENABLE
 694         select CLKDEV_LOOKUP
 695         select CLKSRC_MMIO
 696         select CPU_FREQ
 697         select CPU_SA1100
 698         select GENERIC_CLOCKEVENTS
 699         select HAVE_IDE
 700         select ISA
 701         select NEED_MACH_MEMORY_H
 702         select SPARSE_IRQ
 703         help
 704           Support for StrongARM 11x0 based boards.
 705
 706 config ARCH_S3C24XX
 707         bool "Samsung S3C24XX SoCs"
 708         select ARCH_REQUIRE_GPIOLIB
 709         select ATAGS
 710         select CLKDEV_LOOKUP
 711         select CLKSRC_SAMSUNG_PWM
 712         select GENERIC_CLOCKEVENTS
 713         select GPIO_SAMSUNG
 714         select HAVE_S3C2410_I2C if I2C
 715         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 716         select HAVE_S3C_RTC if RTC_CLASS
 717         select MULTI_IRQ_HANDLER
 718         select NEED_MACH_IO_H
 719         select SAMSUNG_ATAGS
 720         help
 721           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 722           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 723           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 724           Samsung SMDK2410 development board (and derivatives).
 725
 726 config ARCH_S3C64XX
 727         bool "Samsung S3C64XX"
 728         select ARCH_REQUIRE_GPIOLIB
 729         select ARM_AMBA
 730         select ARM_VIC
 731         select ATAGS
 732         select CLKDEV_LOOKUP
 733         select CLKSRC_SAMSUNG_PWM
 734         select COMMON_CLK_SAMSUNG
 735         select CPU_V6K
 736         select GENERIC_CLOCKEVENTS
 737         select GPIO_SAMSUNG
 738         select HAVE_S3C2410_I2C if I2C
 739         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 740         select HAVE_TCM
 741         select NO_IOPORT_MAP
 742         select PLAT_SAMSUNG
 743         select PM_GENERIC_DOMAINS if PM
 744         select S3C_DEV_NAND
 745         select S3C_GPIO_TRACK
 746         select SAMSUNG_ATAGS
 747         select SAMSUNG_WAKEMASK
 748         select SAMSUNG_WDT_RESET
 749         help
 750           Samsung S3C64XX series based systems
 751
 752 config ARCH_DAVINCI
 753         bool "TI DaVinci"
 754         select ARCH_HAS_HOLES_MEMORYMODEL
 755         select ARCH_REQUIRE_GPIOLIB
 756         select CLKDEV_LOOKUP
 757         select GENERIC_ALLOCATOR
 758         select GENERIC_CLOCKEVENTS
 759         select GENERIC_IRQ_CHIP
 760         select HAVE_IDE
 761         select TI_PRIV_EDMA
 762         select USE_OF
 763         select ZONE_DMA
 764         help
 765           Support for TI's DaVinci platform.
 766
 767 config ARCH_OMAP1
 768         bool "TI OMAP1"
 769         depends on MMU
 770         select ARCH_HAS_HOLES_MEMORYMODEL
 771         select ARCH_OMAP
 772         select ARCH_REQUIRE_GPIOLIB
 773         select CLKDEV_LOOKUP
 774         select CLKSRC_MMIO
 775         select GENERIC_CLOCKEVENTS
 776         select GENERIC_IRQ_CHIP
 777         select HAVE_IDE
 778         select IRQ_DOMAIN
 779         select NEED_MACH_IO_H if PCCARD
 780         select NEED_MACH_MEMORY_H
 781         help
 782           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 783
 784 endchoice
 785
 786 menu "Multiple platform selection"
 787         depends on ARCH_MULTIPLATFORM
 788
 789 comment "CPU Core family selection"
 790
 791 config ARCH_MULTI_V4
 792         bool "ARMv4 based platforms (FA526)"
 793         depends on !ARCH_MULTI_V6_V7
 794         select ARCH_MULTI_V4_V5
 795         select CPU_FA526
 796
 797 config ARCH_MULTI_V4T
 798         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 799         depends on !ARCH_MULTI_V6_V7
 800         select ARCH_MULTI_V4_V5
 801         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 802                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 803                 CPU_ARM925T || CPU_ARM940T)
 804
 805 config ARCH_MULTI_V5
 806         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 807         depends on !ARCH_MULTI_V6_V7
 808         select ARCH_MULTI_V4_V5
 809         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 810                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 811                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 812
 813 config ARCH_MULTI_V4_V5
 814         bool
 815
 816 config ARCH_MULTI_V6
 817         bool "ARMv6 based platforms (ARM11)"
 818         select ARCH_MULTI_V6_V7
 819         select CPU_V6K
 820
 821 config ARCH_MULTI_V7
 822         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 823         default y
 824         select ARCH_MULTI_V6_V7
 825         select CPU_V7
 826         select HAVE_SMP
 827
 828 config ARCH_MULTI_V6_V7
 829         bool
 830         select MIGHT_HAVE_CACHE_L2X0
 831
 832 config ARCH_MULTI_CPU_AUTO
 833         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 834         select ARCH_MULTI_V5
 835
 836 endmenu
 837
 838 config ARCH_VIRT
 839         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 840         select ARM_AMBA
 841         select ARM_GIC
 842         select ARM_PSCI
 843         select HAVE_ARM_ARCH_TIMER
 844
 845 #
 846 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 847 # Kconfigs may be included either alphabetically (according to the
 848 # plat- suffix) or along side the corresponding mach-* source.
 849 #
 850 source "arch/arm/mach-mvebu/Kconfig"
 851
 852 source "arch/arm/mach-at91/Kconfig"
 853
 854 source "arch/arm/mach-axxia/Kconfig"
 855
 856 source "arch/arm/mach-bcm/Kconfig"
 857
 858 source "arch/arm/mach-berlin/Kconfig"
 859
 860 source "arch/arm/mach-clps711x/Kconfig"
 861
 862 source "arch/arm/mach-cns3xxx/Kconfig"
 863
 864 source "arch/arm/mach-davinci/Kconfig"
 865
 866 source "arch/arm/mach-dove/Kconfig"
 867
 868 source "arch/arm/mach-ep93xx/Kconfig"
 869
 870 source "arch/arm/mach-footbridge/Kconfig"
 871
 872 source "arch/arm/mach-gemini/Kconfig"
 873
 874 source "arch/arm/mach-highbank/Kconfig"
 875
 876 source "arch/arm/mach-hisi/Kconfig"
 877
 878 source "arch/arm/mach-integrator/Kconfig"
 879
 880 source "arch/arm/mach-iop32x/Kconfig"
 881
 882 source "arch/arm/mach-iop33x/Kconfig"
 883
 884 source "arch/arm/mach-iop13xx/Kconfig"
 885
 886 source "arch/arm/mach-ixp4xx/Kconfig"
 887
 888 source "arch/arm/mach-keystone/Kconfig"
 889
 890 source "arch/arm/mach-ks8695/Kconfig"
 891
 892 source "arch/arm/mach-msm/Kconfig"
 893
 894 source "arch/arm/mach-moxart/Kconfig"
 895
 896 source "arch/arm/mach-mv78xx0/Kconfig"
 897
 898 source "arch/arm/mach-imx/Kconfig"
 899
 900 source "arch/arm/mach-mediatek/Kconfig"
 901
 902 source "arch/arm/mach-mxs/Kconfig"
 903
 904 source "arch/arm/mach-netx/Kconfig"
 905
 906 source "arch/arm/mach-nomadik/Kconfig"
 907
 908 source "arch/arm/mach-nspire/Kconfig"
 909
 910 source "arch/arm/plat-omap/Kconfig"
 911
 912 source "arch/arm/mach-omap1/Kconfig"
 913
 914 source "arch/arm/mach-omap2/Kconfig"
 915
 916 source "arch/arm/mach-orion5x/Kconfig"
 917
 918 source "arch/arm/mach-picoxcell/Kconfig"
 919
 920 source "arch/arm/mach-pxa/Kconfig"
 921 source "arch/arm/plat-pxa/Kconfig"
 922
 923 source "arch/arm/mach-mmp/Kconfig"
 924
 925 source "arch/arm/mach-qcom/Kconfig"
 926
 927 source "arch/arm/mach-realview/Kconfig"
 928
 929 source "arch/arm/mach-rockchip/Kconfig"
 930
 931 source "arch/arm/mach-sa1100/Kconfig"
 932
 933 source "arch/arm/mach-socfpga/Kconfig"
 934
 935 source "arch/arm/mach-spear/Kconfig"
 936
 937 source "arch/arm/mach-sti/Kconfig"
 938
 939 source "arch/arm/mach-s3c24xx/Kconfig"
 940
 941 source "arch/arm/mach-s3c64xx/Kconfig"
 942
 943 source "arch/arm/mach-s5pv210/Kconfig"
 944
 945 source "arch/arm/mach-exynos/Kconfig"
 946 source "arch/arm/plat-samsung/Kconfig"
 947
 948 source "arch/arm/mach-shmobile/Kconfig"
 949
 950 source "arch/arm/mach-sunxi/Kconfig"
 951
 952 source "arch/arm/mach-prima2/Kconfig"
 953
 954 source "arch/arm/mach-tegra/Kconfig"
 955
 956 source "arch/arm/mach-u300/Kconfig"
 957
 958 source "arch/arm/mach-ux500/Kconfig"
 959
 960 source "arch/arm/mach-versatile/Kconfig"
 961
 962 source "arch/arm/mach-vexpress/Kconfig"
 963 source "arch/arm/plat-versatile/Kconfig"
 964
 965 source "arch/arm/mach-vt8500/Kconfig"
 966
 967 source "arch/arm/mach-w90x900/Kconfig"
 968
 969 source "arch/arm/mach-zynq/Kconfig"
 970
 971 # Definitions to make life easier
 972 config ARCH_ACORN
 973         bool
 974
 975 config PLAT_IOP
 976         bool
 977         select GENERIC_CLOCKEVENTS
 978
 979 config PLAT_ORION
 980         bool
 981         select CLKSRC_MMIO
 982         select COMMON_CLK
 983         select GENERIC_IRQ_CHIP
 984         select IRQ_DOMAIN
 985
 986 config PLAT_ORION_LEGACY
 987         bool
 988         select PLAT_ORION
 989
 990 config PLAT_PXA
 991         bool
 992
 993 config PLAT_VERSATILE
 994         bool
 995
 996 config ARM_TIMER_SP804
 997         bool
 998         select CLKSRC_MMIO
 999         select CLKSRC_OF if OF
1000
1001 source "arch/arm/firmware/Kconfig"
1002
1003 source arch/arm/mm/Kconfig
1004
1005 config IWMMXT
1006         bool "Enable iWMMXt support"
1007         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1008         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1009         help
1010           Enable support for iWMMXt context switching at run time if
1011           running on a CPU that supports it.
1012
1013 config MULTI_IRQ_HANDLER
1014         bool
1015         help
1016           Allow each machine to specify it's own IRQ handler at run time.
1017
1018 if !MMU
1019 source "arch/arm/Kconfig-nommu"
1020 endif
1021
1022 config PJ4B_ERRATA_4742
1023         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1024         depends on CPU_PJ4B && MACH_ARMADA_370
1025         default y
1026         help
1027           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1028           Event (WFE) IDLE states, a specific timing sensitivity exists between
1029           the retiring WFI/WFE instructions and the newly issued subsequent
1030           instructions.  This sensitivity can result in a CPU hang scenario.
1031           Workaround:
1032           The software must insert either a Data Synchronization Barrier (DSB)
1033           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1034           instruction
1035
1036 config ARM_ERRATA_326103
1037         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1038         depends on CPU_V6
1039         help
1040           Executing a SWP instruction to read-only memory does not set bit 11
1041           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1042           treat the access as a read, preventing a COW from occurring and
1043           causing the faulting task to livelock.
1044
1045 config ARM_ERRATA_411920
1046         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1047         depends on CPU_V6 || CPU_V6K
1048         help
1049           Invalidation of the Instruction Cache operation can
1050           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1051           It does not affect the MPCore. This option enables the ARM Ltd.
1052           recommended workaround.
1053
1054 config ARM_ERRATA_430973
1055         bool "ARM errata: Stale prediction on replaced interworking branch"
1056         depends on CPU_V7
1057         help
1058           This option enables the workaround for the 430973 Cortex-A8
1059           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1060           interworking branch is replaced with another code sequence at the
1061           same virtual address, whether due to self-modifying code or virtual
1062           to physical address re-mapping, Cortex-A8 does not recover from the
1063           stale interworking branch prediction. This results in Cortex-A8
1064           executing the new code sequence in the incorrect ARM or Thumb state.
1065           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1066           and also flushes the branch target cache at every context switch.
1067           Note that setting specific bits in the ACTLR register may not be
1068           available in non-secure mode.
1069
1070 config ARM_ERRATA_458693
1071         bool "ARM errata: Processor deadlock when a false hazard is created"
1072         depends on CPU_V7
1073         depends on !ARCH_MULTIPLATFORM
1074         help
1075           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1076           erratum. For very specific sequences of memory operations, it is
1077           possible for a hazard condition intended for a cache line to instead
1078           be incorrectly associated with a different cache line. This false
1079           hazard might then cause a processor deadlock. The workaround enables
1080           the L1 caching of the NEON accesses and disables the PLD instruction
1081           in the ACTLR register. Note that setting specific bits in the ACTLR
1082           register may not be available in non-secure mode.
1083
1084 config ARM_ERRATA_460075
1085         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1086         depends on CPU_V7
1087         depends on !ARCH_MULTIPLATFORM
1088         help
1089           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1090           erratum. Any asynchronous access to the L2 cache may encounter a
1091           situation in which recent store transactions to the L2 cache are lost
1092           and overwritten with stale memory contents from external memory. The
1093           workaround disables the write-allocate mode for the L2 cache via the
1094           ACTLR register. Note that setting specific bits in the ACTLR register
1095           may not be available in non-secure mode.
1096
1097 config ARM_ERRATA_742230
1098         bool "ARM errata: DMB operation may be faulty"
1099         depends on CPU_V7 && SMP
1100         depends on !ARCH_MULTIPLATFORM
1101         help
1102           This option enables the workaround for the 742230 Cortex-A9
1103           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1104           between two write operations may not ensure the correct visibility
1105           ordering of the two writes. This workaround sets a specific bit in
1106           the diagnostic register of the Cortex-A9 which causes the DMB
1107           instruction to behave as a DSB, ensuring the correct behaviour of
1108           the two writes.
1109
1110 config ARM_ERRATA_742231
1111         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1112         depends on CPU_V7 && SMP
1113         depends on !ARCH_MULTIPLATFORM
1114         help
1115           This option enables the workaround for the 742231 Cortex-A9
1116           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1117           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1118           accessing some data located in the same cache line, may get corrupted
1119           data due to bad handling of the address hazard when the line gets
1120           replaced from one of the CPUs at the same time as another CPU is
1121           accessing it. This workaround sets specific bits in the diagnostic
1122           register of the Cortex-A9 which reduces the linefill issuing
1123           capabilities of the processor.
1124
1125 config ARM_ERRATA_643719
1126         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1127         depends on CPU_V7 && SMP
1128         help
1129           This option enables the workaround for the 643719 Cortex-A9 (prior to
1130           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1131           register returns zero when it should return one. The workaround
1132           corrects this value, ensuring cache maintenance operations which use
1133           it behave as intended and avoiding data corruption.
1134
1135 config ARM_ERRATA_720789
1136         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1137         depends on CPU_V7
1138         help
1139           This option enables the workaround for the 720789 Cortex-A9 (prior to
1140           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1141           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1142           As a consequence of this erratum, some TLB entries which should be
1143           invalidated are not, resulting in an incoherency in the system page
1144           tables. The workaround changes the TLB flushing routines to invalidate
1145           entries regardless of the ASID.
1146
1147 config ARM_ERRATA_743622
1148         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1149         depends on CPU_V7
1150         depends on !ARCH_MULTIPLATFORM
1151         help
1152           This option enables the workaround for the 743622 Cortex-A9
1153           (r2p*) erratum. Under very rare conditions, a faulty
1154           optimisation in the Cortex-A9 Store Buffer may lead to data
1155           corruption. This workaround sets a specific bit in the diagnostic
1156           register of the Cortex-A9 which disables the Store Buffer
1157           optimisation, preventing the defect from occurring. This has no
1158           visible impact on the overall performance or power consumption of the
1159           processor.
1160
1161 config ARM_ERRATA_751472
1162         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1163         depends on CPU_V7
1164         depends on !ARCH_MULTIPLATFORM
1165         help
1166           This option enables the workaround for the 751472 Cortex-A9 (prior
1167           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1168           completion of a following broadcasted operation if the second
1169           operation is received by a CPU before the ICIALLUIS has completed,
1170           potentially leading to corrupted entries in the cache or TLB.
1171
1172 config ARM_ERRATA_754322
1173         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1174         depends on CPU_V7
1175         help
1176           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1177           r3p*) erratum. A speculative memory access may cause a page table walk
1178           which starts prior to an ASID switch but completes afterwards. This
1179           can populate the micro-TLB with a stale entry which may be hit with
1180           the new ASID. This workaround places two dsb instructions in the mm
1181           switching code so that no page table walks can cross the ASID switch.
1182
1183 config ARM_ERRATA_754327
1184         bool "ARM errata: no automatic Store Buffer drain"
1185         depends on CPU_V7 && SMP
1186         help
1187           This option enables the workaround for the 754327 Cortex-A9 (prior to
1188           r2p0) erratum. The Store Buffer does not have any automatic draining
1189           mechanism and therefore a livelock may occur if an external agent
1190           continuously polls a memory location waiting to observe an update.
1191           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1192           written polling loops from denying visibility of updates to memory.
1193
1194 config ARM_ERRATA_364296
1195         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1196         depends on CPU_V6
1197         help
1198           This options enables the workaround for the 364296 ARM1136
1199           r0p2 erratum (possible cache data corruption with
1200           hit-under-miss enabled). It sets the undocumented bit 31 in
1201           the auxiliary control register and the FI bit in the control
1202           register, thus disabling hit-under-miss without putting the
1203           processor into full low interrupt latency mode. ARM11MPCore
1204           is not affected.
1205
1206 config ARM_ERRATA_764369
1207         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1208         depends on CPU_V7 && SMP
1209         help
1210           This option enables the workaround for erratum 764369
1211           affecting Cortex-A9 MPCore with two or more processors (all
1212           current revisions). Under certain timing circumstances, a data
1213           cache line maintenance operation by MVA targeting an Inner
1214           Shareable memory region may fail to proceed up to either the
1215           Point of Coherency or to the Point of Unification of the
1216           system. This workaround adds a DSB instruction before the
1217           relevant cache maintenance functions and sets a specific bit
1218           in the diagnostic control register of the SCU.
1219
1220 config ARM_ERRATA_775420
1221        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1222        depends on CPU_V7
1223        help
1224          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1225          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1226          operation aborts with MMU exception, it might cause the processor
1227          to deadlock. This workaround puts DSB before executing ISB if
1228          an abort may occur on cache maintenance.
1229
1230 config ARM_ERRATA_798181
1231         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1232         depends on CPU_V7 && SMP
1233         help
1234           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1235           adequately shooting down all use of the old entries. This
1236           option enables the Linux kernel workaround for this erratum
1237           which sends an IPI to the CPUs that are running the same ASID
1238           as the one being invalidated.
1239
1240 config ARM_ERRATA_773022
1241         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1242         depends on CPU_V7
1243         help
1244           This option enables the workaround for the 773022 Cortex-A15
1245           (up to r0p4) erratum. In certain rare sequences of code, the
1246           loop buffer may deliver incorrect instructions. This
1247           workaround disables the loop buffer to avoid the erratum.
1248
1249 endmenu
1250
1251 source "arch/arm/common/Kconfig"
1252
1253 menu "Bus support"
1254
1255 config ARM_AMBA
1256         bool
1257
1258 config ISA
1259         bool
1260         help
1261           Find out whether you have ISA slots on your motherboard.  ISA is the
1262           name of a bus system, i.e. the way the CPU talks to the other stuff
1263           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1264           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1265           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1266
1267 # Select ISA DMA controller support
1268 config ISA_DMA
1269         bool
1270         select ISA_DMA_API
1271
1272 # Select ISA DMA interface
1273 config ISA_DMA_API
1274         bool
1275
1276 config PCI
1277         bool "PCI support" if MIGHT_HAVE_PCI
1278         help
1279           Find out whether you have a PCI motherboard. PCI is the name of a
1280           bus system, i.e. the way the CPU talks to the other stuff inside
1281           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1282           VESA. If you have PCI, say Y, otherwise N.
1283
1284 config PCI_DOMAINS
1285         bool
1286         depends on PCI
1287
1288 config PCI_NANOENGINE
1289         bool "BSE nanoEngine PCI support"
1290         depends on SA1100_NANOENGINE
1291         help
1292           Enable PCI on the BSE nanoEngine board.
1293
1294 config PCI_SYSCALL
1295         def_bool PCI
1296
1297 config PCI_HOST_ITE8152
1298         bool
1299         depends on PCI && MACH_ARMCORE
1300         default y
1301         select DMABOUNCE
1302
1303 source "drivers/pci/Kconfig"
1304 source "drivers/pci/pcie/Kconfig"
1305
1306 source "drivers/pcmcia/Kconfig"
1307
1308 endmenu
1309
1310 menu "Kernel Features"
1311
1312 config HAVE_SMP
1313         bool
1314         help
1315           This option should be selected by machines which have an SMP-
1316           capable CPU.
1317
1318           The only effect of this option is to make the SMP-related
1319           options available to the user for configuration.
1320
1321 config SMP
1322         bool "Symmetric Multi-Processing"
1323         depends on CPU_V6K || CPU_V7
1324         depends on GENERIC_CLOCKEVENTS
1325         depends on HAVE_SMP
1326         depends on MMU || ARM_MPU
1327         help
1328           This enables support for systems with more than one CPU. If you have
1329           a system with only one CPU, say N. If you have a system with more
1330           than one CPU, say Y.
1331
1332           If you say N here, the kernel will run on uni- and multiprocessor
1333           machines, but will use only one CPU of a multiprocessor machine. If
1334           you say Y here, the kernel will run on many, but not all,
1335           uniprocessor machines. On a uniprocessor machine, the kernel
1336           will run faster if you say N here.
1337
1338           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1339           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1340           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1341
1342           If you don't know what to do here, say N.
1343
1344 config SMP_ON_UP
1345         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1346         depends on SMP && !XIP_KERNEL && MMU
1347         default y
1348         help
1349           SMP kernels contain instructions which fail on non-SMP processors.
1350           Enabling this option allows the kernel to modify itself to make
1351           these instructions safe.  Disabling it allows about 1K of space
1352           savings.
1353
1354           If you don't know what to do here, say Y.
1355
1356 config ARM_CPU_TOPOLOGY
1357         bool "Support cpu topology definition"
1358         depends on SMP && CPU_V7
1359         default y
1360         help
1361           Support ARM cpu topology definition. The MPIDR register defines
1362           affinity between processors which is then used to describe the cpu
1363           topology of an ARM System.
1364
1365 config SCHED_MC
1366         bool "Multi-core scheduler support"
1367         depends on ARM_CPU_TOPOLOGY
1368         help
1369           Multi-core scheduler support improves the CPU scheduler's decision
1370           making when dealing with multi-core CPU chips at a cost of slightly
1371           increased overhead in some places. If unsure say N here.
1372
1373 config SCHED_SMT
1374         bool "SMT scheduler support"
1375         depends on ARM_CPU_TOPOLOGY
1376         help
1377           Improves the CPU scheduler's decision making when dealing with
1378           MultiThreading at a cost of slightly increased overhead in some
1379           places. If unsure say N here.
1380
1381 config HAVE_ARM_SCU
1382         bool
1383         help
1384           This option enables support for the ARM system coherency unit
1385
1386 config HAVE_ARM_ARCH_TIMER
1387         bool "Architected timer support"
1388         depends on CPU_V7
1389         select ARM_ARCH_TIMER
1390         select GENERIC_CLOCKEVENTS
1391         help
1392           This option enables support for the ARM architected timer
1393
1394 config HAVE_ARM_TWD
1395         bool
1396         depends on SMP
1397         select CLKSRC_OF if OF
1398         help
1399           This options enables support for the ARM timer and watchdog unit
1400
1401 config MCPM
1402         bool "Multi-Cluster Power Management"
1403         depends on CPU_V7 && SMP
1404         help
1405           This option provides the common power management infrastructure
1406           for (multi-)cluster based systems, such as big.LITTLE based
1407           systems.
1408
1409 config MCPM_QUAD_CLUSTER
1410         bool
1411         depends on MCPM
1412         help
1413           To avoid wasting resources unnecessarily, MCPM only supports up
1414           to 2 clusters by default.
1415           Platforms with 3 or 4 clusters that use MCPM must select this
1416           option to allow the additional clusters to be managed.
1417
1418 config BIG_LITTLE
1419         bool "big.LITTLE support (Experimental)"
1420         depends on CPU_V7 && SMP
1421         select MCPM
1422         help
1423           This option enables support selections for the big.LITTLE
1424           system architecture.
1425
1426 config BL_SWITCHER
1427         bool "big.LITTLE switcher support"
1428         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1429         select ARM_CPU_SUSPEND
1430         select CPU_PM
1431         help
1432           The big.LITTLE "switcher" provides the core functionality to
1433           transparently handle transition between a cluster of A15's
1434           and a cluster of A7's in a big.LITTLE system.
1435
1436 config BL_SWITCHER_DUMMY_IF
1437         tristate "Simple big.LITTLE switcher user interface"
1438         depends on BL_SWITCHER && DEBUG_KERNEL
1439         help
1440           This is a simple and dummy char dev interface to control
1441           the big.LITTLE switcher core code.  It is meant for
1442           debugging purposes only.
1443
1444 choice
1445         prompt "Memory split"
1446         depends on MMU
1447         default VMSPLIT_3G
1448         help
1449           Select the desired split between kernel and user memory.
1450
1451           If you are not absolutely sure what you are doing, leave this
1452           option alone!
1453
1454         config VMSPLIT_3G
1455                 bool "3G/1G user/kernel split"
1456         config VMSPLIT_2G
1457                 bool "2G/2G user/kernel split"
1458         config VMSPLIT_1G
1459                 bool "1G/3G user/kernel split"
1460 endchoice
1461
1462 config PAGE_OFFSET
1463         hex
1464         default PHYS_OFFSET if !MMU
1465         default 0x40000000 if VMSPLIT_1G
1466         default 0x80000000 if VMSPLIT_2G
1467         default 0xC0000000
1468
1469 config NR_CPUS
1470         int "Maximum number of CPUs (2-32)"
1471         range 2 32
1472         depends on SMP
1473         default "4"
1474
1475 config HOTPLUG_CPU
1476         bool "Support for hot-pluggable CPUs"
1477         depends on SMP
1478         help
1479           Say Y here to experiment with turning CPUs off and on.  CPUs
1480           can be controlled through /sys/devices/system/cpu.
1481
1482 config ARM_PSCI
1483         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1484         depends on CPU_V7
1485         help
1486           Say Y here if you want Linux to communicate with system firmware
1487           implementing the PSCI specification for CPU-centric power
1488           management operations described in ARM document number ARM DEN
1489           0022A ("Power State Coordination Interface System Software on
1490           ARM processors").
1491
1492 # The GPIO number here must be sorted by descending number. In case of
1493 # a multiplatform kernel, we just want the highest value required by the
1494 # selected platforms.
1495 config ARCH_NR_GPIO
1496         int
1497         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1498         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1499                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1500         default 416 if ARCH_SUNXI
1501         default 392 if ARCH_U8500
1502         default 352 if ARCH_VT8500
1503         default 288 if ARCH_ROCKCHIP
1504         default 264 if MACH_H4700
1505         default 0
1506         help
1507           Maximum number of GPIOs in the system.
1508
1509           If unsure, leave the default value.
1510
1511 source kernel/Kconfig.preempt
1512
1513 config HZ_FIXED
1514         int
1515         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1516                 ARCH_S5PV210 || ARCH_EXYNOS4
1517         default AT91_TIMER_HZ if ARCH_AT91
1518         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1519         default 0
1520
1521 choice
1522         depends on HZ_FIXED = 0
1523         prompt "Timer frequency"
1524
1525 config HZ_100
1526         bool "100 Hz"
1527
1528 config HZ_200
1529         bool "200 Hz"
1530
1531 config HZ_250
1532         bool "250 Hz"
1533
1534 config HZ_300
1535         bool "300 Hz"
1536
1537 config HZ_500
1538         bool "500 Hz"
1539
1540 config HZ_1000
1541         bool "1000 Hz"
1542
1543 endchoice
1544
1545 config HZ
1546         int
1547         default HZ_FIXED if HZ_FIXED != 0
1548         default 100 if HZ_100
1549         default 200 if HZ_200
1550         default 250 if HZ_250
1551         default 300 if HZ_300
1552         default 500 if HZ_500
1553         default 1000
1554
1555 config SCHED_HRTICK
1556         def_bool HIGH_RES_TIMERS
1557
1558 config THUMB2_KERNEL
1559         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1560         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1561         default y if CPU_THUMBONLY
1562         select AEABI
1563         select ARM_ASM_UNIFIED
1564         select ARM_UNWIND
1565         help
1566           By enabling this option, the kernel will be compiled in
1567           Thumb-2 mode. A compiler/assembler that understand the unified
1568           ARM-Thumb syntax is needed.
1569
1570           If unsure, say N.
1571
1572 config THUMB2_AVOID_R_ARM_THM_JUMP11
1573         bool "Work around buggy Thumb-2 short branch relocations in gas"
1574         depends on THUMB2_KERNEL && MODULES
1575         default y
1576         help
1577           Various binutils versions can resolve Thumb-2 branches to
1578           locally-defined, preemptible global symbols as short-range "b.n"
1579           branch instructions.
1580
1581           This is a problem, because there's no guarantee the final
1582           destination of the symbol, or any candidate locations for a
1583           trampoline, are within range of the branch.  For this reason, the
1584           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1585           relocation in modules at all, and it makes little sense to add
1586           support.
1587
1588           The symptom is that the kernel fails with an "unsupported
1589           relocation" error when loading some modules.
1590
1591           Until fixed tools are available, passing
1592           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1593           code which hits this problem, at the cost of a bit of extra runtime
1594           stack usage in some cases.
1595
1596           The problem is described in more detail at:
1597               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1598
1599           Only Thumb-2 kernels are affected.
1600
1601           Unless you are sure your tools don't have this problem, say Y.
1602
1603 config ARM_ASM_UNIFIED
1604         bool
1605
1606 config AEABI
1607         bool "Use the ARM EABI to compile the kernel"
1608         help
1609           This option allows for the kernel to be compiled using the latest
1610           ARM ABI (aka EABI).  This is only useful if you are using a user
1611           space environment that is also compiled with EABI.
1612
1613           Since there are major incompatibilities between the legacy ABI and
1614           EABI, especially with regard to structure member alignment, this
1615           option also changes the kernel syscall calling convention to
1616           disambiguate both ABIs and allow for backward compatibility support
1617           (selected with CONFIG_OABI_COMPAT).
1618
1619           To use this you need GCC version 4.0.0 or later.
1620
1621 config OABI_COMPAT
1622         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1623         depends on AEABI && !THUMB2_KERNEL
1624         help
1625           This option preserves the old syscall interface along with the
1626           new (ARM EABI) one. It also provides a compatibility layer to
1627           intercept syscalls that have structure arguments which layout
1628           in memory differs between the legacy ABI and the new ARM EABI
1629           (only for non "thumb" binaries). This option adds a tiny
1630           overhead to all syscalls and produces a slightly larger kernel.
1631
1632           The seccomp filter system will not be available when this is
1633           selected, since there is no way yet to sensibly distinguish
1634           between calling conventions during filtering.
1635
1636           If you know you'll be using only pure EABI user space then you
1637           can say N here. If this option is not selected and you attempt
1638           to execute a legacy ABI binary then the result will be
1639           UNPREDICTABLE (in fact it can be predicted that it won't work
1640           at all). If in doubt say N.
1641
1642 config ARCH_HAS_HOLES_MEMORYMODEL
1643         bool
1644
1645 config ARCH_SPARSEMEM_ENABLE
1646         bool
1647
1648 config ARCH_SPARSEMEM_DEFAULT
1649         def_bool ARCH_SPARSEMEM_ENABLE
1650
1651 config ARCH_SELECT_MEMORY_MODEL
1652         def_bool ARCH_SPARSEMEM_ENABLE
1653
1654 config HAVE_ARCH_PFN_VALID
1655         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1656
1657 config HIGHMEM
1658         bool "High Memory Support"
1659         depends on MMU
1660         help
1661           The address space of ARM processors is only 4 Gigabytes large
1662           and it has to accommodate user address space, kernel address
1663           space as well as some memory mapped IO. That means that, if you
1664           have a large amount of physical memory and/or IO, not all of the
1665           memory can be "permanently mapped" by the kernel. The physical
1666           memory that is not permanently mapped is called "high memory".
1667
1668           Depending on the selected kernel/user memory split, minimum
1669           vmalloc space and actual amount of RAM, you may not need this
1670           option which should result in a slightly faster kernel.
1671
1672           If unsure, say n.
1673
1674 config HIGHPTE
1675         bool "Allocate 2nd-level pagetables from highmem"
1676         depends on HIGHMEM
1677
1678 config HW_PERF_EVENTS
1679         bool "Enable hardware performance counter support for perf events"
1680         depends on PERF_EVENTS
1681         default y
1682         help
1683           Enable hardware performance counter support for perf events. If
1684           disabled, perf events will use software events only.
1685
1686 config SYS_SUPPORTS_HUGETLBFS
1687        def_bool y
1688        depends on ARM_LPAE
1689
1690 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1691        def_bool y
1692        depends on ARM_LPAE
1693
1694 config ARCH_WANT_GENERAL_HUGETLB
1695         def_bool y
1696
1697 source "mm/Kconfig"
1698
1699 config FORCE_MAX_ZONEORDER
1700         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1701         range 11 64 if ARCH_SHMOBILE_LEGACY
1702         default "12" if SOC_AM33XX
1703         default "9" if SA1111 || ARCH_EFM32
1704         default "11"
1705         help
1706           The kernel memory allocator divides physically contiguous memory
1707           blocks into "zones", where each zone is a power of two number of
1708           pages.  This option selects the largest power of two that the kernel
1709           keeps in the memory allocator.  If you need to allocate very large
1710           blocks of physically contiguous memory, then you may need to
1711           increase this value.
1712
1713           This config option is actually maximum order plus one. For example,
1714           a value of 11 means that the largest free memory block is 2^10 pages.
1715
1716 config ALIGNMENT_TRAP
1717         bool
1718         depends on CPU_CP15_MMU
1719         default y if !ARCH_EBSA110
1720         select HAVE_PROC_CPU if PROC_FS
1721         help
1722           ARM processors cannot fetch/store information which is not
1723           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1724           address divisible by 4. On 32-bit ARM processors, these non-aligned
1725           fetch/store instructions will be emulated in software if you say
1726           here, which has a severe performance impact. This is necessary for
1727           correct operation of some network protocols. With an IP-only
1728           configuration it is safe to say N, otherwise say Y.
1729
1730 config UACCESS_WITH_MEMCPY
1731         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1732         depends on MMU
1733         default y if CPU_FEROCEON
1734         help
1735           Implement faster copy_to_user and clear_user methods for CPU
1736           cores where a 8-word STM instruction give significantly higher
1737           memory write throughput than a sequence of individual 32bit stores.
1738
1739           A possible side effect is a slight increase in scheduling latency
1740           between threads sharing the same address space if they invoke
1741           such copy operations with large buffers.
1742
1743           However, if the CPU data cache is using a write-allocate mode,
1744           this option is unlikely to provide any performance gain.
1745
1746 config SECCOMP
1747         bool
1748         prompt "Enable seccomp to safely compute untrusted bytecode"
1749         ---help---
1750           This kernel feature is useful for number crunching applications
1751           that may need to compute untrusted bytecode during their
1752           execution. By using pipes or other transports made available to
1753           the process as file descriptors supporting the read/write
1754           syscalls, it's possible to isolate those applications in
1755           their own address space using seccomp. Once seccomp is
1756           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1757           and the task is only allowed to execute a few safe syscalls
1758           defined by each seccomp mode.
1759
1760 config SWIOTLB
1761         def_bool y
1762
1763 config IOMMU_HELPER
1764         def_bool SWIOTLB
1765
1766 config XEN_DOM0
1767         def_bool y
1768         depends on XEN
1769
1770 config XEN
1771         bool "Xen guest support on ARM (EXPERIMENTAL)"
1772         depends on ARM && AEABI && OF
1773         depends on CPU_V7 && !CPU_V6
1774         depends on !GENERIC_ATOMIC64
1775         depends on MMU
1776         select ARCH_DMA_ADDR_T_64BIT
1777         select ARM_PSCI
1778         select SWIOTLB_XEN
1779         help
1780           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1781
1782 endmenu
1783
1784 menu "Boot options"
1785
1786 config USE_OF
1787         bool "Flattened Device Tree support"
1788         select IRQ_DOMAIN
1789         select OF
1790         select OF_EARLY_FLATTREE
1791         select OF_RESERVED_MEM
1792         help
1793           Include support for flattened device tree machine descriptions.
1794
1795 config ATAGS
1796         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1797         default y
1798         help
1799           This is the traditional way of passing data to the kernel at boot
1800           time. If you are solely relying on the flattened device tree (or
1801           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1802           to remove ATAGS support from your kernel binary.  If unsure,
1803           leave this to y.
1804
1805 config DEPRECATED_PARAM_STRUCT
1806         bool "Provide old way to pass kernel parameters"
1807         depends on ATAGS
1808         help
1809           This was deprecated in 2001 and announced to live on for 5 years.
1810           Some old boot loaders still use this way.
1811
1812 # Compressed boot loader in ROM.  Yes, we really want to ask about
1813 # TEXT and BSS so we preserve their values in the config files.
1814 config ZBOOT_ROM_TEXT
1815         hex "Compressed ROM boot loader base address"
1816         default "0"
1817         help
1818           The physical address at which the ROM-able zImage is to be
1819           placed in the target.  Platforms which normally make use of
1820           ROM-able zImage formats normally set this to a suitable
1821           value in their defconfig file.
1822
1823           If ZBOOT_ROM is not enabled, this has no effect.
1824
1825 config ZBOOT_ROM_BSS
1826         hex "Compressed ROM boot loader BSS address"
1827         default "0"
1828         help
1829           The base address of an area of read/write memory in the target
1830           for the ROM-able zImage which must be available while the
1831           decompressor is running. It must be large enough to hold the
1832           entire decompressed kernel plus an additional 128 KiB.
1833           Platforms which normally make use of ROM-able zImage formats
1834           normally set this to a suitable value in their defconfig file.
1835
1836           If ZBOOT_ROM is not enabled, this has no effect.
1837
1838 config ZBOOT_ROM
1839         bool "Compressed boot loader in ROM/flash"
1840         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1841         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1842         help
1843           Say Y here if you intend to execute your compressed kernel image
1844           (zImage) directly from ROM or flash.  If unsure, say N.
1845
1846 choice
1847         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1848         depends on ZBOOT_ROM && ARCH_SH7372
1849         default ZBOOT_ROM_NONE
1850         help
1851           Include experimental SD/MMC loading code in the ROM-able zImage.
1852           With this enabled it is possible to write the ROM-able zImage
1853           kernel image to an MMC or SD card and boot the kernel straight
1854           from the reset vector. At reset the processor Mask ROM will load
1855           the first part of the ROM-able zImage which in turn loads the
1856           rest the kernel image to RAM.
1857
1858 config ZBOOT_ROM_NONE
1859         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1860         help
1861           Do not load image from SD or MMC
1862
1863 config ZBOOT_ROM_MMCIF
1864         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1865         help
1866           Load image from MMCIF hardware block.
1867
1868 config ZBOOT_ROM_SH_MOBILE_SDHI
1869         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1870         help
1871           Load image from SDHI hardware block
1872
1873 endchoice
1874
1875 config ARM_APPENDED_DTB
1876         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1877         depends on OF
1878         help
1879           With this option, the boot code will look for a device tree binary
1880           (DTB) appended to zImage
1881           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1882
1883           This is meant as a backward compatibility convenience for those
1884           systems with a bootloader that can't be upgraded to accommodate
1885           the documented boot protocol using a device tree.
1886
1887           Beware that there is very little in terms of protection against
1888           this option being confused by leftover garbage in memory that might
1889           look like a DTB header after a reboot if no actual DTB is appended
1890           to zImage.  Do not leave this option active in a production kernel
1891           if you don't intend to always append a DTB.  Proper passing of the
1892           location into r2 of a bootloader provided DTB is always preferable
1893           to this option.
1894
1895 config ARM_ATAG_DTB_COMPAT
1896         bool "Supplement the appended DTB with traditional ATAG information"
1897         depends on ARM_APPENDED_DTB
1898         help
1899           Some old bootloaders can't be updated to a DTB capable one, yet
1900           they provide ATAGs with memory configuration, the ramdisk address,
1901           the kernel cmdline string, etc.  Such information is dynamically
1902           provided by the bootloader and can't always be stored in a static
1903           DTB.  To allow a device tree enabled kernel to be used with such
1904           bootloaders, this option allows zImage to extract the information
1905           from the ATAG list and store it at run time into the appended DTB.
1906
1907 choice
1908         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1909         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1910
1911 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1912         bool "Use bootloader kernel arguments if available"
1913         help
1914           Uses the command-line options passed by the boot loader instead of
1915           the device tree bootargs property. If the boot loader doesn't provide
1916           any, the device tree bootargs property will be used.
1917
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1919         bool "Extend with bootloader kernel arguments"
1920         help
1921           The command-line arguments provided by the boot loader will be
1922           appended to the the device tree bootargs property.
1923
1924 endchoice
1925
1926 config CMDLINE
1927         string "Default kernel command string"
1928         default ""
1929         help
1930           On some architectures (EBSA110 and CATS), there is currently no way
1931           for the boot loader to pass arguments to the kernel. For these
1932           architectures, you should supply some command-line options at build
1933           time by entering them here. As a minimum, you should specify the
1934           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1935
1936 choice
1937         prompt "Kernel command line type" if CMDLINE != ""
1938         default CMDLINE_FROM_BOOTLOADER
1939         depends on ATAGS
1940
1941 config CMDLINE_FROM_BOOTLOADER
1942         bool "Use bootloader kernel arguments if available"
1943         help
1944           Uses the command-line options passed by the boot loader. If
1945           the boot loader doesn't provide any, the default kernel command
1946           string provided in CMDLINE will be used.
1947
1948 config CMDLINE_EXTEND
1949         bool "Extend bootloader kernel arguments"
1950         help
1951           The command-line arguments provided by the boot loader will be
1952           appended to the default kernel command string.
1953
1954 config CMDLINE_FORCE
1955         bool "Always use the default kernel command string"
1956         help
1957           Always use the default kernel command string, even if the boot
1958           loader passes other arguments to the kernel.
1959           This is useful if you cannot or don't want to change the
1960           command-line options your boot loader passes to the kernel.
1961 endchoice
1962
1963 config XIP_KERNEL
1964         bool "Kernel Execute-In-Place from ROM"
1965         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1966         help
1967           Execute-In-Place allows the kernel to run from non-volatile storage
1968           directly addressable by the CPU, such as NOR flash. This saves RAM
1969           space since the text section of the kernel is not loaded from flash
1970           to RAM.  Read-write sections, such as the data section and stack,
1971           are still copied to RAM.  The XIP kernel is not compressed since
1972           it has to run directly from flash, so it will take more space to
1973           store it.  The flash address used to link the kernel object files,
1974           and for storing it, is configuration dependent. Therefore, if you
1975           say Y here, you must know the proper physical address where to
1976           store the kernel image depending on your own flash memory usage.
1977
1978           Also note that the make target becomes "make xipImage" rather than
1979           "make zImage" or "make Image".  The final kernel binary to put in
1980           ROM memory will be arch/arm/boot/xipImage.
1981
1982           If unsure, say N.
1983
1984 config XIP_PHYS_ADDR
1985         hex "XIP Kernel Physical Location"
1986         depends on XIP_KERNEL
1987         default "0x00080000"
1988         help
1989           This is the physical address in your flash memory the kernel will
1990           be linked for and stored to.  This address is dependent on your
1991           own flash usage.
1992
1993 config KEXEC
1994         bool "Kexec system call (EXPERIMENTAL)"
1995         depends on (!SMP || PM_SLEEP_SMP)
1996         help
1997           kexec is a system call that implements the ability to shutdown your
1998           current kernel, and to start another kernel.  It is like a reboot
1999           but it is independent of the system firmware.   And like a reboot
2000           you can start any kernel with it, not just Linux.
2001
2002           It is an ongoing process to be certain the hardware in a machine
2003           is properly shutdown, so do not be surprised if this code does not
2004           initially work for you.
2005
2006 config ATAGS_PROC
2007         bool "Export atags in procfs"
2008         depends on ATAGS && KEXEC
2009         default y
2010         help
2011           Should the atags used to boot the kernel be exported in an "atags"
2012           file in procfs. Useful with kexec.
2013
2014 config CRASH_DUMP
2015         bool "Build kdump crash kernel (EXPERIMENTAL)"
2016         help
2017           Generate crash dump after being started by kexec. This should
2018           be normally only set in special crash dump kernels which are
2019           loaded in the main kernel with kexec-tools into a specially
2020           reserved region and then later executed after a crash by
2021           kdump/kexec. The crash dump kernel must be compiled to a
2022           memory address not used by the main kernel
2023
2024           For more details see Documentation/kdump/kdump.txt
2025
2026 config AUTO_ZRELADDR
2027         bool "Auto calculation of the decompressed kernel image address"
2028         help
2029           ZRELADDR is the physical address where the decompressed kernel
2030           image will be placed. If AUTO_ZRELADDR is selected, the address
2031           will be determined at run-time by masking the current IP with
2032           0xf8000000. This assumes the zImage being placed in the first 128MB
2033           from start of memory.
2034
2035 endmenu
2036
2037 menu "CPU Power Management"
2038
2039 source "drivers/cpufreq/Kconfig"
2040
2041 source "drivers/cpuidle/Kconfig"
2042
2043 endmenu
2044
2045 menu "Floating point emulation"
2046
2047 comment "At least one emulation must be selected"
2048
2049 config FPE_NWFPE
2050         bool "NWFPE math emulation"
2051         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2052         ---help---
2053           Say Y to include the NWFPE floating point emulator in the kernel.
2054           This is necessary to run most binaries. Linux does not currently
2055           support floating point hardware so you need to say Y here even if
2056           your machine has an FPA or floating point co-processor podule.
2057
2058           You may say N here if you are going to load the Acorn FPEmulator
2059           early in the bootup.
2060
2061 config FPE_NWFPE_XP
2062         bool "Support extended precision"
2063         depends on FPE_NWFPE
2064         help
2065           Say Y to include 80-bit support in the kernel floating-point
2066           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2067           Note that gcc does not generate 80-bit operations by default,
2068           so in most cases this option only enlarges the size of the
2069           floating point emulator without any good reason.
2070
2071           You almost surely want to say N here.
2072
2073 config FPE_FASTFPE
2074         bool "FastFPE math emulation (EXPERIMENTAL)"
2075         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2076         ---help---
2077           Say Y here to include the FAST floating point emulator in the kernel.
2078           This is an experimental much faster emulator which now also has full
2079           precision for the mantissa.  It does not support any exceptions.
2080           It is very simple, and approximately 3-6 times faster than NWFPE.
2081
2082           It should be sufficient for most programs.  It may be not suitable
2083           for scientific calculations, but you have to check this for yourself.
2084           If you do not feel you need a faster FP emulation you should better
2085           choose NWFPE.
2086
2087 config VFP
2088         bool "VFP-format floating point maths"
2089         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2090         help
2091           Say Y to include VFP support code in the kernel. This is needed
2092           if your hardware includes a VFP unit.
2093
2094           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2095           release notes and additional status information.
2096
2097           Say N if your target does not have VFP hardware.
2098
2099 config VFPv3
2100         bool
2101         depends on VFP
2102         default y if CPU_V7
2103
2104 config NEON
2105         bool "Advanced SIMD (NEON) Extension support"
2106         depends on VFPv3 && CPU_V7
2107         help
2108           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2109           Extension.
2110
2111 config KERNEL_MODE_NEON
2112         bool "Support for NEON in kernel mode"
2113         depends on NEON && AEABI
2114         help
2115           Say Y to include support for NEON in kernel mode.
2116
2117 endmenu
2118
2119 menu "Userspace binary formats"
2120
2121 source "fs/Kconfig.binfmt"
2122
2123 config ARTHUR
2124         tristate "RISC OS personality"
2125         depends on !AEABI
2126         help
2127           Say Y here to include the kernel code necessary if you want to run
2128           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2129           experimental; if this sounds frightening, say N and sleep in peace.
2130           You can also say M here to compile this support as a module (which
2131           will be called arthur).
2132
2133 endmenu
2134
2135 menu "Power management options"
2136
2137 source "kernel/power/Kconfig"
2138
2139 config ARCH_SUSPEND_POSSIBLE
2140         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2141                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2142         def_bool y
2143
2144 config ARM_CPU_SUSPEND
2145         def_bool PM_SLEEP
2146
2147 config ARCH_HIBERNATION_POSSIBLE
2148         bool
2149         depends on MMU
2150         default y if ARCH_SUSPEND_POSSIBLE
2151
2152 endmenu
2153
2154 source "net/Kconfig"
2155
2156 source "drivers/Kconfig"
2157
2158 source "fs/Kconfig"
2159
2160 source "arch/arm/Kconfig.debug"
2161
2162 source "security/Kconfig"
2163
2164 source "crypto/Kconfig"
2165
2166 source "lib/Kconfig"
2167
2168 source "arch/arm/kvm/Kconfig"