arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
  37         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OLD_SIGACTION
  80         select OLD_SIGSUSPEND3
  81         select PERF_USE_VMALLOC
  82         select RTC_LIB
  83         select SYS_SUPPORTS_APM_EMULATION
  84         # Above selects are sorted alphabetically; please add new ones
  85         # according to that.  Thanks.
  86         help
  87           The ARM series is a line of low-power-consumption RISC chip designs
  88           licensed by ARM Ltd and targeted at embedded applications and
  89           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  90           manufactured, but legacy ARM-based PC hardware remains popular in
  91           Europe.  There is an ARM Linux project with a web page at
  92           <http://www.arm.linux.org.uk/>.
  93
  94 config ARM_HAS_SG_CHAIN
  95         select ARCH_HAS_SG_CHAIN
  96         bool
  97
  98 config NEED_SG_DMA_LENGTH
  99         bool
 100
 101 config ARM_DMA_USE_IOMMU
 102         bool
 103         select ARM_HAS_SG_CHAIN
 104         select NEED_SG_DMA_LENGTH
 105
 106 if ARM_DMA_USE_IOMMU
 107
 108 config ARM_DMA_IOMMU_ALIGNMENT
 109         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 110         range 4 9
 111         default 8
 112         help
 113           DMA mapping framework by default aligns all buffers to the smallest
 114           PAGE_SIZE order which is greater than or equal to the requested buffer
 115           size. This works well for buffers up to a few hundreds kilobytes, but
 116           for larger buffers it just a waste of address space. Drivers which has
 117           relatively small addressing window (like 64Mib) might run out of
 118           virtual space with just a few allocations.
 119
 120           With this parameter you can specify the maximum PAGE_SIZE order for
 121           DMA IOMMU buffers. Larger buffers will be aligned only to this
 122           specified order. The order is expressed as a power of two multiplied
 123           by the PAGE_SIZE.
 124
 125 endif
 126
 127 config MIGHT_HAVE_PCI
 128         bool
 129
 130 config SYS_SUPPORTS_APM_EMULATION
 131         bool
 132
 133 config HAVE_TCM
 134         bool
 135         select GENERIC_ALLOCATOR
 136
 137 config HAVE_PROC_CPU
 138         bool
 139
 140 config NO_IOPORT_MAP
 141         bool
 142
 143 config EISA
 144         bool
 145         ---help---
 146           The Extended Industry Standard Architecture (EISA) bus was
 147           developed as an open alternative to the IBM MicroChannel bus.
 148
 149           The EISA bus provided some of the features of the IBM MicroChannel
 150           bus while maintaining backward compatibility with cards made for
 151           the older ISA bus.  The EISA bus saw limited use between 1988 and
 152           1995 when it was made obsolete by the PCI bus.
 153
 154           Say Y here if you are building a kernel for an EISA-based machine.
 155
 156           Otherwise, say N.
 157
 158 config SBUS
 159         bool
 160
 161 config STACKTRACE_SUPPORT
 162         bool
 163         default y
 164
 165 config HAVE_LATENCYTOP_SUPPORT
 166         bool
 167         depends on !SMP
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         depends on !ARCH_REALVIEW || !SPARSEMEM
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 16MB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_EBSA110 || \
 274                         ARCH_FOOTBRIDGE || \
 275                         ARCH_INTEGRATOR || \
 276                         ARCH_IOP13XX || \
 277                         ARCH_KS8695 || \
 278                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 279         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 280         default 0x20000000 if ARCH_S5PV210
 281         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 282         default 0xc0000000 if ARCH_SA1100
 283         help
 284           Please provide the physical address corresponding to the
 285           location of main memory in your system.
 286
 287 config GENERIC_BUG
 288         def_bool y
 289         depends on BUG
 290
 291 config PGTABLE_LEVELS
 292         int
 293         default 3 if ARM_LPAE
 294         default 2
 295
 296 source "init/Kconfig"
 297
 298 source "kernel/Kconfig.freezer"
 299
 300 menu "System Type"
 301
 302 config MMU
 303         bool "MMU-based Paged Memory Management Support"
 304         default y
 305         help
 306           Select if you want MMU-based virtualised addressing space
 307           support by paged memory management. If unsure, say 'Y'.
 308
 309 #
 310 # The "ARM system type" choice list is ordered alphabetically by option
 311 # text.  Please add new entries in the option alphabetic order.
 312 #
 313 choice
 314         prompt "ARM system type"
 315         default ARCH_VERSATILE if !MMU
 316         default ARCH_MULTIPLATFORM if MMU
 317
 318 config ARCH_MULTIPLATFORM
 319         bool "Allow multiple platforms to be selected"
 320         depends on MMU
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_HAS_SG_CHAIN
 323         select ARM_PATCH_PHYS_VIRT
 324         select AUTO_ZRELADDR
 325         select CLKSRC_OF
 326         select COMMON_CLK
 327         select GENERIC_CLOCKEVENTS
 328         select MIGHT_HAVE_PCI
 329         select MULTI_IRQ_HANDLER
 330         select SPARSE_IRQ
 331         select USE_OF
 332
 333 config ARM_SINGLE_ARMV7M
 334         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 335         depends on !MMU
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_NVIC
 338         select AUTO_ZRELADDR
 339         select CLKSRC_OF
 340         select COMMON_CLK
 341         select CPU_V7M
 342         select GENERIC_CLOCKEVENTS
 343         select NO_IOPORT_MAP
 344         select SPARSE_IRQ
 345         select USE_OF
 346
 347 config ARCH_REALVIEW
 348         bool "ARM Ltd. RealView family"
 349         select ARCH_WANT_OPTIONAL_GPIOLIB
 350         select ARM_AMBA
 351         select ARM_TIMER_SP804
 352         select COMMON_CLK
 353         select COMMON_CLK_VERSATILE
 354         select GENERIC_CLOCKEVENTS
 355         select GPIO_PL061 if GPIOLIB
 356         select ICST
 357         select NEED_MACH_MEMORY_H
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_SCHED_CLOCK
 360         help
 361           This enables support for ARM Ltd RealView boards.
 362
 363 config ARCH_VERSATILE
 364         bool "ARM Ltd. Versatile family"
 365         select ARCH_WANT_OPTIONAL_GPIOLIB
 366         select ARM_AMBA
 367         select ARM_TIMER_SP804
 368         select ARM_VIC
 369         select CLKDEV_LOOKUP
 370         select GENERIC_CLOCKEVENTS
 371         select HAVE_MACH_CLKDEV
 372         select ICST
 373         select PLAT_VERSATILE
 374         select PLAT_VERSATILE_CLOCK
 375         select PLAT_VERSATILE_SCHED_CLOCK
 376         select VERSATILE_FPGA_IRQ
 377         help
 378           This enables support for ARM Ltd Versatile board.
 379
 380 config ARCH_CLPS711X
 381         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select AUTO_ZRELADDR
 384         select CLKSRC_MMIO
 385         select COMMON_CLK
 386         select CPU_ARM720T
 387         select GENERIC_CLOCKEVENTS
 388         select MFD_SYSCON
 389         select SOC_BUS
 390         help
 391           Support for Cirrus Logic 711x/721x/731x based boards.
 392
 393 config ARCH_GEMINI
 394         bool "Cortina Systems Gemini"
 395         select ARCH_REQUIRE_GPIOLIB
 396         select CLKSRC_MMIO
 397         select CPU_FA526
 398         select GENERIC_CLOCKEVENTS
 399         help
 400           Support for the Cortina Systems Gemini family SoCs
 401
 402 config ARCH_EBSA110
 403         bool "EBSA-110"
 404         select ARCH_USES_GETTIMEOFFSET
 405         select CPU_SA110
 406         select ISA
 407         select NEED_MACH_IO_H
 408         select NEED_MACH_MEMORY_H
 409         select NO_IOPORT_MAP
 410         help
 411           This is an evaluation board for the StrongARM processor available
 412           from Digital. It has limited hardware on-board, including an
 413           Ethernet interface, two PCMCIA sockets, two serial ports and a
 414           parallel port.
 415
 416 config ARCH_EP93XX
 417         bool "EP93xx-based"
 418         select ARCH_HAS_HOLES_MEMORYMODEL
 419         select ARCH_REQUIRE_GPIOLIB
 420         select ARM_AMBA
 421         select ARM_PATCH_PHYS_VIRT
 422         select ARM_VIC
 423         select AUTO_ZRELADDR
 424         select CLKDEV_LOOKUP
 425         select CLKSRC_MMIO
 426         select CPU_ARM920T
 427         select GENERIC_CLOCKEVENTS
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         select MULTI_IRQ_HANDLER
 542         help
 543           Support for the following Marvell Orion 5x series SoCs:
 544           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 545           Orion-2 (5281), Orion-1-90 (6183).
 546
 547 config ARCH_MMP
 548         bool "Marvell PXA168/910/MMP2"
 549         depends on MMU
 550         select ARCH_REQUIRE_GPIOLIB
 551         select CLKDEV_LOOKUP
 552         select GENERIC_ALLOCATOR
 553         select GENERIC_CLOCKEVENTS
 554         select GPIO_PXA
 555         select IRQ_DOMAIN
 556         select MULTI_IRQ_HANDLER
 557         select PINCTRL
 558         select PLAT_PXA
 559         select SPARSE_IRQ
 560         help
 561           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 562
 563 config ARCH_KS8695
 564         bool "Micrel/Kendin KS8695"
 565         select ARCH_REQUIRE_GPIOLIB
 566         select CLKSRC_MMIO
 567         select CPU_ARM922T
 568         select GENERIC_CLOCKEVENTS
 569         select NEED_MACH_MEMORY_H
 570         help
 571           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 572           System-on-Chip devices.
 573
 574 config ARCH_W90X900
 575         bool "Nuvoton W90X900 CPU"
 576         select ARCH_REQUIRE_GPIOLIB
 577         select CLKDEV_LOOKUP
 578         select CLKSRC_MMIO
 579         select CPU_ARM926T
 580         select GENERIC_CLOCKEVENTS
 581         help
 582           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 583           At present, the w90x900 has been renamed nuc900, regarding
 584           the ARM series product line, you can login the following
 585           link address to know more.
 586
 587           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 588                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 589
 590 config ARCH_LPC32XX
 591         bool "NXP LPC32XX"
 592         select ARCH_REQUIRE_GPIOLIB
 593         select ARM_AMBA
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_MMIO
 596         select CPU_ARM926T
 597         select GENERIC_CLOCKEVENTS
 598         select HAVE_IDE
 599         select USE_OF
 600         help
 601           Support for the NXP LPC32XX family of processors
 602
 603 config ARCH_PXA
 604         bool "PXA2xx/PXA3xx-based"
 605         depends on MMU
 606         select ARCH_MTD_XIP
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_CPU_SUSPEND if PM
 609         select AUTO_ZRELADDR
 610         select COMMON_CLK
 611         select CLKDEV_LOOKUP
 612         select CLKSRC_MMIO
 613         select CLKSRC_OF
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select IRQ_DOMAIN
 618         select MULTI_IRQ_HANDLER
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_SHMOBILE_LEGACY
 625         bool "Renesas ARM SoCs (non-multiplatform)"
 626         select ARCH_SHMOBILE
 627         select ARM_PATCH_PHYS_VIRT if MMU
 628         select CLKDEV_LOOKUP
 629         select CPU_V7
 630         select GENERIC_CLOCKEVENTS
 631         select HAVE_ARM_SCU if SMP
 632         select HAVE_ARM_TWD if SMP
 633         select HAVE_SMP
 634         select MIGHT_HAVE_CACHE_L2X0
 635         select MULTI_IRQ_HANDLER
 636         select NO_IOPORT_MAP
 637         select PINCTRL
 638         select PM_GENERIC_DOMAINS if PM
 639         select SH_CLK_CPG
 640         select SPARSE_IRQ
 641         help
 642           Support for Renesas ARM SoC platforms using a non-multiplatform
 643           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 644           and RZ families.
 645
 646 config ARCH_RPC
 647         bool "RiscPC"
 648         select ARCH_ACORN
 649         select ARCH_MAY_HAVE_PC_FDC
 650         select ARCH_SPARSEMEM_ENABLE
 651         select ARCH_USES_GETTIMEOFFSET
 652         select CPU_SA110
 653         select FIQ
 654         select HAVE_IDE
 655         select HAVE_PATA_PLATFORM
 656         select ISA_DMA_API
 657         select NEED_MACH_IO_H
 658         select NEED_MACH_MEMORY_H
 659         select NO_IOPORT_MAP
 660         select VIRT_TO_BUS
 661         help
 662           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 663           CD-ROM interface, serial and parallel port, and the floppy drive.
 664
 665 config ARCH_SA1100
 666         bool "SA1100-based"
 667         select ARCH_MTD_XIP
 668         select ARCH_REQUIRE_GPIOLIB
 669         select ARCH_SPARSEMEM_ENABLE
 670         select CLKDEV_LOOKUP
 671         select CLKSRC_MMIO
 672         select CPU_FREQ
 673         select CPU_SA1100
 674         select GENERIC_CLOCKEVENTS
 675         select HAVE_IDE
 676         select IRQ_DOMAIN
 677         select ISA
 678         select MULTI_IRQ_HANDLER
 679         select NEED_MACH_MEMORY_H
 680         select SPARSE_IRQ
 681         help
 682           Support for StrongARM 11x0 based boards.
 683
 684 config ARCH_S3C24XX
 685         bool "Samsung S3C24XX SoCs"
 686         select ARCH_REQUIRE_GPIOLIB
 687         select ATAGS
 688         select CLKDEV_LOOKUP
 689         select CLKSRC_SAMSUNG_PWM
 690         select GENERIC_CLOCKEVENTS
 691         select GPIO_SAMSUNG
 692         select HAVE_S3C2410_I2C if I2C
 693         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 694         select HAVE_S3C_RTC if RTC_CLASS
 695         select MULTI_IRQ_HANDLER
 696         select NEED_MACH_IO_H
 697         select SAMSUNG_ATAGS
 698         help
 699           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 700           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 701           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 702           Samsung SMDK2410 development board (and derivatives).
 703
 704 config ARCH_S3C64XX
 705         bool "Samsung S3C64XX"
 706         select ARCH_REQUIRE_GPIOLIB
 707         select ARM_AMBA
 708         select ARM_VIC
 709         select ATAGS
 710         select CLKDEV_LOOKUP
 711         select CLKSRC_SAMSUNG_PWM
 712         select COMMON_CLK_SAMSUNG
 713         select CPU_V6K
 714         select GENERIC_CLOCKEVENTS
 715         select GPIO_SAMSUNG
 716         select HAVE_S3C2410_I2C if I2C
 717         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 718         select HAVE_TCM
 719         select NO_IOPORT_MAP
 720         select PLAT_SAMSUNG
 721         select PM_GENERIC_DOMAINS if PM
 722         select S3C_DEV_NAND
 723         select S3C_GPIO_TRACK
 724         select SAMSUNG_ATAGS
 725         select SAMSUNG_WAKEMASK
 726         select SAMSUNG_WDT_RESET
 727         help
 728           Samsung S3C64XX series based systems
 729
 730 config ARCH_DAVINCI
 731         bool "TI DaVinci"
 732         select ARCH_HAS_HOLES_MEMORYMODEL
 733         select ARCH_REQUIRE_GPIOLIB
 734         select CLKDEV_LOOKUP
 735         select GENERIC_ALLOCATOR
 736         select GENERIC_CLOCKEVENTS
 737         select GENERIC_IRQ_CHIP
 738         select HAVE_IDE
 739         select TI_PRIV_EDMA
 740         select USE_OF
 741         select ZONE_DMA
 742         help
 743           Support for TI's DaVinci platform.
 744
 745 config ARCH_OMAP1
 746         bool "TI OMAP1"
 747         depends on MMU
 748         select ARCH_HAS_HOLES_MEMORYMODEL
 749         select ARCH_OMAP
 750         select ARCH_REQUIRE_GPIOLIB
 751         select CLKDEV_LOOKUP
 752         select CLKSRC_MMIO
 753         select GENERIC_CLOCKEVENTS
 754         select GENERIC_IRQ_CHIP
 755         select HAVE_IDE
 756         select IRQ_DOMAIN
 757         select MULTI_IRQ_HANDLER
 758         select NEED_MACH_IO_H if PCCARD
 759         select NEED_MACH_MEMORY_H
 760         select SPARSE_IRQ
 761         help
 762           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 763
 764 endchoice
 765
 766 menu "Multiple platform selection"
 767         depends on ARCH_MULTIPLATFORM
 768
 769 comment "CPU Core family selection"
 770
 771 config ARCH_MULTI_V4
 772         bool "ARMv4 based platforms (FA526)"
 773         depends on !ARCH_MULTI_V6_V7
 774         select ARCH_MULTI_V4_V5
 775         select CPU_FA526
 776
 777 config ARCH_MULTI_V4T
 778         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 779         depends on !ARCH_MULTI_V6_V7
 780         select ARCH_MULTI_V4_V5
 781         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 782                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 783                 CPU_ARM925T || CPU_ARM940T)
 784
 785 config ARCH_MULTI_V5
 786         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 787         depends on !ARCH_MULTI_V6_V7
 788         select ARCH_MULTI_V4_V5
 789         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 790                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 791                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 792
 793 config ARCH_MULTI_V4_V5
 794         bool
 795
 796 config ARCH_MULTI_V6
 797         bool "ARMv6 based platforms (ARM11)"
 798         select ARCH_MULTI_V6_V7
 799         select CPU_V6K
 800
 801 config ARCH_MULTI_V7
 802         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 803         default y
 804         select ARCH_MULTI_V6_V7
 805         select CPU_V7
 806         select HAVE_SMP
 807
 808 config ARCH_MULTI_V6_V7
 809         bool
 810         select MIGHT_HAVE_CACHE_L2X0
 811
 812 config ARCH_MULTI_CPU_AUTO
 813         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 814         select ARCH_MULTI_V5
 815
 816 endmenu
 817
 818 config ARCH_VIRT
 819         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 820         select ARM_AMBA
 821         select ARM_GIC
 822         select ARM_PSCI
 823         select HAVE_ARM_ARCH_TIMER
 824
 825 #
 826 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 827 # Kconfigs may be included either alphabetically (according to the
 828 # plat- suffix) or along side the corresponding mach-* source.
 829 #
 830 source "arch/arm/mach-mvebu/Kconfig"
 831
 832 source "arch/arm/mach-alpine/Kconfig"
 833
 834 source "arch/arm/mach-asm9260/Kconfig"
 835
 836 source "arch/arm/mach-at91/Kconfig"
 837
 838 source "arch/arm/mach-axxia/Kconfig"
 839
 840 source "arch/arm/mach-bcm/Kconfig"
 841
 842 source "arch/arm/mach-berlin/Kconfig"
 843
 844 source "arch/arm/mach-clps711x/Kconfig"
 845
 846 source "arch/arm/mach-cns3xxx/Kconfig"
 847
 848 source "arch/arm/mach-davinci/Kconfig"
 849
 850 source "arch/arm/mach-digicolor/Kconfig"
 851
 852 source "arch/arm/mach-dove/Kconfig"
 853
 854 source "arch/arm/mach-ep93xx/Kconfig"
 855
 856 source "arch/arm/mach-footbridge/Kconfig"
 857
 858 source "arch/arm/mach-gemini/Kconfig"
 859
 860 source "arch/arm/mach-highbank/Kconfig"
 861
 862 source "arch/arm/mach-hisi/Kconfig"
 863
 864 source "arch/arm/mach-integrator/Kconfig"
 865
 866 source "arch/arm/mach-iop32x/Kconfig"
 867
 868 source "arch/arm/mach-iop33x/Kconfig"
 869
 870 source "arch/arm/mach-iop13xx/Kconfig"
 871
 872 source "arch/arm/mach-ixp4xx/Kconfig"
 873
 874 source "arch/arm/mach-keystone/Kconfig"
 875
 876 source "arch/arm/mach-ks8695/Kconfig"
 877
 878 source "arch/arm/mach-meson/Kconfig"
 879
 880 source "arch/arm/mach-moxart/Kconfig"
 881
 882 source "arch/arm/mach-mv78xx0/Kconfig"
 883
 884 source "arch/arm/mach-imx/Kconfig"
 885
 886 source "arch/arm/mach-mediatek/Kconfig"
 887
 888 source "arch/arm/mach-mxs/Kconfig"
 889
 890 source "arch/arm/mach-netx/Kconfig"
 891
 892 source "arch/arm/mach-nomadik/Kconfig"
 893
 894 source "arch/arm/mach-nspire/Kconfig"
 895
 896 source "arch/arm/plat-omap/Kconfig"
 897
 898 source "arch/arm/mach-omap1/Kconfig"
 899
 900 source "arch/arm/mach-omap2/Kconfig"
 901
 902 source "arch/arm/mach-orion5x/Kconfig"
 903
 904 source "arch/arm/mach-picoxcell/Kconfig"
 905
 906 source "arch/arm/mach-pxa/Kconfig"
 907 source "arch/arm/plat-pxa/Kconfig"
 908
 909 source "arch/arm/mach-mmp/Kconfig"
 910
 911 source "arch/arm/mach-qcom/Kconfig"
 912
 913 source "arch/arm/mach-realview/Kconfig"
 914
 915 source "arch/arm/mach-rockchip/Kconfig"
 916
 917 source "arch/arm/mach-sa1100/Kconfig"
 918
 919 source "arch/arm/mach-socfpga/Kconfig"
 920
 921 source "arch/arm/mach-spear/Kconfig"
 922
 923 source "arch/arm/mach-sti/Kconfig"
 924
 925 source "arch/arm/mach-s3c24xx/Kconfig"
 926
 927 source "arch/arm/mach-s3c64xx/Kconfig"
 928
 929 source "arch/arm/mach-s5pv210/Kconfig"
 930
 931 source "arch/arm/mach-exynos/Kconfig"
 932 source "arch/arm/plat-samsung/Kconfig"
 933
 934 source "arch/arm/mach-shmobile/Kconfig"
 935
 936 source "arch/arm/mach-sunxi/Kconfig"
 937
 938 source "arch/arm/mach-prima2/Kconfig"
 939
 940 source "arch/arm/mach-tegra/Kconfig"
 941
 942 source "arch/arm/mach-u300/Kconfig"
 943
 944 source "arch/arm/mach-uniphier/Kconfig"
 945
 946 source "arch/arm/mach-ux500/Kconfig"
 947
 948 source "arch/arm/mach-versatile/Kconfig"
 949
 950 source "arch/arm/mach-vexpress/Kconfig"
 951 source "arch/arm/plat-versatile/Kconfig"
 952
 953 source "arch/arm/mach-vt8500/Kconfig"
 954
 955 source "arch/arm/mach-w90x900/Kconfig"
 956
 957 source "arch/arm/mach-zx/Kconfig"
 958
 959 source "arch/arm/mach-zynq/Kconfig"
 960
 961 # ARMv7-M architecture
 962 config ARCH_EFM32
 963         bool "Energy Micro efm32"
 964         depends on ARM_SINGLE_ARMV7M
 965         select ARCH_REQUIRE_GPIOLIB
 966         help
 967           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 968           processors.
 969
 970 config ARCH_LPC18XX
 971         bool "NXP LPC18xx/LPC43xx"
 972         depends on ARM_SINGLE_ARMV7M
 973         select ARCH_HAS_RESET_CONTROLLER
 974         select ARM_AMBA
 975         select CLKSRC_LPC32XX
 976         select PINCTRL
 977         help
 978           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 979           high performance microcontrollers.
 980
 981 config ARCH_STM32
 982         bool "STMicrolectronics STM32"
 983         depends on ARM_SINGLE_ARMV7M
 984         select ARCH_HAS_RESET_CONTROLLER
 985         select ARMV7M_SYSTICK
 986         select CLKSRC_STM32
 987         select RESET_CONTROLLER
 988         help
 989           Support for STMicroelectronics STM32 processors.
 990
 991 # Definitions to make life easier
 992 config ARCH_ACORN
 993         bool
 994
 995 config PLAT_IOP
 996         bool
 997         select GENERIC_CLOCKEVENTS
 998
 999 config PLAT_ORION
1000         bool
1001         select CLKSRC_MMIO
1002         select COMMON_CLK
1003         select GENERIC_IRQ_CHIP
1004         select IRQ_DOMAIN
1005
1006 config PLAT_ORION_LEGACY
1007         bool
1008         select PLAT_ORION
1009
1010 config PLAT_PXA
1011         bool
1012
1013 config PLAT_VERSATILE
1014         bool
1015
1016 source "arch/arm/firmware/Kconfig"
1017
1018 source arch/arm/mm/Kconfig
1019
1020 config IWMMXT
1021         bool "Enable iWMMXt support"
1022         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1023         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1024         help
1025           Enable support for iWMMXt context switching at run time if
1026           running on a CPU that supports it.
1027
1028 config MULTI_IRQ_HANDLER
1029         bool
1030         help
1031           Allow each machine to specify it's own IRQ handler at run time.
1032
1033 if !MMU
1034 source "arch/arm/Kconfig-nommu"
1035 endif
1036
1037 config PJ4B_ERRATA_4742
1038         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1039         depends on CPU_PJ4B && MACH_ARMADA_370
1040         default y
1041         help
1042           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1043           Event (WFE) IDLE states, a specific timing sensitivity exists between
1044           the retiring WFI/WFE instructions and the newly issued subsequent
1045           instructions.  This sensitivity can result in a CPU hang scenario.
1046           Workaround:
1047           The software must insert either a Data Synchronization Barrier (DSB)
1048           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1049           instruction
1050
1051 config ARM_ERRATA_326103
1052         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1053         depends on CPU_V6
1054         help
1055           Executing a SWP instruction to read-only memory does not set bit 11
1056           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1057           treat the access as a read, preventing a COW from occurring and
1058           causing the faulting task to livelock.
1059
1060 config ARM_ERRATA_411920
1061         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1062         depends on CPU_V6 || CPU_V6K
1063         help
1064           Invalidation of the Instruction Cache operation can
1065           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1066           It does not affect the MPCore. This option enables the ARM Ltd.
1067           recommended workaround.
1068
1069 config ARM_ERRATA_430973
1070         bool "ARM errata: Stale prediction on replaced interworking branch"
1071         depends on CPU_V7
1072         help
1073           This option enables the workaround for the 430973 Cortex-A8
1074           r1p* erratum. If a code sequence containing an ARM/Thumb
1075           interworking branch is replaced with another code sequence at the
1076           same virtual address, whether due to self-modifying code or virtual
1077           to physical address re-mapping, Cortex-A8 does not recover from the
1078           stale interworking branch prediction. This results in Cortex-A8
1079           executing the new code sequence in the incorrect ARM or Thumb state.
1080           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1081           and also flushes the branch target cache at every context switch.
1082           Note that setting specific bits in the ACTLR register may not be
1083           available in non-secure mode.
1084
1085 config ARM_ERRATA_458693
1086         bool "ARM errata: Processor deadlock when a false hazard is created"
1087         depends on CPU_V7
1088         depends on !ARCH_MULTIPLATFORM
1089         help
1090           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1091           erratum. For very specific sequences of memory operations, it is
1092           possible for a hazard condition intended for a cache line to instead
1093           be incorrectly associated with a different cache line. This false
1094           hazard might then cause a processor deadlock. The workaround enables
1095           the L1 caching of the NEON accesses and disables the PLD instruction
1096           in the ACTLR register. Note that setting specific bits in the ACTLR
1097           register may not be available in non-secure mode.
1098
1099 config ARM_ERRATA_460075
1100         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1101         depends on CPU_V7
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1105           erratum. Any asynchronous access to the L2 cache may encounter a
1106           situation in which recent store transactions to the L2 cache are lost
1107           and overwritten with stale memory contents from external memory. The
1108           workaround disables the write-allocate mode for the L2 cache via the
1109           ACTLR register. Note that setting specific bits in the ACTLR register
1110           may not be available in non-secure mode.
1111
1112 config ARM_ERRATA_742230
1113         bool "ARM errata: DMB operation may be faulty"
1114         depends on CPU_V7 && SMP
1115         depends on !ARCH_MULTIPLATFORM
1116         help
1117           This option enables the workaround for the 742230 Cortex-A9
1118           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1119           between two write operations may not ensure the correct visibility
1120           ordering of the two writes. This workaround sets a specific bit in
1121           the diagnostic register of the Cortex-A9 which causes the DMB
1122           instruction to behave as a DSB, ensuring the correct behaviour of
1123           the two writes.
1124
1125 config ARM_ERRATA_742231
1126         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1127         depends on CPU_V7 && SMP
1128         depends on !ARCH_MULTIPLATFORM
1129         help
1130           This option enables the workaround for the 742231 Cortex-A9
1131           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1132           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1133           accessing some data located in the same cache line, may get corrupted
1134           data due to bad handling of the address hazard when the line gets
1135           replaced from one of the CPUs at the same time as another CPU is
1136           accessing it. This workaround sets specific bits in the diagnostic
1137           register of the Cortex-A9 which reduces the linefill issuing
1138           capabilities of the processor.
1139
1140 config ARM_ERRATA_643719
1141         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1142         depends on CPU_V7 && SMP
1143         default y
1144         help
1145           This option enables the workaround for the 643719 Cortex-A9 (prior to
1146           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1147           register returns zero when it should return one. The workaround
1148           corrects this value, ensuring cache maintenance operations which use
1149           it behave as intended and avoiding data corruption.
1150
1151 config ARM_ERRATA_720789
1152         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1153         depends on CPU_V7
1154         help
1155           This option enables the workaround for the 720789 Cortex-A9 (prior to
1156           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1157           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1158           As a consequence of this erratum, some TLB entries which should be
1159           invalidated are not, resulting in an incoherency in the system page
1160           tables. The workaround changes the TLB flushing routines to invalidate
1161           entries regardless of the ASID.
1162
1163 config ARM_ERRATA_743622
1164         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1165         depends on CPU_V7
1166         depends on !ARCH_MULTIPLATFORM
1167         help
1168           This option enables the workaround for the 743622 Cortex-A9
1169           (r2p*) erratum. Under very rare conditions, a faulty
1170           optimisation in the Cortex-A9 Store Buffer may lead to data
1171           corruption. This workaround sets a specific bit in the diagnostic
1172           register of the Cortex-A9 which disables the Store Buffer
1173           optimisation, preventing the defect from occurring. This has no
1174           visible impact on the overall performance or power consumption of the
1175           processor.
1176
1177 config ARM_ERRATA_751472
1178         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1179         depends on CPU_V7
1180         depends on !ARCH_MULTIPLATFORM
1181         help
1182           This option enables the workaround for the 751472 Cortex-A9 (prior
1183           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1184           completion of a following broadcasted operation if the second
1185           operation is received by a CPU before the ICIALLUIS has completed,
1186           potentially leading to corrupted entries in the cache or TLB.
1187
1188 config ARM_ERRATA_754322
1189         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1190         depends on CPU_V7
1191         help
1192           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1193           r3p*) erratum. A speculative memory access may cause a page table walk
1194           which starts prior to an ASID switch but completes afterwards. This
1195           can populate the micro-TLB with a stale entry which may be hit with
1196           the new ASID. This workaround places two dsb instructions in the mm
1197           switching code so that no page table walks can cross the ASID switch.
1198
1199 config ARM_ERRATA_754327
1200         bool "ARM errata: no automatic Store Buffer drain"
1201         depends on CPU_V7 && SMP
1202         help
1203           This option enables the workaround for the 754327 Cortex-A9 (prior to
1204           r2p0) erratum. The Store Buffer does not have any automatic draining
1205           mechanism and therefore a livelock may occur if an external agent
1206           continuously polls a memory location waiting to observe an update.
1207           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1208           written polling loops from denying visibility of updates to memory.
1209
1210 config ARM_ERRATA_364296
1211         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1212         depends on CPU_V6
1213         help
1214           This options enables the workaround for the 364296 ARM1136
1215           r0p2 erratum (possible cache data corruption with
1216           hit-under-miss enabled). It sets the undocumented bit 31 in
1217           the auxiliary control register and the FI bit in the control
1218           register, thus disabling hit-under-miss without putting the
1219           processor into full low interrupt latency mode. ARM11MPCore
1220           is not affected.
1221
1222 config ARM_ERRATA_764369
1223         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1224         depends on CPU_V7 && SMP
1225         help
1226           This option enables the workaround for erratum 764369
1227           affecting Cortex-A9 MPCore with two or more processors (all
1228           current revisions). Under certain timing circumstances, a data
1229           cache line maintenance operation by MVA targeting an Inner
1230           Shareable memory region may fail to proceed up to either the
1231           Point of Coherency or to the Point of Unification of the
1232           system. This workaround adds a DSB instruction before the
1233           relevant cache maintenance functions and sets a specific bit
1234           in the diagnostic control register of the SCU.
1235
1236 config ARM_ERRATA_775420
1237        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1238        depends on CPU_V7
1239        help
1240          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1241          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1242          operation aborts with MMU exception, it might cause the processor
1243          to deadlock. This workaround puts DSB before executing ISB if
1244          an abort may occur on cache maintenance.
1245
1246 config ARM_ERRATA_798181
1247         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1248         depends on CPU_V7 && SMP
1249         help
1250           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1251           adequately shooting down all use of the old entries. This
1252           option enables the Linux kernel workaround for this erratum
1253           which sends an IPI to the CPUs that are running the same ASID
1254           as the one being invalidated.
1255
1256 config ARM_ERRATA_773022
1257         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1258         depends on CPU_V7
1259         help
1260           This option enables the workaround for the 773022 Cortex-A15
1261           (up to r0p4) erratum. In certain rare sequences of code, the
1262           loop buffer may deliver incorrect instructions. This
1263           workaround disables the loop buffer to avoid the erratum.
1264
1265 endmenu
1266
1267 source "arch/arm/common/Kconfig"
1268
1269 menu "Bus support"
1270
1271 config ISA
1272         bool
1273         help
1274           Find out whether you have ISA slots on your motherboard.  ISA is the
1275           name of a bus system, i.e. the way the CPU talks to the other stuff
1276           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1277           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1278           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1279
1280 # Select ISA DMA controller support
1281 config ISA_DMA
1282         bool
1283         select ISA_DMA_API
1284
1285 # Select ISA DMA interface
1286 config ISA_DMA_API
1287         bool
1288
1289 config PCI
1290         bool "PCI support" if MIGHT_HAVE_PCI
1291         help
1292           Find out whether you have a PCI motherboard. PCI is the name of a
1293           bus system, i.e. the way the CPU talks to the other stuff inside
1294           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1295           VESA. If you have PCI, say Y, otherwise N.
1296
1297 config PCI_DOMAINS
1298         bool
1299         depends on PCI
1300
1301 config PCI_DOMAINS_GENERIC
1302         def_bool PCI_DOMAINS
1303
1304 config PCI_NANOENGINE
1305         bool "BSE nanoEngine PCI support"
1306         depends on SA1100_NANOENGINE
1307         help
1308           Enable PCI on the BSE nanoEngine board.
1309
1310 config PCI_SYSCALL
1311         def_bool PCI
1312
1313 config PCI_HOST_ITE8152
1314         bool
1315         depends on PCI && MACH_ARMCORE
1316         default y
1317         select DMABOUNCE
1318
1319 source "drivers/pci/Kconfig"
1320 source "drivers/pci/pcie/Kconfig"
1321
1322 source "drivers/pcmcia/Kconfig"
1323
1324 endmenu
1325
1326 menu "Kernel Features"
1327
1328 config HAVE_SMP
1329         bool
1330         help
1331           This option should be selected by machines which have an SMP-
1332           capable CPU.
1333
1334           The only effect of this option is to make the SMP-related
1335           options available to the user for configuration.
1336
1337 config SMP
1338         bool "Symmetric Multi-Processing"
1339         depends on CPU_V6K || CPU_V7
1340         depends on GENERIC_CLOCKEVENTS
1341         depends on HAVE_SMP
1342         depends on MMU || ARM_MPU
1343         select IRQ_WORK
1344         help
1345           This enables support for systems with more than one CPU. If you have
1346           a system with only one CPU, say N. If you have a system with more
1347           than one CPU, say Y.
1348
1349           If you say N here, the kernel will run on uni- and multiprocessor
1350           machines, but will use only one CPU of a multiprocessor machine. If
1351           you say Y here, the kernel will run on many, but not all,
1352           uniprocessor machines. On a uniprocessor machine, the kernel
1353           will run faster if you say N here.
1354
1355           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1356           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1357           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1358
1359           If you don't know what to do here, say N.
1360
1361 config SMP_ON_UP
1362         bool "Allow booting SMP kernel on uniprocessor systems"
1363         depends on SMP && !XIP_KERNEL && MMU
1364         default y
1365         help
1366           SMP kernels contain instructions which fail on non-SMP processors.
1367           Enabling this option allows the kernel to modify itself to make
1368           these instructions safe.  Disabling it allows about 1K of space
1369           savings.
1370
1371           If you don't know what to do here, say Y.
1372
1373 config ARM_CPU_TOPOLOGY
1374         bool "Support cpu topology definition"
1375         depends on SMP && CPU_V7
1376         default y
1377         help
1378           Support ARM cpu topology definition. The MPIDR register defines
1379           affinity between processors which is then used to describe the cpu
1380           topology of an ARM System.
1381
1382 config SCHED_MC
1383         bool "Multi-core scheduler support"
1384         depends on ARM_CPU_TOPOLOGY
1385         help
1386           Multi-core scheduler support improves the CPU scheduler's decision
1387           making when dealing with multi-core CPU chips at a cost of slightly
1388           increased overhead in some places. If unsure say N here.
1389
1390 config SCHED_SMT
1391         bool "SMT scheduler support"
1392         depends on ARM_CPU_TOPOLOGY
1393         help
1394           Improves the CPU scheduler's decision making when dealing with
1395           MultiThreading at a cost of slightly increased overhead in some
1396           places. If unsure say N here.
1397
1398 config HAVE_ARM_SCU
1399         bool
1400         help
1401           This option enables support for the ARM system coherency unit
1402
1403 config HAVE_ARM_ARCH_TIMER
1404         bool "Architected timer support"
1405         depends on CPU_V7
1406         select ARM_ARCH_TIMER
1407         select GENERIC_CLOCKEVENTS
1408         help
1409           This option enables support for the ARM architected timer
1410
1411 config HAVE_ARM_TWD
1412         bool
1413         depends on SMP
1414         select CLKSRC_OF if OF
1415         help
1416           This options enables support for the ARM timer and watchdog unit
1417
1418 config MCPM
1419         bool "Multi-Cluster Power Management"
1420         depends on CPU_V7 && SMP
1421         help
1422           This option provides the common power management infrastructure
1423           for (multi-)cluster based systems, such as big.LITTLE based
1424           systems.
1425
1426 config MCPM_QUAD_CLUSTER
1427         bool
1428         depends on MCPM
1429         help
1430           To avoid wasting resources unnecessarily, MCPM only supports up
1431           to 2 clusters by default.
1432           Platforms with 3 or 4 clusters that use MCPM must select this
1433           option to allow the additional clusters to be managed.
1434
1435 config BIG_LITTLE
1436         bool "big.LITTLE support (Experimental)"
1437         depends on CPU_V7 && SMP
1438         select MCPM
1439         help
1440           This option enables support selections for the big.LITTLE
1441           system architecture.
1442
1443 config BL_SWITCHER
1444         bool "big.LITTLE switcher support"
1445         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1446         select ARM_CPU_SUSPEND
1447         select CPU_PM
1448         help
1449           The big.LITTLE "switcher" provides the core functionality to
1450           transparently handle transition between a cluster of A15's
1451           and a cluster of A7's in a big.LITTLE system.
1452
1453 config BL_SWITCHER_DUMMY_IF
1454         tristate "Simple big.LITTLE switcher user interface"
1455         depends on BL_SWITCHER && DEBUG_KERNEL
1456         help
1457           This is a simple and dummy char dev interface to control
1458           the big.LITTLE switcher core code.  It is meant for
1459           debugging purposes only.
1460
1461 choice
1462         prompt "Memory split"
1463         depends on MMU
1464         default VMSPLIT_3G
1465         help
1466           Select the desired split between kernel and user memory.
1467
1468           If you are not absolutely sure what you are doing, leave this
1469           option alone!
1470
1471         config VMSPLIT_3G
1472                 bool "3G/1G user/kernel split"
1473         config VMSPLIT_2G
1474                 bool "2G/2G user/kernel split"
1475         config VMSPLIT_1G
1476                 bool "1G/3G user/kernel split"
1477 endchoice
1478
1479 config PAGE_OFFSET
1480         hex
1481         default PHYS_OFFSET if !MMU
1482         default 0x40000000 if VMSPLIT_1G
1483         default 0x80000000 if VMSPLIT_2G
1484         default 0xC0000000
1485
1486 config NR_CPUS
1487         int "Maximum number of CPUs (2-32)"
1488         range 2 32
1489         depends on SMP
1490         default "4"
1491
1492 config HOTPLUG_CPU
1493         bool "Support for hot-pluggable CPUs"
1494         depends on SMP
1495         help
1496           Say Y here to experiment with turning CPUs off and on.  CPUs
1497           can be controlled through /sys/devices/system/cpu.
1498
1499 config ARM_PSCI
1500         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1501         depends on CPU_V7
1502         select ARM_PSCI_FW
1503         help
1504           Say Y here if you want Linux to communicate with system firmware
1505           implementing the PSCI specification for CPU-centric power
1506           management operations described in ARM document number ARM DEN
1507           0022A ("Power State Coordination Interface System Software on
1508           ARM processors").
1509
1510 # The GPIO number here must be sorted by descending number. In case of
1511 # a multiplatform kernel, we just want the highest value required by the
1512 # selected platforms.
1513 config ARCH_NR_GPIO
1514         int
1515         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1516                 ARCH_ZYNQ
1517         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1518                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1519         default 416 if ARCH_SUNXI
1520         default 392 if ARCH_U8500
1521         default 352 if ARCH_VT8500
1522         default 288 if ARCH_ROCKCHIP
1523         default 264 if MACH_H4700
1524         default 0
1525         help
1526           Maximum number of GPIOs in the system.
1527
1528           If unsure, leave the default value.
1529
1530 source kernel/Kconfig.preempt
1531
1532 config HZ_FIXED
1533         int
1534         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1535                 ARCH_S5PV210 || ARCH_EXYNOS4
1536         default 128 if SOC_AT91RM9200
1537         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1538         default 0
1539
1540 choice
1541         depends on HZ_FIXED = 0
1542         prompt "Timer frequency"
1543
1544 config HZ_100
1545         bool "100 Hz"
1546
1547 config HZ_200
1548         bool "200 Hz"
1549
1550 config HZ_250
1551         bool "250 Hz"
1552
1553 config HZ_300
1554         bool "300 Hz"
1555
1556 config HZ_500
1557         bool "500 Hz"
1558
1559 config HZ_1000
1560         bool "1000 Hz"
1561
1562 endchoice
1563
1564 config HZ
1565         int
1566         default HZ_FIXED if HZ_FIXED != 0
1567         default 100 if HZ_100
1568         default 200 if HZ_200
1569         default 250 if HZ_250
1570         default 300 if HZ_300
1571         default 500 if HZ_500
1572         default 1000
1573
1574 config SCHED_HRTICK
1575         def_bool HIGH_RES_TIMERS
1576
1577 config THUMB2_KERNEL
1578         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1579         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1580         default y if CPU_THUMBONLY
1581         select AEABI
1582         select ARM_ASM_UNIFIED
1583         select ARM_UNWIND
1584         help
1585           By enabling this option, the kernel will be compiled in
1586           Thumb-2 mode. A compiler/assembler that understand the unified
1587           ARM-Thumb syntax is needed.
1588
1589           If unsure, say N.
1590
1591 config THUMB2_AVOID_R_ARM_THM_JUMP11
1592         bool "Work around buggy Thumb-2 short branch relocations in gas"
1593         depends on THUMB2_KERNEL && MODULES
1594         default y
1595         help
1596           Various binutils versions can resolve Thumb-2 branches to
1597           locally-defined, preemptible global symbols as short-range "b.n"
1598           branch instructions.
1599
1600           This is a problem, because there's no guarantee the final
1601           destination of the symbol, or any candidate locations for a
1602           trampoline, are within range of the branch.  For this reason, the
1603           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1604           relocation in modules at all, and it makes little sense to add
1605           support.
1606
1607           The symptom is that the kernel fails with an "unsupported
1608           relocation" error when loading some modules.
1609
1610           Until fixed tools are available, passing
1611           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1612           code which hits this problem, at the cost of a bit of extra runtime
1613           stack usage in some cases.
1614
1615           The problem is described in more detail at:
1616               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1617
1618           Only Thumb-2 kernels are affected.
1619
1620           Unless you are sure your tools don't have this problem, say Y.
1621
1622 config ARM_ASM_UNIFIED
1623         bool
1624
1625 config AEABI
1626         bool "Use the ARM EABI to compile the kernel"
1627         help
1628           This option allows for the kernel to be compiled using the latest
1629           ARM ABI (aka EABI).  This is only useful if you are using a user
1630           space environment that is also compiled with EABI.
1631
1632           Since there are major incompatibilities between the legacy ABI and
1633           EABI, especially with regard to structure member alignment, this
1634           option also changes the kernel syscall calling convention to
1635           disambiguate both ABIs and allow for backward compatibility support
1636           (selected with CONFIG_OABI_COMPAT).
1637
1638           To use this you need GCC version 4.0.0 or later.
1639
1640 config OABI_COMPAT
1641         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1642         depends on AEABI && !THUMB2_KERNEL
1643         help
1644           This option preserves the old syscall interface along with the
1645           new (ARM EABI) one. It also provides a compatibility layer to
1646           intercept syscalls that have structure arguments which layout
1647           in memory differs between the legacy ABI and the new ARM EABI
1648           (only for non "thumb" binaries). This option adds a tiny
1649           overhead to all syscalls and produces a slightly larger kernel.
1650
1651           The seccomp filter system will not be available when this is
1652           selected, since there is no way yet to sensibly distinguish
1653           between calling conventions during filtering.
1654
1655           If you know you'll be using only pure EABI user space then you
1656           can say N here. If this option is not selected and you attempt
1657           to execute a legacy ABI binary then the result will be
1658           UNPREDICTABLE (in fact it can be predicted that it won't work
1659           at all). If in doubt say N.
1660
1661 config ARCH_HAS_HOLES_MEMORYMODEL
1662         bool
1663
1664 config ARCH_SPARSEMEM_ENABLE
1665         bool
1666
1667 config ARCH_SPARSEMEM_DEFAULT
1668         def_bool ARCH_SPARSEMEM_ENABLE
1669
1670 config ARCH_SELECT_MEMORY_MODEL
1671         def_bool ARCH_SPARSEMEM_ENABLE
1672
1673 config HAVE_ARCH_PFN_VALID
1674         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1675
1676 config HAVE_GENERIC_RCU_GUP
1677         def_bool y
1678         depends on ARM_LPAE
1679
1680 config HIGHMEM
1681         bool "High Memory Support"
1682         depends on MMU
1683         help
1684           The address space of ARM processors is only 4 Gigabytes large
1685           and it has to accommodate user address space, kernel address
1686           space as well as some memory mapped IO. That means that, if you
1687           have a large amount of physical memory and/or IO, not all of the
1688           memory can be "permanently mapped" by the kernel. The physical
1689           memory that is not permanently mapped is called "high memory".
1690
1691           Depending on the selected kernel/user memory split, minimum
1692           vmalloc space and actual amount of RAM, you may not need this
1693           option which should result in a slightly faster kernel.
1694
1695           If unsure, say n.
1696
1697 config HIGHPTE
1698         bool "Allocate 2nd-level pagetables from highmem"
1699         depends on HIGHMEM
1700         help
1701           The VM uses one page of physical memory for each page table.
1702           For systems with a lot of processes, this can use a lot of
1703           precious low memory, eventually leading to low memory being
1704           consumed by page tables.  Setting this option will allow
1705           user-space 2nd level page tables to reside in high memory.
1706
1707 config CPU_SW_DOMAIN_PAN
1708         bool "Enable use of CPU domains to implement privileged no-access"
1709         depends on MMU && !ARM_LPAE
1710         default y
1711         help
1712           Increase kernel security by ensuring that normal kernel accesses
1713           are unable to access userspace addresses.  This can help prevent
1714           use-after-free bugs becoming an exploitable privilege escalation
1715           by ensuring that magic values (such as LIST_POISON) will always
1716           fault when dereferenced.
1717
1718           CPUs with low-vector mappings use a best-efforts implementation.
1719           Their lower 1MB needs to remain accessible for the vectors, but
1720           the remainder of userspace will become appropriately inaccessible.
1721
1722 config HW_PERF_EVENTS
1723         def_bool y
1724         depends on ARM_PMU
1725
1726 config SYS_SUPPORTS_HUGETLBFS
1727        def_bool y
1728        depends on ARM_LPAE
1729
1730 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1731        def_bool y
1732        depends on ARM_LPAE
1733
1734 config ARCH_WANT_GENERAL_HUGETLB
1735         def_bool y
1736
1737 config ARM_MODULE_PLTS
1738         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1739         depends on MODULES
1740         help
1741           Allocate PLTs when loading modules so that jumps and calls whose
1742           targets are too far away for their relative offsets to be encoded
1743           in the instructions themselves can be bounced via veneers in the
1744           module's PLT. This allows modules to be allocated in the generic
1745           vmalloc area after the dedicated module memory area has been
1746           exhausted. The modules will use slightly more memory, but after
1747           rounding up to page size, the actual memory footprint is usually
1748           the same.
1749
1750           Say y if you are getting out of memory errors while loading modules
1751
1752 source "mm/Kconfig"
1753
1754 config FORCE_MAX_ZONEORDER
1755         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1756         range 11 64 if ARCH_SHMOBILE_LEGACY
1757         default "12" if SOC_AM33XX
1758         default "9" if SA1111 || ARCH_EFM32
1759         default "11"
1760         help
1761           The kernel memory allocator divides physically contiguous memory
1762           blocks into "zones", where each zone is a power of two number of
1763           pages.  This option selects the largest power of two that the kernel
1764           keeps in the memory allocator.  If you need to allocate very large
1765           blocks of physically contiguous memory, then you may need to
1766           increase this value.
1767
1768           This config option is actually maximum order plus one. For example,
1769           a value of 11 means that the largest free memory block is 2^10 pages.
1770
1771 config ALIGNMENT_TRAP
1772         bool
1773         depends on CPU_CP15_MMU
1774         default y if !ARCH_EBSA110
1775         select HAVE_PROC_CPU if PROC_FS
1776         help
1777           ARM processors cannot fetch/store information which is not
1778           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1779           address divisible by 4. On 32-bit ARM processors, these non-aligned
1780           fetch/store instructions will be emulated in software if you say
1781           here, which has a severe performance impact. This is necessary for
1782           correct operation of some network protocols. With an IP-only
1783           configuration it is safe to say N, otherwise say Y.
1784
1785 config UACCESS_WITH_MEMCPY
1786         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1787         depends on MMU
1788         default y if CPU_FEROCEON
1789         help
1790           Implement faster copy_to_user and clear_user methods for CPU
1791           cores where a 8-word STM instruction give significantly higher
1792           memory write throughput than a sequence of individual 32bit stores.
1793
1794           A possible side effect is a slight increase in scheduling latency
1795           between threads sharing the same address space if they invoke
1796           such copy operations with large buffers.
1797
1798           However, if the CPU data cache is using a write-allocate mode,
1799           this option is unlikely to provide any performance gain.
1800
1801 config SECCOMP
1802         bool
1803         prompt "Enable seccomp to safely compute untrusted bytecode"
1804         ---help---
1805           This kernel feature is useful for number crunching applications
1806           that may need to compute untrusted bytecode during their
1807           execution. By using pipes or other transports made available to
1808           the process as file descriptors supporting the read/write
1809           syscalls, it's possible to isolate those applications in
1810           their own address space using seccomp. Once seccomp is
1811           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1812           and the task is only allowed to execute a few safe syscalls
1813           defined by each seccomp mode.
1814
1815 config SWIOTLB
1816         def_bool y
1817
1818 config IOMMU_HELPER
1819         def_bool SWIOTLB
1820
1821 config XEN_DOM0
1822         def_bool y
1823         depends on XEN
1824
1825 config XEN
1826         bool "Xen guest support on ARM"
1827         depends on ARM && AEABI && OF
1828         depends on CPU_V7 && !CPU_V6
1829         depends on !GENERIC_ATOMIC64
1830         depends on MMU
1831         select ARCH_DMA_ADDR_T_64BIT
1832         select ARM_PSCI
1833         select SWIOTLB_XEN
1834         help
1835           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1836
1837 endmenu
1838
1839 menu "Boot options"
1840
1841 config USE_OF
1842         bool "Flattened Device Tree support"
1843         select IRQ_DOMAIN
1844         select OF
1845         select OF_EARLY_FLATTREE
1846         select OF_RESERVED_MEM
1847         help
1848           Include support for flattened device tree machine descriptions.
1849
1850 config ATAGS
1851         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1852         default y
1853         help
1854           This is the traditional way of passing data to the kernel at boot
1855           time. If you are solely relying on the flattened device tree (or
1856           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1857           to remove ATAGS support from your kernel binary.  If unsure,
1858           leave this to y.
1859
1860 config DEPRECATED_PARAM_STRUCT
1861         bool "Provide old way to pass kernel parameters"
1862         depends on ATAGS
1863         help
1864           This was deprecated in 2001 and announced to live on for 5 years.
1865           Some old boot loaders still use this way.
1866
1867 # Compressed boot loader in ROM.  Yes, we really want to ask about
1868 # TEXT and BSS so we preserve their values in the config files.
1869 config ZBOOT_ROM_TEXT
1870         hex "Compressed ROM boot loader base address"
1871         default "0"
1872         help
1873           The physical address at which the ROM-able zImage is to be
1874           placed in the target.  Platforms which normally make use of
1875           ROM-able zImage formats normally set this to a suitable
1876           value in their defconfig file.
1877
1878           If ZBOOT_ROM is not enabled, this has no effect.
1879
1880 config ZBOOT_ROM_BSS
1881         hex "Compressed ROM boot loader BSS address"
1882         default "0"
1883         help
1884           The base address of an area of read/write memory in the target
1885           for the ROM-able zImage which must be available while the
1886           decompressor is running. It must be large enough to hold the
1887           entire decompressed kernel plus an additional 128 KiB.
1888           Platforms which normally make use of ROM-able zImage formats
1889           normally set this to a suitable value in their defconfig file.
1890
1891           If ZBOOT_ROM is not enabled, this has no effect.
1892
1893 config ZBOOT_ROM
1894         bool "Compressed boot loader in ROM/flash"
1895         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1896         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1897         help
1898           Say Y here if you intend to execute your compressed kernel image
1899           (zImage) directly from ROM or flash.  If unsure, say N.
1900
1901 config ARM_APPENDED_DTB
1902         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1903         depends on OF
1904         help
1905           With this option, the boot code will look for a device tree binary
1906           (DTB) appended to zImage
1907           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1908
1909           This is meant as a backward compatibility convenience for those
1910           systems with a bootloader that can't be upgraded to accommodate
1911           the documented boot protocol using a device tree.
1912
1913           Beware that there is very little in terms of protection against
1914           this option being confused by leftover garbage in memory that might
1915           look like a DTB header after a reboot if no actual DTB is appended
1916           to zImage.  Do not leave this option active in a production kernel
1917           if you don't intend to always append a DTB.  Proper passing of the
1918           location into r2 of a bootloader provided DTB is always preferable
1919           to this option.
1920
1921 config ARM_ATAG_DTB_COMPAT
1922         bool "Supplement the appended DTB with traditional ATAG information"
1923         depends on ARM_APPENDED_DTB
1924         help
1925           Some old bootloaders can't be updated to a DTB capable one, yet
1926           they provide ATAGs with memory configuration, the ramdisk address,
1927           the kernel cmdline string, etc.  Such information is dynamically
1928           provided by the bootloader and can't always be stored in a static
1929           DTB.  To allow a device tree enabled kernel to be used with such
1930           bootloaders, this option allows zImage to extract the information
1931           from the ATAG list and store it at run time into the appended DTB.
1932
1933 choice
1934         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1935         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1936
1937 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938         bool "Use bootloader kernel arguments if available"
1939         help
1940           Uses the command-line options passed by the boot loader instead of
1941           the device tree bootargs property. If the boot loader doesn't provide
1942           any, the device tree bootargs property will be used.
1943
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1945         bool "Extend with bootloader kernel arguments"
1946         help
1947           The command-line arguments provided by the boot loader will be
1948           appended to the the device tree bootargs property.
1949
1950 endchoice
1951
1952 config CMDLINE
1953         string "Default kernel command string"
1954         default ""
1955         help
1956           On some architectures (EBSA110 and CATS), there is currently no way
1957           for the boot loader to pass arguments to the kernel. For these
1958           architectures, you should supply some command-line options at build
1959           time by entering them here. As a minimum, you should specify the
1960           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1961
1962 choice
1963         prompt "Kernel command line type" if CMDLINE != ""
1964         default CMDLINE_FROM_BOOTLOADER
1965         depends on ATAGS
1966
1967 config CMDLINE_FROM_BOOTLOADER
1968         bool "Use bootloader kernel arguments if available"
1969         help
1970           Uses the command-line options passed by the boot loader. If
1971           the boot loader doesn't provide any, the default kernel command
1972           string provided in CMDLINE will be used.
1973
1974 config CMDLINE_EXTEND
1975         bool "Extend bootloader kernel arguments"
1976         help
1977           The command-line arguments provided by the boot loader will be
1978           appended to the default kernel command string.
1979
1980 config CMDLINE_FORCE
1981         bool "Always use the default kernel command string"
1982         help
1983           Always use the default kernel command string, even if the boot
1984           loader passes other arguments to the kernel.
1985           This is useful if you cannot or don't want to change the
1986           command-line options your boot loader passes to the kernel.
1987 endchoice
1988
1989 config XIP_KERNEL
1990         bool "Kernel Execute-In-Place from ROM"
1991         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1992         help
1993           Execute-In-Place allows the kernel to run from non-volatile storage
1994           directly addressable by the CPU, such as NOR flash. This saves RAM
1995           space since the text section of the kernel is not loaded from flash
1996           to RAM.  Read-write sections, such as the data section and stack,
1997           are still copied to RAM.  The XIP kernel is not compressed since
1998           it has to run directly from flash, so it will take more space to
1999           store it.  The flash address used to link the kernel object files,
2000           and for storing it, is configuration dependent. Therefore, if you
2001           say Y here, you must know the proper physical address where to
2002           store the kernel image depending on your own flash memory usage.
2003
2004           Also note that the make target becomes "make xipImage" rather than
2005           "make zImage" or "make Image".  The final kernel binary to put in
2006           ROM memory will be arch/arm/boot/xipImage.
2007
2008           If unsure, say N.
2009
2010 config XIP_PHYS_ADDR
2011         hex "XIP Kernel Physical Location"
2012         depends on XIP_KERNEL
2013         default "0x00080000"
2014         help
2015           This is the physical address in your flash memory the kernel will
2016           be linked for and stored to.  This address is dependent on your
2017           own flash usage.
2018
2019 config KEXEC
2020         bool "Kexec system call (EXPERIMENTAL)"
2021         depends on (!SMP || PM_SLEEP_SMP)
2022         depends on !CPU_V7M
2023         help
2024           kexec is a system call that implements the ability to shutdown your
2025           current kernel, and to start another kernel.  It is like a reboot
2026           but it is independent of the system firmware.   And like a reboot
2027           you can start any kernel with it, not just Linux.
2028
2029           It is an ongoing process to be certain the hardware in a machine
2030           is properly shutdown, so do not be surprised if this code does not
2031           initially work for you.
2032
2033 config ATAGS_PROC
2034         bool "Export atags in procfs"
2035         depends on ATAGS && KEXEC
2036         default y
2037         help
2038           Should the atags used to boot the kernel be exported in an "atags"
2039           file in procfs. Useful with kexec.
2040
2041 config CRASH_DUMP
2042         bool "Build kdump crash kernel (EXPERIMENTAL)"
2043         help
2044           Generate crash dump after being started by kexec. This should
2045           be normally only set in special crash dump kernels which are
2046           loaded in the main kernel with kexec-tools into a specially
2047           reserved region and then later executed after a crash by
2048           kdump/kexec. The crash dump kernel must be compiled to a
2049           memory address not used by the main kernel
2050
2051           For more details see Documentation/kdump/kdump.txt
2052
2053 config AUTO_ZRELADDR
2054         bool "Auto calculation of the decompressed kernel image address"
2055         help
2056           ZRELADDR is the physical address where the decompressed kernel
2057           image will be placed. If AUTO_ZRELADDR is selected, the address
2058           will be determined at run-time by masking the current IP with
2059           0xf8000000. This assumes the zImage being placed in the first 128MB
2060           from start of memory.
2061
2062 endmenu
2063
2064 menu "CPU Power Management"
2065
2066 source "drivers/cpufreq/Kconfig"
2067
2068 source "drivers/cpuidle/Kconfig"
2069
2070 endmenu
2071
2072 menu "Floating point emulation"
2073
2074 comment "At least one emulation must be selected"
2075
2076 config FPE_NWFPE
2077         bool "NWFPE math emulation"
2078         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2079         ---help---
2080           Say Y to include the NWFPE floating point emulator in the kernel.
2081           This is necessary to run most binaries. Linux does not currently
2082           support floating point hardware so you need to say Y here even if
2083           your machine has an FPA or floating point co-processor podule.
2084
2085           You may say N here if you are going to load the Acorn FPEmulator
2086           early in the bootup.
2087
2088 config FPE_NWFPE_XP
2089         bool "Support extended precision"
2090         depends on FPE_NWFPE
2091         help
2092           Say Y to include 80-bit support in the kernel floating-point
2093           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2094           Note that gcc does not generate 80-bit operations by default,
2095           so in most cases this option only enlarges the size of the
2096           floating point emulator without any good reason.
2097
2098           You almost surely want to say N here.
2099
2100 config FPE_FASTFPE
2101         bool "FastFPE math emulation (EXPERIMENTAL)"
2102         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2103         ---help---
2104           Say Y here to include the FAST floating point emulator in the kernel.
2105           This is an experimental much faster emulator which now also has full
2106           precision for the mantissa.  It does not support any exceptions.
2107           It is very simple, and approximately 3-6 times faster than NWFPE.
2108
2109           It should be sufficient for most programs.  It may be not suitable
2110           for scientific calculations, but you have to check this for yourself.
2111           If you do not feel you need a faster FP emulation you should better
2112           choose NWFPE.
2113
2114 config VFP
2115         bool "VFP-format floating point maths"
2116         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2117         help
2118           Say Y to include VFP support code in the kernel. This is needed
2119           if your hardware includes a VFP unit.
2120
2121           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2122           release notes and additional status information.
2123
2124           Say N if your target does not have VFP hardware.
2125
2126 config VFPv3
2127         bool
2128         depends on VFP
2129         default y if CPU_V7
2130
2131 config NEON
2132         bool "Advanced SIMD (NEON) Extension support"
2133         depends on VFPv3 && CPU_V7
2134         help
2135           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2136           Extension.
2137
2138 config KERNEL_MODE_NEON
2139         bool "Support for NEON in kernel mode"
2140         depends on NEON && AEABI
2141         help
2142           Say Y to include support for NEON in kernel mode.
2143
2144 endmenu
2145
2146 menu "Userspace binary formats"
2147
2148 source "fs/Kconfig.binfmt"
2149
2150 endmenu
2151
2152 menu "Power management options"
2153
2154 source "kernel/power/Kconfig"
2155
2156 config ARCH_SUSPEND_POSSIBLE
2157         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2158                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2159         def_bool y
2160
2161 config ARM_CPU_SUSPEND
2162         def_bool PM_SLEEP
2163
2164 config ARCH_HIBERNATION_POSSIBLE
2165         bool
2166         depends on MMU
2167         default y if ARCH_SUSPEND_POSSIBLE
2168
2169 endmenu
2170
2171 source "net/Kconfig"
2172
2173 source "drivers/Kconfig"
2174
2175 source "drivers/firmware/Kconfig"
2176
2177 source "fs/Kconfig"
2178
2179 source "arch/arm/Kconfig.debug"
2180
2181 source "security/Kconfig"
2182
2183 source "crypto/Kconfig"
2184 if CRYPTO
2185 source "arch/arm/crypto/Kconfig"
2186 endif
2187
2188 source "lib/Kconfig"
2189
2190 source "arch/arm/kvm/Kconfig"