arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_MMAP_RND_BITS if MMU
  41         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  42         select HAVE_ARCH_TRACEHOOK
  43         select HAVE_ARM_SMCCC if CPU_V7
  44         select HAVE_CBPF_JIT
  45         select HAVE_CC_STACKPROTECTOR
  46         select HAVE_CONTEXT_TRACKING
  47         select HAVE_C_RECORDMCOUNT
  48         select HAVE_DEBUG_KMEMLEAK
  49         select HAVE_DMA_API_DEBUG
  50         select HAVE_DMA_CONTIGUOUS if MMU
  51         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  53         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  54         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  55         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  56         select HAVE_GENERIC_DMA_COHERENT
  57         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  58         select HAVE_IDE if PCI || ISA || PCMCIA
  59         select HAVE_IRQ_TIME_ACCOUNTING
  60         select HAVE_KERNEL_GZIP
  61         select HAVE_KERNEL_LZ4
  62         select HAVE_KERNEL_LZMA
  63         select HAVE_KERNEL_LZO
  64         select HAVE_KERNEL_XZ
  65         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  66         select HAVE_KRETPROBES if (HAVE_KPROBES)
  67         select HAVE_MEMBLOCK
  68         select HAVE_MOD_ARCH_SPECIFIC
  69         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  70         select HAVE_OPTPROBES if !THUMB2_KERNEL
  71         select HAVE_PERF_EVENTS
  72         select HAVE_PERF_REGS
  73         select HAVE_PERF_USER_STACK_DUMP
  74         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  75         select HAVE_REGS_AND_STACK_ACCESS_API
  76         select HAVE_SYSCALL_TRACEPOINTS
  77         select HAVE_UID16
  78         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  79         select IRQ_FORCED_THREADING
  80         select MODULES_USE_ELF_REL
  81         select NO_BOOTMEM
  82         select OF_EARLY_FLATTREE if OF
  83         select OF_RESERVED_MEM if OF
  84         select OLD_SIGACTION
  85         select OLD_SIGSUSPEND3
  86         select PERF_USE_VMALLOC
  87         select RTC_LIB
  88         select SYS_SUPPORTS_APM_EMULATION
  89         # Above selects are sorted alphabetically; please add new ones
  90         # according to that.  Thanks.
  91         help
  92           The ARM series is a line of low-power-consumption RISC chip designs
  93           licensed by ARM Ltd and targeted at embedded applications and
  94           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  95           manufactured, but legacy ARM-based PC hardware remains popular in
  96           Europe.  There is an ARM Linux project with a web page at
  97           <http://www.arm.linux.org.uk/>.
  98
  99 config ARM_HAS_SG_CHAIN
 100         select ARCH_HAS_SG_CHAIN
 101         bool
 102
 103 config NEED_SG_DMA_LENGTH
 104         bool
 105
 106 config ARM_DMA_USE_IOMMU
 107         bool
 108         select ARM_HAS_SG_CHAIN
 109         select NEED_SG_DMA_LENGTH
 110
 111 if ARM_DMA_USE_IOMMU
 112
 113 config ARM_DMA_IOMMU_ALIGNMENT
 114         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 115         range 4 9
 116         default 8
 117         help
 118           DMA mapping framework by default aligns all buffers to the smallest
 119           PAGE_SIZE order which is greater than or equal to the requested buffer
 120           size. This works well for buffers up to a few hundreds kilobytes, but
 121           for larger buffers it just a waste of address space. Drivers which has
 122           relatively small addressing window (like 64Mib) might run out of
 123           virtual space with just a few allocations.
 124
 125           With this parameter you can specify the maximum PAGE_SIZE order for
 126           DMA IOMMU buffers. Larger buffers will be aligned only to this
 127           specified order. The order is expressed as a power of two multiplied
 128           by the PAGE_SIZE.
 129
 130 endif
 131
 132 config MIGHT_HAVE_PCI
 133         bool
 134
 135 config SYS_SUPPORTS_APM_EMULATION
 136         bool
 137
 138 config HAVE_TCM
 139         bool
 140         select GENERIC_ALLOCATOR
 141
 142 config HAVE_PROC_CPU
 143         bool
 144
 145 config NO_IOPORT_MAP
 146         bool
 147
 148 config EISA
 149         bool
 150         ---help---
 151           The Extended Industry Standard Architecture (EISA) bus was
 152           developed as an open alternative to the IBM MicroChannel bus.
 153
 154           The EISA bus provided some of the features of the IBM MicroChannel
 155           bus while maintaining backward compatibility with cards made for
 156           the older ISA bus.  The EISA bus saw limited use between 1988 and
 157           1995 when it was made obsolete by the PCI bus.
 158
 159           Say Y here if you are building a kernel for an EISA-based machine.
 160
 161           Otherwise, say N.
 162
 163 config SBUS
 164         bool
 165
 166 config STACKTRACE_SUPPORT
 167         bool
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         help
 243           Patch phys-to-virt and virt-to-phys translation functions at
 244           boot and module load time according to the position of the
 245           kernel in system memory.
 246
 247           This can only be used with non-XIP MMU kernels where the base
 248           of physical memory is at a 16MB boundary.
 249
 250           Only disable this option if you know that you do not require
 251           this feature (eg, building a kernel for a single machine) and
 252           you need to shrink the kernel to the minimal size.
 253
 254 config NEED_MACH_IO_H
 255         bool
 256         help
 257           Select this when mach/io.h is required to provide special
 258           definitions for this platform.  The need for mach/io.h should
 259           be avoided when possible.
 260
 261 config NEED_MACH_MEMORY_H
 262         bool
 263         help
 264           Select this when mach/memory.h is required to provide special
 265           definitions for this platform.  The need for mach/memory.h should
 266           be avoided when possible.
 267
 268 config PHYS_OFFSET
 269         hex "Physical address of main memory" if MMU
 270         depends on !ARM_PATCH_PHYS_VIRT
 271         default DRAM_BASE if !MMU
 272         default 0x00000000 if ARCH_EBSA110 || \
 273                         ARCH_FOOTBRIDGE || \
 274                         ARCH_INTEGRATOR || \
 275                         ARCH_IOP13XX || \
 276                         ARCH_KS8695 || \
 277                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 278         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 279         default 0x20000000 if ARCH_S5PV210
 280         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 281         default 0xc0000000 if ARCH_SA1100
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 config ARCH_MMAP_RND_BITS_MIN
 309         default 8
 310
 311 config ARCH_MMAP_RND_BITS_MAX
 312         default 14 if PAGE_OFFSET=0x40000000
 313         default 15 if PAGE_OFFSET=0x80000000
 314         default 16
 315
 316 #
 317 # The "ARM system type" choice list is ordered alphabetically by option
 318 # text.  Please add new entries in the option alphabetic order.
 319 #
 320 choice
 321         prompt "ARM system type"
 322         default ARM_SINGLE_ARMV7M if !MMU
 323         default ARCH_MULTIPLATFORM if MMU
 324
 325 config ARCH_MULTIPLATFORM
 326         bool "Allow multiple platforms to be selected"
 327         depends on MMU
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_HAS_SG_CHAIN
 330         select ARM_PATCH_PHYS_VIRT
 331         select AUTO_ZRELADDR
 332         select CLKSRC_OF
 333         select COMMON_CLK
 334         select GENERIC_CLOCKEVENTS
 335         select MIGHT_HAVE_PCI
 336         select MULTI_IRQ_HANDLER
 337         select SPARSE_IRQ
 338         select USE_OF
 339
 340 config ARM_SINGLE_ARMV7M
 341         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 342         depends on !MMU
 343         select ARCH_WANT_OPTIONAL_GPIOLIB
 344         select ARM_NVIC
 345         select AUTO_ZRELADDR
 346         select CLKSRC_OF
 347         select COMMON_CLK
 348         select CPU_V7M
 349         select GENERIC_CLOCKEVENTS
 350         select NO_IOPORT_MAP
 351         select SPARSE_IRQ
 352         select USE_OF
 353
 354
 355 config ARCH_CLPS711X
 356         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 357         select ARCH_REQUIRE_GPIOLIB
 358         select AUTO_ZRELADDR
 359         select CLKSRC_MMIO
 360         select COMMON_CLK
 361         select CPU_ARM720T
 362         select GENERIC_CLOCKEVENTS
 363         select MFD_SYSCON
 364         select SOC_BUS
 365         help
 366           Support for Cirrus Logic 711x/721x/731x based boards.
 367
 368 config ARCH_GEMINI
 369         bool "Cortina Systems Gemini"
 370         select ARCH_REQUIRE_GPIOLIB
 371         select CLKSRC_MMIO
 372         select CPU_FA526
 373         select GENERIC_CLOCKEVENTS
 374         help
 375           Support for the Cortina Systems Gemini family SoCs
 376
 377 config ARCH_EBSA110
 378         bool "EBSA-110"
 379         select ARCH_USES_GETTIMEOFFSET
 380         select CPU_SA110
 381         select ISA
 382         select NEED_MACH_IO_H
 383         select NEED_MACH_MEMORY_H
 384         select NO_IOPORT_MAP
 385         help
 386           This is an evaluation board for the StrongARM processor available
 387           from Digital. It has limited hardware on-board, including an
 388           Ethernet interface, two PCMCIA sockets, two serial ports and a
 389           parallel port.
 390
 391 config ARCH_EP93XX
 392         bool "EP93xx-based"
 393         select ARCH_HAS_HOLES_MEMORYMODEL
 394         select ARCH_REQUIRE_GPIOLIB
 395         select ARM_AMBA
 396         select ARM_PATCH_PHYS_VIRT
 397         select ARM_VIC
 398         select AUTO_ZRELADDR
 399         select CLKDEV_LOOKUP
 400         select CLKSRC_MMIO
 401         select CPU_ARM920T
 402         select GENERIC_CLOCKEVENTS
 403         help
 404           This enables support for the Cirrus EP93xx series of CPUs.
 405
 406 config ARCH_FOOTBRIDGE
 407         bool "FootBridge"
 408         select CPU_SA110
 409         select FOOTBRIDGE
 410         select GENERIC_CLOCKEVENTS
 411         select HAVE_IDE
 412         select NEED_MACH_IO_H if !MMU
 413         select NEED_MACH_MEMORY_H
 414         help
 415           Support for systems based on the DC21285 companion chip
 416           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 417
 418 config ARCH_NETX
 419         bool "Hilscher NetX based"
 420         select ARM_VIC
 421         select CLKSRC_MMIO
 422         select CPU_ARM926T
 423         select GENERIC_CLOCKEVENTS
 424         help
 425           This enables support for systems based on the Hilscher NetX Soc
 426
 427 config ARCH_IOP13XX
 428         bool "IOP13xx-based"
 429         depends on MMU
 430         select CPU_XSC3
 431         select NEED_MACH_MEMORY_H
 432         select NEED_RET_TO_USER
 433         select PCI
 434         select PLAT_IOP
 435         select VMSPLIT_1G
 436         select SPARSE_IRQ
 437         help
 438           Support for Intel's IOP13XX (XScale) family of processors.
 439
 440 config ARCH_IOP32X
 441         bool "IOP32x-based"
 442         depends on MMU
 443         select ARCH_REQUIRE_GPIOLIB
 444         select CPU_XSCALE
 445         select GPIO_IOP
 446         select NEED_RET_TO_USER
 447         select PCI
 448         select PLAT_IOP
 449         help
 450           Support for Intel's 80219 and IOP32X (XScale) family of
 451           processors.
 452
 453 config ARCH_IOP33X
 454         bool "IOP33x-based"
 455         depends on MMU
 456         select ARCH_REQUIRE_GPIOLIB
 457         select CPU_XSCALE
 458         select GPIO_IOP
 459         select NEED_RET_TO_USER
 460         select PCI
 461         select PLAT_IOP
 462         help
 463           Support for Intel's IOP33X (XScale) family of processors.
 464
 465 config ARCH_IXP4XX
 466         bool "IXP4xx-based"
 467         depends on MMU
 468         select ARCH_HAS_DMA_SET_COHERENT_MASK
 469         select ARCH_REQUIRE_GPIOLIB
 470         select ARCH_SUPPORTS_BIG_ENDIAN
 471         select CLKSRC_MMIO
 472         select CPU_XSCALE
 473         select DMABOUNCE if PCI
 474         select GENERIC_CLOCKEVENTS
 475         select MIGHT_HAVE_PCI
 476         select NEED_MACH_IO_H
 477         select USB_EHCI_BIG_ENDIAN_DESC
 478         select USB_EHCI_BIG_ENDIAN_MMIO
 479         help
 480           Support for Intel's IXP4XX (XScale) family of processors.
 481
 482 config ARCH_DOVE
 483         bool "Marvell Dove"
 484         select ARCH_REQUIRE_GPIOLIB
 485         select CPU_PJ4
 486         select GENERIC_CLOCKEVENTS
 487         select MIGHT_HAVE_PCI
 488         select MULTI_IRQ_HANDLER
 489         select MVEBU_MBUS
 490         select PINCTRL
 491         select PINCTRL_DOVE
 492         select PLAT_ORION_LEGACY
 493         select SPARSE_IRQ
 494         select PM_GENERIC_DOMAINS if PM
 495         help
 496           Support for the Marvell Dove SoC 88AP510
 497
 498 config ARCH_KS8695
 499         bool "Micrel/Kendin KS8695"
 500         select ARCH_REQUIRE_GPIOLIB
 501         select CLKSRC_MMIO
 502         select CPU_ARM922T
 503         select GENERIC_CLOCKEVENTS
 504         select NEED_MACH_MEMORY_H
 505         help
 506           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 507           System-on-Chip devices.
 508
 509 config ARCH_W90X900
 510         bool "Nuvoton W90X900 CPU"
 511         select ARCH_REQUIRE_GPIOLIB
 512         select CLKDEV_LOOKUP
 513         select CLKSRC_MMIO
 514         select CPU_ARM926T
 515         select GENERIC_CLOCKEVENTS
 516         help
 517           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 518           At present, the w90x900 has been renamed nuc900, regarding
 519           the ARM series product line, you can login the following
 520           link address to know more.
 521
 522           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 523                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 524
 525 config ARCH_LPC32XX
 526         bool "NXP LPC32XX"
 527         select ARCH_REQUIRE_GPIOLIB
 528         select ARM_AMBA
 529         select CLKDEV_LOOKUP
 530         select CLKSRC_LPC32XX
 531         select COMMON_CLK
 532         select CPU_ARM926T
 533         select GENERIC_CLOCKEVENTS
 534         select MULTI_IRQ_HANDLER
 535         select SPARSE_IRQ
 536         select USE_OF
 537         help
 538           Support for the NXP LPC32XX family of processors
 539
 540 config ARCH_PXA
 541         bool "PXA2xx/PXA3xx-based"
 542         depends on MMU
 543         select ARCH_MTD_XIP
 544         select ARCH_REQUIRE_GPIOLIB
 545         select ARM_CPU_SUSPEND if PM
 546         select AUTO_ZRELADDR
 547         select COMMON_CLK
 548         select CLKDEV_LOOKUP
 549         select CLKSRC_PXA
 550         select CLKSRC_MMIO
 551         select CLKSRC_OF
 552         select CPU_XSCALE if !CPU_XSC3
 553         select GENERIC_CLOCKEVENTS
 554         select GPIO_PXA
 555         select HAVE_IDE
 556         select IRQ_DOMAIN
 557         select MULTI_IRQ_HANDLER
 558         select PLAT_PXA
 559         select SPARSE_IRQ
 560         help
 561           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 562
 563 config ARCH_RPC
 564         bool "RiscPC"
 565         depends on MMU
 566         select ARCH_ACORN
 567         select ARCH_MAY_HAVE_PC_FDC
 568         select ARCH_SPARSEMEM_ENABLE
 569         select ARCH_USES_GETTIMEOFFSET
 570         select CPU_SA110
 571         select FIQ
 572         select HAVE_IDE
 573         select HAVE_PATA_PLATFORM
 574         select ISA_DMA_API
 575         select NEED_MACH_IO_H
 576         select NEED_MACH_MEMORY_H
 577         select NO_IOPORT_MAP
 578         help
 579           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 580           CD-ROM interface, serial and parallel port, and the floppy drive.
 581
 582 config ARCH_SA1100
 583         bool "SA1100-based"
 584         select ARCH_MTD_XIP
 585         select ARCH_REQUIRE_GPIOLIB
 586         select ARCH_SPARSEMEM_ENABLE
 587         select CLKDEV_LOOKUP
 588         select CLKSRC_MMIO
 589         select CLKSRC_PXA
 590         select CLKSRC_OF if OF
 591         select CPU_FREQ
 592         select CPU_SA1100
 593         select GENERIC_CLOCKEVENTS
 594         select HAVE_IDE
 595         select IRQ_DOMAIN
 596         select ISA
 597         select MULTI_IRQ_HANDLER
 598         select NEED_MACH_MEMORY_H
 599         select SPARSE_IRQ
 600         help
 601           Support for StrongARM 11x0 based boards.
 602
 603 config ARCH_S3C24XX
 604         bool "Samsung S3C24XX SoCs"
 605         select ARCH_REQUIRE_GPIOLIB
 606         select ATAGS
 607         select CLKDEV_LOOKUP
 608         select CLKSRC_SAMSUNG_PWM
 609         select GENERIC_CLOCKEVENTS
 610         select GPIO_SAMSUNG
 611         select HAVE_S3C2410_I2C if I2C
 612         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 613         select HAVE_S3C_RTC if RTC_CLASS
 614         select MULTI_IRQ_HANDLER
 615         select NEED_MACH_IO_H
 616         select SAMSUNG_ATAGS
 617         help
 618           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 619           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 620           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 621           Samsung SMDK2410 development board (and derivatives).
 622
 623 config ARCH_DAVINCI
 624         bool "TI DaVinci"
 625         select ARCH_HAS_HOLES_MEMORYMODEL
 626         select ARCH_REQUIRE_GPIOLIB
 627         select CLKDEV_LOOKUP
 628         select CPU_ARM926T
 629         select GENERIC_ALLOCATOR
 630         select GENERIC_CLOCKEVENTS
 631         select GENERIC_IRQ_CHIP
 632         select HAVE_IDE
 633         select USE_OF
 634         select ZONE_DMA
 635         help
 636           Support for TI's DaVinci platform.
 637
 638 config ARCH_OMAP1
 639         bool "TI OMAP1"
 640         depends on MMU
 641         select ARCH_HAS_HOLES_MEMORYMODEL
 642         select ARCH_OMAP
 643         select ARCH_REQUIRE_GPIOLIB
 644         select CLKDEV_LOOKUP
 645         select CLKSRC_MMIO
 646         select GENERIC_CLOCKEVENTS
 647         select GENERIC_IRQ_CHIP
 648         select HAVE_IDE
 649         select IRQ_DOMAIN
 650         select MULTI_IRQ_HANDLER
 651         select NEED_MACH_IO_H if PCCARD
 652         select NEED_MACH_MEMORY_H
 653         select SPARSE_IRQ
 654         help
 655           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 656
 657 endchoice
 658
 659 menu "Multiple platform selection"
 660         depends on ARCH_MULTIPLATFORM
 661
 662 comment "CPU Core family selection"
 663
 664 config ARCH_MULTI_V4
 665         bool "ARMv4 based platforms (FA526)"
 666         depends on !ARCH_MULTI_V6_V7
 667         select ARCH_MULTI_V4_V5
 668         select CPU_FA526
 669
 670 config ARCH_MULTI_V4T
 671         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 672         depends on !ARCH_MULTI_V6_V7
 673         select ARCH_MULTI_V4_V5
 674         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 675                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 676                 CPU_ARM925T || CPU_ARM940T)
 677
 678 config ARCH_MULTI_V5
 679         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 680         depends on !ARCH_MULTI_V6_V7
 681         select ARCH_MULTI_V4_V5
 682         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 683                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 684                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 685
 686 config ARCH_MULTI_V4_V5
 687         bool
 688
 689 config ARCH_MULTI_V6
 690         bool "ARMv6 based platforms (ARM11)"
 691         select ARCH_MULTI_V6_V7
 692         select CPU_V6K
 693
 694 config ARCH_MULTI_V7
 695         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 696         default y
 697         select ARCH_MULTI_V6_V7
 698         select CPU_V7
 699         select HAVE_SMP
 700
 701 config ARCH_MULTI_V6_V7
 702         bool
 703         select MIGHT_HAVE_CACHE_L2X0
 704
 705 config ARCH_MULTI_CPU_AUTO
 706         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 707         select ARCH_MULTI_V5
 708
 709 endmenu
 710
 711 config ARCH_VIRT
 712         bool "Dummy Virtual Machine"
 713         depends on ARCH_MULTI_V7
 714         select ARM_AMBA
 715         select ARM_GIC
 716         select ARM_GIC_V2M if PCI_MSI
 717         select ARM_GIC_V3
 718         select ARM_PSCI
 719         select HAVE_ARM_ARCH_TIMER
 720
 721 #
 722 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 723 # Kconfigs may be included either alphabetically (according to the
 724 # plat- suffix) or along side the corresponding mach-* source.
 725 #
 726 source "arch/arm/mach-mvebu/Kconfig"
 727
 728 source "arch/arm/mach-alpine/Kconfig"
 729
 730 source "arch/arm/mach-artpec/Kconfig"
 731
 732 source "arch/arm/mach-asm9260/Kconfig"
 733
 734 source "arch/arm/mach-at91/Kconfig"
 735
 736 source "arch/arm/mach-axxia/Kconfig"
 737
 738 source "arch/arm/mach-bcm/Kconfig"
 739
 740 source "arch/arm/mach-berlin/Kconfig"
 741
 742 source "arch/arm/mach-clps711x/Kconfig"
 743
 744 source "arch/arm/mach-cns3xxx/Kconfig"
 745
 746 source "arch/arm/mach-davinci/Kconfig"
 747
 748 source "arch/arm/mach-digicolor/Kconfig"
 749
 750 source "arch/arm/mach-dove/Kconfig"
 751
 752 source "arch/arm/mach-ep93xx/Kconfig"
 753
 754 source "arch/arm/mach-footbridge/Kconfig"
 755
 756 source "arch/arm/mach-gemini/Kconfig"
 757
 758 source "arch/arm/mach-highbank/Kconfig"
 759
 760 source "arch/arm/mach-hisi/Kconfig"
 761
 762 source "arch/arm/mach-integrator/Kconfig"
 763
 764 source "arch/arm/mach-iop32x/Kconfig"
 765
 766 source "arch/arm/mach-iop33x/Kconfig"
 767
 768 source "arch/arm/mach-iop13xx/Kconfig"
 769
 770 source "arch/arm/mach-ixp4xx/Kconfig"
 771
 772 source "arch/arm/mach-keystone/Kconfig"
 773
 774 source "arch/arm/mach-ks8695/Kconfig"
 775
 776 source "arch/arm/mach-meson/Kconfig"
 777
 778 source "arch/arm/mach-moxart/Kconfig"
 779
 780 source "arch/arm/mach-aspeed/Kconfig"
 781
 782 source "arch/arm/mach-mv78xx0/Kconfig"
 783
 784 source "arch/arm/mach-imx/Kconfig"
 785
 786 source "arch/arm/mach-mediatek/Kconfig"
 787
 788 source "arch/arm/mach-mxs/Kconfig"
 789
 790 source "arch/arm/mach-netx/Kconfig"
 791
 792 source "arch/arm/mach-nomadik/Kconfig"
 793
 794 source "arch/arm/mach-nspire/Kconfig"
 795
 796 source "arch/arm/plat-omap/Kconfig"
 797
 798 source "arch/arm/mach-omap1/Kconfig"
 799
 800 source "arch/arm/mach-omap2/Kconfig"
 801
 802 source "arch/arm/mach-orion5x/Kconfig"
 803
 804 source "arch/arm/mach-picoxcell/Kconfig"
 805
 806 source "arch/arm/mach-pxa/Kconfig"
 807 source "arch/arm/plat-pxa/Kconfig"
 808
 809 source "arch/arm/mach-mmp/Kconfig"
 810
 811 source "arch/arm/mach-oxnas/Kconfig"
 812
 813 source "arch/arm/mach-qcom/Kconfig"
 814
 815 source "arch/arm/mach-realview/Kconfig"
 816
 817 source "arch/arm/mach-rockchip/Kconfig"
 818
 819 source "arch/arm/mach-sa1100/Kconfig"
 820
 821 source "arch/arm/mach-socfpga/Kconfig"
 822
 823 source "arch/arm/mach-spear/Kconfig"
 824
 825 source "arch/arm/mach-sti/Kconfig"
 826
 827 source "arch/arm/mach-s3c24xx/Kconfig"
 828
 829 source "arch/arm/mach-s3c64xx/Kconfig"
 830
 831 source "arch/arm/mach-s5pv210/Kconfig"
 832
 833 source "arch/arm/mach-exynos/Kconfig"
 834 source "arch/arm/plat-samsung/Kconfig"
 835
 836 source "arch/arm/mach-shmobile/Kconfig"
 837
 838 source "arch/arm/mach-sunxi/Kconfig"
 839
 840 source "arch/arm/mach-prima2/Kconfig"
 841
 842 source "arch/arm/mach-tango/Kconfig"
 843
 844 source "arch/arm/mach-tegra/Kconfig"
 845
 846 source "arch/arm/mach-u300/Kconfig"
 847
 848 source "arch/arm/mach-uniphier/Kconfig"
 849
 850 source "arch/arm/mach-ux500/Kconfig"
 851
 852 source "arch/arm/mach-versatile/Kconfig"
 853
 854 source "arch/arm/mach-vexpress/Kconfig"
 855 source "arch/arm/plat-versatile/Kconfig"
 856
 857 source "arch/arm/mach-vt8500/Kconfig"
 858
 859 source "arch/arm/mach-w90x900/Kconfig"
 860
 861 source "arch/arm/mach-zx/Kconfig"
 862
 863 source "arch/arm/mach-zynq/Kconfig"
 864
 865 # ARMv7-M architecture
 866 config ARCH_EFM32
 867         bool "Energy Micro efm32"
 868         depends on ARM_SINGLE_ARMV7M
 869         select ARCH_REQUIRE_GPIOLIB
 870         help
 871           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 872           processors.
 873
 874 config ARCH_LPC18XX
 875         bool "NXP LPC18xx/LPC43xx"
 876         depends on ARM_SINGLE_ARMV7M
 877         select ARCH_HAS_RESET_CONTROLLER
 878         select ARM_AMBA
 879         select CLKSRC_LPC32XX
 880         select PINCTRL
 881         help
 882           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 883           high performance microcontrollers.
 884
 885 config ARCH_STM32
 886         bool "STMicrolectronics STM32"
 887         depends on ARM_SINGLE_ARMV7M
 888         select ARCH_HAS_RESET_CONTROLLER
 889         select ARMV7M_SYSTICK
 890         select CLKSRC_STM32
 891         select PINCTRL
 892         select RESET_CONTROLLER
 893         help
 894           Support for STMicroelectronics STM32 processors.
 895
 896 config MACH_STM32F429
 897         bool "STMicrolectronics STM32F429"
 898         depends on ARCH_STM32
 899         default y
 900
 901 config ARCH_MPS2
 902         bool "ARM MPS2 paltform"
 903         depends on ARM_SINGLE_ARMV7M
 904         select ARM_AMBA
 905         select CLKSRC_MPS2
 906         help
 907           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 908           with a range of available cores like Cortex-M3/M4/M7.
 909
 910           Please, note that depends which Application Note is used memory map
 911           for the platform may vary, so adjustment of RAM base might be needed.
 912
 913 # Definitions to make life easier
 914 config ARCH_ACORN
 915         bool
 916
 917 config PLAT_IOP
 918         bool
 919         select GENERIC_CLOCKEVENTS
 920
 921 config PLAT_ORION
 922         bool
 923         select CLKSRC_MMIO
 924         select COMMON_CLK
 925         select GENERIC_IRQ_CHIP
 926         select IRQ_DOMAIN
 927
 928 config PLAT_ORION_LEGACY
 929         bool
 930         select PLAT_ORION
 931
 932 config PLAT_PXA
 933         bool
 934
 935 config PLAT_VERSATILE
 936         bool
 937
 938 source "arch/arm/firmware/Kconfig"
 939
 940 source arch/arm/mm/Kconfig
 941
 942 config IWMMXT
 943         bool "Enable iWMMXt support"
 944         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 945         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 946         help
 947           Enable support for iWMMXt context switching at run time if
 948           running on a CPU that supports it.
 949
 950 config MULTI_IRQ_HANDLER
 951         bool
 952         help
 953           Allow each machine to specify it's own IRQ handler at run time.
 954
 955 if !MMU
 956 source "arch/arm/Kconfig-nommu"
 957 endif
 958
 959 config PJ4B_ERRATA_4742
 960         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 961         depends on CPU_PJ4B && MACH_ARMADA_370
 962         default y
 963         help
 964           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 965           Event (WFE) IDLE states, a specific timing sensitivity exists between
 966           the retiring WFI/WFE instructions and the newly issued subsequent
 967           instructions.  This sensitivity can result in a CPU hang scenario.
 968           Workaround:
 969           The software must insert either a Data Synchronization Barrier (DSB)
 970           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 971           instruction
 972
 973 config ARM_ERRATA_326103
 974         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 975         depends on CPU_V6
 976         help
 977           Executing a SWP instruction to read-only memory does not set bit 11
 978           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 979           treat the access as a read, preventing a COW from occurring and
 980           causing the faulting task to livelock.
 981
 982 config ARM_ERRATA_411920
 983         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 984         depends on CPU_V6 || CPU_V6K
 985         help
 986           Invalidation of the Instruction Cache operation can
 987           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 988           It does not affect the MPCore. This option enables the ARM Ltd.
 989           recommended workaround.
 990
 991 config ARM_ERRATA_430973
 992         bool "ARM errata: Stale prediction on replaced interworking branch"
 993         depends on CPU_V7
 994         help
 995           This option enables the workaround for the 430973 Cortex-A8
 996           r1p* erratum. If a code sequence containing an ARM/Thumb
 997           interworking branch is replaced with another code sequence at the
 998           same virtual address, whether due to self-modifying code or virtual
 999           to physical address re-mapping, Cortex-A8 does not recover from the
1000           stale interworking branch prediction. This results in Cortex-A8
1001           executing the new code sequence in the incorrect ARM or Thumb state.
1002           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1003           and also flushes the branch target cache at every context switch.
1004           Note that setting specific bits in the ACTLR register may not be
1005           available in non-secure mode.
1006
1007 config ARM_ERRATA_458693
1008         bool "ARM errata: Processor deadlock when a false hazard is created"
1009         depends on CPU_V7
1010         depends on !ARCH_MULTIPLATFORM
1011         help
1012           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1013           erratum. For very specific sequences of memory operations, it is
1014           possible for a hazard condition intended for a cache line to instead
1015           be incorrectly associated with a different cache line. This false
1016           hazard might then cause a processor deadlock. The workaround enables
1017           the L1 caching of the NEON accesses and disables the PLD instruction
1018           in the ACTLR register. Note that setting specific bits in the ACTLR
1019           register may not be available in non-secure mode.
1020
1021 config ARM_ERRATA_460075
1022         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1023         depends on CPU_V7
1024         depends on !ARCH_MULTIPLATFORM
1025         help
1026           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1027           erratum. Any asynchronous access to the L2 cache may encounter a
1028           situation in which recent store transactions to the L2 cache are lost
1029           and overwritten with stale memory contents from external memory. The
1030           workaround disables the write-allocate mode for the L2 cache via the
1031           ACTLR register. Note that setting specific bits in the ACTLR register
1032           may not be available in non-secure mode.
1033
1034 config ARM_ERRATA_742230
1035         bool "ARM errata: DMB operation may be faulty"
1036         depends on CPU_V7 && SMP
1037         depends on !ARCH_MULTIPLATFORM
1038         help
1039           This option enables the workaround for the 742230 Cortex-A9
1040           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1041           between two write operations may not ensure the correct visibility
1042           ordering of the two writes. This workaround sets a specific bit in
1043           the diagnostic register of the Cortex-A9 which causes the DMB
1044           instruction to behave as a DSB, ensuring the correct behaviour of
1045           the two writes.
1046
1047 config ARM_ERRATA_742231
1048         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1049         depends on CPU_V7 && SMP
1050         depends on !ARCH_MULTIPLATFORM
1051         help
1052           This option enables the workaround for the 742231 Cortex-A9
1053           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1054           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1055           accessing some data located in the same cache line, may get corrupted
1056           data due to bad handling of the address hazard when the line gets
1057           replaced from one of the CPUs at the same time as another CPU is
1058           accessing it. This workaround sets specific bits in the diagnostic
1059           register of the Cortex-A9 which reduces the linefill issuing
1060           capabilities of the processor.
1061
1062 config ARM_ERRATA_643719
1063         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1064         depends on CPU_V7 && SMP
1065         default y
1066         help
1067           This option enables the workaround for the 643719 Cortex-A9 (prior to
1068           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1069           register returns zero when it should return one. The workaround
1070           corrects this value, ensuring cache maintenance operations which use
1071           it behave as intended and avoiding data corruption.
1072
1073 config ARM_ERRATA_720789
1074         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1075         depends on CPU_V7
1076         help
1077           This option enables the workaround for the 720789 Cortex-A9 (prior to
1078           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1079           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1080           As a consequence of this erratum, some TLB entries which should be
1081           invalidated are not, resulting in an incoherency in the system page
1082           tables. The workaround changes the TLB flushing routines to invalidate
1083           entries regardless of the ASID.
1084
1085 config ARM_ERRATA_743622
1086         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1087         depends on CPU_V7
1088         depends on !ARCH_MULTIPLATFORM
1089         help
1090           This option enables the workaround for the 743622 Cortex-A9
1091           (r2p*) erratum. Under very rare conditions, a faulty
1092           optimisation in the Cortex-A9 Store Buffer may lead to data
1093           corruption. This workaround sets a specific bit in the diagnostic
1094           register of the Cortex-A9 which disables the Store Buffer
1095           optimisation, preventing the defect from occurring. This has no
1096           visible impact on the overall performance or power consumption of the
1097           processor.
1098
1099 config ARM_ERRATA_751472
1100         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1101         depends on CPU_V7
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 751472 Cortex-A9 (prior
1105           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1106           completion of a following broadcasted operation if the second
1107           operation is received by a CPU before the ICIALLUIS has completed,
1108           potentially leading to corrupted entries in the cache or TLB.
1109
1110 config ARM_ERRATA_754322
1111         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1112         depends on CPU_V7
1113         help
1114           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1115           r3p*) erratum. A speculative memory access may cause a page table walk
1116           which starts prior to an ASID switch but completes afterwards. This
1117           can populate the micro-TLB with a stale entry which may be hit with
1118           the new ASID. This workaround places two dsb instructions in the mm
1119           switching code so that no page table walks can cross the ASID switch.
1120
1121 config ARM_ERRATA_754327
1122         bool "ARM errata: no automatic Store Buffer drain"
1123         depends on CPU_V7 && SMP
1124         help
1125           This option enables the workaround for the 754327 Cortex-A9 (prior to
1126           r2p0) erratum. The Store Buffer does not have any automatic draining
1127           mechanism and therefore a livelock may occur if an external agent
1128           continuously polls a memory location waiting to observe an update.
1129           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1130           written polling loops from denying visibility of updates to memory.
1131
1132 config ARM_ERRATA_364296
1133         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1134         depends on CPU_V6
1135         help
1136           This options enables the workaround for the 364296 ARM1136
1137           r0p2 erratum (possible cache data corruption with
1138           hit-under-miss enabled). It sets the undocumented bit 31 in
1139           the auxiliary control register and the FI bit in the control
1140           register, thus disabling hit-under-miss without putting the
1141           processor into full low interrupt latency mode. ARM11MPCore
1142           is not affected.
1143
1144 config ARM_ERRATA_764369
1145         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1146         depends on CPU_V7 && SMP
1147         help
1148           This option enables the workaround for erratum 764369
1149           affecting Cortex-A9 MPCore with two or more processors (all
1150           current revisions). Under certain timing circumstances, a data
1151           cache line maintenance operation by MVA targeting an Inner
1152           Shareable memory region may fail to proceed up to either the
1153           Point of Coherency or to the Point of Unification of the
1154           system. This workaround adds a DSB instruction before the
1155           relevant cache maintenance functions and sets a specific bit
1156           in the diagnostic control register of the SCU.
1157
1158 config ARM_ERRATA_775420
1159        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1160        depends on CPU_V7
1161        help
1162          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1163          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1164          operation aborts with MMU exception, it might cause the processor
1165          to deadlock. This workaround puts DSB before executing ISB if
1166          an abort may occur on cache maintenance.
1167
1168 config ARM_ERRATA_798181
1169         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1170         depends on CPU_V7 && SMP
1171         help
1172           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1173           adequately shooting down all use of the old entries. This
1174           option enables the Linux kernel workaround for this erratum
1175           which sends an IPI to the CPUs that are running the same ASID
1176           as the one being invalidated.
1177
1178 config ARM_ERRATA_773022
1179         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1180         depends on CPU_V7
1181         help
1182           This option enables the workaround for the 773022 Cortex-A15
1183           (up to r0p4) erratum. In certain rare sequences of code, the
1184           loop buffer may deliver incorrect instructions. This
1185           workaround disables the loop buffer to avoid the erratum.
1186
1187 endmenu
1188
1189 source "arch/arm/common/Kconfig"
1190
1191 menu "Bus support"
1192
1193 config ISA
1194         bool
1195         help
1196           Find out whether you have ISA slots on your motherboard.  ISA is the
1197           name of a bus system, i.e. the way the CPU talks to the other stuff
1198           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1199           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1200           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1201
1202 # Select ISA DMA controller support
1203 config ISA_DMA
1204         bool
1205         select ISA_DMA_API
1206
1207 # Select ISA DMA interface
1208 config ISA_DMA_API
1209         bool
1210
1211 config PCI
1212         bool "PCI support" if MIGHT_HAVE_PCI
1213         help
1214           Find out whether you have a PCI motherboard. PCI is the name of a
1215           bus system, i.e. the way the CPU talks to the other stuff inside
1216           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1217           VESA. If you have PCI, say Y, otherwise N.
1218
1219 config PCI_DOMAINS
1220         bool
1221         depends on PCI
1222
1223 config PCI_DOMAINS_GENERIC
1224         def_bool PCI_DOMAINS
1225
1226 config PCI_NANOENGINE
1227         bool "BSE nanoEngine PCI support"
1228         depends on SA1100_NANOENGINE
1229         help
1230           Enable PCI on the BSE nanoEngine board.
1231
1232 config PCI_SYSCALL
1233         def_bool PCI
1234
1235 config PCI_HOST_ITE8152
1236         bool
1237         depends on PCI && MACH_ARMCORE
1238         default y
1239         select DMABOUNCE
1240
1241 source "drivers/pci/Kconfig"
1242
1243 source "drivers/pcmcia/Kconfig"
1244
1245 endmenu
1246
1247 menu "Kernel Features"
1248
1249 config HAVE_SMP
1250         bool
1251         help
1252           This option should be selected by machines which have an SMP-
1253           capable CPU.
1254
1255           The only effect of this option is to make the SMP-related
1256           options available to the user for configuration.
1257
1258 config SMP
1259         bool "Symmetric Multi-Processing"
1260         depends on CPU_V6K || CPU_V7
1261         depends on GENERIC_CLOCKEVENTS
1262         depends on HAVE_SMP
1263         depends on MMU || ARM_MPU
1264         select IRQ_WORK
1265         help
1266           This enables support for systems with more than one CPU. If you have
1267           a system with only one CPU, say N. If you have a system with more
1268           than one CPU, say Y.
1269
1270           If you say N here, the kernel will run on uni- and multiprocessor
1271           machines, but will use only one CPU of a multiprocessor machine. If
1272           you say Y here, the kernel will run on many, but not all,
1273           uniprocessor machines. On a uniprocessor machine, the kernel
1274           will run faster if you say N here.
1275
1276           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1277           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1278           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1279
1280           If you don't know what to do here, say N.
1281
1282 config SMP_ON_UP
1283         bool "Allow booting SMP kernel on uniprocessor systems"
1284         depends on SMP && !XIP_KERNEL && MMU
1285         default y
1286         help
1287           SMP kernels contain instructions which fail on non-SMP processors.
1288           Enabling this option allows the kernel to modify itself to make
1289           these instructions safe.  Disabling it allows about 1K of space
1290           savings.
1291
1292           If you don't know what to do here, say Y.
1293
1294 config ARM_CPU_TOPOLOGY
1295         bool "Support cpu topology definition"
1296         depends on SMP && CPU_V7
1297         default y
1298         help
1299           Support ARM cpu topology definition. The MPIDR register defines
1300           affinity between processors which is then used to describe the cpu
1301           topology of an ARM System.
1302
1303 config SCHED_MC
1304         bool "Multi-core scheduler support"
1305         depends on ARM_CPU_TOPOLOGY
1306         help
1307           Multi-core scheduler support improves the CPU scheduler's decision
1308           making when dealing with multi-core CPU chips at a cost of slightly
1309           increased overhead in some places. If unsure say N here.
1310
1311 config SCHED_SMT
1312         bool "SMT scheduler support"
1313         depends on ARM_CPU_TOPOLOGY
1314         help
1315           Improves the CPU scheduler's decision making when dealing with
1316           MultiThreading at a cost of slightly increased overhead in some
1317           places. If unsure say N here.
1318
1319 config HAVE_ARM_SCU
1320         bool
1321         help
1322           This option enables support for the ARM system coherency unit
1323
1324 config HAVE_ARM_ARCH_TIMER
1325         bool "Architected timer support"
1326         depends on CPU_V7
1327         select ARM_ARCH_TIMER
1328         select GENERIC_CLOCKEVENTS
1329         help
1330           This option enables support for the ARM architected timer
1331
1332 config HAVE_ARM_TWD
1333         bool
1334         select CLKSRC_OF if OF
1335         help
1336           This options enables support for the ARM timer and watchdog unit
1337
1338 config MCPM
1339         bool "Multi-Cluster Power Management"
1340         depends on CPU_V7 && SMP
1341         help
1342           This option provides the common power management infrastructure
1343           for (multi-)cluster based systems, such as big.LITTLE based
1344           systems.
1345
1346 config MCPM_QUAD_CLUSTER
1347         bool
1348         depends on MCPM
1349         help
1350           To avoid wasting resources unnecessarily, MCPM only supports up
1351           to 2 clusters by default.
1352           Platforms with 3 or 4 clusters that use MCPM must select this
1353           option to allow the additional clusters to be managed.
1354
1355 config BIG_LITTLE
1356         bool "big.LITTLE support (Experimental)"
1357         depends on CPU_V7 && SMP
1358         select MCPM
1359         help
1360           This option enables support selections for the big.LITTLE
1361           system architecture.
1362
1363 config BL_SWITCHER
1364         bool "big.LITTLE switcher support"
1365         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1366         select CPU_PM
1367         help
1368           The big.LITTLE "switcher" provides the core functionality to
1369           transparently handle transition between a cluster of A15's
1370           and a cluster of A7's in a big.LITTLE system.
1371
1372 config BL_SWITCHER_DUMMY_IF
1373         tristate "Simple big.LITTLE switcher user interface"
1374         depends on BL_SWITCHER && DEBUG_KERNEL
1375         help
1376           This is a simple and dummy char dev interface to control
1377           the big.LITTLE switcher core code.  It is meant for
1378           debugging purposes only.
1379
1380 choice
1381         prompt "Memory split"
1382         depends on MMU
1383         default VMSPLIT_3G
1384         help
1385           Select the desired split between kernel and user memory.
1386
1387           If you are not absolutely sure what you are doing, leave this
1388           option alone!
1389
1390         config VMSPLIT_3G
1391                 bool "3G/1G user/kernel split"
1392         config VMSPLIT_3G_OPT
1393                 bool "3G/1G user/kernel split (for full 1G low memory)"
1394         config VMSPLIT_2G
1395                 bool "2G/2G user/kernel split"
1396         config VMSPLIT_1G
1397                 bool "1G/3G user/kernel split"
1398 endchoice
1399
1400 config PAGE_OFFSET
1401         hex
1402         default PHYS_OFFSET if !MMU
1403         default 0x40000000 if VMSPLIT_1G
1404         default 0x80000000 if VMSPLIT_2G
1405         default 0xB0000000 if VMSPLIT_3G_OPT
1406         default 0xC0000000
1407
1408 config NR_CPUS
1409         int "Maximum number of CPUs (2-32)"
1410         range 2 32
1411         depends on SMP
1412         default "4"
1413
1414 config HOTPLUG_CPU
1415         bool "Support for hot-pluggable CPUs"
1416         depends on SMP
1417         help
1418           Say Y here to experiment with turning CPUs off and on.  CPUs
1419           can be controlled through /sys/devices/system/cpu.
1420
1421 config ARM_PSCI
1422         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1423         depends on HAVE_ARM_SMCCC
1424         select ARM_PSCI_FW
1425         help
1426           Say Y here if you want Linux to communicate with system firmware
1427           implementing the PSCI specification for CPU-centric power
1428           management operations described in ARM document number ARM DEN
1429           0022A ("Power State Coordination Interface System Software on
1430           ARM processors").
1431
1432 # The GPIO number here must be sorted by descending number. In case of
1433 # a multiplatform kernel, we just want the highest value required by the
1434 # selected platforms.
1435 config ARCH_NR_GPIO
1436         int
1437         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1438                 ARCH_ZYNQ
1439         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1440                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1441         default 416 if ARCH_SUNXI
1442         default 392 if ARCH_U8500
1443         default 352 if ARCH_VT8500
1444         default 288 if ARCH_ROCKCHIP
1445         default 264 if MACH_H4700
1446         default 0
1447         help
1448           Maximum number of GPIOs in the system.
1449
1450           If unsure, leave the default value.
1451
1452 source kernel/Kconfig.preempt
1453
1454 config HZ_FIXED
1455         int
1456         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1457                 ARCH_S5PV210 || ARCH_EXYNOS4
1458         default 128 if SOC_AT91RM9200
1459         default 0
1460
1461 choice
1462         depends on HZ_FIXED = 0
1463         prompt "Timer frequency"
1464
1465 config HZ_100
1466         bool "100 Hz"
1467
1468 config HZ_200
1469         bool "200 Hz"
1470
1471 config HZ_250
1472         bool "250 Hz"
1473
1474 config HZ_300
1475         bool "300 Hz"
1476
1477 config HZ_500
1478         bool "500 Hz"
1479
1480 config HZ_1000
1481         bool "1000 Hz"
1482
1483 endchoice
1484
1485 config HZ
1486         int
1487         default HZ_FIXED if HZ_FIXED != 0
1488         default 100 if HZ_100
1489         default 200 if HZ_200
1490         default 250 if HZ_250
1491         default 300 if HZ_300
1492         default 500 if HZ_500
1493         default 1000
1494
1495 config SCHED_HRTICK
1496         def_bool HIGH_RES_TIMERS
1497
1498 config THUMB2_KERNEL
1499         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1500         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1501         default y if CPU_THUMBONLY
1502         select AEABI
1503         select ARM_ASM_UNIFIED
1504         select ARM_UNWIND
1505         help
1506           By enabling this option, the kernel will be compiled in
1507           Thumb-2 mode. A compiler/assembler that understand the unified
1508           ARM-Thumb syntax is needed.
1509
1510           If unsure, say N.
1511
1512 config THUMB2_AVOID_R_ARM_THM_JUMP11
1513         bool "Work around buggy Thumb-2 short branch relocations in gas"
1514         depends on THUMB2_KERNEL && MODULES
1515         default y
1516         help
1517           Various binutils versions can resolve Thumb-2 branches to
1518           locally-defined, preemptible global symbols as short-range "b.n"
1519           branch instructions.
1520
1521           This is a problem, because there's no guarantee the final
1522           destination of the symbol, or any candidate locations for a
1523           trampoline, are within range of the branch.  For this reason, the
1524           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1525           relocation in modules at all, and it makes little sense to add
1526           support.
1527
1528           The symptom is that the kernel fails with an "unsupported
1529           relocation" error when loading some modules.
1530
1531           Until fixed tools are available, passing
1532           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1533           code which hits this problem, at the cost of a bit of extra runtime
1534           stack usage in some cases.
1535
1536           The problem is described in more detail at:
1537               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1538
1539           Only Thumb-2 kernels are affected.
1540
1541           Unless you are sure your tools don't have this problem, say Y.
1542
1543 config ARM_ASM_UNIFIED
1544         bool
1545
1546 config ARM_PATCH_IDIV
1547         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1548         depends on CPU_32v7 && !XIP_KERNEL
1549         default y
1550         help
1551           The ARM compiler inserts calls to __aeabi_idiv() and
1552           __aeabi_uidiv() when it needs to perform division on signed
1553           and unsigned integers. Some v7 CPUs have support for the sdiv
1554           and udiv instructions that can be used to implement those
1555           functions.
1556
1557           Enabling this option allows the kernel to modify itself to
1558           replace the first two instructions of these library functions
1559           with the sdiv or udiv plus "bx lr" instructions when the CPU
1560           it is running on supports them. Typically this will be faster
1561           and less power intensive than running the original library
1562           code to do integer division.
1563
1564 config AEABI
1565         bool "Use the ARM EABI to compile the kernel"
1566         help
1567           This option allows for the kernel to be compiled using the latest
1568           ARM ABI (aka EABI).  This is only useful if you are using a user
1569           space environment that is also compiled with EABI.
1570
1571           Since there are major incompatibilities between the legacy ABI and
1572           EABI, especially with regard to structure member alignment, this
1573           option also changes the kernel syscall calling convention to
1574           disambiguate both ABIs and allow for backward compatibility support
1575           (selected with CONFIG_OABI_COMPAT).
1576
1577           To use this you need GCC version 4.0.0 or later.
1578
1579 config OABI_COMPAT
1580         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1581         depends on AEABI && !THUMB2_KERNEL
1582         help
1583           This option preserves the old syscall interface along with the
1584           new (ARM EABI) one. It also provides a compatibility layer to
1585           intercept syscalls that have structure arguments which layout
1586           in memory differs between the legacy ABI and the new ARM EABI
1587           (only for non "thumb" binaries). This option adds a tiny
1588           overhead to all syscalls and produces a slightly larger kernel.
1589
1590           The seccomp filter system will not be available when this is
1591           selected, since there is no way yet to sensibly distinguish
1592           between calling conventions during filtering.
1593
1594           If you know you'll be using only pure EABI user space then you
1595           can say N here. If this option is not selected and you attempt
1596           to execute a legacy ABI binary then the result will be
1597           UNPREDICTABLE (in fact it can be predicted that it won't work
1598           at all). If in doubt say N.
1599
1600 config ARCH_HAS_HOLES_MEMORYMODEL
1601         bool
1602
1603 config ARCH_SPARSEMEM_ENABLE
1604         bool
1605
1606 config ARCH_SPARSEMEM_DEFAULT
1607         def_bool ARCH_SPARSEMEM_ENABLE
1608
1609 config ARCH_SELECT_MEMORY_MODEL
1610         def_bool ARCH_SPARSEMEM_ENABLE
1611
1612 config HAVE_ARCH_PFN_VALID
1613         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1614
1615 config HAVE_GENERIC_RCU_GUP
1616         def_bool y
1617         depends on ARM_LPAE
1618
1619 config HIGHMEM
1620         bool "High Memory Support"
1621         depends on MMU
1622         help
1623           The address space of ARM processors is only 4 Gigabytes large
1624           and it has to accommodate user address space, kernel address
1625           space as well as some memory mapped IO. That means that, if you
1626           have a large amount of physical memory and/or IO, not all of the
1627           memory can be "permanently mapped" by the kernel. The physical
1628           memory that is not permanently mapped is called "high memory".
1629
1630           Depending on the selected kernel/user memory split, minimum
1631           vmalloc space and actual amount of RAM, you may not need this
1632           option which should result in a slightly faster kernel.
1633
1634           If unsure, say n.
1635
1636 config HIGHPTE
1637         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1638         depends on HIGHMEM
1639         default y
1640         help
1641           The VM uses one page of physical memory for each page table.
1642           For systems with a lot of processes, this can use a lot of
1643           precious low memory, eventually leading to low memory being
1644           consumed by page tables.  Setting this option will allow
1645           user-space 2nd level page tables to reside in high memory.
1646
1647 config CPU_SW_DOMAIN_PAN
1648         bool "Enable use of CPU domains to implement privileged no-access"
1649         depends on MMU && !ARM_LPAE
1650         default y
1651         help
1652           Increase kernel security by ensuring that normal kernel accesses
1653           are unable to access userspace addresses.  This can help prevent
1654           use-after-free bugs becoming an exploitable privilege escalation
1655           by ensuring that magic values (such as LIST_POISON) will always
1656           fault when dereferenced.
1657
1658           CPUs with low-vector mappings use a best-efforts implementation.
1659           Their lower 1MB needs to remain accessible for the vectors, but
1660           the remainder of userspace will become appropriately inaccessible.
1661
1662 config HW_PERF_EVENTS
1663         def_bool y
1664         depends on ARM_PMU
1665
1666 config SYS_SUPPORTS_HUGETLBFS
1667        def_bool y
1668        depends on ARM_LPAE
1669
1670 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1671        def_bool y
1672        depends on ARM_LPAE
1673
1674 config ARCH_WANT_GENERAL_HUGETLB
1675         def_bool y
1676
1677 config ARM_MODULE_PLTS
1678         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1679         depends on MODULES
1680         help
1681           Allocate PLTs when loading modules so that jumps and calls whose
1682           targets are too far away for their relative offsets to be encoded
1683           in the instructions themselves can be bounced via veneers in the
1684           module's PLT. This allows modules to be allocated in the generic
1685           vmalloc area after the dedicated module memory area has been
1686           exhausted. The modules will use slightly more memory, but after
1687           rounding up to page size, the actual memory footprint is usually
1688           the same.
1689
1690           Say y if you are getting out of memory errors while loading modules
1691
1692 source "mm/Kconfig"
1693
1694 config FORCE_MAX_ZONEORDER
1695         int "Maximum zone order"
1696         default "12" if SOC_AM33XX
1697         default "9" if SA1111 || ARCH_EFM32
1698         default "11"
1699         help
1700           The kernel memory allocator divides physically contiguous memory
1701           blocks into "zones", where each zone is a power of two number of
1702           pages.  This option selects the largest power of two that the kernel
1703           keeps in the memory allocator.  If you need to allocate very large
1704           blocks of physically contiguous memory, then you may need to
1705           increase this value.
1706
1707           This config option is actually maximum order plus one. For example,
1708           a value of 11 means that the largest free memory block is 2^10 pages.
1709
1710 config ALIGNMENT_TRAP
1711         bool
1712         depends on CPU_CP15_MMU
1713         default y if !ARCH_EBSA110
1714         select HAVE_PROC_CPU if PROC_FS
1715         help
1716           ARM processors cannot fetch/store information which is not
1717           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1718           address divisible by 4. On 32-bit ARM processors, these non-aligned
1719           fetch/store instructions will be emulated in software if you say
1720           here, which has a severe performance impact. This is necessary for
1721           correct operation of some network protocols. With an IP-only
1722           configuration it is safe to say N, otherwise say Y.
1723
1724 config UACCESS_WITH_MEMCPY
1725         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1726         depends on MMU
1727         default y if CPU_FEROCEON
1728         help
1729           Implement faster copy_to_user and clear_user methods for CPU
1730           cores where a 8-word STM instruction give significantly higher
1731           memory write throughput than a sequence of individual 32bit stores.
1732
1733           A possible side effect is a slight increase in scheduling latency
1734           between threads sharing the same address space if they invoke
1735           such copy operations with large buffers.
1736
1737           However, if the CPU data cache is using a write-allocate mode,
1738           this option is unlikely to provide any performance gain.
1739
1740 config SECCOMP
1741         bool
1742         prompt "Enable seccomp to safely compute untrusted bytecode"
1743         ---help---
1744           This kernel feature is useful for number crunching applications
1745           that may need to compute untrusted bytecode during their
1746           execution. By using pipes or other transports made available to
1747           the process as file descriptors supporting the read/write
1748           syscalls, it's possible to isolate those applications in
1749           their own address space using seccomp. Once seccomp is
1750           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1751           and the task is only allowed to execute a few safe syscalls
1752           defined by each seccomp mode.
1753
1754 config SWIOTLB
1755         def_bool y
1756
1757 config IOMMU_HELPER
1758         def_bool SWIOTLB
1759
1760 config PARAVIRT
1761         bool "Enable paravirtualization code"
1762         help
1763           This changes the kernel so it can modify itself when it is run
1764           under a hypervisor, potentially improving performance significantly
1765           over full virtualization.
1766
1767 config PARAVIRT_TIME_ACCOUNTING
1768         bool "Paravirtual steal time accounting"
1769         select PARAVIRT
1770         default n
1771         help
1772           Select this option to enable fine granularity task steal time
1773           accounting. Time spent executing other tasks in parallel with
1774           the current vCPU is discounted from the vCPU power. To account for
1775           that, there can be a small performance impact.
1776
1777           If in doubt, say N here.
1778
1779 config XEN_DOM0
1780         def_bool y
1781         depends on XEN
1782
1783 config XEN
1784         bool "Xen guest support on ARM"
1785         depends on ARM && AEABI && OF
1786         depends on CPU_V7 && !CPU_V6
1787         depends on !GENERIC_ATOMIC64
1788         depends on MMU
1789         select ARCH_DMA_ADDR_T_64BIT
1790         select ARM_PSCI
1791         select SWIOTLB_XEN
1792         select PARAVIRT
1793         help
1794           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1795
1796 endmenu
1797
1798 menu "Boot options"
1799
1800 config USE_OF
1801         bool "Flattened Device Tree support"
1802         select IRQ_DOMAIN
1803         select OF
1804         help
1805           Include support for flattened device tree machine descriptions.
1806
1807 config ATAGS
1808         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1809         default y
1810         help
1811           This is the traditional way of passing data to the kernel at boot
1812           time. If you are solely relying on the flattened device tree (or
1813           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1814           to remove ATAGS support from your kernel binary.  If unsure,
1815           leave this to y.
1816
1817 config DEPRECATED_PARAM_STRUCT
1818         bool "Provide old way to pass kernel parameters"
1819         depends on ATAGS
1820         help
1821           This was deprecated in 2001 and announced to live on for 5 years.
1822           Some old boot loaders still use this way.
1823
1824 # Compressed boot loader in ROM.  Yes, we really want to ask about
1825 # TEXT and BSS so we preserve their values in the config files.
1826 config ZBOOT_ROM_TEXT
1827         hex "Compressed ROM boot loader base address"
1828         default "0"
1829         help
1830           The physical address at which the ROM-able zImage is to be
1831           placed in the target.  Platforms which normally make use of
1832           ROM-able zImage formats normally set this to a suitable
1833           value in their defconfig file.
1834
1835           If ZBOOT_ROM is not enabled, this has no effect.
1836
1837 config ZBOOT_ROM_BSS
1838         hex "Compressed ROM boot loader BSS address"
1839         default "0"
1840         help
1841           The base address of an area of read/write memory in the target
1842           for the ROM-able zImage which must be available while the
1843           decompressor is running. It must be large enough to hold the
1844           entire decompressed kernel plus an additional 128 KiB.
1845           Platforms which normally make use of ROM-able zImage formats
1846           normally set this to a suitable value in their defconfig file.
1847
1848           If ZBOOT_ROM is not enabled, this has no effect.
1849
1850 config ZBOOT_ROM
1851         bool "Compressed boot loader in ROM/flash"
1852         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1853         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1854         help
1855           Say Y here if you intend to execute your compressed kernel image
1856           (zImage) directly from ROM or flash.  If unsure, say N.
1857
1858 config ARM_APPENDED_DTB
1859         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1860         depends on OF
1861         help
1862           With this option, the boot code will look for a device tree binary
1863           (DTB) appended to zImage
1864           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1865
1866           This is meant as a backward compatibility convenience for those
1867           systems with a bootloader that can't be upgraded to accommodate
1868           the documented boot protocol using a device tree.
1869
1870           Beware that there is very little in terms of protection against
1871           this option being confused by leftover garbage in memory that might
1872           look like a DTB header after a reboot if no actual DTB is appended
1873           to zImage.  Do not leave this option active in a production kernel
1874           if you don't intend to always append a DTB.  Proper passing of the
1875           location into r2 of a bootloader provided DTB is always preferable
1876           to this option.
1877
1878 config ARM_ATAG_DTB_COMPAT
1879         bool "Supplement the appended DTB with traditional ATAG information"
1880         depends on ARM_APPENDED_DTB
1881         help
1882           Some old bootloaders can't be updated to a DTB capable one, yet
1883           they provide ATAGs with memory configuration, the ramdisk address,
1884           the kernel cmdline string, etc.  Such information is dynamically
1885           provided by the bootloader and can't always be stored in a static
1886           DTB.  To allow a device tree enabled kernel to be used with such
1887           bootloaders, this option allows zImage to extract the information
1888           from the ATAG list and store it at run time into the appended DTB.
1889
1890 choice
1891         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1892         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1893
1894 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1895         bool "Use bootloader kernel arguments if available"
1896         help
1897           Uses the command-line options passed by the boot loader instead of
1898           the device tree bootargs property. If the boot loader doesn't provide
1899           any, the device tree bootargs property will be used.
1900
1901 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1902         bool "Extend with bootloader kernel arguments"
1903         help
1904           The command-line arguments provided by the boot loader will be
1905           appended to the the device tree bootargs property.
1906
1907 endchoice
1908
1909 config CMDLINE
1910         string "Default kernel command string"
1911         default ""
1912         help
1913           On some architectures (EBSA110 and CATS), there is currently no way
1914           for the boot loader to pass arguments to the kernel. For these
1915           architectures, you should supply some command-line options at build
1916           time by entering them here. As a minimum, you should specify the
1917           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1918
1919 choice
1920         prompt "Kernel command line type" if CMDLINE != ""
1921         default CMDLINE_FROM_BOOTLOADER
1922         depends on ATAGS
1923
1924 config CMDLINE_FROM_BOOTLOADER
1925         bool "Use bootloader kernel arguments if available"
1926         help
1927           Uses the command-line options passed by the boot loader. If
1928           the boot loader doesn't provide any, the default kernel command
1929           string provided in CMDLINE will be used.
1930
1931 config CMDLINE_EXTEND
1932         bool "Extend bootloader kernel arguments"
1933         help
1934           The command-line arguments provided by the boot loader will be
1935           appended to the default kernel command string.
1936
1937 config CMDLINE_FORCE
1938         bool "Always use the default kernel command string"
1939         help
1940           Always use the default kernel command string, even if the boot
1941           loader passes other arguments to the kernel.
1942           This is useful if you cannot or don't want to change the
1943           command-line options your boot loader passes to the kernel.
1944 endchoice
1945
1946 config XIP_KERNEL
1947         bool "Kernel Execute-In-Place from ROM"
1948         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1949         help
1950           Execute-In-Place allows the kernel to run from non-volatile storage
1951           directly addressable by the CPU, such as NOR flash. This saves RAM
1952           space since the text section of the kernel is not loaded from flash
1953           to RAM.  Read-write sections, such as the data section and stack,
1954           are still copied to RAM.  The XIP kernel is not compressed since
1955           it has to run directly from flash, so it will take more space to
1956           store it.  The flash address used to link the kernel object files,
1957           and for storing it, is configuration dependent. Therefore, if you
1958           say Y here, you must know the proper physical address where to
1959           store the kernel image depending on your own flash memory usage.
1960
1961           Also note that the make target becomes "make xipImage" rather than
1962           "make zImage" or "make Image".  The final kernel binary to put in
1963           ROM memory will be arch/arm/boot/xipImage.
1964
1965           If unsure, say N.
1966
1967 config XIP_PHYS_ADDR
1968         hex "XIP Kernel Physical Location"
1969         depends on XIP_KERNEL
1970         default "0x00080000"
1971         help
1972           This is the physical address in your flash memory the kernel will
1973           be linked for and stored to.  This address is dependent on your
1974           own flash usage.
1975
1976 config KEXEC
1977         bool "Kexec system call (EXPERIMENTAL)"
1978         depends on (!SMP || PM_SLEEP_SMP)
1979         depends on !CPU_V7M
1980         select KEXEC_CORE
1981         help
1982           kexec is a system call that implements the ability to shutdown your
1983           current kernel, and to start another kernel.  It is like a reboot
1984           but it is independent of the system firmware.   And like a reboot
1985           you can start any kernel with it, not just Linux.
1986
1987           It is an ongoing process to be certain the hardware in a machine
1988           is properly shutdown, so do not be surprised if this code does not
1989           initially work for you.
1990
1991 config ATAGS_PROC
1992         bool "Export atags in procfs"
1993         depends on ATAGS && KEXEC
1994         default y
1995         help
1996           Should the atags used to boot the kernel be exported in an "atags"
1997           file in procfs. Useful with kexec.
1998
1999 config CRASH_DUMP
2000         bool "Build kdump crash kernel (EXPERIMENTAL)"
2001         help
2002           Generate crash dump after being started by kexec. This should
2003           be normally only set in special crash dump kernels which are
2004           loaded in the main kernel with kexec-tools into a specially
2005           reserved region and then later executed after a crash by
2006           kdump/kexec. The crash dump kernel must be compiled to a
2007           memory address not used by the main kernel
2008
2009           For more details see Documentation/kdump/kdump.txt
2010
2011 config AUTO_ZRELADDR
2012         bool "Auto calculation of the decompressed kernel image address"
2013         help
2014           ZRELADDR is the physical address where the decompressed kernel
2015           image will be placed. If AUTO_ZRELADDR is selected, the address
2016           will be determined at run-time by masking the current IP with
2017           0xf8000000. This assumes the zImage being placed in the first 128MB
2018           from start of memory.
2019
2020 config EFI_STUB
2021         bool
2022
2023 config EFI
2024         bool "UEFI runtime support"
2025         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2026         select UCS2_STRING
2027         select EFI_PARAMS_FROM_FDT
2028         select EFI_STUB
2029         select EFI_ARMSTUB
2030         select EFI_RUNTIME_WRAPPERS
2031         ---help---
2032           This option provides support for runtime services provided
2033           by UEFI firmware (such as non-volatile variables, realtime
2034           clock, and platform reset). A UEFI stub is also provided to
2035           allow the kernel to be booted as an EFI application. This
2036           is only useful for kernels that may run on systems that have
2037           UEFI firmware.
2038
2039 endmenu
2040
2041 menu "CPU Power Management"
2042
2043 source "drivers/cpufreq/Kconfig"
2044
2045 source "drivers/cpuidle/Kconfig"
2046
2047 endmenu
2048
2049 menu "Floating point emulation"
2050
2051 comment "At least one emulation must be selected"
2052
2053 config FPE_NWFPE
2054         bool "NWFPE math emulation"
2055         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2056         ---help---
2057           Say Y to include the NWFPE floating point emulator in the kernel.
2058           This is necessary to run most binaries. Linux does not currently
2059           support floating point hardware so you need to say Y here even if
2060           your machine has an FPA or floating point co-processor podule.
2061
2062           You may say N here if you are going to load the Acorn FPEmulator
2063           early in the bootup.
2064
2065 config FPE_NWFPE_XP
2066         bool "Support extended precision"
2067         depends on FPE_NWFPE
2068         help
2069           Say Y to include 80-bit support in the kernel floating-point
2070           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2071           Note that gcc does not generate 80-bit operations by default,
2072           so in most cases this option only enlarges the size of the
2073           floating point emulator without any good reason.
2074
2075           You almost surely want to say N here.
2076
2077 config FPE_FASTFPE
2078         bool "FastFPE math emulation (EXPERIMENTAL)"
2079         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2080         ---help---
2081           Say Y here to include the FAST floating point emulator in the kernel.
2082           This is an experimental much faster emulator which now also has full
2083           precision for the mantissa.  It does not support any exceptions.
2084           It is very simple, and approximately 3-6 times faster than NWFPE.
2085
2086           It should be sufficient for most programs.  It may be not suitable
2087           for scientific calculations, but you have to check this for yourself.
2088           If you do not feel you need a faster FP emulation you should better
2089           choose NWFPE.
2090
2091 config VFP
2092         bool "VFP-format floating point maths"
2093         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2094         help
2095           Say Y to include VFP support code in the kernel. This is needed
2096           if your hardware includes a VFP unit.
2097
2098           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2099           release notes and additional status information.
2100
2101           Say N if your target does not have VFP hardware.
2102
2103 config VFPv3
2104         bool
2105         depends on VFP
2106         default y if CPU_V7
2107
2108 config NEON
2109         bool "Advanced SIMD (NEON) Extension support"
2110         depends on VFPv3 && CPU_V7
2111         help
2112           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2113           Extension.
2114
2115 config KERNEL_MODE_NEON
2116         bool "Support for NEON in kernel mode"
2117         depends on NEON && AEABI
2118         help
2119           Say Y to include support for NEON in kernel mode.
2120
2121 endmenu
2122
2123 menu "Userspace binary formats"
2124
2125 source "fs/Kconfig.binfmt"
2126
2127 endmenu
2128
2129 menu "Power management options"
2130
2131 source "kernel/power/Kconfig"
2132
2133 config ARCH_SUSPEND_POSSIBLE
2134         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2135                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2136         def_bool y
2137
2138 config ARM_CPU_SUSPEND
2139         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2140         depends on ARCH_SUSPEND_POSSIBLE
2141
2142 config ARCH_HIBERNATION_POSSIBLE
2143         bool
2144         depends on MMU
2145         default y if ARCH_SUSPEND_POSSIBLE
2146
2147 endmenu
2148
2149 source "net/Kconfig"
2150
2151 source "drivers/Kconfig"
2152
2153 source "drivers/firmware/Kconfig"
2154
2155 source "fs/Kconfig"
2156
2157 source "arch/arm/Kconfig.debug"
2158
2159 source "security/Kconfig"
2160
2161 source "crypto/Kconfig"
2162 if CRYPTO
2163 source "arch/arm/crypto/Kconfig"
2164 endif
2165
2166 source "lib/Kconfig"
2167
2168 source "arch/arm/kvm/Kconfig"