5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select NO_MACH_MEMORY_H
329 Support for Broadcom's BCMRing platform.
332 bool "Cirrus Logic CLPS711x/EP721x-based"
334 select ARCH_USES_GETTIMEOFFSET
336 Support for Cirrus Logic 711x/721x based boards.
339 bool "Cavium Networks CNS3XXX family"
341 select GENERIC_CLOCKEVENTS
343 select MIGHT_HAVE_PCI
344 select PCI_DOMAINS if PCI
345 select NO_MACH_MEMORY_H
347 Support for Cavium Networks CNS3XXX platform.
350 bool "Cortina Systems Gemini"
352 select ARCH_REQUIRE_GPIOLIB
353 select ARCH_USES_GETTIMEOFFSET
354 select NO_MACH_MEMORY_H
356 Support for the Cortina Systems Gemini family SoCs
359 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
363 select GENERIC_CLOCKEVENTS
365 select GENERIC_IRQ_CHIP
369 Support for CSR SiRFSoC ARM Cortex A9 Platform
376 select ARCH_USES_GETTIMEOFFSET
378 This is an evaluation board for the StrongARM processor available
379 from Digital. It has limited hardware on-board, including an
380 Ethernet interface, two PCMCIA sockets, two serial ports and a
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_HAS_HOLES_MEMORYMODEL
391 select ARCH_USES_GETTIMEOFFSET
393 This enables support for the Cirrus EP93xx series of CPUs.
395 config ARCH_FOOTBRIDGE
399 select GENERIC_CLOCKEVENTS
401 Support for systems based on the DC21285 companion chip
402 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
405 bool "Freescale MXC/iMX-based"
406 select GENERIC_CLOCKEVENTS
407 select ARCH_REQUIRE_GPIOLIB
410 select GENERIC_IRQ_CHIP
411 select HAVE_SCHED_CLOCK
413 Support for Freescale MXC/iMX-based family of processors
416 bool "Freescale MXS-based"
417 select GENERIC_CLOCKEVENTS
418 select ARCH_REQUIRE_GPIOLIB
421 select NO_MACH_MEMORY_H
423 Support for Freescale MXS-based family of processors
426 bool "Hilscher NetX based"
430 select GENERIC_CLOCKEVENTS
431 select NO_MACH_MEMORY_H
433 This enables support for systems based on the Hilscher NetX Soc
436 bool "Hynix HMS720x-based"
439 select ARCH_USES_GETTIMEOFFSET
440 select NO_MACH_MEMORY_H
442 This enables support for systems based on the Hynix HMS720x
450 select ARCH_SUPPORTS_MSI
453 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
462 select NO_MACH_MEMORY_H
464 Support for Intel's 80219 and IOP32X (XScale) family of
473 select ARCH_REQUIRE_GPIOLIB
474 select NO_MACH_MEMORY_H
476 Support for Intel's IOP33X (XScale) family of processors.
483 select ARCH_USES_GETTIMEOFFSET
485 Support for Intel's IXP23xx (XScale) family of processors.
488 bool "IXP2400/2800-based"
492 select ARCH_USES_GETTIMEOFFSET
494 Support for Intel's IXP2400/2800 (XScale) family of processors.
502 select GENERIC_CLOCKEVENTS
503 select HAVE_SCHED_CLOCK
504 select MIGHT_HAVE_PCI
505 select DMABOUNCE if PCI
506 select NO_MACH_MEMORY_H
508 Support for Intel's IXP4XX (XScale) family of processors.
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
517 select NO_MACH_MEMORY_H
519 Support for the Marvell Dove SoC 88AP510
522 bool "Marvell Kirkwood"
525 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
528 select NO_MACH_MEMORY_H
530 Support for the following Marvell Kirkwood series SoCs:
531 88F6180, 88F6192 and 88F6281.
537 select ARCH_REQUIRE_GPIOLIB
540 select USB_ARCH_HAS_OHCI
543 select GENERIC_CLOCKEVENTS
544 select NO_MACH_MEMORY_H
546 Support for the NXP LPC32XX family of processors
549 bool "Marvell MV78xx0"
552 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
555 select NO_MACH_MEMORY_H
557 Support for the following Marvell MV78xx0 series SoCs:
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
568 select NO_MACH_MEMORY_H
570 Support for the following Marvell Orion 5x series SoCs:
571 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
572 Orion-2 (5281), Orion-1-90 (6183).
575 bool "Marvell PXA168/910/MMP2"
577 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select HAVE_SCHED_CLOCK
584 select NO_MACH_MEMORY_H
586 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
589 bool "Micrel/Kendin KS8695"
591 select ARCH_REQUIRE_GPIOLIB
592 select ARCH_USES_GETTIMEOFFSET
594 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
595 System-on-Chip devices.
598 bool "Nuvoton W90X900 CPU"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NO_MACH_MEMORY_H
606 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
607 At present, the w90x900 has been renamed nuc900, regarding
608 the ARM series product line, you can login the following
609 link address to know more.
611 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
612 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
615 bool "Nuvoton NUC93X CPU"
618 select NO_MACH_MEMORY_H
620 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
621 low-power and high performance MPEG-4/JPEG multimedia controller chip.
628 select GENERIC_CLOCKEVENTS
631 select HAVE_SCHED_CLOCK
632 select ARCH_HAS_CPUFREQ
633 select NO_MACH_MEMORY_H
635 This enables support for NVIDIA Tegra based systems (Tegra APX,
636 Tegra 6xx and Tegra 2 series).
639 bool "Philips Nexperia PNX4008 Mobile"
642 select ARCH_USES_GETTIMEOFFSET
643 select NO_MACH_MEMORY_H
645 This enables support for Philips PNX4008 mobile platform.
648 bool "PXA2xx/PXA3xx-based"
651 select ARCH_HAS_CPUFREQ
654 select ARCH_REQUIRE_GPIOLIB
655 select GENERIC_CLOCKEVENTS
656 select HAVE_SCHED_CLOCK
661 select MULTI_IRQ_HANDLER
662 select NO_MACH_MEMORY_H
664 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
669 select GENERIC_CLOCKEVENTS
670 select ARCH_REQUIRE_GPIOLIB
672 select NO_MACH_MEMORY_H
674 Support for Qualcomm MSM/QSD based systems. This runs on the
675 apps processor of the MSM/QSD and depends on a shared memory
676 interface to the modem processor which runs the baseband
677 stack and controls some vital subsystems
678 (clock and power control, etc).
681 bool "Renesas SH-Mobile / R-Mobile"
684 select HAVE_MACH_CLKDEV
685 select GENERIC_CLOCKEVENTS
688 select MULTI_IRQ_HANDLER
689 select PM_GENERIC_DOMAINS if PM
691 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
698 select ARCH_MAY_HAVE_PC_FDC
699 select HAVE_PATA_PLATFORM
702 select ARCH_SPARSEMEM_ENABLE
703 select ARCH_USES_GETTIMEOFFSET
705 On the Acorn Risc-PC, Linux can support the internal IDE disk and
706 CD-ROM interface, serial and parallel port, and the floppy drive.
713 select ARCH_SPARSEMEM_ENABLE
715 select ARCH_HAS_CPUFREQ
717 select GENERIC_CLOCKEVENTS
719 select HAVE_SCHED_CLOCK
721 select ARCH_REQUIRE_GPIOLIB
723 Support for StrongARM 11x0 based boards.
726 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
728 select ARCH_HAS_CPUFREQ
731 select ARCH_USES_GETTIMEOFFSET
732 select HAVE_S3C2410_I2C if I2C
733 select NO_MACH_MEMORY_H
735 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
736 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
737 the Samsung SMDK2410 development board (and derivatives).
739 Note, the S3C2416 and the S3C2450 are so close that they even share
740 the same SoC ID code. This means that there is no separate machine
741 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
744 bool "Samsung S3C64XX"
751 select ARCH_USES_GETTIMEOFFSET
752 select ARCH_HAS_CPUFREQ
753 select ARCH_REQUIRE_GPIOLIB
754 select SAMSUNG_CLKSRC
755 select SAMSUNG_IRQ_VIC_TIMER
756 select SAMSUNG_IRQ_UART
757 select S3C_GPIO_TRACK
758 select S3C_GPIO_PULL_UPDOWN
759 select S3C_GPIO_CFG_S3C24XX
760 select S3C_GPIO_CFG_S3C64XX
762 select USB_ARCH_HAS_OHCI
763 select SAMSUNG_GPIOLIB_4BIT
764 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 Samsung S3C64XX series based systems
770 bool "Samsung S5P6440 S5P6450"
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select GENERIC_CLOCKEVENTS
778 select HAVE_SCHED_CLOCK
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C_RTC if RTC_CLASS
782 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
786 bool "Samsung S5PC100"
791 select ARM_L1_CACHE_SHIFT_6
792 select ARCH_USES_GETTIMEOFFSET
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C_RTC if RTC_CLASS
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select NO_MACH_MEMORY_H
798 Samsung S5PC100 series based systems
801 bool "Samsung S5PV210/S5PC110"
803 select ARCH_SPARSEMEM_ENABLE
804 select ARCH_HAS_HOLES_MEMORYMODEL
809 select ARM_L1_CACHE_SHIFT_6
810 select ARCH_HAS_CPUFREQ
811 select GENERIC_CLOCKEVENTS
812 select HAVE_SCHED_CLOCK
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C_RTC if RTC_CLASS
815 select HAVE_S3C2410_WATCHDOG if WATCHDOG
817 Samsung S5PV210/S5PC110 series based systems
820 bool "Samsung EXYNOS4"
822 select ARCH_SPARSEMEM_ENABLE
823 select ARCH_HAS_HOLES_MEMORYMODEL
827 select ARCH_HAS_CPUFREQ
828 select GENERIC_CLOCKEVENTS
829 select HAVE_S3C_RTC if RTC_CLASS
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 Samsung EXYNOS4 series based systems
842 select ARCH_USES_GETTIMEOFFSET
844 Support for the StrongARM based Digital DNARD machine, also known
845 as "Shark" (<http://www.shark-linux.de/shark.html>).
848 bool "Telechips TCC ARM926-based systems"
853 select GENERIC_CLOCKEVENTS
854 select NO_MACH_MEMORY_H
856 Support for Telechips TCC ARM926-based systems.
859 bool "ST-Ericsson U300 Series"
863 select HAVE_SCHED_CLOCK
867 select GENERIC_CLOCKEVENTS
869 select HAVE_MACH_CLKDEV
872 Support for ST-Ericsson U300 series mobile platforms.
875 bool "ST-Ericsson U8500 Series"
878 select GENERIC_CLOCKEVENTS
880 select ARCH_REQUIRE_GPIOLIB
881 select ARCH_HAS_CPUFREQ
882 select NO_MACH_MEMORY_H
884 Support for ST-Ericsson's Ux500 architecture
887 bool "STMicroelectronics Nomadik"
892 select GENERIC_CLOCKEVENTS
893 select ARCH_REQUIRE_GPIOLIB
894 select NO_MACH_MEMORY_H
896 Support for the Nomadik platform by ST-Ericsson
900 select GENERIC_CLOCKEVENTS
901 select ARCH_REQUIRE_GPIOLIB
905 select GENERIC_ALLOCATOR
906 select GENERIC_IRQ_CHIP
907 select ARCH_HAS_HOLES_MEMORYMODEL
908 select NO_MACH_MEMORY_H
910 Support for TI's DaVinci platform.
915 select ARCH_REQUIRE_GPIOLIB
916 select ARCH_HAS_CPUFREQ
918 select GENERIC_CLOCKEVENTS
919 select HAVE_SCHED_CLOCK
920 select ARCH_HAS_HOLES_MEMORYMODEL
922 Support for TI's OMAP platform (OMAP1/2/3/4).
927 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_CLOCKEVENTS
932 select NO_MACH_MEMORY_H
934 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
937 bool "VIA/WonderMedia 85xx"
940 select ARCH_HAS_CPUFREQ
941 select GENERIC_CLOCKEVENTS
942 select ARCH_REQUIRE_GPIOLIB
944 select NO_MACH_MEMORY_H
946 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
949 bool "Xilinx Zynq ARM Cortex A9 Platform"
952 select GENERIC_CLOCKEVENTS
958 select NO_MACH_MEMORY_H
960 Support for Xilinx Zynq ARM Cortex A9 Platform
964 # This is sorted alphabetically by mach-* pathname. However, plat-*
965 # Kconfigs may be included either alphabetically (according to the
966 # plat- suffix) or along side the corresponding mach-* source.
968 source "arch/arm/mach-at91/Kconfig"
970 source "arch/arm/mach-bcmring/Kconfig"
972 source "arch/arm/mach-clps711x/Kconfig"
974 source "arch/arm/mach-cns3xxx/Kconfig"
976 source "arch/arm/mach-davinci/Kconfig"
978 source "arch/arm/mach-dove/Kconfig"
980 source "arch/arm/mach-ep93xx/Kconfig"
982 source "arch/arm/mach-footbridge/Kconfig"
984 source "arch/arm/mach-gemini/Kconfig"
986 source "arch/arm/mach-h720x/Kconfig"
988 source "arch/arm/mach-integrator/Kconfig"
990 source "arch/arm/mach-iop32x/Kconfig"
992 source "arch/arm/mach-iop33x/Kconfig"
994 source "arch/arm/mach-iop13xx/Kconfig"
996 source "arch/arm/mach-ixp4xx/Kconfig"
998 source "arch/arm/mach-ixp2000/Kconfig"
1000 source "arch/arm/mach-ixp23xx/Kconfig"
1002 source "arch/arm/mach-kirkwood/Kconfig"
1004 source "arch/arm/mach-ks8695/Kconfig"
1006 source "arch/arm/mach-lpc32xx/Kconfig"
1008 source "arch/arm/mach-msm/Kconfig"
1010 source "arch/arm/mach-mv78xx0/Kconfig"
1012 source "arch/arm/plat-mxc/Kconfig"
1014 source "arch/arm/mach-mxs/Kconfig"
1016 source "arch/arm/mach-netx/Kconfig"
1018 source "arch/arm/mach-nomadik/Kconfig"
1019 source "arch/arm/plat-nomadik/Kconfig"
1021 source "arch/arm/mach-nuc93x/Kconfig"
1023 source "arch/arm/plat-omap/Kconfig"
1025 source "arch/arm/mach-omap1/Kconfig"
1027 source "arch/arm/mach-omap2/Kconfig"
1029 source "arch/arm/mach-orion5x/Kconfig"
1031 source "arch/arm/mach-pxa/Kconfig"
1032 source "arch/arm/plat-pxa/Kconfig"
1034 source "arch/arm/mach-mmp/Kconfig"
1036 source "arch/arm/mach-realview/Kconfig"
1038 source "arch/arm/mach-sa1100/Kconfig"
1040 source "arch/arm/plat-samsung/Kconfig"
1041 source "arch/arm/plat-s3c24xx/Kconfig"
1042 source "arch/arm/plat-s5p/Kconfig"
1044 source "arch/arm/plat-spear/Kconfig"
1046 source "arch/arm/plat-tcc/Kconfig"
1049 source "arch/arm/mach-s3c2410/Kconfig"
1050 source "arch/arm/mach-s3c2412/Kconfig"
1051 source "arch/arm/mach-s3c2416/Kconfig"
1052 source "arch/arm/mach-s3c2440/Kconfig"
1053 source "arch/arm/mach-s3c2443/Kconfig"
1057 source "arch/arm/mach-s3c64xx/Kconfig"
1060 source "arch/arm/mach-s5p64x0/Kconfig"
1062 source "arch/arm/mach-s5pc100/Kconfig"
1064 source "arch/arm/mach-s5pv210/Kconfig"
1066 source "arch/arm/mach-exynos4/Kconfig"
1068 source "arch/arm/mach-shmobile/Kconfig"
1070 source "arch/arm/mach-tegra/Kconfig"
1072 source "arch/arm/mach-u300/Kconfig"
1074 source "arch/arm/mach-ux500/Kconfig"
1076 source "arch/arm/mach-versatile/Kconfig"
1078 source "arch/arm/mach-vexpress/Kconfig"
1079 source "arch/arm/plat-versatile/Kconfig"
1081 source "arch/arm/mach-vt8500/Kconfig"
1083 source "arch/arm/mach-w90x900/Kconfig"
1085 # Definitions to make life easier
1091 select GENERIC_CLOCKEVENTS
1092 select HAVE_SCHED_CLOCK
1097 select GENERIC_IRQ_CHIP
1098 select HAVE_SCHED_CLOCK
1103 config PLAT_VERSATILE
1106 config ARM_TIMER_SP804
1110 source arch/arm/mm/Kconfig
1113 bool "Enable iWMMXt support"
1114 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1115 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1117 Enable support for iWMMXt context switching at run time if
1118 running on a CPU that supports it.
1120 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1123 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1127 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1128 (!ARCH_OMAP3 || OMAP3_EMU)
1132 config MULTI_IRQ_HANDLER
1135 Allow each machine to specify it's own IRQ handler at run time.
1138 source "arch/arm/Kconfig-nommu"
1141 config ARM_ERRATA_411920
1142 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1143 depends on CPU_V6 || CPU_V6K
1145 Invalidation of the Instruction Cache operation can
1146 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1147 It does not affect the MPCore. This option enables the ARM Ltd.
1148 recommended workaround.
1150 config ARM_ERRATA_430973
1151 bool "ARM errata: Stale prediction on replaced interworking branch"
1154 This option enables the workaround for the 430973 Cortex-A8
1155 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1156 interworking branch is replaced with another code sequence at the
1157 same virtual address, whether due to self-modifying code or virtual
1158 to physical address re-mapping, Cortex-A8 does not recover from the
1159 stale interworking branch prediction. This results in Cortex-A8
1160 executing the new code sequence in the incorrect ARM or Thumb state.
1161 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1162 and also flushes the branch target cache at every context switch.
1163 Note that setting specific bits in the ACTLR register may not be
1164 available in non-secure mode.
1166 config ARM_ERRATA_458693
1167 bool "ARM errata: Processor deadlock when a false hazard is created"
1170 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1171 erratum. For very specific sequences of memory operations, it is
1172 possible for a hazard condition intended for a cache line to instead
1173 be incorrectly associated with a different cache line. This false
1174 hazard might then cause a processor deadlock. The workaround enables
1175 the L1 caching of the NEON accesses and disables the PLD instruction
1176 in the ACTLR register. Note that setting specific bits in the ACTLR
1177 register may not be available in non-secure mode.
1179 config ARM_ERRATA_460075
1180 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1183 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1184 erratum. Any asynchronous access to the L2 cache may encounter a
1185 situation in which recent store transactions to the L2 cache are lost
1186 and overwritten with stale memory contents from external memory. The
1187 workaround disables the write-allocate mode for the L2 cache via the
1188 ACTLR register. Note that setting specific bits in the ACTLR register
1189 may not be available in non-secure mode.
1191 config ARM_ERRATA_742230
1192 bool "ARM errata: DMB operation may be faulty"
1193 depends on CPU_V7 && SMP
1195 This option enables the workaround for the 742230 Cortex-A9
1196 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1197 between two write operations may not ensure the correct visibility
1198 ordering of the two writes. This workaround sets a specific bit in
1199 the diagnostic register of the Cortex-A9 which causes the DMB
1200 instruction to behave as a DSB, ensuring the correct behaviour of
1203 config ARM_ERRATA_742231
1204 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1205 depends on CPU_V7 && SMP
1207 This option enables the workaround for the 742231 Cortex-A9
1208 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1209 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1210 accessing some data located in the same cache line, may get corrupted
1211 data due to bad handling of the address hazard when the line gets
1212 replaced from one of the CPUs at the same time as another CPU is
1213 accessing it. This workaround sets specific bits in the diagnostic
1214 register of the Cortex-A9 which reduces the linefill issuing
1215 capabilities of the processor.
1217 config PL310_ERRATA_588369
1218 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1219 depends on CACHE_L2X0
1221 The PL310 L2 cache controller implements three types of Clean &
1222 Invalidate maintenance operations: by Physical Address
1223 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1224 They are architecturally defined to behave as the execution of a
1225 clean operation followed immediately by an invalidate operation,
1226 both performing to the same memory location. This functionality
1227 is not correctly implemented in PL310 as clean lines are not
1228 invalidated as a result of these operations.
1230 config ARM_ERRATA_720789
1231 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1232 depends on CPU_V7 && SMP
1234 This option enables the workaround for the 720789 Cortex-A9 (prior to
1235 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1236 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1237 As a consequence of this erratum, some TLB entries which should be
1238 invalidated are not, resulting in an incoherency in the system page
1239 tables. The workaround changes the TLB flushing routines to invalidate
1240 entries regardless of the ASID.
1242 config PL310_ERRATA_727915
1243 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1244 depends on CACHE_L2X0
1246 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1247 operation (offset 0x7FC). This operation runs in background so that
1248 PL310 can handle normal accesses while it is in progress. Under very
1249 rare circumstances, due to this erratum, write data can be lost when
1250 PL310 treats a cacheable write transaction during a Clean &
1251 Invalidate by Way operation.
1253 config ARM_ERRATA_743622
1254 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1257 This option enables the workaround for the 743622 Cortex-A9
1258 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1259 optimisation in the Cortex-A9 Store Buffer may lead to data
1260 corruption. This workaround sets a specific bit in the diagnostic
1261 register of the Cortex-A9 which disables the Store Buffer
1262 optimisation, preventing the defect from occurring. This has no
1263 visible impact on the overall performance or power consumption of the
1266 config ARM_ERRATA_751472
1267 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1268 depends on CPU_V7 && SMP
1270 This option enables the workaround for the 751472 Cortex-A9 (prior
1271 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1272 completion of a following broadcasted operation if the second
1273 operation is received by a CPU before the ICIALLUIS has completed,
1274 potentially leading to corrupted entries in the cache or TLB.
1276 config ARM_ERRATA_753970
1277 bool "ARM errata: cache sync operation may be faulty"
1278 depends on CACHE_PL310
1280 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1282 Under some condition the effect of cache sync operation on
1283 the store buffer still remains when the operation completes.
1284 This means that the store buffer is always asked to drain and
1285 this prevents it from merging any further writes. The workaround
1286 is to replace the normal offset of cache sync operation (0x730)
1287 by another offset targeting an unmapped PL310 register 0x740.
1288 This has the same effect as the cache sync operation: store buffer
1289 drain and waiting for all buffers empty.
1291 config ARM_ERRATA_754322
1292 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1295 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1296 r3p*) erratum. A speculative memory access may cause a page table walk
1297 which starts prior to an ASID switch but completes afterwards. This
1298 can populate the micro-TLB with a stale entry which may be hit with
1299 the new ASID. This workaround places two dsb instructions in the mm
1300 switching code so that no page table walks can cross the ASID switch.
1302 config ARM_ERRATA_754327
1303 bool "ARM errata: no automatic Store Buffer drain"
1304 depends on CPU_V7 && SMP
1306 This option enables the workaround for the 754327 Cortex-A9 (prior to
1307 r2p0) erratum. The Store Buffer does not have any automatic draining
1308 mechanism and therefore a livelock may occur if an external agent
1309 continuously polls a memory location waiting to observe an update.
1310 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1311 written polling loops from denying visibility of updates to memory.
1315 source "arch/arm/common/Kconfig"
1325 Find out whether you have ISA slots on your motherboard. ISA is the
1326 name of a bus system, i.e. the way the CPU talks to the other stuff
1327 inside your box. Other bus systems are PCI, EISA, MicroChannel
1328 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1329 newer boards don't support it. If you have ISA, say Y, otherwise N.
1331 # Select ISA DMA controller support
1336 # Select ISA DMA interface
1341 bool "PCI support" if MIGHT_HAVE_PCI
1343 Find out whether you have a PCI motherboard. PCI is the name of a
1344 bus system, i.e. the way the CPU talks to the other stuff inside
1345 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1346 VESA. If you have PCI, say Y, otherwise N.
1352 config PCI_NANOENGINE
1353 bool "BSE nanoEngine PCI support"
1354 depends on SA1100_NANOENGINE
1356 Enable PCI on the BSE nanoEngine board.
1361 # Select the host bridge type
1362 config PCI_HOST_VIA82C505
1364 depends on PCI && ARCH_SHARK
1367 config PCI_HOST_ITE8152
1369 depends on PCI && MACH_ARMCORE
1373 source "drivers/pci/Kconfig"
1375 source "drivers/pcmcia/Kconfig"
1379 menu "Kernel Features"
1381 source "kernel/time/Kconfig"
1384 bool "Symmetric Multi-Processing"
1385 depends on CPU_V6K || CPU_V7
1386 depends on GENERIC_CLOCKEVENTS
1387 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1388 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1389 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1390 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1391 select USE_GENERIC_SMP_HELPERS
1392 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1394 This enables support for systems with more than one CPU. If you have
1395 a system with only one CPU, like most personal computers, say N. If
1396 you have a system with more than one CPU, say Y.
1398 If you say N here, the kernel will run on single and multiprocessor
1399 machines, but will use only one CPU of a multiprocessor machine. If
1400 you say Y here, the kernel will run on many, but not all, single
1401 processor machines. On a single processor machine, the kernel will
1402 run faster if you say N here.
1404 See also <file:Documentation/i386/IO-APIC.txt>,
1405 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1406 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1408 If you don't know what to do here, say N.
1411 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1412 depends on EXPERIMENTAL
1413 depends on SMP && !XIP_KERNEL
1416 SMP kernels contain instructions which fail on non-SMP processors.
1417 Enabling this option allows the kernel to modify itself to make
1418 these instructions safe. Disabling it allows about 1K of space
1421 If you don't know what to do here, say Y.
1426 This option enables support for the ARM system coherency unit
1433 This options enables support for the ARM timer and watchdog unit
1436 prompt "Memory split"
1439 Select the desired split between kernel and user memory.
1441 If you are not absolutely sure what you are doing, leave this
1445 bool "3G/1G user/kernel split"
1447 bool "2G/2G user/kernel split"
1449 bool "1G/3G user/kernel split"
1454 default 0x40000000 if VMSPLIT_1G
1455 default 0x80000000 if VMSPLIT_2G
1459 int "Maximum number of CPUs (2-32)"
1465 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1466 depends on SMP && HOTPLUG && EXPERIMENTAL
1468 Say Y here to experiment with turning CPUs off and on. CPUs
1469 can be controlled through /sys/devices/system/cpu.
1472 bool "Use local timer interrupts"
1475 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1477 Enable support for local timers on SMP platforms, rather then the
1478 legacy IPI broadcast method. Local timers allows the system
1479 accounting to be spread across the timer interval, preventing a
1480 "thundering herd" at every timer tick.
1482 source kernel/Kconfig.preempt
1486 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1487 ARCH_S5PV210 || ARCH_EXYNOS4
1488 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1489 default AT91_TIMER_HZ if ARCH_AT91
1490 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1493 config THUMB2_KERNEL
1494 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1495 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1497 select ARM_ASM_UNIFIED
1499 By enabling this option, the kernel will be compiled in
1500 Thumb-2 mode. A compiler/assembler that understand the unified
1501 ARM-Thumb syntax is needed.
1505 config THUMB2_AVOID_R_ARM_THM_JUMP11
1506 bool "Work around buggy Thumb-2 short branch relocations in gas"
1507 depends on THUMB2_KERNEL && MODULES
1510 Various binutils versions can resolve Thumb-2 branches to
1511 locally-defined, preemptible global symbols as short-range "b.n"
1512 branch instructions.
1514 This is a problem, because there's no guarantee the final
1515 destination of the symbol, or any candidate locations for a
1516 trampoline, are within range of the branch. For this reason, the
1517 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1518 relocation in modules at all, and it makes little sense to add
1521 The symptom is that the kernel fails with an "unsupported
1522 relocation" error when loading some modules.
1524 Until fixed tools are available, passing
1525 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1526 code which hits this problem, at the cost of a bit of extra runtime
1527 stack usage in some cases.
1529 The problem is described in more detail at:
1530 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1532 Only Thumb-2 kernels are affected.
1534 Unless you are sure your tools don't have this problem, say Y.
1536 config ARM_ASM_UNIFIED
1540 bool "Use the ARM EABI to compile the kernel"
1542 This option allows for the kernel to be compiled using the latest
1543 ARM ABI (aka EABI). This is only useful if you are using a user
1544 space environment that is also compiled with EABI.
1546 Since there are major incompatibilities between the legacy ABI and
1547 EABI, especially with regard to structure member alignment, this
1548 option also changes the kernel syscall calling convention to
1549 disambiguate both ABIs and allow for backward compatibility support
1550 (selected with CONFIG_OABI_COMPAT).
1552 To use this you need GCC version 4.0.0 or later.
1555 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1556 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1559 This option preserves the old syscall interface along with the
1560 new (ARM EABI) one. It also provides a compatibility layer to
1561 intercept syscalls that have structure arguments which layout
1562 in memory differs between the legacy ABI and the new ARM EABI
1563 (only for non "thumb" binaries). This option adds a tiny
1564 overhead to all syscalls and produces a slightly larger kernel.
1565 If you know you'll be using only pure EABI user space then you
1566 can say N here. If this option is not selected and you attempt
1567 to execute a legacy ABI binary then the result will be
1568 UNPREDICTABLE (in fact it can be predicted that it won't work
1569 at all). If in doubt say Y.
1571 config ARCH_HAS_HOLES_MEMORYMODEL
1574 config ARCH_SPARSEMEM_ENABLE
1577 config ARCH_SPARSEMEM_DEFAULT
1578 def_bool ARCH_SPARSEMEM_ENABLE
1580 config ARCH_SELECT_MEMORY_MODEL
1581 def_bool ARCH_SPARSEMEM_ENABLE
1583 config HAVE_ARCH_PFN_VALID
1584 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1587 bool "High Memory Support"
1590 The address space of ARM processors is only 4 Gigabytes large
1591 and it has to accommodate user address space, kernel address
1592 space as well as some memory mapped IO. That means that, if you
1593 have a large amount of physical memory and/or IO, not all of the
1594 memory can be "permanently mapped" by the kernel. The physical
1595 memory that is not permanently mapped is called "high memory".
1597 Depending on the selected kernel/user memory split, minimum
1598 vmalloc space and actual amount of RAM, you may not need this
1599 option which should result in a slightly faster kernel.
1604 bool "Allocate 2nd-level pagetables from highmem"
1607 config HW_PERF_EVENTS
1608 bool "Enable hardware performance counter support for perf events"
1609 depends on PERF_EVENTS && CPU_HAS_PMU
1612 Enable hardware performance counter support for perf events. If
1613 disabled, perf events will use software events only.
1617 config FORCE_MAX_ZONEORDER
1618 int "Maximum zone order" if ARCH_SHMOBILE
1619 range 11 64 if ARCH_SHMOBILE
1620 default "9" if SA1111
1623 The kernel memory allocator divides physically contiguous memory
1624 blocks into "zones", where each zone is a power of two number of
1625 pages. This option selects the largest power of two that the kernel
1626 keeps in the memory allocator. If you need to allocate very large
1627 blocks of physically contiguous memory, then you may need to
1628 increase this value.
1630 This config option is actually maximum order plus one. For example,
1631 a value of 11 means that the largest free memory block is 2^10 pages.
1634 bool "Timer and CPU usage LEDs"
1635 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1636 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1637 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1638 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1639 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1640 ARCH_AT91 || ARCH_DAVINCI || \
1641 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1643 If you say Y here, the LEDs on your machine will be used
1644 to provide useful information about your current system status.
1646 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1647 be able to select which LEDs are active using the options below. If
1648 you are compiling a kernel for the EBSA-110 or the LART however, the
1649 red LED will simply flash regularly to indicate that the system is
1650 still functional. It is safe to say Y here if you have a CATS
1651 system, but the driver will do nothing.
1654 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1655 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1656 || MACH_OMAP_PERSEUS2
1658 depends on !GENERIC_CLOCKEVENTS
1659 default y if ARCH_EBSA110
1661 If you say Y here, one of the system LEDs (the green one on the
1662 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1663 will flash regularly to indicate that the system is still
1664 operational. This is mainly useful to kernel hackers who are
1665 debugging unstable kernels.
1667 The LART uses the same LED for both Timer LED and CPU usage LED
1668 functions. You may choose to use both, but the Timer LED function
1669 will overrule the CPU usage LED.
1672 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1674 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1675 || MACH_OMAP_PERSEUS2
1678 If you say Y here, the red LED will be used to give a good real
1679 time indication of CPU usage, by lighting whenever the idle task
1680 is not currently executing.
1682 The LART uses the same LED for both Timer LED and CPU usage LED
1683 functions. You may choose to use both, but the Timer LED function
1684 will overrule the CPU usage LED.
1686 config ALIGNMENT_TRAP
1688 depends on CPU_CP15_MMU
1689 default y if !ARCH_EBSA110
1690 select HAVE_PROC_CPU if PROC_FS
1692 ARM processors cannot fetch/store information which is not
1693 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1694 address divisible by 4. On 32-bit ARM processors, these non-aligned
1695 fetch/store instructions will be emulated in software if you say
1696 here, which has a severe performance impact. This is necessary for
1697 correct operation of some network protocols. With an IP-only
1698 configuration it is safe to say N, otherwise say Y.
1700 config UACCESS_WITH_MEMCPY
1701 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1702 depends on MMU && EXPERIMENTAL
1703 default y if CPU_FEROCEON
1705 Implement faster copy_to_user and clear_user methods for CPU
1706 cores where a 8-word STM instruction give significantly higher
1707 memory write throughput than a sequence of individual 32bit stores.
1709 A possible side effect is a slight increase in scheduling latency
1710 between threads sharing the same address space if they invoke
1711 such copy operations with large buffers.
1713 However, if the CPU data cache is using a write-allocate mode,
1714 this option is unlikely to provide any performance gain.
1718 prompt "Enable seccomp to safely compute untrusted bytecode"
1720 This kernel feature is useful for number crunching applications
1721 that may need to compute untrusted bytecode during their
1722 execution. By using pipes or other transports made available to
1723 the process as file descriptors supporting the read/write
1724 syscalls, it's possible to isolate those applications in
1725 their own address space using seccomp. Once seccomp is
1726 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1727 and the task is only allowed to execute a few safe syscalls
1728 defined by each seccomp mode.
1730 config CC_STACKPROTECTOR
1731 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1732 depends on EXPERIMENTAL
1734 This option turns on the -fstack-protector GCC feature. This
1735 feature puts, at the beginning of functions, a canary value on
1736 the stack just before the return address, and validates
1737 the value just before actually returning. Stack based buffer
1738 overflows (that need to overwrite this return address) now also
1739 overwrite the canary, which gets detected and the attack is then
1740 neutralized via a kernel panic.
1741 This feature requires gcc version 4.2 or above.
1743 config DEPRECATED_PARAM_STRUCT
1744 bool "Provide old way to pass kernel parameters"
1746 This was deprecated in 2001 and announced to live on for 5 years.
1747 Some old boot loaders still use this way.
1754 bool "Flattened Device Tree support"
1756 select OF_EARLY_FLATTREE
1759 Include support for flattened device tree machine descriptions.
1761 # Compressed boot loader in ROM. Yes, we really want to ask about
1762 # TEXT and BSS so we preserve their values in the config files.
1763 config ZBOOT_ROM_TEXT
1764 hex "Compressed ROM boot loader base address"
1767 The physical address at which the ROM-able zImage is to be
1768 placed in the target. Platforms which normally make use of
1769 ROM-able zImage formats normally set this to a suitable
1770 value in their defconfig file.
1772 If ZBOOT_ROM is not enabled, this has no effect.
1774 config ZBOOT_ROM_BSS
1775 hex "Compressed ROM boot loader BSS address"
1778 The base address of an area of read/write memory in the target
1779 for the ROM-able zImage which must be available while the
1780 decompressor is running. It must be large enough to hold the
1781 entire decompressed kernel plus an additional 128 KiB.
1782 Platforms which normally make use of ROM-able zImage formats
1783 normally set this to a suitable value in their defconfig file.
1785 If ZBOOT_ROM is not enabled, this has no effect.
1788 bool "Compressed boot loader in ROM/flash"
1789 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1791 Say Y here if you intend to execute your compressed kernel image
1792 (zImage) directly from ROM or flash. If unsure, say N.
1795 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1796 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1797 default ZBOOT_ROM_NONE
1799 Include experimental SD/MMC loading code in the ROM-able zImage.
1800 With this enabled it is possible to write the the ROM-able zImage
1801 kernel image to an MMC or SD card and boot the kernel straight
1802 from the reset vector. At reset the processor Mask ROM will load
1803 the first part of the the ROM-able zImage which in turn loads the
1804 rest the kernel image to RAM.
1806 config ZBOOT_ROM_NONE
1807 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1809 Do not load image from SD or MMC
1811 config ZBOOT_ROM_MMCIF
1812 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1814 Load image from MMCIF hardware block.
1816 config ZBOOT_ROM_SH_MOBILE_SDHI
1817 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1819 Load image from SDHI hardware block
1824 string "Default kernel command string"
1827 On some architectures (EBSA110 and CATS), there is currently no way
1828 for the boot loader to pass arguments to the kernel. For these
1829 architectures, you should supply some command-line options at build
1830 time by entering them here. As a minimum, you should specify the
1831 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1834 prompt "Kernel command line type" if CMDLINE != ""
1835 default CMDLINE_FROM_BOOTLOADER
1837 config CMDLINE_FROM_BOOTLOADER
1838 bool "Use bootloader kernel arguments if available"
1840 Uses the command-line options passed by the boot loader. If
1841 the boot loader doesn't provide any, the default kernel command
1842 string provided in CMDLINE will be used.
1844 config CMDLINE_EXTEND
1845 bool "Extend bootloader kernel arguments"
1847 The command-line arguments provided by the boot loader will be
1848 appended to the default kernel command string.
1850 config CMDLINE_FORCE
1851 bool "Always use the default kernel command string"
1853 Always use the default kernel command string, even if the boot
1854 loader passes other arguments to the kernel.
1855 This is useful if you cannot or don't want to change the
1856 command-line options your boot loader passes to the kernel.
1860 bool "Kernel Execute-In-Place from ROM"
1861 depends on !ZBOOT_ROM
1863 Execute-In-Place allows the kernel to run from non-volatile storage
1864 directly addressable by the CPU, such as NOR flash. This saves RAM
1865 space since the text section of the kernel is not loaded from flash
1866 to RAM. Read-write sections, such as the data section and stack,
1867 are still copied to RAM. The XIP kernel is not compressed since
1868 it has to run directly from flash, so it will take more space to
1869 store it. The flash address used to link the kernel object files,
1870 and for storing it, is configuration dependent. Therefore, if you
1871 say Y here, you must know the proper physical address where to
1872 store the kernel image depending on your own flash memory usage.
1874 Also note that the make target becomes "make xipImage" rather than
1875 "make zImage" or "make Image". The final kernel binary to put in
1876 ROM memory will be arch/arm/boot/xipImage.
1880 config XIP_PHYS_ADDR
1881 hex "XIP Kernel Physical Location"
1882 depends on XIP_KERNEL
1883 default "0x00080000"
1885 This is the physical address in your flash memory the kernel will
1886 be linked for and stored to. This address is dependent on your
1890 bool "Kexec system call (EXPERIMENTAL)"
1891 depends on EXPERIMENTAL
1893 kexec is a system call that implements the ability to shutdown your
1894 current kernel, and to start another kernel. It is like a reboot
1895 but it is independent of the system firmware. And like a reboot
1896 you can start any kernel with it, not just Linux.
1898 It is an ongoing process to be certain the hardware in a machine
1899 is properly shutdown, so do not be surprised if this code does not
1900 initially work for you. It may help to enable device hotplugging
1904 bool "Export atags in procfs"
1908 Should the atags used to boot the kernel be exported in an "atags"
1909 file in procfs. Useful with kexec.
1912 bool "Build kdump crash kernel (EXPERIMENTAL)"
1913 depends on EXPERIMENTAL
1915 Generate crash dump after being started by kexec. This should
1916 be normally only set in special crash dump kernels which are
1917 loaded in the main kernel with kexec-tools into a specially
1918 reserved region and then later executed after a crash by
1919 kdump/kexec. The crash dump kernel must be compiled to a
1920 memory address not used by the main kernel
1922 For more details see Documentation/kdump/kdump.txt
1924 config AUTO_ZRELADDR
1925 bool "Auto calculation of the decompressed kernel image address"
1926 depends on !ZBOOT_ROM && !ARCH_U300
1928 ZRELADDR is the physical address where the decompressed kernel
1929 image will be placed. If AUTO_ZRELADDR is selected, the address
1930 will be determined at run-time by masking the current IP with
1931 0xf8000000. This assumes the zImage being placed in the first 128MB
1932 from start of memory.
1936 menu "CPU Power Management"
1940 source "drivers/cpufreq/Kconfig"
1943 tristate "CPUfreq driver for i.MX CPUs"
1944 depends on ARCH_MXC && CPU_FREQ
1946 This enables the CPUfreq driver for i.MX CPUs.
1948 config CPU_FREQ_SA1100
1951 config CPU_FREQ_SA1110
1954 config CPU_FREQ_INTEGRATOR
1955 tristate "CPUfreq driver for ARM Integrator CPUs"
1956 depends on ARCH_INTEGRATOR && CPU_FREQ
1959 This enables the CPUfreq driver for ARM Integrator CPUs.
1961 For details, take a look at <file:Documentation/cpu-freq>.
1967 depends on CPU_FREQ && ARCH_PXA && PXA25x
1969 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1974 Internal configuration node for common cpufreq on Samsung SoC
1976 config CPU_FREQ_S3C24XX
1977 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1978 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1981 This enables the CPUfreq driver for the Samsung S3C24XX family
1984 For details, take a look at <file:Documentation/cpu-freq>.
1988 config CPU_FREQ_S3C24XX_PLL
1989 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1990 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1992 Compile in support for changing the PLL frequency from the
1993 S3C24XX series CPUfreq driver. The PLL takes time to settle
1994 after a frequency change, so by default it is not enabled.
1996 This also means that the PLL tables for the selected CPU(s) will
1997 be built which may increase the size of the kernel image.
1999 config CPU_FREQ_S3C24XX_DEBUG
2000 bool "Debug CPUfreq Samsung driver core"
2001 depends on CPU_FREQ_S3C24XX
2003 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2005 config CPU_FREQ_S3C24XX_IODEBUG
2006 bool "Debug CPUfreq Samsung driver IO timing"
2007 depends on CPU_FREQ_S3C24XX
2009 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2011 config CPU_FREQ_S3C24XX_DEBUGFS
2012 bool "Export debugfs for CPUFreq"
2013 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2015 Export status information via debugfs.
2019 source "drivers/cpuidle/Kconfig"
2023 menu "Floating point emulation"
2025 comment "At least one emulation must be selected"
2028 bool "NWFPE math emulation"
2029 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2031 Say Y to include the NWFPE floating point emulator in the kernel.
2032 This is necessary to run most binaries. Linux does not currently
2033 support floating point hardware so you need to say Y here even if
2034 your machine has an FPA or floating point co-processor podule.
2036 You may say N here if you are going to load the Acorn FPEmulator
2037 early in the bootup.
2040 bool "Support extended precision"
2041 depends on FPE_NWFPE
2043 Say Y to include 80-bit support in the kernel floating-point
2044 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2045 Note that gcc does not generate 80-bit operations by default,
2046 so in most cases this option only enlarges the size of the
2047 floating point emulator without any good reason.
2049 You almost surely want to say N here.
2052 bool "FastFPE math emulation (EXPERIMENTAL)"
2053 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2055 Say Y here to include the FAST floating point emulator in the kernel.
2056 This is an experimental much faster emulator which now also has full
2057 precision for the mantissa. It does not support any exceptions.
2058 It is very simple, and approximately 3-6 times faster than NWFPE.
2060 It should be sufficient for most programs. It may be not suitable
2061 for scientific calculations, but you have to check this for yourself.
2062 If you do not feel you need a faster FP emulation you should better
2066 bool "VFP-format floating point maths"
2067 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2069 Say Y to include VFP support code in the kernel. This is needed
2070 if your hardware includes a VFP unit.
2072 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2073 release notes and additional status information.
2075 Say N if your target does not have VFP hardware.
2083 bool "Advanced SIMD (NEON) Extension support"
2084 depends on VFPv3 && CPU_V7
2086 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2091 menu "Userspace binary formats"
2093 source "fs/Kconfig.binfmt"
2096 tristate "RISC OS personality"
2099 Say Y here to include the kernel code necessary if you want to run
2100 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2101 experimental; if this sounds frightening, say N and sleep in peace.
2102 You can also say M here to compile this support as a module (which
2103 will be called arthur).
2107 menu "Power management options"
2109 source "kernel/power/Kconfig"
2111 config ARCH_SUSPEND_POSSIBLE
2112 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2113 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2114 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2119 source "net/Kconfig"
2121 source "drivers/Kconfig"
2125 source "arch/arm/Kconfig.debug"
2127 source "security/Kconfig"
2129 source "crypto/Kconfig"
2131 source "lib/Kconfig"