2 * Copyright (C) 2015 Phytec Messtechnik GmbH
3 * Author: Teresa Remmet <t.remmet@phytec.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include "am33xx.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "Phytec AM335x phyCORE";
15 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
24 cpu0-supply = <&vdd1_reg>;
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
34 compatible = "simple-bus";
36 vcc5v: fixedregulator@0 {
37 compatible = "regulator-fixed";
38 regulator-name = "vcc5v";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
58 ethernet0_pins: pinmux_ethernet0 {
59 pinctrl-single,pins = <
60 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
61 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
62 AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
63 AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
64 AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
65 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
66 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
67 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
71 mdio_pins: pinmux_mdio {
72 pinctrl-single,pins = <
74 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
75 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
81 phy_id = <&davinci_mdio>, <0>;
83 dual_emac_res_vlan = <1>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&mdio_pins>;
94 pinctrl-names = "default";
95 pinctrl-0 = <ðernet0_pins>;
105 i2c0_pins: pinmux_i2c0 {
106 pinctrl-single,pins = <
107 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
108 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins>;
116 clock-frequency = <400000>;
123 i2c_eeprom: eeprom@52 {
124 compatible = "atmel,24c32";
131 compatible = "rv4162";
139 nandflash_pins: pinmux_nandflash {
140 pinctrl-single,pins = <
141 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
142 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
143 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
144 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
145 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
146 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
147 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
148 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
149 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
150 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
151 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
152 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
153 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
154 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
165 pinctrl-names = "default";
166 pinctrl-0 = <&nandflash_pins>;
167 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
168 nandflash: nand@0,0 {
169 compatible = "ti,omap2-nand";
170 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
171 interrupt-parent = <&gpmc>;
172 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
173 <1 IRQ_TYPE_NONE>; /* termcount */
174 nand-bus-width = <8>;
175 ti,nand-ecc-opt = "bch8";
176 gpmc,device-nand = "true";
177 gpmc,device-width = <1>;
178 gpmc,sync-clk-ps = <0>;
180 gpmc,cs-rd-off-ns = <30>;
181 gpmc,cs-wr-off-ns = <30>;
182 gpmc,adv-on-ns = <0>;
183 gpmc,adv-rd-off-ns = <30>;
184 gpmc,adv-wr-off-ns = <30>;
186 gpmc,we-off-ns = <20>;
187 gpmc,oe-on-ns = <10>;
188 gpmc,oe-off-ns = <30>;
189 gpmc,access-ns = <30>;
190 gpmc,rd-cycle-ns = <30>;
191 gpmc,wr-cycle-ns = <30>;
192 gpmc,bus-turnaround-ns = <0>;
193 gpmc,cycle2cycle-delay-ns = <50>;
194 gpmc,cycle2cycle-diffcsen;
195 gpmc,clk-activation-ns = <0>;
196 gpmc,wr-access-ns = <30>;
197 gpmc,wr-data-mux-bus-ns = <0>;
201 #address-cells = <1>;
209 label = "xload_backup1";
210 reg = <0x20000 0x20000>;
213 label = "xload_backup2";
214 reg = <0x40000 0x20000>;
217 label = "xload_backup3";
218 reg = <0x60000 0x20000>;
222 reg = <0x80000 0x80000>;
225 label = "bareboxenv";
226 reg = <0x100000 0x40000>;
230 reg = <0x140000 0x40000>;
234 reg = <0x180000 0x800000>;
238 reg = <0x980000 0x0>;
244 #include "tps65910.dtsi"
247 vcc1-supply = <&vcc5v>;
248 vcc2-supply = <&vcc5v>;
249 vcc3-supply = <&vcc5v>;
250 vcc4-supply = <&vcc5v>;
251 vcc5-supply = <&vcc5v>;
252 vcc6-supply = <&vcc5v>;
253 vcc7-supply = <&vcc5v>;
254 vccio-supply = <&vcc5v>;
257 vrtc_reg: regulator@0 {
261 vio_reg: regulator@1 {
265 vdd1_reg: regulator@2 {
266 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
267 regulator-name = "vdd_mpu";
268 regulator-min-microvolt = <912500>;
269 regulator-max-microvolt = <1378000>;
274 vdd2_reg: regulator@3 {
275 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
276 regulator-name = "vdd_core";
277 regulator-min-microvolt = <912500>;
278 regulator-max-microvolt = <1150000>;
283 vdd3_reg: regulator@4 {
287 vdig1_reg: regulator@5 {
288 regulator-name = "vdig1_1p8v";
289 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <1800000>;
293 vdig2_reg: regulator@6 {
297 vpll_reg: regulator@7 {
301 vdac_reg: regulator@8 {
305 vaux1_reg: regulator@9 {
309 vaux2_reg: regulator@10 {
313 vaux33_reg: regulator@11 {
317 vmmc_reg: regulator@12 {
318 regulator-min-microvolt = <3300000>;
319 regulator-max-microvolt = <3300000>;
327 spi0_pins: pinmux_spi0 {
328 pinctrl-single,pins = <
329 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
330 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
331 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
332 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
338 pinctrl-names = "default";
339 pinctrl-0 = <&spi0_pins>;
342 serial_flash: m25p80@0 {
343 compatible = "m25p80";
344 spi-max-frequency = <48000000>;
348 #address-cells = <1>;
357 reg = <0x20000 0x80000>;
360 label = "bareboxenv";
361 reg = <0xa0000 0x20000>;
365 reg = <0xc0000 0x20000>;