2 * Device Tree Source for AM43xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 sys_clkin_ck: sys_clkin_ck@40 {
13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
19 crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
21 compatible = "ti,mux-clock";
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
27 sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
29 compatible = "ti,mux-clock";
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
35 adc_tsc_fck: adc_tsc_fck {
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
43 dcan0_fck: dcan0_fck {
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
51 dcan1_fck: dcan1_fck {
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
59 mcasp0_fck: mcasp0_fck {
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
67 mcasp1_fck: mcasp1_fck {
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
75 smartreflex0_fck: smartreflex0_fck {
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
83 smartreflex1_fck: smartreflex1_fck {
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
93 compatible = "fixed-factor-clock";
94 clocks = <&sys_clkin_ck>;
101 compatible = "fixed-factor-clock";
102 clocks = <&sys_clkin_ck>;
107 ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
109 compatible = "ti,gate-clock";
110 clocks = <&l4ls_gclk>;
115 ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
117 compatible = "ti,gate-clock";
118 clocks = <&l4ls_gclk>;
123 ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
125 compatible = "ti,gate-clock";
126 clocks = <&l4ls_gclk>;
131 ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
133 compatible = "ti,gate-clock";
134 clocks = <&l4ls_gclk>;
139 ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
141 compatible = "ti,gate-clock";
142 clocks = <&l4ls_gclk>;
147 ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
149 compatible = "ti,gate-clock";
150 clocks = <&l4ls_gclk>;
156 clk_32768_ck: clk_32768_ck {
158 compatible = "fixed-clock";
159 clock-frequency = <32768>;
162 clk_rc32k_ck: clk_rc32k_ck {
164 compatible = "fixed-clock";
165 clock-frequency = <32768>;
168 virt_19200000_ck: virt_19200000_ck {
170 compatible = "fixed-clock";
171 clock-frequency = <19200000>;
174 virt_24000000_ck: virt_24000000_ck {
176 compatible = "fixed-clock";
177 clock-frequency = <24000000>;
180 virt_25000000_ck: virt_25000000_ck {
182 compatible = "fixed-clock";
183 clock-frequency = <25000000>;
186 virt_26000000_ck: virt_26000000_ck {
188 compatible = "fixed-clock";
189 clock-frequency = <26000000>;
192 tclkin_ck: tclkin_ck {
194 compatible = "fixed-clock";
195 clock-frequency = <26000000>;
198 dpll_core_ck: dpll_core_ck@2d20 {
200 compatible = "ti,am3-dpll-core-clock";
201 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
202 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
205 dpll_core_x2_ck: dpll_core_x2_ck {
207 compatible = "ti,am3-dpll-x2-clock";
208 clocks = <&dpll_core_ck>;
211 dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
213 compatible = "ti,divider-clock";
214 clocks = <&dpll_core_x2_ck>;
216 ti,autoidle-shift = <8>;
218 ti,index-starts-at-one;
219 ti,invert-autoidle-bit;
222 dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
224 compatible = "ti,divider-clock";
225 clocks = <&dpll_core_x2_ck>;
227 ti,autoidle-shift = <8>;
229 ti,index-starts-at-one;
230 ti,invert-autoidle-bit;
233 dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
235 compatible = "ti,divider-clock";
236 clocks = <&dpll_core_x2_ck>;
238 ti,autoidle-shift = <8>;
240 ti,index-starts-at-one;
241 ti,invert-autoidle-bit;
244 dpll_mpu_ck: dpll_mpu_ck@2d60 {
246 compatible = "ti,am3-dpll-clock";
247 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
248 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
251 dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
253 compatible = "ti,divider-clock";
254 clocks = <&dpll_mpu_ck>;
256 ti,autoidle-shift = <8>;
258 ti,index-starts-at-one;
259 ti,invert-autoidle-bit;
262 mpu_periphclk: mpu_periphclk {
264 compatible = "fixed-factor-clock";
265 clocks = <&dpll_mpu_m2_ck>;
270 dpll_ddr_ck: dpll_ddr_ck@2da0 {
272 compatible = "ti,am3-dpll-clock";
273 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
274 reg = <0x2da0>, <0x2da4>, <0x2dac>;
277 dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
279 compatible = "ti,divider-clock";
280 clocks = <&dpll_ddr_ck>;
282 ti,autoidle-shift = <8>;
284 ti,index-starts-at-one;
285 ti,invert-autoidle-bit;
288 dpll_disp_ck: dpll_disp_ck@2e20 {
290 compatible = "ti,am3-dpll-clock";
291 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
292 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
295 dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
297 compatible = "ti,divider-clock";
298 clocks = <&dpll_disp_ck>;
300 ti,autoidle-shift = <8>;
302 ti,index-starts-at-one;
303 ti,invert-autoidle-bit;
307 dpll_per_ck: dpll_per_ck@2de0 {
309 compatible = "ti,am3-dpll-j-type-clock";
310 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
311 reg = <0x2de0>, <0x2de4>, <0x2dec>;
314 dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
316 compatible = "ti,divider-clock";
317 clocks = <&dpll_per_ck>;
319 ti,autoidle-shift = <8>;
321 ti,index-starts-at-one;
322 ti,invert-autoidle-bit;
325 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
327 compatible = "fixed-factor-clock";
328 clocks = <&dpll_per_m2_ck>;
333 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
335 compatible = "fixed-factor-clock";
336 clocks = <&dpll_per_m2_ck>;
341 clk_24mhz: clk_24mhz {
343 compatible = "fixed-factor-clock";
344 clocks = <&dpll_per_m2_ck>;
349 clkdiv32k_ck: clkdiv32k_ck {
351 compatible = "fixed-factor-clock";
352 clocks = <&clk_24mhz>;
357 clkdiv32k_ick: clkdiv32k_ick@2a38 {
359 compatible = "ti,gate-clock";
360 clocks = <&clkdiv32k_ck>;
365 sysclk_div: sysclk_div {
367 compatible = "fixed-factor-clock";
368 clocks = <&dpll_core_m4_ck>;
373 pruss_ocp_gclk: pruss_ocp_gclk@4248 {
375 compatible = "ti,mux-clock";
376 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
380 clk_32k_tpm_ck: clk_32k_tpm_ck {
382 compatible = "fixed-clock";
383 clock-frequency = <32768>;
386 timer1_fck: timer1_fck@4200 {
388 compatible = "ti,mux-clock";
389 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
393 timer2_fck: timer2_fck@4204 {
395 compatible = "ti,mux-clock";
396 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
400 timer3_fck: timer3_fck@4208 {
402 compatible = "ti,mux-clock";
403 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
407 timer4_fck: timer4_fck@420c {
409 compatible = "ti,mux-clock";
410 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
414 timer5_fck: timer5_fck@4210 {
416 compatible = "ti,mux-clock";
417 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
421 timer6_fck: timer6_fck@4214 {
423 compatible = "ti,mux-clock";
424 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
428 timer7_fck: timer7_fck@4218 {
430 compatible = "ti,mux-clock";
431 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
435 wdt1_fck: wdt1_fck@422c {
437 compatible = "ti,mux-clock";
438 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
444 compatible = "fixed-factor-clock";
445 clocks = <&dpll_core_m4_ck>;
450 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
452 compatible = "fixed-factor-clock";
453 clocks = <&sysclk_div>;
458 l4hs_gclk: l4hs_gclk {
460 compatible = "fixed-factor-clock";
461 clocks = <&dpll_core_m4_ck>;
468 compatible = "fixed-factor-clock";
469 clocks = <&dpll_core_m4_div2_ck>;
474 l4ls_gclk: l4ls_gclk {
476 compatible = "fixed-factor-clock";
477 clocks = <&dpll_core_m4_div2_ck>;
482 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
484 compatible = "fixed-factor-clock";
485 clocks = <&dpll_core_m5_ck>;
490 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
492 compatible = "ti,mux-clock";
493 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
497 dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
499 compatible = "ti,divider-clock";
500 clocks = <&dpll_core_m5_ck>;
503 ti,dividers = <2>, <5>;
506 clk_32k_mosc_ck: clk_32k_mosc_ck {
508 compatible = "fixed-clock";
509 clock-frequency = <32768>;
512 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
514 compatible = "ti,mux-clock";
515 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
519 gpio0_dbclk: gpio0_dbclk@2b68 {
521 compatible = "ti,gate-clock";
522 clocks = <&gpio0_dbclk_mux_ck>;
527 gpio1_dbclk: gpio1_dbclk@8c78 {
529 compatible = "ti,gate-clock";
530 clocks = <&clkdiv32k_ick>;
535 gpio2_dbclk: gpio2_dbclk@8c80 {
537 compatible = "ti,gate-clock";
538 clocks = <&clkdiv32k_ick>;
543 gpio3_dbclk: gpio3_dbclk@8c88 {
545 compatible = "ti,gate-clock";
546 clocks = <&clkdiv32k_ick>;
551 gpio4_dbclk: gpio4_dbclk@8c90 {
553 compatible = "ti,gate-clock";
554 clocks = <&clkdiv32k_ick>;
559 gpio5_dbclk: gpio5_dbclk@8c98 {
561 compatible = "ti,gate-clock";
562 clocks = <&clkdiv32k_ick>;
569 compatible = "fixed-factor-clock";
570 clocks = <&dpll_per_m2_ck>;
575 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
577 compatible = "ti,mux-clock";
578 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
583 gfx_fck_div_ck: gfx_fck_div_ck@423c {
585 compatible = "ti,divider-clock";
586 clocks = <&gfx_fclk_clksel_ck>;
591 disp_clk: disp_clk@4244 {
593 compatible = "ti,mux-clock";
594 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
599 dpll_extdev_ck: dpll_extdev_ck@2e60 {
601 compatible = "ti,am3-dpll-clock";
602 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
603 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
606 dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
608 compatible = "ti,divider-clock";
609 clocks = <&dpll_extdev_ck>;
611 ti,autoidle-shift = <8>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
617 mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
619 compatible = "ti,mux-clock";
620 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
624 synctimer_32kclk: synctimer_32kclk@2a30 {
626 compatible = "ti,gate-clock";
627 clocks = <&mux_synctimer32k_ck>;
632 timer8_fck: timer8_fck@421c {
634 compatible = "ti,mux-clock";
635 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
639 timer9_fck: timer9_fck@4220 {
641 compatible = "ti,mux-clock";
642 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
646 timer10_fck: timer10_fck@4224 {
648 compatible = "ti,mux-clock";
649 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
653 timer11_fck: timer11_fck@4228 {
655 compatible = "ti,mux-clock";
656 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
660 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
662 compatible = "fixed-factor-clock";
663 clocks = <&dpll_core_m5_ck>;
668 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
670 compatible = "fixed-factor-clock";
671 clocks = <&cpsw_50m_clkdiv>;
676 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
678 compatible = "ti,am3-dpll-x2-clock";
679 clocks = <&dpll_ddr_ck>;
682 dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
684 compatible = "ti,divider-clock";
685 clocks = <&dpll_ddr_x2_ck>;
687 ti,autoidle-shift = <8>;
689 ti,index-starts-at-one;
690 ti,invert-autoidle-bit;
693 dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
695 compatible = "ti,fixed-factor-clock";
696 clocks = <&dpll_per_ck>;
699 ti,autoidle-shift = <8>;
701 ti,invert-autoidle-bit;
704 dll_aging_clk_div: dll_aging_clk_div@4250 {
706 compatible = "ti,divider-clock";
707 clocks = <&sys_clkin_ck>;
709 ti,dividers = <8>, <16>, <32>;
712 div_core_25m_ck: div_core_25m_ck {
714 compatible = "fixed-factor-clock";
715 clocks = <&sysclk_div>;
720 func_12m_clk: func_12m_clk {
722 compatible = "fixed-factor-clock";
723 clocks = <&dpll_per_m2_ck>;
728 vtp_clk_div: vtp_clk_div {
730 compatible = "fixed-factor-clock";
731 clocks = <&sys_clkin_ck>;
736 usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
738 compatible = "ti,mux-clock";
739 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
743 usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
745 compatible = "ti,gate-clock";
746 clocks = <&usbphy_32khz_clkmux>;
751 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
753 compatible = "ti,gate-clock";
754 clocks = <&usbphy_32khz_clkmux>;
759 usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
761 compatible = "ti,gate-clock";
762 clocks = <&dpll_per_clkdcoldo>;
767 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
769 compatible = "ti,gate-clock";
770 clocks = <&dpll_per_clkdcoldo>;
775 clkout1_osc_div_ck: clkout1_osc_div_ck {
777 compatible = "ti,divider-clock";
778 clocks = <&sys_clkin_ck>;
784 clkout1_src2_mux_ck: clkout1_src2_mux_ck {
786 compatible = "ti,mux-clock";
787 clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
788 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
793 clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
795 compatible = "ti,divider-clock";
796 clocks = <&clkout1_src2_mux_ck>;
802 clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
804 compatible = "ti,divider-clock";
805 clocks = <&clkout1_src2_pre_div_ck>;
808 ti,index-power-of-two;
812 clkout1_mux_ck: clkout1_mux_ck {
814 compatible = "ti,mux-clock";
815 clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
816 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
821 clkout1_ck: clkout1_ck {
823 compatible = "ti,gate-clock";
824 clocks = <&clkout1_mux_ck>;