arch/arm/boot/dts/arm-realview-eb-a9mp.dts

   1 /*
   2  * Copyright 2016 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include "arm-realview-eb-mp.dtsi"
  25
  26 / {
  27         model = "ARM RealView EB Cortex A9 MPCore";
  28
  29         /*
  30          * This is the Cortex A9 MPCore tile used with the
  31          * RealView EB.
  32          */
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36                 enable-method = "arm,realview-smp";
  37
  38                 A9_0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <0>;
  42                         next-level-cache = <&L2>;
  43                 };
  44
  45                 A9_1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         reg = <1>;
  49                         next-level-cache = <&L2>;
  50                 };
  51
  52                 A9_2: cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                 };
  58
  59                 A9_3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a9";
  62                         reg = <3>;
  63                         next-level-cache = <&L2>;
  64                 };
  65         };
  66 };
  67
  68 &pmu {
  69         interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
  70 };