arch/arm/boot/dts/armada-385-db-ap.dts

   1 /*
   2  * Device Tree file for Marvell Armada 385 Access Point Development board
   3  * (DB-88F6820-AP)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Nadav Haklai <nadavh@marvell.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is licensed under the terms of the GNU General Public
  15  *     License version 2.  This program is licensed "as is" without
  16  *     any warranty of any kind, whether express or implied.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43 #include "armada-385.dtsi"
  44
  45 #include <dt-bindings/gpio/gpio.h>
  46
  47 / {
  48         model = "Marvell Armada 385 Access Point Development Board";
  49         compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
  50
  51         chosen {
  52                 stdout-path = "serial1:115200n8";
  53         };
  54
  55         memory {
  56                 device_type = "memory";
  57                 reg = <0x00000000 0x80000000>; /* 2GB */
  58         };
  59
  60         soc {
  61                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  62                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  63
  64                 internal-regs {
  65                         spi1: spi@10680 {
  66                                 pinctrl-names = "default";
  67                                 pinctrl-0 = <&spi1_pins>;
  68                                 status = "okay";
  69
  70                                 spi-flash@0 {
  71                                         #address-cells = <1>;
  72                                         #size-cells = <1>;
  73                                         compatible = "st,m25p128", "jedec,spi-nor";
  74                                         reg = <0>; /* Chip select 0 */
  75                                         spi-max-frequency = <54000000>;
  76                                 };
  77                         };
  78
  79                         i2c0: i2c@11000 {
  80                                 pinctrl-names = "default";
  81                                 pinctrl-0 = <&i2c0_pins>;
  82                                 status = "okay";
  83
  84                                 /*
  85                                  * This bus is wired to two EEPROM
  86                                  * sockets, one of which holding the
  87                                  * board ID used by the bootloader.
  88                                  * Erasing this EEPROM's content will
  89                                  * brick the board.
  90                                  * Use this bus with caution.
  91                                  */
  92                         };
  93
  94                         mdio@72004 {
  95                                 pinctrl-names = "default";
  96                                 pinctrl-0 = <&mdio_pins>;
  97
  98                                 phy0: ethernet-phy@1 {
  99                                         reg = <1>;
 100                                 };
 101
 102                                 phy1: ethernet-phy@4 {
 103                                         reg = <4>;
 104                                 };
 105
 106                                 phy2: ethernet-phy@6 {
 107                                         reg = <6>;
 108                                 };
 109                         };
 110
 111                         /* UART0 is exposed through the JP8 connector */
 112                         uart0: serial@12000 {
 113                                 pinctrl-names = "default";
 114                                 pinctrl-0 = <&uart0_pins>;
 115                                 status = "okay";
 116                         };
 117
 118                         /*
 119                          * UART1 is exposed through a FTDI chip
 120                          * wired to the mini-USB connector
 121                          */
 122                         uart1: serial@12100 {
 123                                 pinctrl-names = "default";
 124                                 pinctrl-0 = <&uart1_pins>;
 125                                 status = "okay";
 126                         };
 127
 128                         pinctrl@18000 {
 129                                 xhci0_vbus_pins: xhci0-vbus-pins {
 130                                         marvell,pins = "mpp44";
 131                                         marvell,function = "gpio";
 132                                 };
 133                         };
 134
 135                         ethernet@30000 {
 136                                 status = "okay";
 137                                 phy = <&phy2>;
 138                                 phy-mode = "sgmii";
 139                         };
 140
 141                         ethernet@34000 {
 142                                 status = "okay";
 143                                 phy = <&phy1>;
 144                                 phy-mode = "sgmii";
 145                         };
 146
 147                         ethernet@70000 {
 148                                 pinctrl-names = "default";
 149
 150                                 /*
 151                                  * The Reference Clock 0 is used to
 152                                  * provide a clock to the PHY
 153                                  */
 154                                 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
 155                                 status = "okay";
 156                                 phy = <&phy0>;
 157                                 phy-mode = "rgmii-id";
 158                         };
 159
 160                         nfc: flash@d0000 {
 161                                 status = "okay";
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164
 165                                 num-cs = <1>;
 166                                 nand-ecc-strength = <4>;
 167                                 nand-ecc-step-size = <512>;
 168                                 marvell,nand-keep-config;
 169                                 marvell,nand-enable-arbiter;
 170                                 nand-on-flash-bbt;
 171                         };
 172
 173                         usb3@f0000 {
 174                                 status = "okay";
 175                                 usb-phy = <&usb3_phy>;
 176                         };
 177                 };
 178
 179                 pcie-controller {
 180                         status = "okay";
 181
 182                         /*
 183                          * The three PCIe units are accessible through
 184                          * standard mini-PCIe slots on the board.
 185                          */
 186                         pcie@1,0 {
 187                                 /* Port 0, Lane 0 */
 188                                 status = "okay";
 189                         };
 190
 191                         pcie@2,0 {
 192                                 /* Port 1, Lane 0 */
 193                                 status = "okay";
 194                         };
 195
 196                         pcie@3,0 {
 197                                 /* Port 2, Lane 0 */
 198                                 status = "okay";
 199                         };
 200                 };
 201         };
 202
 203         usb3_phy: usb3_phy {
 204                 compatible = "usb-nop-xceiv";
 205                 vcc-supply = <&reg_xhci0_vbus>;
 206         };
 207
 208         reg_xhci0_vbus: xhci0-vbus {
 209                 compatible = "regulator-fixed";
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&xhci0_vbus_pins>;
 212                 regulator-name = "xhci0-vbus";
 213                 regulator-min-microvolt = <5000000>;
 214                 regulator-max-microvolt = <5000000>;
 215                 enable-active-high;
 216                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 217         };
 218 };