arch/arm/boot/dts/armada-388-clearfog.dts

   1 /*
   2  * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
   3  *
   4  *  Copyright (C) 2015 Russell King
   5  *
   6  * This board is in development; the contents of this file work with
   7  * the A1 rev 2.0 of the board, which does not represent final
   8  * production board.  Things will change, don't expect this file to
   9  * remain compatible info the future.
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License
  18  *     version 2 as published by the Free Software Foundation.
  19  *
  20  *     This file is distributed in the hope that it will be useful
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include "armada-388.dtsi"
  51 #include "armada-38x-solidrun-microsom.dtsi"
  52
  53 / {
  54         model = "SolidRun Clearfog A1";
  55         compatible = "solidrun,clearfog-a1", "marvell,armada388",
  56                 "marvell,armada385", "marvell,armada380";
  57
  58         aliases {
  59                 /* So that mvebu u-boot can update the MAC addresses */
  60                 ethernet1 = &eth0;
  61                 ethernet2 = &eth1;
  62                 ethernet3 = &eth2;
  63         };
  64
  65         chosen {
  66                 stdout-path = "serial0:115200n8";
  67         };
  68
  69         reg_3p3v: regulator-3p3v {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "3P3V";
  72                 regulator-min-microvolt = <3300000>;
  73                 regulator-max-microvolt = <3300000>;
  74                 regulator-always-on;
  75         };
  76
  77         soc {
  78                 internal-regs {
  79                         ethernet@30000 {
  80                                 phy-mode = "sgmii";
  81                                 buffer-manager = <&bm>;
  82                                 bm,pool-long = <2>;
  83                                 bm,pool-short = <1>;
  84                                 status = "okay";
  85
  86                                 fixed-link {
  87                                         speed = <1000>;
  88                                         full-duplex;
  89                                 };
  90                         };
  91
  92                         ethernet@34000 {
  93                                 phy-mode = "sgmii";
  94                                 buffer-manager = <&bm>;
  95                                 bm,pool-long = <3>;
  96                                 bm,pool-short = <1>;
  97                                 status = "okay";
  98
  99                                 fixed-link {
 100                                         speed = <1000>;
 101                                         full-duplex;
 102                                 };
 103                         };
 104
 105                         i2c@11000 {
 106                                 /* Is there anything on this? */
 107                                 clock-frequency = <100000>;
 108                                 pinctrl-0 = <&i2c0_pins>;
 109                                 pinctrl-names = "default";
 110                                 status = "okay";
 111
 112                                 /*
 113                                  * PCA9655 GPIO expander, up to 1MHz clock.
 114                                  *  0-CON3 CLKREQ#
 115                                  *  1-CON3 PERST#
 116                                  *  2-CON2 PERST#
 117                                  *  3-CON3 W_DISABLE
 118                                  *  4-CON2 CLKREQ#
 119                                  *  5-USB3 overcurrent
 120                                  *  6-USB3 power
 121                                  *  7-CON2 W_DISABLE
 122                                  *  8-JP4 P1
 123                                  *  9-JP4 P4
 124                                  * 10-JP4 P5
 125                                  * 11-m.2 DEVSLP
 126                                  * 12-SFP_LOS
 127                                  * 13-SFP_TX_FAULT
 128                                  * 14-SFP_TX_DISABLE
 129                                  * 15-SFP_MOD_DEF0
 130                                  */
 131                                 expander0: gpio-expander@20 {
 132                                         /*
 133                                          * This is how it should be:
 134                                          * compatible = "onnn,pca9655",
 135                                          *       "nxp,pca9555";
 136                                          * but you can't do this because of
 137                                          * the way I2C works.
 138                                          */
 139                                         compatible = "nxp,pca9555";
 140                                         gpio-controller;
 141                                         #gpio-cells = <2>;
 142                                         reg = <0x20>;
 143
 144                                         pcie1_0_clkreq {
 145                                                 gpio-hog;
 146                                                 gpios = <0 GPIO_ACTIVE_LOW>;
 147                                                 input;
 148                                                 line-name = "pcie1.0-clkreq";
 149                                         };
 150                                         pcie1_0_w_disable {
 151                                                 gpio-hog;
 152                                                 gpios = <3 GPIO_ACTIVE_LOW>;
 153                                                 output-low;
 154                                                 line-name = "pcie1.0-w-disable";
 155                                         };
 156                                         pcie2_0_clkreq {
 157                                                 gpio-hog;
 158                                                 gpios = <4 GPIO_ACTIVE_LOW>;
 159                                                 input;
 160                                                 line-name = "pcie2.0-clkreq";
 161                                         };
 162                                         pcie2_0_w_disable {
 163                                                 gpio-hog;
 164                                                 gpios = <7 GPIO_ACTIVE_LOW>;
 165                                                 output-low;
 166                                                 line-name = "pcie2.0-w-disable";
 167                                         };
 168                                         usb3_ilimit {
 169                                                 gpio-hog;
 170                                                 gpios = <5 GPIO_ACTIVE_LOW>;
 171                                                 input;
 172                                                 line-name = "usb3-current-limit";
 173                                         };
 174                                         usb3_power {
 175                                                 gpio-hog;
 176                                                 gpios = <6 GPIO_ACTIVE_HIGH>;
 177                                                 output-high;
 178                                                 line-name = "usb3-power";
 179                                         };
 180                                         m2_devslp {
 181                                                 gpio-hog;
 182                                                 gpios = <11 GPIO_ACTIVE_HIGH>;
 183                                                 output-low;
 184                                                 line-name = "m.2 devslp";
 185                                         };
 186                                         sfp_los {
 187                                                 /* SFP loss of signal */
 188                                                 gpio-hog;
 189                                                 gpios = <12 GPIO_ACTIVE_HIGH>;
 190                                                 input;
 191                                                 line-name = "sfp-los";
 192                                         };
 193                                         sfp_tx_fault {
 194                                                 /* SFP laser fault */
 195                                                 gpio-hog;
 196                                                 gpios = <13 GPIO_ACTIVE_HIGH>;
 197                                                 input;
 198                                                 line-name = "sfp-tx-fault";
 199                                         };
 200                                         sfp_tx_disable {
 201                                                 /* SFP transmit disable */
 202                                                 gpio-hog;
 203                                                 gpios = <14 GPIO_ACTIVE_HIGH>;
 204                                                 output-low;
 205                                                 line-name = "sfp-tx-disable";
 206                                         };
 207                                         sfp_mod_def0 {
 208                                                 /* SFP module present */
 209                                                 gpio-hog;
 210                                                 gpios = <15 GPIO_ACTIVE_LOW>;
 211                                                 input;
 212                                                 line-name = "sfp-mod-def0";
 213                                         };
 214                                 };
 215
 216                                 /* The MCP3021 is 100kHz clock only */
 217                                 mikrobus_adc: mcp3021@4c {
 218                                         compatible = "microchip,mcp3021";
 219                                         reg = <0x4c>;
 220                                 };
 221
 222                                 /* Also something at 0x64 */
 223                         };
 224
 225                         i2c@11100 {
 226                                 /*
 227                                  * Routed to SFP, mikrobus, and PCIe.
 228                                  * SFP limits this to 100kHz, and requires
 229                                  *  an AT24C01A/02/04 with address pins tied
 230                                  *  low, which takes addresses 0x50 and 0x51.
 231                                  * Mikrobus doesn't specify beyond an I2C
 232                                  *  bus being present.
 233                                  * PCIe uses ARP to assign addresses, or
 234                                  *  0x63-0x64.
 235                                  */
 236                                 clock-frequency = <100000>;
 237                                 pinctrl-0 = <&clearfog_i2c1_pins>;
 238                                 pinctrl-names = "default";
 239                                 status = "okay";
 240                         };
 241
 242                         mdio@72004 {
 243                                 pinctrl-0 = <&mdio_pins>;
 244                                 pinctrl-names = "default";
 245
 246                                 phy_dedicated: ethernet-phy@0 {
 247                                         /*
 248                                          * Annoyingly, the marvell phy driver
 249                                          * configures the LED register, rather
 250                                          * than preserving reset-loaded setting.
 251                                          * We undo that rubbish here.
 252                                          */
 253                                         marvell,reg-init = <3 16 0 0x101e>;
 254                                         reg = <0>;
 255                                 };
 256                         };
 257
 258                         pinctrl@18000 {
 259                                 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
 260                                         marvell,pins = "mpp46";
 261                                         marvell,function = "ref";
 262                                 };
 263                                 clearfog_dsa0_pins: clearfog-dsa0-pins {
 264                                         marvell,pins = "mpp23", "mpp41";
 265                                         marvell,function = "gpio";
 266                                 };
 267                                 clearfog_i2c1_pins: i2c1-pins {
 268                                         /* SFP, PCIe, mSATA, mikrobus */
 269                                         marvell,pins = "mpp26", "mpp27";
 270                                         marvell,function = "i2c1";
 271                                 };
 272                                 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
 273                                         marvell,pins = "mpp20";
 274                                         marvell,function = "gpio";
 275                                 };
 276                                 clearfog_sdhci_pins: clearfog-sdhci-pins {
 277                                         marvell,pins = "mpp21", "mpp28",
 278                                                        "mpp37", "mpp38",
 279                                                        "mpp39", "mpp40";
 280                                         marvell,function = "sd0";
 281                                 };
 282                                 clearfog_spi1_cs_pins: spi1-cs-pins {
 283                                         marvell,pins = "mpp55";
 284                                         marvell,function = "spi1";
 285                                 };
 286                                 mikro_pins: mikro-pins {
 287                                         /* int: mpp22 rst: mpp29 */
 288                                         marvell,pins = "mpp22", "mpp29";
 289                                         marvell,function = "gpio";
 290                                 };
 291                                 mikro_spi_pins: mikro-spi-pins {
 292                                         marvell,pins = "mpp43";
 293                                         marvell,function = "spi1";
 294                                 };
 295                                 mikro_uart_pins: mikro-uart-pins {
 296                                         marvell,pins = "mpp24", "mpp25";
 297                                         marvell,function = "ua1";
 298                                 };
 299                                 rear_button_pins: rear-button-pins {
 300                                         marvell,pins = "mpp34";
 301                                         marvell,function = "gpio";
 302                                 };
 303                         };
 304
 305                         sata@a8000 {
 306                                 /* pinctrl? */
 307                                 status = "okay";
 308                         };
 309
 310                         sata@e0000 {
 311                                 /* pinctrl? */
 312                                 status = "okay";
 313                         };
 314
 315                         sdhci@d8000 {
 316                                 bus-width = <4>;
 317                                 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 318                                 no-1-8-v;
 319                                 pinctrl-0 = <&clearfog_sdhci_pins
 320                                              &clearfog_sdhci_cd_pins>;
 321                                 pinctrl-names = "default";
 322                                 status = "okay";
 323                                 vmmc = <&reg_3p3v>;
 324                                 wp-inverted;
 325                         };
 326
 327                         serial@12100 {
 328                                 /* mikrobus uart */
 329                                 pinctrl-0 = <&mikro_uart_pins>;
 330                                 pinctrl-names = "default";
 331                                 status = "okay";
 332                         };
 333
 334                         spi@10680 {
 335                                 /*
 336                                  * We don't seem to have the W25Q32 on the
 337                                  * A1 Rev 2.0 boards, so disable SPI.
 338                                  * CS0: W25Q32 (doesn't appear to be present)
 339                                  * CS1:
 340                                  * CS2: mikrobus
 341                                  */
 342                                 pinctrl-0 = <&spi1_pins
 343                                              &clearfog_spi1_cs_pins
 344                                              &mikro_spi_pins>;
 345                                 pinctrl-names = "default";
 346                                 status = "okay";
 347
 348                                 spi-flash@0 {
 349                                         #address-cells = <1>;
 350                                         #size-cells = <0>;
 351                                         compatible = "w25q32", "jedec,spi-nor";
 352                                         reg = <0>; /* Chip select 0 */
 353                                         spi-max-frequency = <3000000>;
 354                                         status = "disabled";
 355                                 };
 356                         };
 357
 358                         usb@58000 {
 359                                 /* CON3, nearest  power. */
 360                                 status = "okay";
 361                         };
 362
 363                         usb3@f0000 {
 364                                 /* CON2, nearest CPU, USB2 only. */
 365                                 status = "okay";
 366                         };
 367
 368                         usb3@f8000 {
 369                                 /* CON7 */
 370                                 status = "okay";
 371                         };
 372                 };
 373
 374                 pcie-controller {
 375                         status = "okay";
 376                         /*
 377                          * The two PCIe units are accessible through
 378                          * the mini-PCIe connectors on the board.
 379                          */
 380                         pcie@2,0 {
 381                                 /* Port 1, Lane 0. CON3, nearest power. */
 382                                 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
 383                                 status = "okay";
 384                         };
 385                         pcie@3,0 {
 386                                 /* Port 2, Lane 0. CON2, nearest CPU. */
 387                                 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
 388                                 status = "okay";
 389                         };
 390                 };
 391         };
 392
 393         dsa@0 {
 394                 compatible = "marvell,dsa";
 395                 dsa,ethernet = <&eth1>;
 396                 dsa,mii-bus = <&mdio>;
 397                 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
 398                 pinctrl-names = "default";
 399                 #address-cells = <2>;
 400                 #size-cells = <0>;
 401
 402                 switch@0 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         reg = <4 0>;
 406
 407                         port@0 {
 408                                 reg = <0>;
 409                                 label = "lan1";
 410                         };
 411
 412                         port@1 {
 413                                 reg = <1>;
 414                                 label = "lan2";
 415                         };
 416
 417                         port@2 {
 418                                 reg = <2>;
 419                                 label = "lan3";
 420                         };
 421
 422                         port@3 {
 423                                 reg = <3>;
 424                                 label = "lan4";
 425                         };
 426
 427                         port@4 {
 428                                 reg = <4>;
 429                                 label = "lan5";
 430                         };
 431
 432                         port@5 {
 433                                 reg = <5>;
 434                                 label = "cpu";
 435                         };
 436
 437                         port@6 {
 438                                 /* 88E1512 external phy */
 439                                 reg = <6>;
 440                                 label = "lan6";
 441                                 fixed-link {
 442                                         speed = <1000>;
 443                                         full-duplex;
 444                                 };
 445                         };
 446                 };
 447         };
 448
 449         gpio-keys {
 450                 compatible = "gpio-keys";
 451                 pinctrl-0 = <&rear_button_pins>;
 452                 pinctrl-names = "default";
 453
 454                 button_0 {
 455                         /* The rear SW3 button */
 456                         label = "Rear Button";
 457                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 458                         linux,can-disable;
 459                         linux,code = <BTN_0>;
 460                 };
 461         };
 462 };