arch/arm/boot/dts/armada-xp-axpwifiap.dts

   1 /*
   2  * Device Tree file for Marvell RD-AXPWiFiAP.
   3  *
   4  * Note: this board is shipped with a new generation boot loader that
   5  * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
   6  * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
   7  * used.
   8  *
   9  * Copyright (C) 2013 Marvell
  10  *
  11  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public
  14  * License version 2.  This program is licensed "as is" without any
  15  * warranty of any kind, whether express or implied.
  16  */
  17
  18 /dts-v1/;
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/input/input.h>
  21 #include "armada-xp-mv78230.dtsi"
  22
  23 / {
  24         model = "Marvell RD-AXPWiFiAP";
  25         compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
  26
  27         chosen {
  28                 bootargs = "console=ttyS0,115200 earlyprintk";
  29         };
  30
  31         memory {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
  34         };
  35
  36         soc {
  37                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  38                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
  39
  40                 pcie-controller {
  41                         status = "okay";
  42
  43                         /* First mini-PCIe port */
  44                         pcie@1,0 {
  45                                 /* Port 0, Lane 0 */
  46                                 status = "okay";
  47                         };
  48
  49                         /* Second mini-PCIe port */
  50                         pcie@2,0 {
  51                                 /* Port 0, Lane 1 */
  52                                 status = "okay";
  53                         };
  54
  55                         /* Renesas uPD720202 USB 3.0 controller */
  56                         pcie@3,0 {
  57                                 /* Port 0, Lane 3 */
  58                                 status = "okay";
  59                         };
  60                 };
  61
  62                 internal-regs {
  63                         serial@12000 {
  64                                 status = "okay";
  65                         };
  66
  67                         serial@12100 {
  68                                 status = "okay";
  69                         };
  70
  71                         sata@a0000 {
  72                                 nr-ports = <1>;
  73                                 status = "okay";
  74                         };
  75
  76                         mdio {
  77                                 phy0: ethernet-phy@0 {
  78                                         reg = <0>;
  79                                 };
  80
  81                                 phy1: ethernet-phy@1 {
  82                                         reg = <1>;
  83                                 };
  84                         };
  85
  86                         ethernet@70000 {
  87                                 pinctrl-0 = <&ge0_rgmii_pins>;
  88                                 pinctrl-names = "default";
  89                                 status = "okay";
  90                                 phy = <&phy0>;
  91                                 phy-mode = "rgmii-id";
  92                         };
  93                         ethernet@74000 {
  94                                 pinctrl-0 = <&ge1_rgmii_pins>;
  95                                 pinctrl-names = "default";
  96                                 status = "okay";
  97                                 phy = <&phy1>;
  98                                 phy-mode = "rgmii-id";
  99                         };
 100
 101                         spi0: spi@10600 {
 102                                 status = "okay";
 103
 104                                 spi-flash@0 {
 105                                         #address-cells = <1>;
 106                                         #size-cells = <1>;
 107                                         compatible = "n25q128a13";
 108                                         reg = <0>; /* Chip select 0 */
 109                                         spi-max-frequency = <108000000>;
 110                                 };
 111                         };
 112                 };
 113         };
 114
 115         gpio_keys {
 116                 compatible = "gpio-keys";
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119                 pinctrl-0 = <&keys_pin>;
 120                 pinctrl-names = "default";
 121
 122                 button@1 {
 123                         label = "Factory Reset Button";
 124                         linux,code = <KEY_SETUP>;
 125                         gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 126                 };
 127         };
 128 };
 129
 130 &pinctrl {
 131         pinctrl-0 = <&phy_int_pin>;
 132         pinctrl-names = "default";
 133
 134         keys_pin: keys-pin {
 135                 marvell,pins = "mpp33";
 136                 marvell,function = "gpio";
 137         };
 138
 139         phy_int_pin: phy-int-pin {
 140                 marvell,pins = "mpp32";
 141                 marvell,function = "gpio";
 142         };
 143 };