arch/arm/boot/dts/armada-xp-mv78460.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  *
  12  * Contains definitions specific to the Armada XP MV78460 SoC that are not
  13  * common to all Armada XP SoCs.
  14  */
  15
  16 /include/ "armada-xp.dtsi"
  17
  18 / {
  19         model = "Marvell Armada XP MV78460 SoC";
  20         compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26                 eth3 = &eth3;
  27         };
  28
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "marvell,sheeva-v7";
  37                         reg = <0>;
  38                         clocks = <&cpuclk 0>;
  39                 };
  40
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "marvell,sheeva-v7";
  44                         reg = <1>;
  45                         clocks = <&cpuclk 1>;
  46                 };
  47
  48                 cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "marvell,sheeva-v7";
  51                         reg = <2>;
  52                         clocks = <&cpuclk 2>;
  53                 };
  54
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "marvell,sheeva-v7";
  58                         reg = <3>;
  59                         clocks = <&cpuclk 3>;
  60                 };
  61         };
  62
  63         soc {
  64                 internal-regs {
  65                         pinctrl {
  66                                 compatible = "marvell,mv78460-pinctrl";
  67                                 reg = <0x18000 0x38>;
  68
  69                                 sdio_pins: sdio-pins {
  70                                         marvell,pins = "mpp30", "mpp31", "mpp32",
  71                                                        "mpp33", "mpp34", "mpp35";
  72                                         marvell,function = "sd0";
  73                                 };
  74                         };
  75
  76                         gpio0: gpio@18100 {
  77                                 compatible = "marvell,orion-gpio";
  78                                 reg = <0x18100 0x40>;
  79                                 ngpios = <32>;
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                                 interrupt-controller;
  83                                 #interrupts-cells = <2>;
  84                                 interrupts = <82>, <83>, <84>, <85>;
  85                         };
  86
  87                         gpio1: gpio@18140 {
  88                                 compatible = "marvell,orion-gpio";
  89                                 reg = <0x18140 0x40>;
  90                                 ngpios = <32>;
  91                                 gpio-controller;
  92                                 #gpio-cells = <2>;
  93                                 interrupt-controller;
  94                                 #interrupts-cells = <2>;
  95                                 interrupts = <87>, <88>, <89>, <90>;
  96                         };
  97
  98                         gpio2: gpio@18180 {
  99                                 compatible = "marvell,orion-gpio";
 100                                 reg = <0x18180 0x40>;
 101                                 ngpios = <3>;
 102                                 gpio-controller;
 103                                 #gpio-cells = <2>;
 104                                 interrupt-controller;
 105                                 #interrupts-cells = <2>;
 106                                 interrupts = <91>;
 107                         };
 108
 109                         eth3: ethernet@34000 {
 110                                 compatible = "marvell,armada-370-neta";
 111                                 reg = <0x34000 0x4000>;
 112                                 interrupts = <14>;
 113                                 clocks = <&gateclk 1>;
 114                                 status = "disabled";
 115                         };
 116
 117                         /*
 118                          * MV78460 has 4 PCIe units Gen2.0: Two units can be
 119                          * configured as x4 or quad x1 lanes. Two units are
 120                          * x4/x1.
 121                          */
 122                         pcie-controller {
 123                                 compatible = "marvell,armada-xp-pcie";
 124                                 status = "disabled";
 125                                 device_type = "pci";
 126
 127                                 #address-cells = <3>;
 128                                 #size-cells = <2>;
 129
 130                                 bus-range = <0x00 0xff>;
 131
 132                                 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 133                                         0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
 134                                         0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
 135                                         0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
 136                                         0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
 137                                         0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 138                                         0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
 139                                         0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
 140                                         0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
 141                                         0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
 142                                         0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 143                                         0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
 144
 145                                 pcie@1,0 {
 146                                         device_type = "pci";
 147                                         assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 148                                         reg = <0x0800 0 0 0 0>;
 149                                         #address-cells = <3>;
 150                                         #size-cells = <2>;
 151                                         #interrupt-cells = <1>;
 152                                         ranges;
 153                                         interrupt-map-mask = <0 0 0 0>;
 154                                         interrupt-map = <0 0 0 0 &mpic 58>;
 155                                         marvell,pcie-port = <0>;
 156                                         marvell,pcie-lane = <0>;
 157                                         clocks = <&gateclk 5>;
 158                                         status = "disabled";
 159                                 };
 160
 161                                 pcie@2,0 {
 162                                         device_type = "pci";
 163                                         assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 164                                         reg = <0x1000 0 0 0 0>;
 165                                         #address-cells = <3>;
 166                                         #size-cells = <2>;
 167                                         #interrupt-cells = <1>;
 168                                         ranges;
 169                                         interrupt-map-mask = <0 0 0 0>;
 170                                         interrupt-map = <0 0 0 0 &mpic 59>;
 171                                         marvell,pcie-port = <0>;
 172                                         marvell,pcie-lane = <1>;
 173                                         clocks = <&gateclk 6>;
 174                                         status = "disabled";
 175                                 };
 176
 177                                 pcie@3,0 {
 178                                         device_type = "pci";
 179                                         assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 180                                         reg = <0x1800 0 0 0 0>;
 181                                         #address-cells = <3>;
 182                                         #size-cells = <2>;
 183                                         #interrupt-cells = <1>;
 184                                         ranges;
 185                                         interrupt-map-mask = <0 0 0 0>;
 186                                         interrupt-map = <0 0 0 0 &mpic 60>;
 187                                         marvell,pcie-port = <0>;
 188                                         marvell,pcie-lane = <2>;
 189                                         clocks = <&gateclk 7>;
 190                                         status = "disabled";
 191                                 };
 192
 193                                 pcie@4,0 {
 194                                         device_type = "pci";
 195                                         assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 196                                         reg = <0x2000 0 0 0 0>;
 197                                         #address-cells = <3>;
 198                                         #size-cells = <2>;
 199                                         #interrupt-cells = <1>;
 200                                         ranges;
 201                                         interrupt-map-mask = <0 0 0 0>;
 202                                         interrupt-map = <0 0 0 0 &mpic 61>;
 203                                         marvell,pcie-port = <0>;
 204                                         marvell,pcie-lane = <3>;
 205                                         clocks = <&gateclk 8>;
 206                                         status = "disabled";
 207                                 };
 208
 209                                 pcie@5,0 {
 210                                         device_type = "pci";
 211                                         assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 212                                         reg = <0x2800 0 0 0 0>;
 213                                         #address-cells = <3>;
 214                                         #size-cells = <2>;
 215                                         #interrupt-cells = <1>;
 216                                         ranges;
 217                                         interrupt-map-mask = <0 0 0 0>;
 218                                         interrupt-map = <0 0 0 0 &mpic 62>;
 219                                         marvell,pcie-port = <1>;
 220                                         marvell,pcie-lane = <0>;
 221                                         clocks = <&gateclk 9>;
 222                                         status = "disabled";
 223                                 };
 224
 225                                 pcie@6,0 {
 226                                         device_type = "pci";
 227                                         assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 228                                         reg = <0x3000 0 0 0 0>;
 229                                         #address-cells = <3>;
 230                                         #size-cells = <2>;
 231                                         #interrupt-cells = <1>;
 232                                         ranges;
 233                                         interrupt-map-mask = <0 0 0 0>;
 234                                         interrupt-map = <0 0 0 0 &mpic 63>;
 235                                         marvell,pcie-port = <1>;
 236                                         marvell,pcie-lane = <1>;
 237                                         clocks = <&gateclk 10>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 pcie@7,0 {
 242                                         device_type = "pci";
 243                                         assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 244                                         reg = <0x3800 0 0 0 0>;
 245                                         #address-cells = <3>;
 246                                         #size-cells = <2>;
 247                                         #interrupt-cells = <1>;
 248                                         ranges;
 249                                         interrupt-map-mask = <0 0 0 0>;
 250                                         interrupt-map = <0 0 0 0 &mpic 64>;
 251                                         marvell,pcie-port = <1>;
 252                                         marvell,pcie-lane = <2>;
 253                                         clocks = <&gateclk 11>;
 254                                         status = "disabled";
 255                                 };
 256
 257                                 pcie@8,0 {
 258                                         device_type = "pci";
 259                                         assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 260                                         reg = <0x4000 0 0 0 0>;
 261                                         #address-cells = <3>;
 262                                         #size-cells = <2>;
 263                                         #interrupt-cells = <1>;
 264                                         ranges;
 265                                         interrupt-map-mask = <0 0 0 0>;
 266                                         interrupt-map = <0 0 0 0 &mpic 65>;
 267                                         marvell,pcie-port = <1>;
 268                                         marvell,pcie-lane = <3>;
 269                                         clocks = <&gateclk 12>;
 270                                         status = "disabled";
 271                                 };
 272                                 pcie@9,0 {
 273                                         device_type = "pci";
 274                                         assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 275                                         reg = <0x4800 0 0 0 0>;
 276                                         #address-cells = <3>;
 277                                         #size-cells = <2>;
 278                                         #interrupt-cells = <1>;
 279                                         ranges;
 280                                         interrupt-map-mask = <0 0 0 0>;
 281                                         interrupt-map = <0 0 0 0 &mpic 99>;
 282                                         marvell,pcie-port = <2>;
 283                                         marvell,pcie-lane = <0>;
 284                                         clocks = <&gateclk 26>;
 285                                         status = "disabled";
 286                                 };
 287
 288                                 pcie@10,0 {
 289                                         device_type = "pci";
 290                                         assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 291                                         reg = <0x5000 0 0 0 0>;
 292                                         #address-cells = <3>;
 293                                         #size-cells = <2>;
 294                                         #interrupt-cells = <1>;
 295                                         ranges;
 296                                         interrupt-map-mask = <0 0 0 0>;
 297                                         interrupt-map = <0 0 0 0 &mpic 103>;
 298                                         marvell,pcie-port = <3>;
 299                                         marvell,pcie-lane = <0>;
 300                                         clocks = <&gateclk 27>;
 301                                         status = "disabled";
 302                                 };
 303                         };
 304                 };
 305         };
 306 };