ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
[deliverable/linux.git] / arch / arm / boot / dts / armada-xp.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
17 */
18
19 #include "armada-370-xp.dtsi"
20
21 / {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 eth2 = &eth2;
27 };
28
29 soc {
30 internal-regs {
31 L2: l2-cache {
32 compatible = "marvell,aurora-system-cache";
33 reg = <0x08000 0x1000>;
34 cache-id-part = <0x100>;
35 wt-override;
36 };
37
38 interrupt-controller@20000 {
39 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
40 };
41
42 armada-370-xp-pmsu@22000 {
43 compatible = "marvell,armada-370-xp-pmsu";
44 reg = <0x22100 0x430>, <0x20800 0x20>;
45 };
46
47 serial@12200 {
48 compatible = "snps,dw-apb-uart";
49 reg = <0x12200 0x100>;
50 reg-shift = <2>;
51 interrupts = <43>;
52 reg-io-width = <1>;
53 status = "disabled";
54 };
55 serial@12300 {
56 compatible = "snps,dw-apb-uart";
57 reg = <0x12300 0x100>;
58 reg-shift = <2>;
59 interrupts = <44>;
60 reg-io-width = <1>;
61 status = "disabled";
62 };
63
64 timer@20300 {
65 marvell,timer-25Mhz;
66 };
67
68 coreclk: mvebu-sar@18230 {
69 compatible = "marvell,armada-xp-core-clock";
70 reg = <0x18230 0x08>;
71 #clock-cells = <1>;
72 };
73
74 cpuclk: clock-complex@18700 {
75 #clock-cells = <1>;
76 compatible = "marvell,armada-xp-cpu-clock";
77 reg = <0x18700 0xA0>;
78 clocks = <&coreclk 1>;
79 };
80
81 gateclk: clock-gating-control@18220 {
82 compatible = "marvell,armada-xp-gating-clock";
83 reg = <0x18220 0x4>;
84 clocks = <&coreclk 0>;
85 #clock-cells = <1>;
86 };
87
88 system-controller@18200 {
89 compatible = "marvell,armada-370-xp-system-controller";
90 reg = <0x18200 0x500>;
91 };
92
93 eth2: ethernet@30000 {
94 compatible = "marvell,armada-370-neta";
95 reg = <0x30000 0x4000>;
96 interrupts = <12>;
97 clocks = <&gateclk 2>;
98 status = "disabled";
99 };
100
101 xor@60900 {
102 compatible = "marvell,orion-xor";
103 reg = <0x60900 0x100
104 0x60b00 0x100>;
105 clocks = <&gateclk 22>;
106 status = "okay";
107
108 xor10 {
109 interrupts = <51>;
110 dmacap,memcpy;
111 dmacap,xor;
112 };
113 xor11 {
114 interrupts = <52>;
115 dmacap,memcpy;
116 dmacap,xor;
117 dmacap,memset;
118 };
119 };
120
121 xor@f0900 {
122 compatible = "marvell,orion-xor";
123 reg = <0xF0900 0x100
124 0xF0B00 0x100>;
125 clocks = <&gateclk 28>;
126 status = "okay";
127
128 xor00 {
129 interrupts = <94>;
130 dmacap,memcpy;
131 dmacap,xor;
132 };
133 xor01 {
134 interrupts = <95>;
135 dmacap,memcpy;
136 dmacap,xor;
137 dmacap,memset;
138 };
139 };
140
141 usb@50000 {
142 clocks = <&gateclk 18>;
143 };
144
145 usb@51000 {
146 clocks = <&gateclk 19>;
147 };
148
149 usb@52000 {
150 compatible = "marvell,orion-ehci";
151 reg = <0x52000 0x500>;
152 interrupts = <47>;
153 clocks = <&gateclk 20>;
154 status = "disabled";
155 };
156
157 thermal@182b0 {
158 compatible = "marvell,armadaxp-thermal";
159 reg = <0x182b0 0x4
160 0x184d0 0x4>;
161 status = "okay";
162 };
163 };
164 };
165 };
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