2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
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43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include "skeleton.dtsi"
47 compatible = "axis,artpec6";
48 interrupt-parent = <&intc>;
56 compatible = "arm,cortex-a9";
58 next-level-cache = <&pl310>;
63 compatible = "arm,cortex-a9";
65 next-level-cache = <&pl310>;
70 compatible = "axis,artpec6-syscon", "syscon";
71 reg = <0xf8000000 0x48>;
75 compatible = "arm,psci-0.2", "arm,psci";
77 psci_version = <0x84000000>;
78 cpu_on = <0x84000003>;
79 system_reset = <0x84000009>;
83 compatible = "arm,cortex-a9-scu";
84 reg = <0xfaf00000 0x58>;
87 /* Main external clock driving CPU and peripherals */
90 compatible = "fixed-clock";
91 clock-frequency = <50000000>;
94 eth_phy_ref_clk: eth_phy_ref_clk {
96 compatible = "fixed-clock";
97 clock-frequency = <125000000>;
100 clkctrl: clkctrl@0xf8000000 {
102 compatible = "axis,artpec6-clkctrl";
103 reg = <0xf8000000 0x48>;
105 clock-names = "sys_refclk";
109 compatible = "arm,cortex-a9-global-timer";
110 reg = <0xfaf00200 0x20>;
111 interrupts = <GIC_PPI 11 0xf01>;
112 clocks = <&clkctrl 1>;
116 compatible = "arm,cortex-a9-twd-timer";
117 reg = <0xfaf00600 0x20>;
118 interrupts = <GIC_PPI 13 0xf04>;
119 clocks = <&clkctrl 1>;
123 intc: interrupt-controller@faf01000 {
124 interrupt-controller;
125 compatible = "arm,cortex-a9-gic";
126 #interrupt-cells = <3>;
127 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
130 pl310: cache-controller@faf10000 {
131 compatible = "arm,pl310-cache";
134 reg = <0xfaf10000 0x1000>;
135 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
136 arm,data-latency = <1 1 1>;
137 arm,tag-latency = <1 1 1>;
138 arm,filter-ranges = <0x0 0x80000000>;
142 compatible = "arm,cortex-a9-pmu";
143 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-parent = <&intc>;
149 compatible = "simple-bus";
150 #address-cells = <0x1>;
152 interrupt-parent = <&intc>;
154 dma-ranges = <0x80000000 0x00000000 0x40000000>;
157 ethernet: ethernet@f8010000 {
158 clock-names = "phy_ref_clk", "apb_pclk";
159 clocks = <ð_phy_ref_clk>,
161 compatible = "snps,dwc-qos-ethernet-4.10";
162 interrupt-parent = <&intc>;
163 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
164 reg = <0xf8010000 0x4000>;
166 snps,write-requests = <2>;
167 snps,read-requests = <16>;
174 uart0: serial@f8036000 {
175 compatible = "arm,pl011", "arm,primecell";
176 reg = <0xf8036000 0x1000>;
177 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clkctrl 13>,
180 clock-names = "uart_clk", "apb_pclk";
183 uart1: serial@f8037000 {
184 compatible = "arm,pl011", "arm,primecell";
185 reg = <0xf8037000 0x1000>;
186 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clkctrl 13>,
189 clock-names = "uart_clk", "apb_pclk";
192 uart2: serial@f8038000 {
193 compatible = "arm,pl011", "arm,primecell";
194 reg = <0xf8038000 0x1000>;
195 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clkctrl 13>,
198 clock-names = "uart_clk", "apb_pclk";
201 uart3: serial@f8039000 {
202 compatible = "arm,pl011", "arm,primecell";
203 reg = <0xf8039000 0x1000>;
204 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clkctrl 13>,
207 clock-names = "uart_clk", "apb_pclk";