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pwm: Update DT bindings to reference pwm.txt for cells documentation
[deliverable/linux.git] / arch / arm / boot / dts / at91sam9x5.dtsi
1 /*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 #include "skeleton.dtsi"
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17
18 / {
19 model = "Atmel AT91SAM9x5 family SoC";
20 compatible = "atmel,at91sam9x5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 gpio0 = &pioA;
29 gpio1 = &pioB;
30 gpio2 = &pioC;
31 gpio3 = &pioD;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
34 i2c0 = &i2c0;
35 i2c1 = &i2c1;
36 i2c2 = &i2c2;
37 ssc0 = &ssc0;
38 };
39 cpus {
40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
46 };
47 };
48
49 memory {
50 reg = <0x20000000 0x10000000>;
51 };
52
53 ahb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 apb {
60 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 aic: interrupt-controller@fffff000 {
66 #interrupt-cells = <3>;
67 compatible = "atmel,at91rm9200-aic";
68 interrupt-controller;
69 reg = <0xfffff000 0x200>;
70 atmel,external-irqs = <31>;
71 };
72
73 ramc0: ramc@ffffe800 {
74 compatible = "atmel,at91sam9g45-ddramc";
75 reg = <0xffffe800 0x200>;
76 };
77
78 pmc: pmc@fffffc00 {
79 compatible = "atmel,at91rm9200-pmc";
80 reg = <0xfffffc00 0x100>;
81 };
82
83 rstc@fffffe00 {
84 compatible = "atmel,at91sam9g45-rstc";
85 reg = <0xfffffe00 0x10>;
86 };
87
88 shdwc@fffffe10 {
89 compatible = "atmel,at91sam9x5-shdwc";
90 reg = <0xfffffe10 0x10>;
91 };
92
93 pit: timer@fffffe30 {
94 compatible = "atmel,at91sam9260-pit";
95 reg = <0xfffffe30 0xf>;
96 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
97 };
98
99 tcb0: timer@f8008000 {
100 compatible = "atmel,at91sam9x5-tcb";
101 reg = <0xf8008000 0x100>;
102 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
103 };
104
105 tcb1: timer@f800c000 {
106 compatible = "atmel,at91sam9x5-tcb";
107 reg = <0xf800c000 0x100>;
108 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
109 };
110
111 dma0: dma-controller@ffffec00 {
112 compatible = "atmel,at91sam9g45-dma";
113 reg = <0xffffec00 0x200>;
114 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
115 #dma-cells = <2>;
116 };
117
118 dma1: dma-controller@ffffee00 {
119 compatible = "atmel,at91sam9g45-dma";
120 reg = <0xffffee00 0x200>;
121 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
122 #dma-cells = <2>;
123 };
124
125 pinctrl@fffff400 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
129 ranges = <0xfffff400 0xfffff400 0x800>;
130
131 /* shared pinctrl settings */
132 dbgu {
133 pinctrl_dbgu: dbgu-0 {
134 atmel,pins =
135 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
136 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
137 };
138 };
139
140 usart0 {
141 pinctrl_usart0: usart0-0 {
142 atmel,pins =
143 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
144 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
145 };
146
147 pinctrl_usart0_rts: usart0_rts-0 {
148 atmel,pins =
149 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
150 };
151
152 pinctrl_usart0_cts: usart0_cts-0 {
153 atmel,pins =
154 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
155 };
156
157 pinctrl_usart0_sck: usart0_sck-0 {
158 atmel,pins =
159 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
160 };
161 };
162
163 usart1 {
164 pinctrl_usart1: usart1-0 {
165 atmel,pins =
166 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
167 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
168 };
169
170 pinctrl_usart1_rts: usart1_rts-0 {
171 atmel,pins =
172 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
173 };
174
175 pinctrl_usart1_cts: usart1_cts-0 {
176 atmel,pins =
177 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
178 };
179
180 pinctrl_usart1_sck: usart1_sck-0 {
181 atmel,pins =
182 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
183 };
184 };
185
186 usart2 {
187 pinctrl_usart2: usart2-0 {
188 atmel,pins =
189 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
190 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
191 };
192
193 pinctrl_uart2_rts: uart2_rts-0 {
194 atmel,pins =
195 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
196 };
197
198 pinctrl_uart2_cts: uart2_cts-0 {
199 atmel,pins =
200 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
201 };
202
203 pinctrl_usart2_sck: usart2_sck-0 {
204 atmel,pins =
205 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
206 };
207 };
208
209 usart3 {
210 pinctrl_usart3: usart3-0 {
211 atmel,pins =
212 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
213 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
214 };
215
216 pinctrl_usart3_rts: usart3_rts-0 {
217 atmel,pins =
218 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
219 };
220
221 pinctrl_usart3_cts: usart3_cts-0 {
222 atmel,pins =
223 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
224 };
225
226 pinctrl_usart3_sck: usart3_sck-0 {
227 atmel,pins =
228 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
229 };
230 };
231
232 uart0 {
233 pinctrl_uart0: uart0-0 {
234 atmel,pins =
235 <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
236 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
237 };
238 };
239
240 uart1 {
241 pinctrl_uart1: uart1-0 {
242 atmel,pins =
243 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
244 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
245 };
246 };
247
248 nand {
249 pinctrl_nand: nand-0 {
250 atmel,pins =
251 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
252 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
253 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
254 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
255 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
256 AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
257 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
258 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
259 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
260 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
261 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
262 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
263 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
264 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
265 };
266
267 pinctrl_nand_16bits: nand_16bits-0 {
268 atmel,pins =
269 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
270 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
271 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
272 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
273 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
274 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
275 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
276 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
277 };
278 };
279
280 macb0 {
281 pinctrl_macb0_rmii: macb0_rmii-0 {
282 atmel,pins =
283 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
284 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
285 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
286 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
287 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
288 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
289 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
290 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
291 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
292 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
293 };
294
295 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
296 atmel,pins =
297 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
298 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
299 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
300 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
301 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
302 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
303 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
304 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
305 };
306 };
307
308 mmc0 {
309 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
310 atmel,pins =
311 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
312 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
313 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
314 };
315
316 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
317 atmel,pins =
318 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
319 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
320 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
321 };
322 };
323
324 mmc1 {
325 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
326 atmel,pins =
327 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
328 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
329 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
330 };
331
332 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
333 atmel,pins =
334 <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
335 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
336 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
337 };
338 };
339
340 ssc0 {
341 pinctrl_ssc0_tx: ssc0_tx-0 {
342 atmel,pins =
343 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
344 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
345 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
346 };
347
348 pinctrl_ssc0_rx: ssc0_rx-0 {
349 atmel,pins =
350 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
351 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
352 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
353 };
354 };
355
356 spi0 {
357 pinctrl_spi0: spi0-0 {
358 atmel,pins =
359 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
360 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
361 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
362 };
363 };
364
365 spi1 {
366 pinctrl_spi1: spi1-0 {
367 atmel,pins =
368 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
369 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
370 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
371 };
372 };
373
374 i2c0 {
375 pinctrl_i2c0: i2c0-0 {
376 atmel,pins =
377 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
378 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
379 };
380 };
381
382 i2c1 {
383 pinctrl_i2c1: i2c1-0 {
384 atmel,pins =
385 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
386 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
387 };
388 };
389
390 i2c2 {
391 pinctrl_i2c2: i2c2-0 {
392 atmel,pins =
393 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
394 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
395 };
396 };
397
398 i2c_gpio0 {
399 pinctrl_i2c_gpio0: i2c_gpio0-0 {
400 atmel,pins =
401 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
402 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
403 };
404 };
405
406 i2c_gpio1 {
407 pinctrl_i2c_gpio1: i2c_gpio1-0 {
408 atmel,pins =
409 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
410 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
411 };
412 };
413
414 i2c_gpio2 {
415 pinctrl_i2c_gpio2: i2c_gpio2-0 {
416 atmel,pins =
417 <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
418 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
419 };
420 };
421
422 tcb0 {
423 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
424 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
425 };
426
427 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
428 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
429 };
430
431 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
432 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
433 };
434
435 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
436 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
437 };
438
439 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
440 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
441 };
442
443 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
444 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
445 };
446
447 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
448 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
449 };
450
451 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
452 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
453 };
454
455 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
456 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
457 };
458 };
459
460 tcb1 {
461 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
462 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
463 };
464
465 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
466 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
467 };
468
469 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
470 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
471 };
472
473 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
474 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
475 };
476
477 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
478 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
479 };
480
481 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
482 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
483 };
484
485 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
486 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
487 };
488
489 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
490 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
491 };
492
493 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
494 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
495 };
496 };
497
498 pioA: gpio@fffff400 {
499 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
500 reg = <0xfffff400 0x200>;
501 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
502 #gpio-cells = <2>;
503 gpio-controller;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 };
507
508 pioB: gpio@fffff600 {
509 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
510 reg = <0xfffff600 0x200>;
511 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
512 #gpio-cells = <2>;
513 gpio-controller;
514 #gpio-lines = <19>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 };
518
519 pioC: gpio@fffff800 {
520 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
521 reg = <0xfffff800 0x200>;
522 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
523 #gpio-cells = <2>;
524 gpio-controller;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 };
528
529 pioD: gpio@fffffa00 {
530 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
531 reg = <0xfffffa00 0x200>;
532 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
533 #gpio-cells = <2>;
534 gpio-controller;
535 #gpio-lines = <22>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 };
539 };
540
541 ssc0: ssc@f0010000 {
542 compatible = "atmel,at91sam9g45-ssc";
543 reg = <0xf0010000 0x4000>;
544 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
547 status = "disabled";
548 };
549
550 mmc0: mmc@f0008000 {
551 compatible = "atmel,hsmci";
552 reg = <0xf0008000 0x600>;
553 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
554 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
555 dma-names = "rxtx";
556 #address-cells = <1>;
557 #size-cells = <0>;
558 status = "disabled";
559 };
560
561 mmc1: mmc@f000c000 {
562 compatible = "atmel,hsmci";
563 reg = <0xf000c000 0x600>;
564 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
565 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
566 dma-names = "rxtx";
567 #address-cells = <1>;
568 #size-cells = <0>;
569 status = "disabled";
570 };
571
572 dbgu: serial@fffff200 {
573 compatible = "atmel,at91sam9260-usart";
574 reg = <0xfffff200 0x200>;
575 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_dbgu>;
578 status = "disabled";
579 };
580
581 usart0: serial@f801c000 {
582 compatible = "atmel,at91sam9260-usart";
583 reg = <0xf801c000 0x200>;
584 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_usart0>;
587 status = "disabled";
588 };
589
590 usart1: serial@f8020000 {
591 compatible = "atmel,at91sam9260-usart";
592 reg = <0xf8020000 0x200>;
593 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_usart1>;
596 status = "disabled";
597 };
598
599 usart2: serial@f8024000 {
600 compatible = "atmel,at91sam9260-usart";
601 reg = <0xf8024000 0x200>;
602 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_usart2>;
605 status = "disabled";
606 };
607
608 macb0: ethernet@f802c000 {
609 compatible = "cdns,at32ap7000-macb", "cdns,macb";
610 reg = <0xf802c000 0x100>;
611 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_macb0_rmii>;
614 status = "disabled";
615 };
616
617 macb1: ethernet@f8030000 {
618 compatible = "cdns,at32ap7000-macb", "cdns,macb";
619 reg = <0xf8030000 0x100>;
620 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
621 status = "disabled";
622 };
623
624 i2c0: i2c@f8010000 {
625 compatible = "atmel,at91sam9x5-i2c";
626 reg = <0xf8010000 0x100>;
627 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
628 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
629 <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
630 dma-names = "tx", "rx";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&pinctrl_i2c0>;
635 status = "disabled";
636 };
637
638 i2c1: i2c@f8014000 {
639 compatible = "atmel,at91sam9x5-i2c";
640 reg = <0xf8014000 0x100>;
641 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
642 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
643 <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
644 dma-names = "tx", "rx";
645 #address-cells = <1>;
646 #size-cells = <0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_i2c1>;
649 status = "disabled";
650 };
651
652 i2c2: i2c@f8018000 {
653 compatible = "atmel,at91sam9x5-i2c";
654 reg = <0xf8018000 0x100>;
655 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
656 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
657 <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
658 dma-names = "tx", "rx";
659 #address-cells = <1>;
660 #size-cells = <0>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_i2c2>;
663 status = "disabled";
664 };
665
666 uart0: serial@f8040000 {
667 compatible = "atmel,at91sam9260-usart";
668 reg = <0xf8040000 0x200>;
669 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_uart0>;
672 status = "disabled";
673 };
674
675 uart1: serial@f8044000 {
676 compatible = "atmel,at91sam9260-usart";
677 reg = <0xf8044000 0x200>;
678 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_uart1>;
681 status = "disabled";
682 };
683
684 adc0: adc@f804c000 {
685 compatible = "atmel,at91sam9260-adc";
686 reg = <0xf804c000 0x100>;
687 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
688 atmel,adc-use-external;
689 atmel,adc-channels-used = <0xffff>;
690 atmel,adc-vref = <3300>;
691 atmel,adc-num-channels = <12>;
692 atmel,adc-startup-time = <40>;
693 atmel,adc-channel-base = <0x50>;
694 atmel,adc-drdy-mask = <0x1000000>;
695 atmel,adc-status-register = <0x30>;
696 atmel,adc-trigger-register = <0xc0>;
697 atmel,adc-res = <8 10>;
698 atmel,adc-res-names = "lowres", "highres";
699 atmel,adc-use-res = "highres";
700
701 trigger@0 {
702 trigger-name = "external-rising";
703 trigger-value = <0x1>;
704 trigger-external;
705 };
706
707 trigger@1 {
708 trigger-name = "external-falling";
709 trigger-value = <0x2>;
710 trigger-external;
711 };
712
713 trigger@2 {
714 trigger-name = "external-any";
715 trigger-value = <0x3>;
716 trigger-external;
717 };
718
719 trigger@3 {
720 trigger-name = "continuous";
721 trigger-value = <0x6>;
722 };
723 };
724
725 spi0: spi@f0000000 {
726 #address-cells = <1>;
727 #size-cells = <0>;
728 compatible = "atmel,at91rm9200-spi";
729 reg = <0xf0000000 0x100>;
730 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
731 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
732 <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
733 dma-names = "tx", "rx";
734 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_spi0>;
736 status = "disabled";
737 };
738
739 spi1: spi@f0004000 {
740 #address-cells = <1>;
741 #size-cells = <0>;
742 compatible = "atmel,at91rm9200-spi";
743 reg = <0xf0004000 0x100>;
744 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
745 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
746 <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
747 dma-names = "tx", "rx";
748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_spi1>;
750 status = "disabled";
751 };
752
753 usb2: gadget@f803c000 {
754 #address-cells = <1>;
755 #size-cells = <0>;
756 compatible = "atmel,at91sam9rl-udc";
757 reg = <0x00500000 0x80000
758 0xf803c000 0x400>;
759 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
760 status = "disabled";
761
762 ep0 {
763 reg = <0>;
764 atmel,fifo-size = <64>;
765 atmel,nb-banks = <1>;
766 };
767
768 ep1 {
769 reg = <1>;
770 atmel,fifo-size = <1024>;
771 atmel,nb-banks = <2>;
772 atmel,can-dma;
773 atmel,can-isoc;
774 };
775
776 ep2 {
777 reg = <2>;
778 atmel,fifo-size = <1024>;
779 atmel,nb-banks = <2>;
780 atmel,can-dma;
781 atmel,can-isoc;
782 };
783
784 ep3 {
785 reg = <3>;
786 atmel,fifo-size = <1024>;
787 atmel,nb-banks = <3>;
788 atmel,can-dma;
789 };
790
791 ep4 {
792 reg = <4>;
793 atmel,fifo-size = <1024>;
794 atmel,nb-banks = <3>;
795 atmel,can-dma;
796 };
797
798 ep5 {
799 reg = <5>;
800 atmel,fifo-size = <1024>;
801 atmel,nb-banks = <3>;
802 atmel,can-dma;
803 atmel,can-isoc;
804 };
805
806 ep6 {
807 reg = <6>;
808 atmel,fifo-size = <1024>;
809 atmel,nb-banks = <3>;
810 atmel,can-dma;
811 atmel,can-isoc;
812 };
813 };
814
815 watchdog@fffffe40 {
816 compatible = "atmel,at91sam9260-wdt";
817 reg = <0xfffffe40 0x10>;
818 status = "disabled";
819 };
820
821 rtc@fffffeb0 {
822 compatible = "atmel,at91sam9x5-rtc";
823 reg = <0xfffffeb0 0x40>;
824 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
825 status = "disabled";
826 };
827 };
828
829 nand0: nand@40000000 {
830 compatible = "atmel,at91rm9200-nand";
831 #address-cells = <1>;
832 #size-cells = <1>;
833 reg = <0x40000000 0x10000000
834 0xffffe000 0x600 /* PMECC Registers */
835 0xffffe600 0x200 /* PMECC Error Location Registers */
836 0x00108000 0x18000 /* PMECC looup table in ROM code */
837 >;
838 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
839 atmel,nand-addr-offset = <21>;
840 atmel,nand-cmd-offset = <22>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_nand>;
843 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
844 &pioD 4 GPIO_ACTIVE_HIGH
845 0
846 >;
847 status = "disabled";
848 };
849
850 usb0: ohci@00600000 {
851 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
852 reg = <0x00600000 0x100000>;
853 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
854 status = "disabled";
855 };
856
857 usb1: ehci@00700000 {
858 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
859 reg = <0x00700000 0x100000>;
860 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
861 status = "disabled";
862 };
863 };
864
865 i2c@0 {
866 compatible = "i2c-gpio";
867 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
868 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
869 >;
870 i2c-gpio,sda-open-drain;
871 i2c-gpio,scl-open-drain;
872 i2c-gpio,delay-us = <2>; /* ~100 kHz */
873 #address-cells = <1>;
874 #size-cells = <0>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&pinctrl_i2c_gpio0>;
877 status = "disabled";
878 };
879
880 i2c@1 {
881 compatible = "i2c-gpio";
882 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
883 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
884 >;
885 i2c-gpio,sda-open-drain;
886 i2c-gpio,scl-open-drain;
887 i2c-gpio,delay-us = <2>; /* ~100 kHz */
888 #address-cells = <1>;
889 #size-cells = <0>;
890 pinctrl-names = "default";
891 pinctrl-0 = <&pinctrl_i2c_gpio1>;
892 status = "disabled";
893 };
894
895 i2c@2 {
896 compatible = "i2c-gpio";
897 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
898 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
899 >;
900 i2c-gpio,sda-open-drain;
901 i2c-gpio,scl-open-drain;
902 i2c-gpio,delay-us = <2>; /* ~100 kHz */
903 #address-cells = <1>;
904 #size-cells = <0>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pinctrl_i2c_gpio2>;
907 status = "disabled";
908 };
909 };
Linux kernel - Deliverables
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