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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
36 #include "skeleton.dtsi"
39 compatible = "brcm,cygnus";
40 model = "Broadcom Cygnus SoC";
41 interrupt-parent = <&gic>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
55 /include/ "bcm-cygnus-clock.dtsi"
57 pinctrl: pinctrl@0x0301d0c8 {
58 compatible = "brcm,cygnus-pinmux";
59 reg = <0x0301d0c8 0x30>,
63 gpio_crmu: gpio@03024800 {
64 compatible = "brcm,cygnus-crmu-gpio";
65 reg = <0x03024800 0x50>,
71 gpio_ccm: gpio@1800a000 {
72 compatible = "brcm,cygnus-ccm-gpio";
73 reg = <0x1800a000 0x50>,
77 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
81 gpio_asiu: gpio@180a5000 {
82 compatible = "brcm,cygnus-asiu-gpio";
83 reg = <0x180a5000 0x668>;
90 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
96 compatible = "arm,amba-bus", "simple-bus";
97 interrupt-parent = <&gic>;
101 compatible = "arm,sp805" , "arm,primecell";
102 reg = <0x18009000 0x1000>;
103 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&axi81_clk>;
105 clock-names = "apb_pclk";
110 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
111 reg = <0x18008000 0x100>;
112 #address-cells = <1>;
114 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
115 clock-frequency = <100000>;
120 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
121 reg = <0x1800b000 0x100>;
122 #address-cells = <1>;
124 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
125 clock-frequency = <100000>;
129 uart0: serial@18020000 {
130 compatible = "snps,dw-apb-uart";
131 reg = <0x18020000 0x100>;
134 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&axi81_clk>;
136 clock-frequency = <100000000>;
140 uart1: serial@18021000 {
141 compatible = "snps,dw-apb-uart";
142 reg = <0x18021000 0x100>;
145 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&axi81_clk>;
147 clock-frequency = <100000000>;
151 uart2: serial@18022000 {
152 compatible = "snps,dw-apb-uart";
153 reg = <0x18020000 0x100>;
156 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&axi81_clk>;
158 clock-frequency = <100000000>;
162 uart3: serial@18023000 {
163 compatible = "snps,dw-apb-uart";
164 reg = <0x18023000 0x100>;
167 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&axi81_clk>;
169 clock-frequency = <100000000>;
173 gic: interrupt-controller@19021000 {
174 compatible = "arm,cortex-a9-gic";
175 #interrupt-cells = <3>;
176 #address-cells = <0>;
177 interrupt-controller;
178 reg = <0x19021000 0x1000>,
183 compatible = "arm,pl310-cache";
184 reg = <0x19022000 0x1000>;
190 compatible = "arm,cortex-a9-global-timer";
191 reg = <0x19020200 0x100>;
192 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&periph_clk>;