arch/arm/boot/dts/bcm-nsp.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-nsp.h>
  36
  37 #include "skeleton.dtsi"
  38
  39 / {
  40         compatible = "brcm,nsp";
  41         model = "Broadcom Northstar Plus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x0>;
  53                 };
  54
  55                 cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         next-level-cache = <&L2>;
  59                         enable-method = "brcm,bcm-nsp-smp";
  60                         secondary-boot-reg = <0xffff042c>;
  61                         reg = <0x1>;
  62                 };
  63         };
  64
  65         mpcore {
  66                 compatible = "simple-bus";
  67                 ranges = <0x00000000 0x19000000 0x00023000>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70
  71                 cpus {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         cpu@0 {
  76                                 device_type = "cpu";
  77                                 compatible = "arm,cortex-a9";
  78                                 next-level-cache = <&L2>;
  79                                 reg = <0x0>;
  80                         };
  81                 };
  82
  83                 a9pll: arm_clk@00000 {
  84                         #clock-cells = <0>;
  85                         compatible = "brcm,nsp-armpll";
  86                         clocks = <&osc>;
  87                         reg = <0x00000 0x1000>;
  88                 };
  89
  90                 timer@20200 {
  91                         compatible = "arm,cortex-a9-global-timer";
  92                         reg = <0x20200 0x100>;
  93                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  94                         clocks = <&periph_clk>;
  95                 };
  96
  97                 twd-timer@20600 {
  98                         compatible = "arm,cortex-a9-twd-timer";
  99                         reg = <0x20600 0x20>;
 100                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 101                                                   IRQ_TYPE_LEVEL_HIGH)>;
 102                         clocks = <&periph_clk>;
 103                 };
 104
 105                 twd-watchdog@20620 {
 106                         compatible = "arm,cortex-a9-twd-wdt";
 107                         reg = <0x20620 0x20>;
 108                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 109                                                   IRQ_TYPE_LEVEL_HIGH)>;
 110                         clocks = <&periph_clk>;
 111                 };
 112
 113                 gic: interrupt-controller@21000 {
 114                         compatible = "arm,cortex-a9-gic";
 115                         #interrupt-cells = <3>;
 116                         #address-cells = <0>;
 117                         interrupt-controller;
 118                         reg = <0x21000 0x1000>,
 119                               <0x20100 0x100>;
 120                 };
 121
 122                 L2: l2-cache {
 123                         compatible = "arm,pl310-cache";
 124                         reg = <0x22000 0x1000>;
 125                         cache-unified;
 126                         cache-level = <2>;
 127                 };
 128         };
 129
 130         clocks {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134
 135                 osc: oscillator {
 136                         #clock-cells = <0>;
 137                         compatible = "fixed-clock";
 138                         clock-frequency = <25000000>;
 139                 };
 140
 141                 iprocmed: iprocmed {
 142                         #clock-cells = <0>;
 143                         compatible = "fixed-factor-clock";
 144                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 145                         clock-div = <2>;
 146                         clock-mult = <1>;
 147                 };
 148
 149                 iprocslow: iprocslow {
 150                         #clock-cells = <0>;
 151                         compatible = "fixed-factor-clock";
 152                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 153                         clock-div = <4>;
 154                         clock-mult = <1>;
 155                 };
 156
 157                 periph_clk: periph_clk {
 158                         #clock-cells = <0>;
 159                         compatible = "fixed-factor-clock";
 160                         clocks = <&a9pll>;
 161                         clock-div = <2>;
 162                         clock-mult = <1>;
 163                 };
 164         };
 165
 166         axi {
 167                 compatible = "simple-bus";
 168                 ranges = <0x00000000 0x18000000 0x0011ba08>;
 169                 #address-cells = <1>;
 170                 #size-cells = <1>;
 171
 172                 uart0: serial@0300 {
 173                         compatible = "ns16550a";
 174                         reg = <0x0300 0x100>;
 175                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 176                         clocks = <&osc>;
 177                         status = "disabled";
 178                 };
 179
 180                 uart1: serial@0400 {
 181                         compatible = "ns16550a";
 182                         reg = <0x0400 0x100>;
 183                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 184                         clocks = <&osc>;
 185                         status = "disabled";
 186                 };
 187
 188                 pcie0: pcie@12000 {
 189                         compatible = "brcm,iproc-pcie";
 190                         reg = <0x12000 0x1000>;
 191
 192                         #interrupt-cells = <1>;
 193                         interrupt-map-mask = <0 0 0 0>;
 194                         interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
 195
 196                         linux,pci-domain = <0>;
 197
 198                         bus-range = <0x00 0xff>;
 199
 200                         #address-cells = <3>;
 201                         #size-cells = <2>;
 202                         device_type = "pci";
 203
 204                         /* Note: The HW does not support I/O resources.  So,
 205                          * only the memory resource range is being specified.
 206                          */
 207                         ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
 208
 209                         status = "disabled";
 210                 };
 211
 212                 pcie1: pcie@13000 {
 213                         compatible = "brcm,iproc-pcie";
 214                         reg = <0x13000 0x1000>;
 215
 216                         #interrupt-cells = <1>;
 217                         interrupt-map-mask = <0 0 0 0>;
 218                         interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
 219
 220                         linux,pci-domain = <1>;
 221
 222                         bus-range = <0x00 0xff>;
 223
 224                         #address-cells = <3>;
 225                         #size-cells = <2>;
 226                         device_type = "pci";
 227
 228                         /* Note: The HW does not support I/O resources.  So,
 229                          * only the memory resource range is being specified.
 230                          */
 231                         ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
 232
 233                         status = "disabled";
 234                 };
 235
 236                 pcie2: pcie@14000 {
 237                         compatible = "brcm,iproc-pcie";
 238                         reg = <0x14000 0x1000>;
 239
 240                         #interrupt-cells = <1>;
 241                         interrupt-map-mask = <0 0 0 0>;
 242                         interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
 243
 244                         linux,pci-domain = <2>;
 245
 246                         bus-range = <0x00 0xff>;
 247
 248                         #address-cells = <3>;
 249                         #size-cells = <2>;
 250                         device_type = "pci";
 251
 252                         /* Note: The HW does not support I/O resources.  So,
 253                          * only the memory resource range is being specified.
 254                          */
 255                         ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
 256
 257                         status = "disabled";
 258                 };
 259
 260                 nand: nand@26000 {
 261                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 262                         reg = <0x026000 0x600>,
 263                               <0x11b408 0x600>,
 264                               <0x026f00 0x20>;
 265                         reg-names = "nand", "iproc-idm", "iproc-ext";
 266                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 267
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270
 271                         brcm,nand-has-wp;
 272                 };
 273
 274                 i2c0: i2c@38000 {
 275                         compatible = "brcm,iproc-i2c";
 276                         reg = <0x38000 0x50>;
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
 280                         clock-frequency = <100000>;
 281                 };
 282
 283                 lcpll0: lcpll0@3f100 {
 284                         #clock-cells = <1>;
 285                         compatible = "brcm,nsp-lcpll0";
 286                         reg = <0x3f100 0x14>;
 287                         clocks = <&osc>;
 288                         clock-output-names = "lcpll0", "pcie_phy", "sdio",
 289                                              "ddr_phy";
 290                 };
 291
 292                 genpll: genpll@3f140 {
 293                         #clock-cells = <1>;
 294                         compatible = "brcm,nsp-genpll";
 295                         reg = <0x3f140 0x24>;
 296                         clocks = <&osc>;
 297                         clock-output-names = "genpll", "phy", "ethernetclk",
 298                                              "usbclk", "iprocfast", "sata1",
 299                                              "sata2";
 300                 };
 301
 302                 pinctrl: pinctrl@3f1c0 {
 303                         compatible = "brcm,nsp-pinmux";
 304                         reg = <0x3f1c0 0x04>,
 305                               <0x30028 0x04>,
 306                               <0x3f408 0x04>;
 307                 };
 308         };
 309 };