arch/arm/boot/dts/bcm5301x.dtsi

   1 /*
   2  * Broadcom BCM470X / BCM5301X ARM platform code.
   3  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
   4  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
   5  *
   6  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <dt-bindings/clock/bcm-nsp.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         interrupt-parent = <&gic>;
  20
  21         chosen {
  22                 stdout-path = &uart0;
  23         };
  24
  25         chipcommonA {
  26                 compatible = "simple-bus";
  27                 ranges = <0x00000000 0x18000000 0x00001000>;
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 uart0: serial@0300 {
  32                         compatible = "ns16550";
  33                         reg = <0x0300 0x100>;
  34                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  35                         clocks = <&iprocslow>;
  36                         status = "disabled";
  37                 };
  38
  39                 uart1: serial@0400 {
  40                         compatible = "ns16550";
  41                         reg = <0x0400 0x100>;
  42                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  43                         clocks = <&iprocslow>;
  44                         status = "disabled";
  45                 };
  46         };
  47
  48         mpcore {
  49                 compatible = "simple-bus";
  50                 ranges = <0x00000000 0x19000000 0x00023000>;
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53
  54                 a9pll: arm_clk@00000 {
  55                         #clock-cells = <0>;
  56                         compatible = "brcm,nsp-armpll";
  57                         clocks = <&osc>;
  58                         reg = <0x00000 0x1000>;
  59                 };
  60
  61                 scu@20000 {
  62                         compatible = "arm,cortex-a9-scu";
  63                         reg = <0x20000 0x100>;
  64                 };
  65
  66                 timer@20200 {
  67                         compatible = "arm,cortex-a9-global-timer";
  68                         reg = <0x20200 0x100>;
  69                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  70                         clocks = <&periph_clk>;
  71                 };
  72
  73                 local-timer@20600 {
  74                         compatible = "arm,cortex-a9-twd-timer";
  75                         reg = <0x20600 0x100>;
  76                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  77                         clocks = <&periph_clk>;
  78                 };
  79
  80                 gic: interrupt-controller@21000 {
  81                         compatible = "arm,cortex-a9-gic";
  82                         #interrupt-cells = <3>;
  83                         #address-cells = <0>;
  84                         interrupt-controller;
  85                         reg = <0x21000 0x1000>,
  86                               <0x20100 0x100>;
  87                 };
  88
  89                 L2: cache-controller@22000 {
  90                         compatible = "arm,pl310-cache";
  91                         reg = <0x22000 0x1000>;
  92                         cache-unified;
  93                         arm,shared-override;
  94                         prefetch-data = <1>;
  95                         prefetch-instr = <1>;
  96                         cache-level = <2>;
  97                 };
  98         };
  99
 100         pmu {
 101                 compatible = "arm,cortex-a9-pmu";
 102                 interrupts =
 103                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 104                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 105         };
 106
 107         clocks {
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 ranges;
 111
 112                 osc: oscillator {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <25000000>;
 116                 };
 117
 118                 iprocmed: iprocmed {
 119                         #clock-cells = <0>;
 120                         compatible = "fixed-factor-clock";
 121                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 122                         clock-div = <2>;
 123                         clock-mult = <1>;
 124                 };
 125
 126                 iprocslow: iprocslow {
 127                         #clock-cells = <0>;
 128                         compatible = "fixed-factor-clock";
 129                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 130                         clock-div = <4>;
 131                         clock-mult = <1>;
 132                 };
 133
 134                 periph_clk: periph_clk {
 135                         #clock-cells = <0>;
 136                         compatible = "fixed-factor-clock";
 137                         clocks = <&a9pll>;
 138                         clock-div = <2>;
 139                         clock-mult = <1>;
 140                 };
 141         };
 142
 143         axi@18000000 {
 144                 compatible = "brcm,bus-axi";
 145                 reg = <0x18000000 0x1000>;
 146                 ranges = <0x00000000 0x18000000 0x00100000>;
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149
 150                 #interrupt-cells = <1>;
 151                 interrupt-map-mask = <0x000fffff 0xffff>;
 152                 interrupt-map =
 153                         /* ChipCommon */
 154                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 155
 156                         /* Switch Register Access Block */
 157                         <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 158                         <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 159                         <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 160                         <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 161                         <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 162                         <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 163                         <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 164                         <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 165                         <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 166                         <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 167                         <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 168                         <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 169                         <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 170
 171                         /* PCIe Controller 0 */
 172                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 173                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 174                         <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 175                         <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 176                         <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 177                         <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 178
 179                         /* PCIe Controller 1 */
 180                         <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 181                         <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 182                         <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 183                         <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 184                         <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 185                         <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 186
 187                         /* PCIe Controller 2 */
 188                         <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 189                         <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 190                         <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 191                         <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 192                         <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 193                         <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 194
 195                         /* USB 2.0 Controller */
 196                         <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 197
 198                         /* USB 3.0 Controller */
 199                         <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 200
 201                         /* Ethernet Controller 0 */
 202                         <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 203
 204                         /* Ethernet Controller 1 */
 205                         <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 206
 207                         /* Ethernet Controller 2 */
 208                         <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 209
 210                         /* Ethernet Controller 3 */
 211                         <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 212
 213                         /* NAND Controller */
 214                         <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 215                         <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 216                         <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 217                         <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 218                         <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 219                         <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 220                         <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 221                         <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 222
 223                 chipcommon: chipcommon@0 {
 224                         reg = <0x00000000 0x1000>;
 225
 226                         gpio-controller;
 227                         #gpio-cells = <2>;
 228                 };
 229
 230                 usb2: usb2@21000 {
 231                         reg = <0x00021000 0x1000>;
 232
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                 };
 236
 237                 usb3: usb3@23000 {
 238                         reg = <0x00023000 0x1000>;
 239
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                 };
 243
 244                 spi@29000 {
 245                         reg = <0x00029000 0x1000>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248
 249                         spi_nor: spi-nor@0 {
 250                                 compatible = "jedec,spi-nor";
 251                                 reg = <0>;
 252                                 spi-max-frequency = <20000000>;
 253                                 linux,part-probe = "ofpart", "bcm47xxpart";
 254                                 status = "disabled";
 255                         };
 256                 };
 257
 258                 gmac0: ethernet@24000 {
 259                         reg = <0x24000 0x800>;
 260                 };
 261
 262                 gmac1: ethernet@25000 {
 263                         reg = <0x25000 0x800>;
 264                 };
 265
 266                 gmac2: ethernet@26000 {
 267                         reg = <0x26000 0x800>;
 268                 };
 269
 270                 gmac3: ethernet@27000 {
 271                         reg = <0x27000 0x800>;
 272                 };
 273         };
 274
 275         lcpll0: lcpll0@1800c100 {
 276                 #clock-cells = <1>;
 277                 compatible = "brcm,nsp-lcpll0";
 278                 reg = <0x1800c100 0x14>;
 279                 clocks = <&osc>;
 280                 clock-output-names = "lcpll0", "pcie_phy", "sdio",
 281                                      "ddr_phy";
 282         };
 283
 284         genpll: genpll@1800c140 {
 285                 #clock-cells = <1>;
 286                 compatible = "brcm,nsp-genpll";
 287                 reg = <0x1800c140 0x24>;
 288                 clocks = <&osc>;
 289                 clock-output-names = "genpll", "phy", "ethernetclk",
 290                                      "usbclk", "iprocfast", "sata1",
 291                                      "sata2";
 292         };
 293
 294         srab: srab@18007000 {
 295                 compatible = "brcm,bcm5301x-srab";
 296                 reg = <0x18007000 0x1000>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299
 300                 status = "disabled";
 301
 302                 /* ports are defined in board DTS */
 303         };
 304
 305         rng: rng@18004000 {
 306                 compatible = "brcm,bcm5301x-rng";
 307                 reg = <0x18004000 0x14>;
 308         };
 309
 310         nand: nand@18028000 {
 311                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 312                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 313                 reg-names = "nand", "iproc-idm", "iproc-ext";
 314                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 315
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318
 319                 brcm,nand-has-wp;
 320         };
 321 };