2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
19 interrupt-parent = <&gic>;
26 compatible = "simple-bus";
27 ranges = <0x00000000 0x18000000 0x00001000>;
32 compatible = "ns16550";
34 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&iprocslow>;
40 compatible = "ns16550";
42 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&iprocslow>;
49 compatible = "simple-bus";
50 ranges = <0x00000000 0x19000000 0x00023000>;
54 a9pll: arm_clk@00000 {
56 compatible = "brcm,nsp-armpll";
58 reg = <0x00000 0x1000>;
62 compatible = "arm,cortex-a9-scu";
63 reg = <0x20000 0x100>;
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x20200 0x100>;
69 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&periph_clk>;
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x20600 0x100>;
76 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&periph_clk>;
80 gic: interrupt-controller@21000 {
81 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
85 reg = <0x21000 0x1000>,
89 L2: cache-controller@22000 {
90 compatible = "arm,pl310-cache";
91 reg = <0x22000 0x1000>;
101 compatible = "arm,cortex-a9-pmu";
103 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
108 #address-cells = <1>;
114 compatible = "fixed-clock";
115 clock-frequency = <25000000>;
120 compatible = "fixed-factor-clock";
121 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
126 iprocslow: iprocslow {
128 compatible = "fixed-factor-clock";
129 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
134 periph_clk: periph_clk {
136 compatible = "fixed-factor-clock";
144 compatible = "brcm,bus-axi";
145 reg = <0x18000000 0x1000>;
146 ranges = <0x00000000 0x18000000 0x00100000>;
147 #address-cells = <1>;
150 #interrupt-cells = <1>;
151 interrupt-map-mask = <0x000fffff 0xffff>;
154 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
156 /* Switch Register Access Block */
157 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
158 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
159 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
160 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
161 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
162 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
163 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
164 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
165 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
171 /* PCIe Controller 0 */
172 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
179 /* PCIe Controller 1 */
180 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
181 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
187 /* PCIe Controller 2 */
188 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
189 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
195 /* USB 2.0 Controller */
196 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
198 /* USB 3.0 Controller */
199 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
201 /* Ethernet Controller 0 */
202 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
204 /* Ethernet Controller 1 */
205 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
207 /* Ethernet Controller 2 */
208 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
210 /* Ethernet Controller 3 */
211 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
213 /* NAND Controller */
214 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
215 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
216 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
217 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
218 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
219 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
220 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
221 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
223 chipcommon: chipcommon@0 {
224 reg = <0x00000000 0x1000>;
231 reg = <0x00021000 0x1000>;
233 #address-cells = <1>;
238 reg = <0x00023000 0x1000>;
240 #address-cells = <1>;
245 reg = <0x00029000 0x1000>;
246 #address-cells = <1>;
250 compatible = "jedec,spi-nor";
252 spi-max-frequency = <20000000>;
253 linux,part-probe = "ofpart", "bcm47xxpart";
258 gmac0: ethernet@24000 {
259 reg = <0x24000 0x800>;
262 gmac1: ethernet@25000 {
263 reg = <0x25000 0x800>;
266 gmac2: ethernet@26000 {
267 reg = <0x26000 0x800>;
270 gmac3: ethernet@27000 {
271 reg = <0x27000 0x800>;
275 lcpll0: lcpll0@1800c100 {
277 compatible = "brcm,nsp-lcpll0";
278 reg = <0x1800c100 0x14>;
280 clock-output-names = "lcpll0", "pcie_phy", "sdio",
284 genpll: genpll@1800c140 {
286 compatible = "brcm,nsp-genpll";
287 reg = <0x1800c140 0x24>;
289 clock-output-names = "genpll", "phy", "ethernetclk",
290 "usbclk", "iprocfast", "sata1",
294 srab: srab@18007000 {
295 compatible = "brcm,bcm5301x-srab";
296 reg = <0x18007000 0x1000>;
297 #address-cells = <1>;
302 /* ports are defined in board DTS */
306 compatible = "brcm,bcm5301x-rng";
307 reg = <0x18004000 0x14>;
310 nand: nand@18028000 {
311 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
312 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
313 reg-names = "nand", "iproc-idm", "iproc-ext";
314 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;